TL/F/5967
CD4043BM/CD4043BC Quad TRI-STATEÉNOR R/S Latches
CD4044BM/CD4044BC Quad TRI-STATE NAND R/S Latches
February 1988
CD4043BM/CD4043BC Quad TRI-STATEÉ
NOR R/S Latches
CD4044BM/CD4044BC Quad TRI-STATE
NAND R/S Latches
General Description
CD4043BM/CD4043BC are quad cross-couple TRI-STATE
CMOS NOR latches, and CD4044BM/CD4044BC are quad
cross-couple TRI-STATE CMOS NAND latches. Each latch
has a separate Q output and individual SET and RESET
inputs. There is a common TRI-STATE ENABLE input for all
four latches. A logic ‘‘1’’ on the ENABLE input connects the
latch states to the Q outputs. A logic ‘‘0’’ on the ENABLE
input disconnects the latch states from the Q outputs result-
ing in an open circuit condition on the Q output. The
TRI-STATE feature allows common bussing of the outputs.
Features
YWide supply voltage range 3V to 15V
YLow power 100 nW (typ.)
YHigh noise immunity 0.45 VDD (typ.)
YSeparate SET and RESET inputs for each latch
YNOR and NAND configuration
YTRI-STATE output with common output enable
Applications
YMultiple bus storage
YStrobed register
YFour bits of independent storage with output enable
YGeneral digital logic
Connection Diagrams
CD4043BM/CD4043BC
Dual-In-Line and Flat Packages
TL/F/5967–3
Top View
CD4044BM/CD4044BC
Dual-In-Line and Flat Packages
TL/F/5967–4
Top View
Truth Table
CD4043BM/CD4043BC
SRE Q
XX0OC
001NC
101 1
011 0
111 D
CD4044BM/CD4044BC
SRE Q
XX0OC
111NC
011 1
101 0
001DD
Order Number CD4043B or CD4044B
OC Ð TRI-STATE
NC Ð No change
X Ð Don’t care
DÐ Dominated by Se1 input
DD Ð Dominated by Re0 input
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VDD)b0.5V to a18V
Input Voltage (VIN)b0.5V to VDD a0.5V
Storage Temperature Range (TS)b65§Ctoa
150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§C
Recommended Operating
Conditions (Note 2)
Supply Voltage (VDD) 3.0V to 15V
Input Voltage (VIN) 0 to VDD V
Operating Temperature Range (TA)
CD4043BM, CD4044BM b55§Ctoa
125§C
CD4043BC, CD4044BC b40§Ctoa
85§C
DC Electrical Characteristics CD4043BM/CD4044BM (Note 2)
Symbol Parameter Conditions b55§Ca25§Ca125§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent VDD e5V, VIN eVDD or VSS 5.0 0.01 5.0 150 mA
Device Current VDD e10V, VIN eVDD or VSS 10 0.01 10 300 mA
VDD e15V, VIN eVDD or VSS 20 0.02 20 600 mA
VOL Low Level
l
IO
l
s1mA, VIL e0V, VIH eVDD
Output Voltage VDD e5.0V 0.05 0 0.05 0.05 V
VDD e10V 0.05 0 0.05 0.05 V
VDD e15V 0.05 0 0.05 0.05 V
VOH High Level
l
IO
l
s1mA, VIL e0V, VIH eVDD
Output Voltage VDD e5.0V 4.95 4.95 5.0 4.95 V
VDD e10V 9.95 9.95 10 9.95 V
VDD e15V 14.95 14.95 15 14.95 V
VIL Low Level
l
IO
l
s1mA
Input Voltage VDD e5.0V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD e10V, VOe1.0V or 9.0V 3.0 4.5 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level
l
IO
l
s1mA
Input Voltage VDD e5.0V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V
VDD e5.0V, VOe1.0V or 9.0V 7.0 7.0 5.5 7.0 V
VDD e15V, VOe1.5V or 13.5V 11 11 8.25 11 V
IOL Low Level VIL e0V, VIH eVDD
Output Current VDD e5.0V, VOe0.4V 0.64 0.51 1.0 0.36 mA
VDD e10V, VOe0.5V 1.6 1.3 2.6 0.9 mA
VDD e15V, VOe1.5V 4.2 3.4 6.8 2.4 mA
IOH High Level VIL e0V, VIH eVDD
Output Current VDD e5.0V, VOe4.6V b0.64 b0.51 b0.4 b0.36 mA
VDD e10V, VOe9.5V b1.6 b1.3 b1.0 b0.9 mA
VDD e15V, VOe13.5V b4.2 b3.4 b3.0 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.1 b10-5 b0.1 b1.0 mA
VDD e15V, VIN e15V 0.1 10-5 0.1 1.0 mA
DC Electrical Characteristics CD4043BC/CD4044BC (Note 2)
Symbol Parameter Conditions b40§Ca25§Ca85§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent VDD e5V, VIN eVDD or VSS 20 0.01 20 150 mA
Device Current VDD e10V, VIN eVDD or VSS 40 0.01 40 300 mA
VDD e15V, VIN eVDD or VSS 80 0.02 80 600 mA
VOL Low Level
l
IO
l
s1mA, VIL e0V, VIH eVDD
Output Voltage VDD e5.0V 0.05 0 0.05 0.05 V
VDD e10V 0.05 0 0.05 0.05 V
VDD e15V 0.05 0 0.05 0.05 V
VOH High Level
l
IO
l
s1mA, VIL e0V, VIH eVDD
Output Voltage VDD e5.0V 4.95 4.95 5.0 4.95 V
VDD e10V 9.95 9.95 10 9.95 V
VDD e15V 14.95 14.95 15 14.95 V
2
DC Electrical Characteristics CD4043BC/CD4044BC (Continued)
Symbol Parameter Conditions b40§Ca25§Ca85§CUnits
Min Max Min Typ Max Min Max
VIL Low Level
l
IO
l
s1mA
Input Voltage VDD e5.0V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD e10V, VOe1.0V or 9.0V 3.0 4.5 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level
l
IO
l
s1mA
Input Voltage VDD e5.0V, VOe0.5V or 4.5V 3.5 3.5 3.5 V
VDD e5.0V, VOe1.0V or 9.0V 7.0 7.0 7.0 V
VDD e15V, VOe1.5V or 13.5V 11 11 11 V
IOL Low Level VIL e0V, VIH eVDD
Output Current VDD e5.0V, VOe0.4V 0.52 0.44 0.88 0.36 mA
(Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.2 0.9 mA
VDD e15V, VOe1.5V 3.6 3.0 6.0 2.4 mA
IOH High Level VIL e0V, VIH eVDD
Output Current VDD e5.0V, VOe4.6V b0.52 b0.44 b0.32 b0.36 mA
(Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b0.8 b0.9 mA
VDD e15V, VOe13.5V b3.6 b3.0 b2.4 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.3 b0.3 b1.0 mA
VDD e15V, VIN e15V 0.3 0.3 1.0 mA
AC Electrical Characteristics*
TAe25§C, CLe50 pF, RLe200k, input tretfe20 ns, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
tPLH,t
PHL Propagation Delay S or R to Q VDD e5.0V 175 350 ns
VDD e10V 75 175 ns
VDD e15V 60 120 ns
tPZH,t
PHZ Propagation Delay Enable to Q (High) VDD e5.0V 115 230 ns
VDD e10V 55 110 ns
VDD e15V 40 80 ns
tPZL,t
PLZ Propagation Delay Enable to Q (Low) VDD e5.0V 100 200 ns
VDD e10V 50 100 ns
VDD e15V 40 80 ns
tTHL,t
TLH Transition Time VDD e5.0V 100 200 ns
VDD e10V 50 100 ns
VDD e15V 40 80 ns
tWO Minimum SET or RESET Pulse Width VDD e5.0V 80 160 ns
VDD e10V 40 80 ns
VDD e15V 20 40 ns
CIN Input Capacitance 5.0 7.5 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
3
Schematic Diagrams
CD4043BM/CD4043BC
TL/F/5967–1
CD4044BM/CD4044BC
TL/F/5967–2
Timing Waveforms
CD4043B
TL/F/5967–5
CD4044B
TL/F/5967–6
Enable Timing
TL/F/5967–7
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4043BMJ, CD4043BCJ, CD4044BMJ or CD4044BCJ
NS Package Number J16A
5
CD4043BM/CD4043BC Quad TRI-STATEÉNOR R/S Latches
CD4044BM/CD4044BC Quad TRI-STATE NAND R/S Latches
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4043BMN, CD4043BCN, CD4044BMN or CD4044BCN
NS Package Number N16E
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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