ASAHI KASEI [AK5701] AK5701 PLL & MIC-AMP16-Bit Stereo ADC AK570116bit A/DAK5701 ALC(Auto Level Control) PLLDSP AK570124pin QFN 1. : 16bits 2. - 2 - or - (+30dB/+15dB or 0dB) - : 1.8Vpp@VA=3.0V (= 0.6 x AVDD) - ADC: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB - HPF (fc=3.4Hz@fs=44.1kHz) - Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) 3. : - PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz - PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz - PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - EXT Master/Slave Mode: 7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs) 4. PLL: - MCKI pin: 27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz, 11.2896MHz - EXLRCK pin: 1fs - EXBCLK pin: 32fs/64fs 5. 6. : MSB First, 2's compliment - DSP Mode, 16bit, I2S 7. P: 3 8. : - AVDD: 2.4 3.6V - DVDD: 1.6 3.6V 9. : 8mA 10. Ta = -30 85C 11. : 24pin QFN (4mm x 4mm) MS0404-J-00 2005/08 -1- ASAHI KASEI [AK5701] DVDD DVSS PDN LIN1 RIN1 LIN2 S E L ADC ALC or HPF MIX IVOL RIN2 LRCK Audio I/F Controller BCLK S E L SDTO MPWR VCOM AVDD AVSS VCOC Control Register PLL MCKO MCKI CSP EXLRCK EXBCLK EXSDTI CSN CCLK CDTI Figure 1. MS0404-J-00 2005/08 -2- ASAHI KASEI [AK5701] -30 +85C AK5701 AK5701VN AKD5701 24pin QFN (0.5mm pitch) PDN CSN CCLK CDTI MCKI EXBCLK 18 17 16 15 14 13 MCKO RIN1 22 Top View 9 CSP LIN1 23 8 SDTO VCOC 24 7 LRCK 6 10 BCLK AK5701VN 5 21 DVSS LIN2 4 EXSDTI DVDD 11 3 20 AVDD RIN2 2 EXLRCK AVSS 12 1 19 VCOM MPWR AK5355VN ALC I/F PLL AK5355VN +15dB/0dB Left justified, I2S 2.1 3.6V 20pin QFN (4.2mm x 4.2mm) MS0404-J-00 AK5701 +30dB/+15dB/0dB DSP Mode, Left justified, I2S AVDD=2.4 3.6V DVDD=1.6 3.6V 24pin QFN (4mm x 4mm) 2005/08 -3- ASAHI KASEI [AK5701] No. Pin Name I/O Function , 0.5 x AVDD ADC 2 AVSS 3 AVDD 4 DVDD 5 DVSS 6 BCLK O 7 LRCK O 8 SDTO O 9 CSP I "H": CSN pin = "H" active, C1-0 = "01" "L": CSN pin = "L" active, C1-0 = "10" 10 MCKO O 11 EXSDTI I 12 EXLRCK I 13 EXBCLK I 14 MCKI I 15 CDTI I 16 CCLK I (CSP pin = "H") 17 CSN I 18 PDN I "H": "L": 19 MPWR O RIN2 I (MDIF2 bit = "0") Rch2 20 RIN+ I (MDIF2 bit = "1") Rch LIN2 I (MDIF2 bit = "0") Lch2 21 I (MDIF2 bit = "1") Rch RIN- RIN1 I (MDIF1 bit = "0") Rch1 22 I (MDIF1 bit = "1") Lch LIN- LIN1 I (MDIF1 bit = "0") Lch1 23 LIN+ I (MDIF1 bit = "1") Lch PLL 24 VCOC O AVSS Note 1. (LIN1, RIN1, LIN2, RIN2) 1 VCOM O Analog Digital MPWR, VCOC, LIN1/LIN+, RIN1/LIN-, LIN2/RIN-, RIN2/RIN+ BCLK, LRCK, SDTO, MCKO MCKI, EXBCLK, EXLRCK, EXSDTI MS0404-J-00 DVSS 2005/08 -4- ASAHI KASEI [AK5701] (AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital |AVSS - DVSS| (Note 3) Input Current, Any Pin Except Supplies Analog Input Voltage (Note 4) Digital Input Voltage (Note 5) Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -30 -65 max 4.6 4.6 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V mA V V C C Note 2. Note 3. AVSSDVSS Note 4. LIN1/LIN+, RIN1/LIN-, LIN2/RIN-, RIN2/RIN+ pins Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins : (AVSS, DVSS=0V; Note 2) Parameter Power Supplies Analog (Note 6) Digital Symbol AVDD DVDD min 2.4 1.6 typ 3.0 3.0 Max 3.6 AVDD Units V V Note 2. Note 6. AVDD, DVDDAVDDOFF DVDDDVDDOFFAVDDOFF : MS0404-J-00 2005/08 -5- ASAHI KASEI [AK5701] (Ta=25C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Min Typ max Units Parameter MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = "0" (Single-ended inputs) Input MGAIN1-0 bits = "00" 40 60 80 k Resistance MGAIN1-0 bits = "01" or "10" 20 30 40 k MGAIN1-0 bits = "00" 0 dB Gain MGAIN1-0 bits = "01" +15 dB MGAIN1-0 bits = "10" +30 dB MIC Amplifier: LIN+, LIN-, RIN+, RIN- pins; MDIF1 = MDIF2 bits = "1" (Full-differential input) Input Voltage (Note 7) MGAIN1-0 bits = "01" 0.37 Vpp MGAIN1-0 bits = "10" 0.066 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 8) 2.02 2.25 2.48 V Load Resistance 0.5 k Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins (Single-ended inputs) ADC IVOL, MGAIN=+15dB, IVOL=0dB, ALC=OFF Resolution 16 Bits MGAIN=+30dB 0.057 Vpp Input Voltage (Note 9) MGAIN=+15dB 0.27 0.32 0.37 Vpp MGAIN=0dB 1.53 1.80 2.07 Vpp 67 77 dB S/(N+D) (-0.5dBFS) (Note 10) 79 87 dB D-Range (-60dBFS, A-weighted) (Note 11) S/N (A-weighted) (Note 11) 79 87 dB Interchannel Isolation (Note 12) 80 90 dB MGAIN=+30dB 0.2 dB Interchannel Gain Mismatch MGAIN=+15dB 0.2 1.0 dB MGAIN=0dB 0.2 0.5 dB Power Supplies: Power Supply Current: AVDD+DVDD Power Up (PDN pin = "H") (Note 13) 8 12 mA Power Down (PDN pin = "L") (Note 14) 1 20 A Note 7. AC MGAIN1-0 bits = "00"LIN+, LIN-, RIN+, RIN- pinAVDDVin = |(L/RIN+) - (L/RIN-)| = 0.123 x AVDD (max)@MGAIN1-0 bits = "01", 0.022 x AVDD (max)@MGAIN1-0 bits = "10". ADC Note 8. AVDDVout = 0.75 x AVDD (typ) Note 9. AVDDVin = 0.107 x AVDD (typ)@MGAIN1-0 bits = "01" (+15dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = "00" (0dB) Note 10. 78dB(typ)@MGAIN=0dB, 72dB(typ)@MGAIN=+30dB Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB Note 12. 100dB(typ)@MGAIN=0dB, 80dB(typ)@MGAIN=+30dB Note 13. PLL Master Mode (MCKI=12MHz)PMADL = PMADR = PMVCM = PMPLL = PMMP = M/S bits = "1", MCKO = "0"MPWR pin0mA AVDD=6.4mA(typ), DVDD=1.6mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = "0"): AVDD=5.7mA(typ), DVDD=1.3mA(typ). Bypass Mode (THR bit = "1", PMADL = PMADR = M/S bits = "0"), fs=8kHz: AVDD=1A(typ), DVDD=150A(typ). Note 14. DVDDDVSS MS0404-J-00 2005/08 -6- ASAHI KASEI [AK5701] (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; fs=44.1kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 15) PB 0 0.1dB -1.0dB -3.0dB Stopband (Note 15) SB 25.7 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 16) GD Group Delay Distortion GD ADC Digital Filter (HPF): HPF1-0 bits = "00" Frequency Response (Note 15) -3.0dB FR -0.5dB -0.1dB typ max Units 20.0 21.1 18 0 17.4 0.1 - kHz kHz kHz kHz dB dB 1/fs s 3.4 10 22 - Hz Hz Hz Note 15. fs () PB=20.0kHz(@-1.0dB)0.454 x fs(ADC)1kHz Note 16. 16 DC (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V) Parameter Symbol min High-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIH 70%DVDD Except CSP pin; 1.6V DVDD <2.2V VIH 80%DVDD CSP pin VIH 90%DVDD Low-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIL Except CSP pin; 1.6V DVDD <2.2V VIL CSP pin VIL High-Level Output Voltage (Iout= -200A) VOH DVDD-0.2 Low-Level Output Voltage (Iout= 200A) VOL Input Leakage Current (Note 17) Iin - typ max Units - - V V V - 30%DVDD 20%DVDD 10%DVDD 0.2 10 V V V V V A Note 17. CSP pin = "H"CCLK pin(typ. 100k) MS0404-J-00 2005/08 -7- ASAHI KASEI [AK5701] (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; CL=20pF) Parameter Symbol min PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 256fs at fs=32kHz, 29.4kHz dMCK LRCK Output Timing Frequency Except DSP Mode 1 fs 7.35 DSP Mode 1 (Note 18) fsd 14.7 DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BCLK Output Timing Period BCKO1-0 bit = "01" tBCK BCKO1-0 bit = "10" tBCK Duty Cycle dBCK PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 256fs at fs=32kHz, 29.4kHz dMCK EXLRCK Input Timing Frequency fs 7.35 DSP Mode: Pulse Width High tLRCKH tBCK-60 Except DSP Mode: Duty Cycle Duty 45 EXBCLK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK PLL Slave Mode (PLL Reference Clock = EXLRCK pin) EXLRCK Input Timing Frequency fs 7.35 DSP Mode: Pulse Width High tLRCKH tBCK-60 Except DSP Mode: Duty Cycle Duty 45 EXBCLK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 240 Pulse Width High tBCKH 240 typ max Units - 27 - MHz ns ns - 12.288 MHz 50 33 60 - % % tBCK 50 48 96 - kHz kHz ns % 1/(32fs) 1/(64fs) 50 - ns ns % - 27 - MHz ns ns - 12.288 MHz 50 33 60 - % % - 48 1/fs - tBCK 55 kHz ns % - 1/(32fs) - ns ns ns - 48 1/fs - tBCK 55 kHz ns % - 1/(32fs) - ns ns ns Note 18. 7.35kHz 48kHz MS0404-J-00 2005/08 -8- ASAHI KASEI [AK5701] Parameter Symbol PLL Slave Mode (PLL Reference Clock = EXBCLK pin) EXLRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period PLL3-0 bits = "0010" tBCK PLL3-0 bits = "0011" tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH EXLRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BCLK Output Timing Period BCKO1-0 bit = "01" tBCK BCKO1-0 bit = "10" tBCK Duty Cycle dBCK MS0404-J-00 min typ max Units 7.35 tBCK-60 45 - 48 1/fs - tBCK 55 kHz ns % 0.4 x tBCK 0.4 x tBCK 1/(32fs) 1/(64fs) - - ns ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 7.35 7.35 tBCK-60 45 - 48 26 13 1/fs - tBCK 55 kHz kHz kHz ns % 312.5 130 130 - - ns ns ns 1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK - 12.288 13.312 13.312 - MHz MHz MHz ns ns 7.35 - tBCK 50 48 - kHz ns % - 1/(32fs) 1/(64fs) 50 - ns ns % 2005/08 -9- ASAHI KASEI Parameter Audio Interface Timing (DSP Mode) Master Mode LRCK "" to BCLK "" (Note 19) LRCK "" to BCLK "" (Note 20) BCLK "" to SDTO (BCKP bit = "0") BCLK "" to SDTO (BCKP bit = "1") Slave Mode EXLRCK "" to EXBCLK "" (Note 19) EXLRCK "" to EXBCLK "" (Note 20) EXBCLK "" to EXLRCK "" (Note 19) EXBCLK "" to EXLRCK "" (Note 20) EXBCLK "" to SDTO (BCKP bit = "0") EXBCLK "" to SDTO (BCKP bit = "1") Audio Interface Timing (Left justified & I2S) Master Mode BCLK "" to LRCK Edge (Note 21) LRCK Edge to SDTO (MSB) (Except I2S mode) BCLK "" to SDTO Slave Mode EXLRCK Edge to EXBCLK "" (Note 21) EXBCLK "" to EXLRCK Edge (Note 21) EXLRCK Edge to SDTO (MSB) (Except I2S mode) EXBCLK "" to SDTO [AK5701] Symbol min typ Max Units tDBF tDBF tBSD tBSD 0.5 x tBCK - 40 0.5 x tBCK - 40 -70 -70 0.5 x tBCK 0.5 x tBCK - 0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 ns ns ns ns tLRB tLRB tBLR tBLR tBSD tBSD 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK - - 80 80 ns ns ns ns ns ns tMBLR tLRD -40 -70 - 40 70 ns ns tBSD -70 - 70 ns tLRB tBLR tLRD 50 50 - - 80 ns ns ns tBSD - - 80 ns Note 19. MSBS, BCKP bits = "00" or "11" Note 20. MSBS, BCKP bits = "01" or "10" Note 21. EXLRCKEXBCLK "" MS0404-J-00 2005/08 - 10 - ASAHI KASEI Parameter Control Interface Timing (CSP pin = "L") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Control Interface Timing (CSP pin = "H") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "L" Time CSN "" to CCLK "" CCLK "" to CSN "" Power-down & Reset Timing PDN Pulse Width (Note 22) PMADL or PMADR "" to SDTO valid (Note 23) HPF1-0 bits = "00" HPF1-0 bits = "01" HPF1-0 bits = "10" [AK5701] Symbol min typ max Units tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 142 56 56 28 28 150 50 50 - - ns ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 142 56 56 28 28 150 50 50 - - ns ns ns ns ns ns ns ns tPD 150 - - ns tPDV tPDV tPDV - 3088 1552 784 - 1/fs 1/fs 1/fs Note 22. AK5701PDN pin = "L" Note 23. PMADL bitPMADR bitLRCK "" MS0404-J-00 2005/08 - 11 - ASAHI KASEI [AK5701] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%DVDD LRCK tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 50%DVDD BCLK tBCKH tBCKL 1/fMCK dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100 MCKO 50%DVDD tMCKL dMCK = tMCKL x fMCK x 100 Figure 2. Clock Timing (PLL/EXT Master mode) tLRCKH LRCK 50%DVDD tBCK tDBF dBCK BCLK (BCKP = "0") 50%DVDD BCLK (BCKP = "1") 50%DVDD tBSD SDTO MSB 50%DVDD Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "0") MS0404-J-00 2005/08 - 12 - ASAHI KASEI [AK5701] tLRCKH LRCK 50%DVDD tBCK tDBF dBCK BCLK (BCKP = "1") 50%DVDD BCLK (BCKP = "0") 50%DVDD tBSD SDTO MSB 50%DVDD Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "1") 50%DVDD LRCK tMBLR tBCKL BCLK 50%DVDD tLRD tBSD SDTO 50%DVDD Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode) MS0404-J-00 2005/08 - 13 - ASAHI KASEI [AK5701] 1/fs VIH EXLRCK VIL tLRCKH tBLR tBCK VIH EXBCLK (BCKP = "0") VIL tBCKH tBCKL VIH EXBCLK (BCKP = "1") VIL Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0) 1/fs VIH EXLRCK VIL tLRCKH tBLR tBCK VIH EXBCLK (BCKP = "1") VIL tBCKH tBCKL VIH EXBCLK (BCKP = "0") VIL Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1) MS0404-J-00 2005/08 - 14 - ASAHI KASEI [AK5701] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH EXLRCK VIL tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH EXBCLK VIL tBCKH tBCKL fMCK 50%DVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) tLRCKH VIH EXLRCK VIL tLRB VIH EXBCLK VIL (BCKP = "0") VIH EXBCLK (BCKP = "1") VIL tBSD SDTO MSB 50%DVDD Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) MS0404-J-00 2005/08 - 15 - ASAHI KASEI [AK5701] tLRCKH VIH EXLRCK VIL tLRB VIH EXBCLK VIL (BCKP = "1") VIH EXBCLK (BCKP = "0") VIL tBSD SDTO 50%DVDD MSB Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH EXLRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH EXBCLK VIL tBCKH tBCKL Figure 11. Clock Timing (EXT Slave mode) MS0404-J-00 2005/08 - 16 - ASAHI KASEI [AK5701] VIH EXLRCK VIL tBLR tLRB VIH EXBCLK VIL tLRD SDTO tBSD MSB 50%DVDD Figure 12. Audio Interface Timing (PLL/EXT Slave mode) MS0404-J-00 2005/08 - 17 - ASAHI KASEI [AK5701] VIH CSN VIL tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 13. WRITE Command Input Timing (CSP pin = "L") tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 14. WRITE Data Input Timing (CSP pin = "L") MS0404-J-00 2005/08 - 18 - ASAHI KASEI [AK5701] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 15. WRITE Command Input Timing (CSP pin = "H") tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 16. WRITE Data Input Timing (CSP pin = "H") MS0404-J-00 2005/08 - 19 - ASAHI KASEI [AK5701] PMADL bit or PMADR bit tPDV SDTO 50%DVDD Figure 17. Power Down & Reset Timing 1 tPD PDN VIL Figure 18. Power Down & Reset Timing 2 MS0404-J-00 2005/08 - 20 - ASAHI KASEI [AK5701] I/F5(See Table 1 and Table 2.) Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode (Note 24) 1 1 See Table 4 Figure 19 PLL Slave Mode 1 1 0 See Table 4 Figure 21 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 Figure 20 (PLL Reference Clock: EXLRCK or EXBCLK pin) EXT Slave Mode 0 0 x Figure 22 EXT Master Mode (Note 25) 0 1 x Figure 23 Note 24. PLL Master ModeM/S bit = "1", PMPLL bit = "0", MCKO bit = "1"MCKO pin Note 25. EXT Master ModeFigure 49 Table 1. Clock Mode Setting (x: Don't care) Mode PLL Master Mode MCKO bit MCKO pin 0 "L" PS1-0 bits "L" PS1-0 bits 1 PLL Slave Mode (PLL Reference Clock: MCKI pin) 0 1 MCKI pin PLL3-0 bits PLL3-0 bits PLL Slave Mode (PLL Reference Clock: EXLRCK or EXBCLK pin) 0 "L" GND EXT Slave Mode 0 "L" FS1-0 bits EXT Master Mode 0 "L" FS1-0 bits BCLK pin, LRCK pin, EXBCLK pin EXLRCK pin BCLK pin LRCK pin (BCKO1-0 (1fs) (Note 26) bits) EXBCLK pin EXLRCK pin (1fs) ( 32fs) EXBCLK pin EXLRCK pin (PLL3-0 bits (1fs) ) EXBCLK pin EXLRCK pin (1fs) ( 32fs) BCLK pin LRCK pin (BCKO1-0 (1fs) bits) Table 2. Clock pins state in Clock Mode Note 26. PLL Master ModeDSP Mode 1LRCK2fs M/S bit"1""0" AK5701 (PDN pin = "L") M/S bit "1" M/S bit 0 1 Mode Slave Mode EXBCLK, EXLRCK Master Mode BCLK, LRCK Table 3. Select Master/Salve Mode MS0404-J-00 Default 2005/08 - 21 - ASAHI KASEI [AK5701] PLL PMPLL bit = "1"PLLFS3-0 bit, PLL3-0 bit PLLPMPLL bit "0" AE "1" Table 4 1) PLL Mode Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit PLL 0 2 0 0 0 0 0 1 0 0 EXLRCK pin EXBCLK pin 1fs 32fs 3 0 0 1 1 EXBCLK pin 64fs 4 5 6 7 8 9 12 13 14 15 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Others VCOC pin R,C R[] C[F] 6.8k 220n 10k 4.7n 10k 10n 10k 4.7n 10k 10n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 4.7n 10k 10n 10k 10n 10k 220n 10k 220n PLL (max) 80ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 60ms 60ms MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 19.2MHz MCKI pin 12MHz (Note 27) MCKI pin 13.5MHz MCKI pin 27MHz MCKI pin 13MHz MCKI pin 26MHz Others N/A Table 4. Setting of PLL Mode (fs: Sampling Frequency) Note 27. PLL3-0 bits = "0110" "1001"Table 5 Default 2) PLL Mode MCKITable 5 Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 7.35kHz 0 1 0 4 0 7.349918kHz (Note 28) 11.025kHz 0 1 1 5 0 11.024877kHz (Note 28) 14.7kHz 0 1 0 6 1 14.69984kHz (Note 28) 22.05kHz 0 7 1 1 1 22.04975kHz (Note 28) 32kHz 10 1 0 1 0 48kHz 11 1 0 1 1 29.4kHz 1 14 1 1 0 29.39967kHz (Note 28) 44.1kHz 1 15 1 1 1 Default 44.0995kHz (Note 28) Others Others N/A Table 5. Setting of Sampling Frequency at PMPLL bit = "1" and Reference Clock=MCKI pin Note 28. PLL3-0 bits = "1001" MS0404-J-00 2005/08 - 22 - ASAHI KASEI [AK5701] EXLRCK or EXBCLKFS3, FS2 bit(Table 6) FS3 bit FS2 bit Sampling Frequency Mode FS1 bit FS0 bit Range 0 0 Don't care Don't care 7.35kHz fs 12kHz 0 0 1 Don't care Don't care 12kHz < fs 24kHz 1 1 Don't care Don't care Don't care 24kHz < fs 48kHz 2 Default Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = "1" and Reference=EXLRCK/EXBCLK PLL 1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PMPLL bit = "0" AE "1"PLLBCLKLRCK "L"MCKO bit = "1"MCKO pinMCKO bit = "0" MCKO pin "L"(See Table 7) DSP Mode 0, 1PMPLL bit = "0" AE "1"PLLBCLKLRCKLch DSP Mode 0, 1MSBS bit = "0", BCKP bit = "1"MSBS bit = "1", BCKP bit = "0"BCLK1 "H"21/(256fs) PMPLL bit = "0"BCLK, LRCK "L" MCKO pin BCLK pin LRCK pin MCKO bit = "0" MCKO bit = "1" "L" Output "L" Output "L" Output PMPLL bit "0" AE "1" "L" Output PLL Unlock () "L" Output 1fs Output (*) See Table 9 See Table 10 PLL Lock Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") * DSP Mode 1LRCK2fs PLL State 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PMPLL bit = "0" AE "1"PLLMCKO PLLMCKO pinTable 9 PLLADC MCKO pin MCKO bit = "0" MCKO bit = "1" "L" Output PMPLL bit "0" AE "1" "L" Output PLL Unlock () "L" Output See Table 9 PLL Lock Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PLL State MS0404-J-00 2005/08 - 23 - ASAHI KASEI [AK5701] PLL Master Mode (PMPLL bit = "1", M/S bit = "1") 11.2896MHz, 12MHz , 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz PLLMCKO, BCLK, LRCK(MCKO) PS1-0 bit (Table 9)MCKO bitON/OFFBCLKBCKO1-0 bits 32fs or 64fs(See Table 10) 11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz DSP or P AK5701 MCKI MCKO BCLK LRCK 256fs/128fs/64fs/32fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTI SDTO Figure 19. PLL Master Mode Mode 0 1 2 3 PS1 bit PS0 bit MCKO pin 0 0 256fs Default 0 1 128fs 1 0 64fs 1 1 32fs Table 9. MCKO (PLL, MCKO bit = "1") BCKO1 bit BCKO0 bit BCLK 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 10. BCLK Output Frequency at Master Mode MS0404-J-00 2005/08 - 24 - ASAHI KASEI [AK5701] PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") MCKI, EXBCLK or EXLRCK pinPLLAK5701 PLLPLL3-0 bit(Table 4) a) PLL : EXBCLK or EXLRCK pin FS3-0 bit7.35kHz 48kHz(See Table 6.) AK5701 DSP or P MCKI EXBCLK EXLRCK 32fs, 64fs 1fs BCLK LRCK SDTI SDTO Figure 20. PLL Slave Mode 1 (PLL Reference Clock: EXLRCK or EXBCLK pin) b) PLL : MCKI pin MCKOEXBCLK, EXLRCKMCKOEXLRCK (MCKO pin)PS1-0 bit (Table 9) MCKO bitON/OFFFS3-0 bit(See Table 5) 11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz AK5701 DSP or P MCKI MCKO EXBCLK EXLRCK 256fs/128fs/64fs/32fs 32fs 1fs MCLK BCLK LRCK SDTI SDTO Figure 21. PLL Slave Mode 2 (PLL Reference Clock: MCKI pin) ADC(PMADL bit = "1" or PMADR bit = "1")(MCKI, EXBCLK, EXLRCK) (PMADL=PMADR bits = "0") MS0404-J-00 2005/08 - 25 - ASAHI KASEI [AK5701] EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") PMPLL bit"0"(EXT Slave Mode)MCKI pinPLL ADCCODECI/F MCKI (256fs, 512fs or 1024fs), EXBCLK (32fs), EXLRCK(fs) MCKIEXLRCKMCKI FS1-0 bit(See Table 11) Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don't care 0 0 256fs 7.35kHz 48kHz Don't care 0 1 1024fs 7.35kHz 13kHz Don't care 1 0 512fs 7.35kHz 26kHz Don't care 1 1 256fs Default 7.35kHz 48kHz Table 11. EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") MCKI FS3-2 bits FS1 bit FS0 bit ADC(PMADL bit = "1" or PMADR bit = "1")(MCKI, EXBCLK, EXLRCK) (PMADL=PMADR bits = "0") AK5701 DSP or P MCKO 256fs, 512fs or 1024fs MCKI MCLK EXBCLK EXLRCK 32fs 1fs BCLK LRCK SDTI SDTO Figure 22. EXT Slave Mode MS0404-J-00 2005/08 - 26 - ASAHI KASEI [AK5701] EXT Master Mode (PMPLL bit = "0", M/S bit = "1", TE3-0 bits = "0101", TMASTER bit = "1") Figure 49(EXT Master Mode) MCKI pinPLLADCMCKI (256fs, 512fs or 1024fs)MCKIFS1-0 bit(See Table 12) Mode FS3-2 bits 0 1 2 3 Don't care Don't care Don't care Don't care MCKI Input Sampling Frequency Frequency Range 0 0 256fs 7.35kHz 48kHz 0 1 1024fs 7.35kHz 13kHz 1 0 512fs 7.35kHz 26kHz 1 1 256fs 7.35kHz 48kHz Table 12. EXT Master ModeMCKI FS1 bit FS0 bit Default ADC(PMADL bit = "1" or PMADR bit = "1")MCKIMCKI MCKI(PMADL=PMADR bits = "0") AK5701 DSP or P MCKO 256fs, 512fs or 1024fs MCKI BCLK LRCK MCLK 32fs or 64fs 1fs BCLK LRCK SDTI SDTO Figure 23. EXT Master Mode BCKO1 bit BCKO0 bit BCLK 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 13. BCLK Output Frequency at Master Mode MS0404-J-00 2005/08 - 27 - ASAHI KASEI [AK5701] THR bit = "1", M/S bit = "0", PMADL bit = "0", PMADR bit = "0"EXLRCK, EXBCLK, EXSDTI pins LRCK, BCLK, SDTO pins THR bit = "1", M/S bit = "0"PMADL bit = "1" or PMADR bit = "1"EXLRCK, EXBCLK pins LRCK, BCLK pinsSDTO pinADC THR bit M/S bit 0 0 1 0 1 1 PMADL bit PMADR bit "00" "01"/"10"/"11" "00" "01"/"10"/"11" "00" "01"/"10"/"11" "00" "01"/"10"/"11" DSP or P BCLK/LRCK SDTO "L" "L" "L" ADC data Output "L" Output ADC data EXBCLK/EXLRCK EXSDTI EXBCLK/EXLRCK ADC data N/A N/A Output ADC data Table 14. Bypass Mode Select BCLK 1fs SDTI Figure Power down Slave mode Power down Master mode Bypass mode Slave & Bypass N/A Master mode Default Figure 24 Figure 25 DSP or P AK5701 32fs LRCK Mode 32fs BCLK EXBCLK LRCK EXLRCK SDTO EXSDTI BCLK 1fs LRCK SDTO Figure 24. Bypass Mode DSP or P BCLK LRCK SDTI DSP or P AK5701 32fs 1fs 32fs BCLK EXBCLK LRCK EXLRCK SDTO LIN/RIN BCLK 1fs LRCK Analog In Figure 25. Slave & Bypass Mode MS0404-J-00 2005/08 - 28 - ASAHI KASEI [AK5701] 4(Table 15)DIF1-0 bitMSB2's DSP Mode 1PLL Master ModeLRCK, BCLK, SDTO EXLRCK, EXBCLK, SDTOMode 2Mode 3SDTO BCLK/EXBCLK "" Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO BCLK, EXBCLK DSP Mode 0 32fs DSP Mode 1 32fs 32fs I2S 32fs Table 15. Audio Interface Format Figure See Table 16 Figure 34 Figure 35 Default Mode 0, 1 (DSP0, 1)BCKP, MSBS bitI/F BCKP bit = "0"SDTOBCLK/EXBCLK "" BCKP bit = "1"SDTOBCLK/EXBCLK "" MSBS bitMSBBCLK/EXBCLK DIF1 0 0 DIF0 0 1 MSBS BCKP Audio Interface Format SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK ""(Figure 26) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK ""(Figure 27) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 28) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 29) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK ""(Figure 30) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK ""(Figure 31) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 32) SDTOMSBLRCK/EXLRCK ""1 BCLK/EXBCLK "" BCLK/EXBCLK "" (Figure 33) Table 16. Audio Interface Format in Mode 0, 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Default ADC16bit8bit16bit16bit "-1"8bit "-1"8bit "-1"DAC16bit "-256"8bit16bit (128) MS0404-J-00 2005/08 - 29 - ASAHI KASEI [AK5701] EXLRCK LRCK 15 0 EXBCLK(32fs) BCLK(32fs) 1 8 2 14 15 16 18 29 30 31 0 Rch Lch SDTO(o) 17 15 14 8 2 0 1 1 8 2 14 15 16 2 1 15 14 0 18 13 30 31 Rch Lch 15 14 17 8 2 0 1 1/fs 15 14 2 1 0 1/fs 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = "0", MSBS = "0", M/S = "0" or "1") EXLRCK LRCK 15 0 EXBCLK(32fs) BCLK(32fs) 1 8 2 14 15 16 Lch SDTO(o) 15 14 8 2 17 29 30 31 0 1 Lch 15 14 15 14 2 1 0 8 2 Rch 0 1 18 14 15 16 17 18 13 30 31 Rch 8 2 0 1 2 15 14 1 0 1/fs 1/fs 15:MSB, 0:LSB Figure 27. Mode 0 Timing (BCKP = "1", MSBS = "0", M/S = "0" or "1") EXLRCK LRCK 15 0 EXBCLK(32fs) BCLK(32fs) 1 8 2 14 15 16 18 29 30 31 0 Rch Lch SDTO(o) 17 15 14 8 2 1 8 2 14 15 16 1 0 17 18 13 30 31 Rch Lch 2 15 14 0 1 15 14 8 2 1 0 2 15 14 1 0 1/fs 1/fs 15:MSB, 0:LSB Figure 28. Mode 0 Timing (BCKP = "0", MSBS = "1", M/S = "0" or "1") EXLRCK LRCK 15 EXBCLK(32fs) BCLK(32fs) SDTO(o) 0 1 8 2 14 15 16 18 29 30 31 0 Rch Lch 15 14 17 8 2 1 0 15 14 1 8 2 14 15 16 1 0 15 14 18 13 30 31 Rch Lch 2 17 8 2 1 0 15 14 2 1 0 1/fs 1/fs 15:MSB, 0:LSB Figure 29. Mode 0 Timing (BCKP = "1", MSBS = "1", M/S = "0" or "1") MS0404-J-00 2005/08 - 30 - ASAHI KASEI [AK5701] LRCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 11 12 13 14 15 0 BCLK(32fs) Lch SDTO(o) 0 15 Rch 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 17 3 18 2 29 0 1 30 31 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 3 2 0 1 17 18 13 30 31 11 12 13 14 15 BCLK(64fs) Lch SDTO(o) Rch 15 14 8 2 0 1 15 14 8 2 0 1 1/fs 15:MSB, 0:LSB Figure 30. Mode 1 Timing (BCKP = "0", MSBS = "0", M/S = "1") LRCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 0 BCLK(32fs) Lch SDTO(o) 0 15 Rch 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 17 3 18 2 29 0 1 30 31 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 3 2 0 1 17 18 13 30 31 11 12 13 14 15 BCLK(64fs) Lch SDTO(o) Rch 15 14 8 2 0 1 15 14 8 2 0 1 1/fs 15:MSB, 0:LSB Figure 31. Mode 1 Timing (BCKP = "1", MSBS = "0", M/S = "1") LRCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 0 BCLK(32fs) Lch SDTO(o) 0 15 Rch 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 17 3 18 2 29 0 1 30 31 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 3 2 0 1 17 18 13 30 31 11 12 13 14 15 BCLK(64fs) Lch SDTO(o) Rch 15 14 8 2 0 1 15 14 8 2 0 1 1/fs 15:MSB, 0:LSB Figure 32. Mode 1 Timing (BCKP = "0", MSBS = "1", M/S = "1") LRCK 15 0 1 8 2 8 9 10 11 12 13 14 15 0 1 8 2 8 9 10 0 BCLK(32fs) Lch SDTO(o) 0 15 Rch 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 17 3 18 2 29 0 1 30 31 15 14 0 1 8 8 8 2 6 7 14 15 5 16 4 17 3 18 2 13 0 1 30 31 BCLK(64fs) Lch SDTO(o) 15 14 Rch 8 2 1 0 15 14 8 2 1 0 1/fs 15:MSB, 0:LSB Figure 33. Mode 1 Timing (BCKP = "1", MSBS = "1", M/S = "1") MS0404-J-00 2005/08 - 31 - ASAHI KASEI [AK5701] EXLRCK LRCK 0 1 2 8 3 9 10 11 12 13 14 15 0 1 2 8 3 9 10 11 12 13 14 15 0 1 EXBCLK(32fs) BCLK(32fs) 15 14 13 SDTO(o) 0 1 2 8 7 3 6 14 5 15 4 16 3 17 2 1 18 0 31 15 14 13 0 1 2 8 7 3 6 14 5 15 4 16 3 17 2 1 18 0 31 15 0 1 EXBCLK(64fs) BCLK(64fs) 15 14 13 SDTO(o) 13 2 1 0 15 14 13 2 1 1 0 15 15:MSB, 0:LSB Lch Data Rch Data Figure 34. Mode 2 (, M/S = "0" or "1") EXLRCK LRCK 0 1 2 4 3 9 10 11 12 13 14 15 0 1 2 3 4 9 10 11 12 13 14 15 0 1 EXBCLK(32fs) BCLK(32fs) 0 SDTO(o) 0 15 1 14 13 2 3 7 4 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 15 14 13 1 2 3 7 4 7 14 6 15 5 16 4 17 3 18 2 1 31 0 0 1 EXBCLK(64fs) BCLK(64fs) 15 14 13 SDTO(o) 2 1 0 15 14 13 2 2 1 0 15:MSB, 0:LSB Rch Data Lch Data Figure 35. Mode 3 (I2S, M/S = "0" or "1") PMADL, PMADR, MIX bitsADC ALC(ALC bit = "1")(ALC bit = "0") PMADL bit 0 0 1 1 PMADR bit 0 1 0 MIX bit ADC Lch data ADC Rch data x All "0" All "0" x Rch Input Signal Rch Input Signal x Lch Input Signal Lch Input Signal 0 Lch Input Signal Rch Input Signal 1 1 (L+R)/2 (L+R)/2 Table 17. (x: Don't care) MS0404-J-00 Default 2005/08 - 32 - ASAHI KASEI [AK5701] HPF AK5701DCHPFHPFHPF1-0 bits (fs)3.4Hz (@fs= 44.1kHz) fc fs=44.1kHz fs=22.05kHz fs=11.025kHz 3.4Hz 1.7Hz 0.85Hz 6.8Hz 3.4Hz 1.7Hz 13.6Hz 6.8Hz 3.4Hz N/A N/A N/A Table 18. HPF HPF1 bit HPF0 bit 0 0 1 1 0 1 0 1 Default AK5701MDIF1, MDIF2 bit = "0"INL, INR bitLIN1/LIN2, RIN1/RIN2MDIF1, MDIF2 bit = "1"LIN1, RIN1, LIN2, RIN2 pin LIN+, LIN-, RIN-, RIN+ pin(Figure 37) MDIF1 bit MDIF2 bit 0 0 1 1 0 1 INL bit INR bit Lch 0 LIN1 0 1 LIN1 0 LIN2 1 1 LIN2 0 x LIN1 1 x N/A 0 N/A x 1 LIN+/- x x LIN+/- Table 19. MIC/Line In Path Select Rch RIN1 RIN2 RIN1 RIN2 RIN+/- N/A N/A RIN2 RIN+/- Default AK5701 LIN1/LIN+ pin INL bit ADC Lch RIN1/ LIN- pin MDIF1 bit INR bit RIN2/ RIN+ pin ADC Rch LIN2/ RIN- pin MDIF2 bit Figure 36. MS0404-J-00 2005/08 - 33 - ASAHI KASEI [AK5701] AK5701 MPWR pin 1k MIC-Amp IN1- pin IN1+ pin 1k Figure 37. (MDIF1/2 bits = "1") AK5701MGAIN1-0 bit (Table 20)MGAIN1-0 bits = "00"typ. 60kMGAIN1-0 bits = "01", "10"typ. 30k MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +15dB 0 +30dB 1 N/A Table 20. Default PMMP bit = "1"MPWR pin(0.75 x AVDD)V (typ)min. 0.5k2 min. 2k MPWR pin(Figure 38) PMMP bit MPWR pin 0 Hi-Z 1 Output Table 21. Default MIC Power 2k 2k 2k 2k MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 38. MIC Block Circuit MS0404-J-00 2005/08 - 34 - ASAHI KASEI [AK5701] ALC ALC bit = "1"ALCALC 1. ALC ALCLch, RchALC(Table 22) LMAT1-0 bit(Table 23)IVL, IVR(L/R) IVL, IVRL/R ZELMN bit = "0"()ALCIVL, IVRL/R ALCZTM1-0 bit(Table 24) ZELMN bit = "1"()ALCIVL, IVR(: 1/fs) LMAT1-0 bit1 step ALC bit "0"ALC LMTH1 0 0 1 1 LMTH0 ALC ALC 0 Default ALC Output -2.5dBFS -2.5dBFS > ALC Output -4.1dBFS 1 ALC Output -4.1dBFS -4.1dBFS > ALC Output -6.0dBFS 0 ALC Output -6.0dBFS -6.0dBFS > ALC Output -8.5dBFS 1 ALC Output -8.5dBFS -8.5dBFS > ALC Output -12dBFS Table 22. ALC ZELMN 0 1 ZTM1 ZTM0 0 0 1 1 0 1 0 1 LMAT1 LMAT0 ALC ATT 0 0 1 step 0.375dB Default 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 23. ALC ATT 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 24. ALC MS0404-J-00 Default 2005/08 - 35 - ASAHI KASEI 2. [AK5701] ALC ALCWTM1-0(Table 25)ALC (Table 22)ALCALC (Table 27) ZTM1-0(Table 24) RGAIN1-0 bit(Table 26)IVL, IVR(L/R)ALC WTM1-0WTM1-0ZTM1-0 ZTM1-0ALC IVL, IVR30HRGAIN1-0 bit = "01"(2 steps)ALC IVL, IVR32H0.75dB(0.375dB x 2)IVL, IVR (REF7-0) IVL, IVR ALC () Output Signal < () () > Output Signal ALCALC WTM1 WTM0 0 0 1 1 0 1 0 1 RGAIN1 0 0 1 1 ALC 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 25. ALC Default RGAIN0 GAIN STEP 0 1 step 0.375dB Default 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 26. ALC REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H -53.25 02H -53.625 01H -54.0 00H MUTE Table 27. ALC MS0404-J-00 2005/08 - 36 - ASAHI KASEI 3. [AK5701] ALC Table 28ALC Register Name Comment LMTH ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data as ZTM1-0 bits Maximum gain at recovery operation WTM1-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Data 01 0 00 Data 01 0 10 fs=44.1kHz Operation -4.1dBFS Enable 11.6ms 00 16ms 10 11.6ms E1H +30dB E1H +30dB 91H 0dB 91H 0dB 1 step 1 step Enable 00 00 1 1 step 1 step Enable Gain of IVOL Limiter ATT step Recovery GAIN step ALC enable fs=8kHz Operation -4.1dBFS Enable 16ms 00 00 1 Table 28. ALC ALCALC(ALC bit = "0"PMADL = PMADR bits = "0") LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = -4.1dBFS Manual Mode WR (IVL/R7-0) ALC bit = "1" * The value of IVOL should be (1) Addr=18H&19H, Data=91H the same or smaller than REF's WR (ZTM1-0, WTM1-0) (2) Addr=1AH, Data=00H WR (REF7-0) (3) Addr=1BH, Data=E1H WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= "1") (4) Addr=1CH, Data=81H ALC Operation Note : WR : Write Figure 39. ALC MS0404-J-00 2005/08 - 37 - ASAHI KASEI [AK5701] () ALC bit = "0" 1. 2. 3. ALC(ZTM1-0, LMTH) ALC IVL7-0, IVR7-0 bit(Table 29)L/R ZTM1-0 bit PMADL = PMADR bits = "0"IVL7-0, IVR7-0 bitsPMADL bit = "1" or PMADR bit = "1"ADCIVOL IVL7-0 GAIN (dB) Step IVR7-0 F1H +36.0 F0H +35.625 EFH +35.25 : : 92H +0.375 0.375dB 91H 0.0 Default 90H -0.375 : : 03H -53.25 02H -53.625 01H -54 00H MUTE Table 29. MS0404-J-00 2005/08 - 38 - ASAHI KASEI [AK5701] IVL7-0, IVR7-0 bit ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) Disable E1(+30dB) --> F1(+36dB) (1) E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 40. ALCIVOL (1) ALCIVLIVRIVLALC bit = "1" IVL7-0 bitsALC (WTM1-0 bits) + (ZTM1-0 bits) (2) ALCIVL, IVR(18H, 19H)ALCDisable ALCEnable ALC bit = "0"ALC bit = "1" PDN pin "L" AK5701 PMADL=PMADR bits = "0"PMADL bitPMADR bit "0" "1"ADC HPF1-0 bits = "00"3088/fs=70.0ms@fs=44.1kHz (Table 30)ADC2's "0" ADC HPF1 bit HPF0 bit 0 0 3088/fs 0 1 1552/fs 1 0 784/fs 1 1 Cycle Init Cycle fs=44.1kHz fs=22.05kHz 70.0ms 140.0ms () 70.4ms 35.2ms () 17.8ms 35.6ms N/A N/A N/A Table 30. ADC MS0404-J-00 fs=11.025kHz 280.1ms Default 140.8ms 71.1ms () N/A 2005/08 - 39 - ASAHI KASEI [AK5701] 3I/F(CSN, CCLK, CDTI)CSP pinCSN pinChip address 1) CSP pin = "L" I/FChip address (2bits, "10"), Read/Write (1bit, "1"), Register address (MSB first, 5bits) Control Data (MSB first, 8bits)CCLK "" "" CSN ""16CCLK ""CCLK 7MHz (max)PDN pin = "L" CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1" C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data Figure 41. (CSP pin = "L") 2) CSP pin = "H" I/FChip address (2bits, "01"), Read/Write (1bit, "1"), Register address (MSB first, 5bits) Control Data (MSB first, 8bits)CCLK "" "" CSN ""16CCLK ""CCLK 7MHz (max)PDN pin = "L" CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "0" "1" "1" C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = "0", C0 = "1"); Fixed to "01" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data Figure 42. (CSP pin = "H") MS0404-J-00 2005/08 - 40 - ASAHI KASEI [AK5701] Addr 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH Register Name Power Management PLL Control Signal Select Mic Gain Control Audio Format Select fs Select Clock Output Select Volume Control Lch Input Volume Control Rch Input Volume Control Timer Select ALC Mode Control 1 ALC Mode Control 2 Mode Control 1 Mode Control 2 D7 0 0 0 0 0 HPF1 0 0 IVL7 IVR7 0 REF7 ALC TE3 0 D6 0 0 0 0 0 HPF0 0 0 IVL6 IVR6 0 REF6 ZELMN TE2 0 D5 0 PLL3 0 0 1 BCKO1 0 0 IVL5 IVR5 0 REF5 LMAT1 TE1 0 D4 0 PLL2 PMMP 0 MIX BCKO0 0 0 IVL4 IVR4 0 REF4 LMAT0 TE0 0 D3 0 PLL1 MDIF2 0 MSBS FS3 THR 0 IVL3 IVR3 ZTM1 REF3 RGAIN1 0 0 D2 PMVCM PLL0 MDIF1 0 BCKP FS2 MCKO 0 IVL2 IVR2 ZTM0 REF2 RGAIN0 0 0 D1 PMADR M/S INR D0 PMADL PMPLL INL MGAIN1 MGAIN0 DIF1 FS1 PS1 0 IVL1 IVR1 WTM1 REF1 LMTH1 0 DIF0 FS0 PS0 IVOLC IVL0 IVR0 WTM0 REF0 LMTH0 0 0 TMASTER Note 29. PDN pin "L" Note 30. "0" "1" "1" "0" 10H-1EH MS0404-J-00 2005/08 - 41 - ASAHI KASEI [AK5701] Addr 10H Register Name Power Management Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 PMVCM 0 D1 PMADR 0 D0 PMADL 0 PMADL: MIC-Amp Lch, ADC Lch 0: Power down (Default) 1: Power up PMADR: MIC-Amp Rch, ADC Rch 0: Power down (Default) 1: Power up PMADLPMADR bit "0" "1"(3088/fs=70.0ms@fs= 44.1kHz, HPF1-0 bits = "00")ADC PMVCM: VCOM 0: Power down (Default) 1: Power up PMVCM bit"1"PMVCM bit "0"PMADL, PMADR, PMPLL, PMMP, MCKO bits"0" ON/OFF ("1"/"0") PDN pin"L" PMVCM, PMADL, PMADR, PMPLL, MCKO bits"0" 20A(typ) (typ. 1A)PDN pin = "L" ADCADC Addr 11H Register Name PLL Control Default D7 0 0 D6 0 0 D5 PLL3 1 D4 PLL2 0 D3 PLL1 0 D2 PLL0 1 D1 M/S 0 D0 PMPLL 0 PMPLL: PLL 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up M/S: Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PLL3-0: PLL(See Table 4) Default: "1001"(MCKI pin=12MHz) MS0404-J-00 2005/08 - 42 - ASAHI KASEI Addr 12H Register Name Signal Select Default [AK5701] D7 0 0 D6 0 0 D5 0 0 D4 PMMP 0 D3 MDIF2 0 D2 MDIF1 0 D1 INR 0 D0 INL 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 D0 MGAIN1 MGAIN0 0 1 D4 MIX 0 D3 MSBS 0 D1 DIF1 1 D0 DIF0 1 INL: ADC Lch 0: LIN1 pin (Default) 1: LIN2 pin INR: ADC Rch 0: RIN1 pin (Default) 1: RIN2 pin MDIF1: ADC Lch 0: (LIN1/LIN2 pin: Default) 1: (LIN+/LIN- pin) MDIF2: ADC Rch 0: (RIN1/RIN2 pin: Default) 1: (RIN+/RIN- pin) PMMP: MPWR pin 0: Power down: Hi-Z (Default) 1: Power up Addr 13H Register Name Mic Gain Control Default D7 0 0 D6 0 0 MGAIN1-0: (See Table 20) Default: "01"(+15dB) Addr 14H Register Name Audio Format Select Default D7 0 0 D6 0 0 D5 1 1 D2 BCKP 0 DIF1-0: (See Table 15) Default: "11" (I2S) BCKP: DSP ModeBCLK/EXBCLK (See Table 16) "0": ""SDTO(Default) "1": ""SDTO MSBS: DSP ModeLRCK/EXLRCK (See Table 16) "0": LRCK/EXLRCK ""BCLK/EXBCLK (Default) "1": LRCK/EXLRCK ""BCLK/EXBCLK 1 MIX: ADC(see Table 17) "0": Normal operation (Default) "1": (L+R)/2 MS0404-J-00 2005/08 - 43 - ASAHI KASEI Addr 15H Register Name fs Select Default [AK5701] D7 HPF1 0 D6 HPF0 0 D5 BCKO1 0 D4 BCKO0 1 D3 FS3 1 D2 FS2 1 D1 FS1 1 D0 FS0 1 FS3-0: (See Table 5 and Table 6)MCKI(See Table 11) Default: "1111" (44.1kHz) PLLEXTMCKI BCKO1-0: BCLK (See Table 10) Default: "01" (32fs) HPF1-0: HPFADC(Table 18, Table 30) Default: "00" (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs) Addr 16H Register Name Clock Output Select Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 THR 0 D2 MCKO 0 D1 PS1 0 D0 PS0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 IVOLC 1 PS1-0: MCKO(Table 9) Default: "00"(256fs) MCKO: MCKO 0: Disable: MCKO pin = "L" (Default) 1: Enable: Output frequency is selected by PS1-0 bits. THR: (Table 14) 0: OFF (Default) 1: ON Addr 17H Register Name Volume Control Default D7 0 0 D6 0 0 IVOLC: IVOL 0: Independent 1: Dependent (Default) IVOLC bit = "1"IVL7-0 bitIVOLIVR7-0 bitIVL7-0 bit Addr 18H 19H Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 0 D5 IVL5 IVR5 0 D4 IVL4 IVR4 1 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: ; 0.375dB step, 242 Level (Table 29) Default: "91H" (0dB) MS0404-J-00 2005/08 - 44 - ASAHI KASEI Addr 1AH Register Name Timer Select Default [AK5701] D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 ZTM1 0 D2 ZTM0 0 D1 WTM1 0 D0 WTM0 0 WTM1-0: ALC(see Table 25) Default: "00" (128/fs) ALC ZTM1-0: ALC(see Table 24) Default: "00" (128/fs) ALC Addr 1BH Register Name ALC Mode Control 1 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 D1 REF1 0 D0 REF0 1 D1 LMTH1 0 D0 LMTH0 0 REF7-0: ALC0.375dB step, 242 Level (Table 27) Default: "E1H" (+30.0dB) Addr 1CH Register Name ALC Mode Control 2 Default D7 ALC 0 D6 ZELMN 0 D5 LMAT1 0 D4 LMAT0 0 D3 D2 RGAIN1 RGAIN0 0 0 LMTH1-0: ALC/(see Table 22) Default: "00" RGAIN1-0: ALC(see Table 26) Default: "00" LMAT1-0: ALCATT(see Table 23) Default: "00" ZELMN: ALC 0: Enable (Default) 1: Disable ALC: ALC 0: ALC Disable (Default) 1: ALC Enable MS0404-J-00 2005/08 - 45 - ASAHI KASEI Addr 1DH Register Name Mode Control 1 Default [AK5701] D7 TE3 1 D6 TE2 0 D5 TE1 1 D4 TE0 0 D3 0 0 D2 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 D1 D0 0 0 TE3-0: EXT Master Mode Enable "0101"1EH EXT Master Mode "1010" "1010", "0101" Default: "1010" Addr 1EH Register Name Mode Control 2 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 TMASTER 0 TMASTER: EXT Master Mode TE3-0 bits = "0101" 0: Except EXT Master Mode (Default) 1: EXT Master Mode MS0404-J-00 2005/08 - 46 - ASAHI KASEI [AK5701] Figure 43Figure 44(AKD5701) 17 16 15 14 CSN CCLK CDTI MCKI 21 LIN2 AK5701VN 22 RIN1 Top View MCKO 10 BCLK DSP 10u 0.1u 10u 0.1u 2.2u Power Supply 2.4 3.6V 6 7 DVSS LRCK DVDD 24 VCOC 5 8 4 SDTO AVDD 23 LIN1 3 9 Rp Cp 11 CSP 0.1u 0.1 x Cp (Note) EXSDTI AVSS 1u 20 RIN2 2 1u Internal MIC EXLRCK 12 VCOM 1u DSP 19 MPWR 1 1u External MIC EXBCLK 13 18 2.2k 2.2k 2.2k 2.2k PDN P Power Supply 1.6 3.6V Analog Ground Digital Ground Note: - AK5701AVSS, DVSS - - EXT(PMPLL bit = "0") VCOC pin - PLL(PMPLL bit = "1") CpRpTable 4Cp+Rp0.1 x Cp - 100msAC1F Figure 43. () MS0404-J-00 2005/08 - 47 - ASAHI KASEI [AK5701] 17 16 15 14 CSN CCLK CDTI MCKI 20 RIN2 EXSDTI 21 LIN2 AK5701VN 22 RIN1 Top View 11 MCKO 10 DVSS BCLK 6 DSP 10u 0.1u 2.2u Power Supply 2.4 3.6V 10u 0.1u DVDD 7 5 LRCK 4 24 VCOC AVDD 8 3 SDTO AVSS 23 LIN1 2 9 VCOM CSP Rp Cp EXBCLK 13 18 EXLRCK 12 0.1u 0.1 x Cp (Note) DSP 19 MPWR 1 Line In PDN P Power Supply 1.6 3.6V Analog Ground Digital Ground Note: - AK5701AVSS, DVSS - - EXT(PMPLL bit = "0") VCOC pin - PLL(PMPLL bit = "1") CpRpTable 4Cp+Rp0.1 x Cp Figure 44. () MS0404-J-00 2005/08 - 48 - ASAHI KASEI [AK5701] 1. AVDD, DVDD AVDD, DVDD AVSS, DVSS PC 2. AVDD pinAVDDAVSS0.1F VCOM 2.2F0.1FAVSS VCOM pin VCOM pin 3. 60k (typ)@MGAIN1-0 bits = "00", 30k (typ)@MGAIN1-0 bits = "01" or "10"(0.5 x AVDD)0.6 x AVDD Vpp(typ)@MGAIN 1-0 bits = "00"DC fc=1/(2RC)2's(2) DC(ADCDC)HPF(fc=3.4Hz@HPF1-0 bits = "00", fs=44.1kHz) AK5701AVSSAVDD MS0404-J-00 2005/08 - 49 - ASAHI KASEI [AK5701] ADCPower-up 1. PLL Example: Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (1) Power Supply & PDN pin = "L" AE "H" (4) MCKO bit (Addr:16H, D2) (2)Addr:11H, Data:12H Addr:14H, Data:23H Addr:15H, Data:2FH PMPLL bit (Addr:11H, D0) (5) MCKI pin Input (3)Addr:10H, Data:04H M/S bit (Addr:11H, D1) 40msec(max) (6) BCLK pin LRCK pin Output (4)Addr:16H, Data:04H Addr:11H, Data:13H Output MCKO, BCLK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 45. Clock Set Up Sequence (1) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits (2a) M/S bit = "1" , PLL3-0, FS3-0, BCKO1-0 (2b) DIF1-0 (3) VCOM: PMVCM bit = "0" AE "1" VCOM (4) MCKO: MCKO bit = "1" MCKO: MCKO bit = "0" (5) PMPLL bit = "0" AE "1"MCKI pinPLL PLLMCKI=12MHz40ms(max)(Table 4) (6) PLLBCLK, LRCK (7) MCKO bit = "1"MCKO pin (8) MCKO bit = "1"PLLMCKO pin MS0404-J-00 2005/08 - 50 - ASAHI KASEI [AK5701] 2. PLL(EXLRCK or EXBCLK pin) Example: Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz Power Supply (1) PDN pin (2) 4fs (1)ofPower Supply & PDN pin = "L" AE "H" (3) PMVCM bit (Addr:10H, D2) (2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Input (3) Addr:10H, Data:04H (4) Internal Clock (5) (4) Addr:11H, Data:0DH Figure 46. Clock Set Up Sequence (2) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) DIF1-0, FS3-0, PLL3-0 bits (3) VCOM: PMVCM bit = "0" AE "1" VCOM (4) PMPLL bit = "0" AE "1"PLL(EXLRCK or EXBCLK pin)PLL PLLEXLRCKPLL160ms(max), EXBCLKPLLVCOC pin10k+4.7nF2ms(max)(Table 4) (5) PLL MS0404-J-00 2005/08 - 51 - ASAHI KASEI [AK5701] 3. PLL(MCKI pin) Example: Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) Power Supply & PDN pin = "L" AE "H" (1) PDN pin (2) (2)Addr:11H, Data:10H Addr:14H, Data:23H Addr:15H, Data:2FH (3) PMVCM bit (Addr:10H, D2) (4) MCKO bit (Addr:16H, D2) (3)Addr:10H, Data:04H PMPLL bit (Addr:11H, D0) (5) MCKI pin (4)Addr:16H, Data:04H Addr:11H, Data:11H Input 40msec(max) (6) MCKO pin MCKO output start Output (7) (8) EXBCLK pin EXLRCK pin Input EXBCLK and EXLRCK input start Figure 47. Clock Set Up Sequence (3) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits (3) VCOM PMVCM bit = "0" AE "1" VCOM (4) MCKO : MCKO bit = "1" (5) PMPLL bit = "0" AE "1"MCKI pinPLL PLLMCKI=12MHz40ms(max)(Table 4) (6) PLLMCKO pin (7) MCKO pin (8) MCKOEXBCLK, EXLRCK MS0404-J-00 2005/08 - 52 - ASAHI KASEI [AK5701] 4. () Example: Audio I/F Format: I2S Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable (1) Power Supply & PDN pin = "L" AE "H" Power Supply (1) PDN pin (2) (2) Addr:11H, Data:00H Addr:14H, Data:23H Addr:15H, Data:2FH (3) PMVCM bit (Addr:10H, D2) (4) MCKI pin Input (3) Addr:10H, Data:04H (4) EXLRCK pin EXBCLK pin Input MCKI, EXBCLK and EXLRCK input Figure 48. Clock Set Up Sequence (4) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) DIF1-0, FS1-0 bits (3) VCOM PMVCM bit = "0" AE "1" VCOM (4) MCKI, EXLRCK, EXBCLK MS0404-J-00 2005/08 - 53 - ASAHI KASEI [AK5701] 5. () Power Supply (1) Example: PDN pin (2) Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select: 256fs Sampling Frequency: 44.1kHz (3) PMVCM bit (Addr:10H, D2) MCKI pin (1) Power Supply & PDN pin = "L" AE "H" Input M/S bit (Addr:11H, D1) TE3-0 bits (Addr:1DH, D7-4) "1010" (2)Addr:11H, Data:26H Addr:14H, Data:23H Addr:15H, Data:2FH Addr:1DH, Data:50H Addr:1EH, Data:02H BCLK and LRCK output "0101" TMASTER bit (Addr:1EH, D1) BCLK pin LRCK pin Output (3)Addr:10H, Data:04H Figure 49. Clock Set Up Sequence (5) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0, TMASTER bits (2a) M/S bit = "1", FS3-0, BCKO1-0 (2b) DIF1-0 (2c) TE3-0 bits = "0101" (2d) TMASTER bit = "1": BCLK, LRCK (3) VCOM PMVCM bit = "0" AE "1" VCOM EXT Master ModePDN pin = "L" AE "H"TE3-0 bits = "1010"Table 1 MS0404-J-00 2005/08 - 54 - ASAHI KASEI [AK5701] 6. & Example: Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz Power Supply (1) 4fs (1)ofPower Supply & PDN pin = "L" AE "H" PDN pin (2) (3) PMVCM bit (2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH Addr:16H, Data:08H (Addr:10H, D2) PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Input (3) Addr:10H, Data:04H (4) Internal Clock (5) (4) Addr:11H, Data:0DH Figure 50. Clock Set Up Sequence (6) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) THR bit = "1"DIF1-0, FS3-0, PLL3-0 bits (3) VCOM: PMVCM bit = "0" AE "1" VCOM (4) PMPLL bit = "0" AE "1"PLL(EXLRCK or EXBCLK pin)PLL PLLEXLRCKPLL160ms(max), EXBCLKPLLVCOC pin10k+4.7nF2ms(max)(Table 4) (5) PLL MS0404-J-00 2005/08 - 55 - ASAHI KASEI [AK5701] 7. Power Supply (1) (1) Power Supply & PDN pin = "L" AE "H" PDN pin (2) THR bit (2) Addr:16H, Data:08H (Addr:16H, D3) EXLRCK pin EXBCLK pin EXSDTI pin (3) Input MCKI, EXBCLK and EXLRCK input Figure 51. Clock Set Up Sequence (7) <> (1) PDN pin "L" AE "H" AK5701150ns "L" (2) THR bit = "1" (3) EXLRCK, EXBCLK, EXSDTILRCK, BCLK, SDTO MS0404-J-00 2005/08 - 56 - ASAHI KASEI [AK5701] () Example: PLL Master Mode Audio I/F Format:I2S Sampling Frequency:44.1kHz Pre MIC AMP:+15dB MIC Power On ALC setting:Refer to Figrure 37 ALC bit = "1" (1) Addr:15H, Data:2FH FS3-0 bits (Addr:15H, D3-0) X,XXX 1111 (2) Addr:12H, Data:10H Addr:13H, Data:01H (1) MIC Control (Addr:12H, D4 & Addr:13H, D1-0) Timer Control (Addr:1AH) ALC Control 1 (Addr:1BH) ALC Control 2 (Addr:1CH) 0, 01 1, 01 (3) Addr:1AH, Data:0AH (2) XXH 0AH (4) Addr:1BH, Data:E1H (3) XXH E1H (5) Addr:1CH, Data:81H (4) XXH 81H 01H ALC State (6) Addr:10H, Data:07H (8) (5) ALC Disable ALC Enable ALC Disable Recording PMADL/R bit (Addr:10H, D1-0) 3088 / fs (7) Addr:10H, Data:01H (7) (6) ADC Internal State Power Down Initialize Normal State Power Down (8) Addr:1CH, Data:01H Figure 52. MIC Input Recording Sequence <> fs=44.1kHzALCALC "Figure 39. ALC " (1) (FS3-0 bits)PLL PLL(6)ADC (2) ( 72H&73H) (3) ALC Timer ( 7AH) (4) ALC REF( 7BH) (5) LMTH1-0, RGAIN1-0, LMAT1-0, ALC bits( 7CH) (6) ADC : PMADL = PMADR bits = "0" "1" ADC3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = "00" ALC(IVL/R7-0 bits)(0dB) 100msPMVCM=PMMP bits = "1"2msPMPLL bit = "1" 6msPMADL=PMADR bits = "1" (7) ADC: PMADL = PMADR bits = "1" "0" ADCALCDisable ALC(ALC bit = "0") ADC (PMADL = PMADR bits = "0")PMADL = PMADR bits = "0" (IVL/R7-0 bits) (8) ALC Disable: ALC bit = "1" "0" MS0404-J-00 2005/08 - 57 - ASAHI KASEI [AK5701] ADC 1. PLL Example: (1) Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 44.1kHz PMPLL bit (Addr:11H, D0) M/S bit (Addr:11H, D1) (1) Addr:11H, Data:10H (2) MCKO bit "H" or "L" (2) Addr:16H, Data:00H (Addr:16H, D2) (3) External MCKI Input (3) Stop an external MCKI Figure 53. Clock Stopping Sequence (1) <> (1) PLL: PMPLL=M/S bits = "1" "0" (2) MCKO: MCKO bit = "1" "0" (3) 2. PLL(EXLRCK, EXBCLK pin) Example Audio I/F Format : I2S PLL Reference clock: EXBCLK BCLK frequency: 64fs Sampling Frequency: 44.1kHz (1) PMPLL bit (Addr:11H, D0) (2) EXBCLK Input (1) Addr:11H, Data:0CH (2) EXLRCK Input (2) Stop the external clocks Figure 54. Clock Stopping Sequence (2) <> (1) PLL: PMPLL bit = "1" "0" (2) * & MS0404-J-00 2005/08 - 58 - ASAHI KASEI [AK5701] 3. PLL(MCKI pin) Example Audio I/F Format: I2S PLL Reference clock: MCKI=11.2896MHz EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz (1) PMPLL bit (1) Addr:11H, Data:10H (Addr:11H, D0) (2) MCKO bit (2) Addr:16H, Data:00H (Addr:16H, D2) (3) External MCKI Input (3) Stop the external clocks Figure 55. Clock Stopping Sequence (3) <> (1) PLL: PMPLL bit = "1" "0" (2) MCKO: MCKO bit = "1" "0" (3) 4. () (1) External MCKI Input Example (1) EXBCLK Input EXLRCK Input Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz (1) (1) Stop the external clocks Figure 56. Clock Stopping Sequence (4) <> (1) * 5. () (1) External MCKI Input Example BCLK Output "H" or "L" LRCK Output "H" or "L" Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz (1) Stop MCKI Figure 57. Clock Stopping Sequence (5) <> (1) MCKIBCLKLRCK "H" "L" MS0404-J-00 2005/08 - 59 - ASAHI KASEI [AK5701] PMVCM bit = "0"20A(typ) (typ. 1A)PDN pin = "L" MS0404-J-00 2005/08 - 60 - ASAHI KASEI [AK5701] 24pin QFN (Unit: mm) 4.0 0.1 2.4 0.15 13 18 19 2.4 0.15 4.0 0.1 12 A Exposed Pad 24 7 0.40 0.1 6 1 B 0.5 0.2 0.08 0.10 M PIN #1 ID (0.35 x 45 ) 0.75 0.05 0.23 0.05 : (Exposed Pad) : : : MS0404-J-00 2005/08 - 61 - ASAHI KASEI [AK5701] 5701 XXXX 1 XXXX : Date code identifier (4) Date (YY/MM/DD) 05/08/04 Revision 00 Reason Page Contents * * *() * * * MS0404-J-00 2005/08 - 62 -