W632GG6KB
16M 8 BANKS 16 BIT DDR3 SDRAM
Publication Release Date: Dec. 03, 2015
Revision: A06
- 1 -
Table of Contents-
1. GENERAL DESCRIPTION ................................................................................................................... 5
2. FEATURES ........................................................................................................................................... 5
3. ORDER INFORMATION ....................................................................................................................... 6
4. KEY PARAMETERS ............................................................................................................................. 7
5. BALL CONFIGURATION ...................................................................................................................... 8
6. BALL DESCRIPTION ............................................................................................................................ 9
7. BLOCK DIAGRAM .............................................................................................................................. 11
8. FUNCTIONAL DESCRIPTION ............................................................................................................ 12
8.1 Basic Functionality .............................................................................................................................. 12
8.2 RESET and Initialization Procedure .................................................................................................... 12
8.2.1 Power-up Initialization Sequence ..................................................................................... 12
8.2.2 Reset Initialization with Stable Power .............................................................................. 14
8.3 Programming the Mode Registers ....................................................................................................... 15
8.3.1 Mode Register MR0 ......................................................................................................... 17
8.3.1.1 Burst Length, Type and Order ................................................................................ 18
8.3.1.2 CAS Latency ........................................................................................................... 18
8.3.1.3 Test Mode............................................................................................................... 19
8.3.1.4 DLL Reset............................................................................................................... 19
8.3.1.5 Write Recovery ....................................................................................................... 19
8.3.1.6 Precharge PD DLL ................................................................................................. 19
8.3.2 Mode Register MR1 ......................................................................................................... 20
8.3.2.1 DLL Enable/Disable ................................................................................................ 20
8.3.2.2 Output Driver Impedance Control ........................................................................... 21
8.3.2.3 ODT RTT Values .................................................................................................... 21
8.3.2.4 Additive Latency (AL) ............................................................................................. 21
8.3.2.5 Write leveling .......................................................................................................... 21
8.3.2.6 Output Disable ........................................................................................................ 21
8.3.3 Mode Register MR2 ......................................................................................................... 22
8.3.3.1 Partial Array Self Refresh (PASR) .......................................................................... 23
8.3.3.2 CAS Write Latency (CWL) ...................................................................................... 23
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 23
8.3.3.4 Dynamic ODT (Rtt_WR) ......................................................................................... 23
8.3.4 Mode Register MR3 ......................................................................................................... 24
8.3.4.1 Multi Purpose Register (MPR) ................................................................................ 24
8.4 No OPeration (NOP) Command .......................................................................................................... 25
8.5 Deselect Command ............................................................................................................................. 25
8.6 DLL-off Mode ...................................................................................................................................... 25
8.7 DLL on/off switching procedure ........................................................................................................... 26
8.7.1 DLL “on” to DLL “off” Procedure .......................................................................... 26
8.7.2 DLL “off” to DLL “on” Procedure .......................................................................... 27
8.8 Input clock frequency change.............................................................................................................. 28
8.8.1 Frequency change during Self-Refresh ............................................................................ 28
8.8.2 Frequency change during Precharge Power-down .......................................................... 28
8.9 Write Leveling ..................................................................................................................................... 30
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 2 -
8.9.1 DRAM setting for write leveling & DRAM termination function in that mode .................... 31
8.9.2 Write Leveling Procedure ................................................................................................. 31
8.9.3 Write Leveling Mode Exit ................................................................................................. 33
8.10 Multi Purpose Register ........................................................................................................................ 34
8.10.1 MPR Functional Description ............................................................................................. 35
8.10.2 MPR Register Address Definition ..................................................................................... 36
8.10.3 Relevant Timing Parameters ............................................................................................ 36
8.10.4 Protocol Example ............................................................................................................. 36
8.11 ACTIVE Command .............................................................................................................................. 42
8.12 PRECHARGE Command .................................................................................................................... 42
8.13 READ Operation ................................................................................................................................. 43
8.13.1 READ Burst Operation ..................................................................................................... 43
8.13.2 READ Timing Definitions .................................................................................................. 44
8.13.2.1 READ Timing; Clock to Data Strobe relationship .................................................... 45
8.13.2.2 READ Timing; Data Strobe to Data relationship ..................................................... 46
8.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 47
8.13.2.4 tRPRE Calculation .................................................................................................. 48
8.13.2.5 tRPST Calculation .................................................................................................. 48
8.13.2.6 Burst Read Operation followed by a Precharge ...................................................... 54
8.14 WRITE Operation ................................................................................................................................ 56
8.14.1 DDR3 Burst Operation ..................................................................................................... 56
8.14.2 WRITE Timing Violations ................................................................................................. 56
8.14.2.1 Motivation ............................................................................................................... 56
8.14.2.2 Data Setup and Hold Violations .............................................................................. 56
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations ..................................................... 56
8.14.2.4 Write Timing Parameters ........................................................................................ 56
8.14.3 Write Data Mask ............................................................................................................... 57
8.14.4 tWPRE Calculation ........................................................................................................... 58
8.14.5 tWPST Calculation ........................................................................................................... 58
8.15 Refresh Command .............................................................................................................................. 65
8.16 Self-Refresh Operation ....................................................................................................................... 67
8.17 Power-Down Modes ............................................................................................................................ 69
8.17.1 Power-Down Entry and Exit ............................................................................................. 69
8.17.2 Power-Down clarifications - Case 1 ................................................................................. 75
8.17.3 Power-Down clarifications - Case 2 ................................................................................. 75
8.17.4 Power-Down clarifications - Case 3 ................................................................................. 76
8.18 ZQ Calibration Commands .................................................................................................................. 77
8.18.1 ZQ Calibration Description ............................................................................................... 77
8.18.2 ZQ Calibration Timing ...................................................................................................... 78
8.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 78
8.19 On-Die Termination (ODT) .................................................................................................................. 79
8.19.1 ODT Mode Register and ODT Truth Table ...................................................................... 79
8.19.2 Synchronous ODT Mode .................................................................................................. 80
8.19.2.1 ODT Latency and Posted ODT ............................................................................... 80
8.19.2.2 Timing Parameters ................................................................................................. 80
8.19.2.3 ODT during Reads .................................................................................................. 82
8.19.3 Dynamic ODT .................................................................................................................. 83
8.19.3.1 Functional Description: ........................................................................................... 83
8.19.3.2 ODT Timing Diagrams ............................................................................................ 84
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 3 -
8.19.4 Asynchronous ODT Mode ................................................................................................ 88
8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions .......................................... 89
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 89
8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit ..... 92
8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods 93
9. OPERATION MODE ........................................................................................................................... 94
9.1 Command Truth Table ........................................................................................................................ 94
9.2 CKE Truth Table ................................................................................................................................. 96
9.3 Simplified State Diagram ..................................................................................................................... 97
10. ELECTRICAL CHARACTERISTICS ................................................................................................... 98
10.1 Absolute Maximum Ratings ................................................................................................................ 98
10.2 Operating Temperature Condition ....................................................................................................... 98
10.3 DC & AC Operating Conditions ........................................................................................................... 98
10.3.1 Recommended DC Operating Conditions ........................................................................ 98
10.4 Input and Output Leakage Currents .................................................................................................... 99
10.5 Interface Test Conditions .................................................................................................................... 99
10.6 DC and AC Input Measurement Levels ............................................................................................. 100
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals .................. 100
10.6.2 DC and AC Input Levels for Single-Ended Data Signals ................................................ 101
10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ........... 103
10.6.4 Single-ended requirements for differential signals ......................................................... 104
10.6.5 Differential Input Cross Point Voltage ............................................................................ 105
10.6.6 Slew Rate Definitions for Single-Ended Input Signals .................................................... 106
10.6.7 Slew Rate Definitions for Differential Input Signals ........................................................ 106
10.7 DC and AC Output Measurement Levels .......................................................................................... 107
10.7.1 Output Slew Rate Definition and Requirements ............................................................. 107
10.7.1.1 Single Ended Output Slew Rate ........................................................................... 108
10.7.1.2 Differential Output Slew Rate ............................................................................... 109
10.8 34 ohm Output Driver DC Electrical Characteristics .......................................................................... 110
10.8.1 Output Driver Temperature and Voltage sensitivity ........................................................ 112
10.9 On-Die Termination (ODT) Levels and Characteristics ..................................................................... 113
10.9.1 ODT Levels and I-V Characteristics ............................................................................... 113
10.9.2 ODT DC Electrical Characteristics ................................................................................. 114
10.9.3 ODT Temperature and Voltage sensitivity ..................................................................... 114
10.9.4 Design guide lines for RTTPU and RTTPD ....................................................................... 115
10.10 ODT Timing Definitions ............................................................................................................ 116
10.10.1 Test Load for ODT Timings ............................................................................................ 116
10.10.2 ODT Timing Definitions .................................................................................................. 116
10.11 Input/Output Capacitance ........................................................................................................ 120
10.12 Overshoot and Undershoot Specifications ............................................................................... 121
10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins: ....................... 121
10.12.2 AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins: ......... 121
10.13 IDD and IDDQ Specification Parameters and Test Conditions ................................................ 122
10.13.1 IDD and IDDQ Measurement Conditions ....................................................................... 122
10.13.2 IDD Current Specifications ............................................................................................. 132
10.14 Clock Specification .................................................................................................................. 133
10.15 Speed Bins .............................................................................................................................. 134
10.15.1 DDR3-1333 Speed Bin and Operating Conditions ......................................................... 134
10.15.2 DDR3-1600 Speed Bin and Operating Conditions ......................................................... 135
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 4 -
10.15.3 DDR3-1866 Speed Bin and Operating Conditions ......................................................... 136
10.15.4 Speed Bin General Notes .............................................................................................. 137
10.16 AC Characteristics ................................................................................................................... 138
10.16.1 AC Timing and Operating Condition for -11 speed grade .............................................. 138
10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades........................... 142
10.16.3 Timing Parameter Notes ................................................................................................ 146
10.16.4 Address / Command Setup, Hold and Derating ............................................................. 149
10.16.5 Data Setup, Hold and Slew Rate Derating ..................................................................... 156
11. PACKAGE SPECIFICATION ............................................................................................................ 158
12. REVISION HISTORY ........................................................................................................................ 159
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 5 -
1. GENERAL DESCRIPTION
The W632GG6KB is a 2G bits DDR3 SDRAM, organized as 16,777,216 words 8 banks 16 bits.
This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W632GG6KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I speed
grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is
guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I speed grades are compliant to the
DDR3-1333 (9-9-9) specification (the 15I industrial grade which is guaranteed to support -40°C ≤
TCASE ≤ 95°C).
The W632GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 6 -
System level timing calibration support via write leveling and MPR read pattern
ZQ Calibration for output driver and ODT using external reference resistor to ground
Asynchronous RESET# pin for Power-up initialization sequence and reset function
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during
writes
2K Byte page size
Interface: SSTL_15
Packaged in WBGA 96 Ball (9x13 mm2), using lead free materials with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W632GG6KB-11
DDR3-1866 (13-13-13)
0°C ≤ TCASE ≤ 95°C
W632GG6KB-12
DDR3-1600 (11-11-11)
0°C ≤ TCASE ≤ 95°C
W632GG6KB12I
DDR3-1600 (11-11-11)
-40°C ≤ TCASE ≤ 95°C
W632GG6KB-15
DDR3-1333 (9-9-9)
0°C ≤ TCASE ≤ 95°C
W632GG6KB15I
DDR3-1333 (9-9-9)
-40°C ≤ TCASE ≤ 95°C
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 7 -
4. KEY PARAMETERS
Speed Bin
DDR3-1866
DDR3-1600
DDR3-1333
Unit
CL-nRCD-nRP
13-13-13
11-11-11
9-9-9
Part Number Extension
-11
-12/12I
-15/15I
Sym.
Min.
Max.
Min.
Max.
Min.
Max.
fCKMAX
933
800
667
MHz
tAA
13.91
20
13.75
(13.125) *5
20
13.5
(13.125) *5
20
nS
tRCD
13.91
13.75
(13.125) *5
13.5
(13.125) *5
nS
tRP
13.91
13.75
(13.125) *5
13.5
(13.125) *5
nS
tRC
47.91
48.75
(48.125) *5
49.5
(49.125) *5
nS
tRAS
34
9 * tREFI
35
9 * tREFI
36
9 * tREFI
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
2.5
3.3
2.5
3.3
nS
CL = 7
CWL = 6
tCK(AVG)
Reserved
1.875
< 2.5
1.875
< 2.5
nS
CL = 8
CWL = 6
tCK(AVG)
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
nS
CL = 9
CWL = 7
tCK(AVG)
Reserved
1.5
< 1.875
1.5
< 1.875
nS
CL = 10
CWL = 7
tCK(AVG)
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
nS
CL = 11
CWL = 8
tCK(AVG)
Reserved
1.25
< 1.5
Reserved
nS
CL = 13
CWL = 9
tCK(AVG)
1.07
< 1.25
Reserved
Reserved
nS
Sup_CL
6, 8, 10, 13
6, (7), 8, (9), 10, 11
6, (7), 8, 9, 10
nCK
Sup_CWL
5, 6, 7, 9
5, 6, 7, 8
5, 6, 7
nCK
Average periodic
refresh Interval
-40°C ≤ TCASE ≤ 85°C
tREFI
*2
7.8 *2, 3
7.8 *2, 3
μS
0°C ≤ TCASE ≤ 85°C
7.8 *1
7.8 *1
7.8 *1
μS
85°C < TCASE ≤ 95°C
3.9 *4
3.9 *4
3.9 *4
μS
IDD0
115
105
100
mA
IDD1
140
130
125
mA
IDD4R
280
250
235
mA
IDD4W
250
220
200
mA
IDD5B
155
150
145
mA
IDD6
19
19
19
mA
IDD7
400
380
370
mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤ TCASE < 0°C is not available.
3. 12I and 15I speed grades support -40°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings
must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)
should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11)
devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for
tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21,
23) also should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333
(9-9-9) and 48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 8 -
5. BALL CONFIGURATION
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
DQU4
M
N
DQSU#
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK#
A10/AP
NC
A12/BC# BA1
VREFCA
ZQ
VDD
VSS
DQL5
VSS
DQL3
VSSQ
VSSQ
DQU2
DQU6
VDDQ VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
DQU7
VSS
DQU1
DMU
DQL0
DQSL
DQSL#
DQL4
RAS#
CAS#
WE#
BA2
A0
A3
BA0
CS#
VDD
VSS
VDDQ
DQL6
DQL2
VSSQ
VDDQ
DQU3
VDD
DQU5
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
P
R
T
A1
A11
NC A8
A6
A4 VSS
VDD
VSS
VSS
VDD
VSS RESET#
A7
A5 A2
A9
A13
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 9 -
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
TYPE
DESCRIPTION
J7, K7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
K9
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates,
internal clock signals and device input buffers and output drivers.
Taking CKE Low provides Precharge Power Down and Self-Refresh
operation (all banks idle), or Active Power Down (row Active in any
bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and
VREFDQ have become stable during the power on and initialization
sequence, they must be maintained during all operations (including
Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are
disabled during power down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
L2
CS#
Input
Chip Select: All commands are masked when CS# is registered HIGH.
CS# provides for external Rank selection on systems with multiple
Ranks. CS# is considered part of the command code.
K1
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR3 SDRAM. When enabled, ODT is
applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU, and DML
signal. The ODT signal will be ignored if Mode Registers MR1 and
MR2 are programmed to disable ODT and during Self Refresh.
J3, K3, L3
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
D3, E7
DMU, DML
Input
Input Data Mask: DMU and DML are the input mask signals control the
lower or upper bytes for write data. Input data is masked when
DMU/DML is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS.
M2, N8, M3
BA0−BA2
Input
Bank Address Inputs: BA0−BA2 define to which bank an Active, Read,
Write, or Precharge command is being applied. Bank address also
determines which mode register is to be accessed during a MRS
cycle.
N3, P7, P3, N2, P8,
P2, R8, R2, T8, R3,
L7, R7, N7, T3
A0−A13
Input
Address Inputs: Provide the row address for Active commands and the
column address for Read/Write commands to select one location out
of the memory array in the respective bank. (A10/AP and A12/BC#
have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set command.
Row address: A0−A13.
Column address: A0−A9.
L7
A10/AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to
determine whether Auto-precharge should be performed to the
accessed bank after the Read/Write operation.
(HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled
during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by bank addresses.
N7
A12/BC#
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See section 9.1
“Command Truth Table” on page 94 for details.
T2
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is
LOW, and inactive when RESET# is HIGH. RESET# must be HIGH
during normal operation. RESET# is a CMOS rai to rail signal with DC
high and low at 80% and 20% of VDD, RESET# active is destructive to
data contents.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 10 -
E3, F7, F2, F8, H3,
H8, G2, H7
DQL0−DQL7
Input/Output
Data Input/Output: Lower byte of Bi-directional data bus.
D7, C3, C8, C2, A7,
A2, B8, A3
DQU0−DQU7
Input/Output
Data Input/Output: Upper byte of Bi-directional data bus.
F3, G3
DQSL, DQSL#
Input/Output
Lower byte data Strobe: Data Strobe output with read data, input with
write data of DQL[7:0]. Edge-aligned with read data, centered in write
data. DQSL is paired with DQSL# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
C7, B7
DQSU, DQSU#
Input/Output
Upper byte data Strobe: Data Strobe output with read data, input with
write data of DQU[7:0]. Edge-aligned with read data, centered in write
data. DQSU is paired with DQSU# to provide differential pair signaling
to the system during read and write data transfer. DDR3 SDRAM
supports differential data strobe only and does not support single-
ended.
B2, D9, G7, K2, K8,
N1, N9, R1, R9
VDD
Supply
Power Supply: 1.5V ± 0.075V.
A9, B3, E1, G8, J2,
J8, M1, M9, P1, P9,
T1, T9
VSS
Supply
Ground.
A1, A8, C1, C9, D2,
E9, F1, H2, H9
VDDQ
Supply
DQ Power Supply: 1.5V ± 0.075V.
B1, B9, D1, D8, E2,
E8, F9, G1, G9
VSSQ
Supply
DQ Ground.
H1
VREFDQ
Supply
Reference voltage for DQ.
M8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
L8
ZQ
Supply
External reference ball for output drive and On-Die Termination
Impedance calibration: This ball needs an external 240 Ω ± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
J1, J9, L1, L9, M7,
T7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.
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7. BLOCK DIAGRAM
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
SENSE
AMPLIFIER
DATA CONTROL CIRCUIT
DM MASK LOGIC
DQ
BUFFER
COLUMN
DECODER
SENSE
AMPLIFIER
NOTE: The cell array configuration is 16384 * 1024 * 16
ROW DECODER
ROW DECODERROW DECODER
A0
A9
A11
A12
A13
CS#
RAS#
CAS#
WE#
CK, CK#
PREFETCH REGISTER
ODT
CONTROL
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
COLUMN
DECODER
SENSE
AMPLIFIER
COLUMN
DECODER
CELL ARRAY
BANK #5
ROW DECODER ROW DECODER
ROW DECODERROW DECODER
ODT
CELL ARRAY
BANK #7
CELL ARRAY
BANK #4
CELL ARRAY
BANK #6
CELL ARRAY
BANK #3
CELL ARRAY
BANK #2
CELL ARRAY
BANK #1
ZQ CAL
ZQCL, ZQCS
RZQ
VSSQ
ZQ
To ODT/output drivers
BA2
BA1
BA0
COLUMN
DECODER
SENSE
AMPLIFIER
ROW DECODER
CELL ARRAY
BANK #0
DLL
CK, CK#
WRITE
drivers
READ
drivers
DQL0−DQL7
LDQS, LDQS#
DQU0−DQU7
LDQS, LDQS#
DQL0−DQL7
LDQS, LDQS#
DQU0−DQU7
UDQS, UDQS#
LDM, UDM
LDM, UDM
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8. FUNCTIONAL DESCRIPTION
8.1 Basic Functionality
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an
eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists
of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-
bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write
command. The address bits registered coincident with the Active command are used to select the
bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The address bits
registered coincident with the Read or Write command are used to select the starting column location
for the burst operation, determine if the auto precharge command is to be issued (via A10), and select
BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined
manner. The following sections provide detailed information covering device reset and initialization,
register definition, command descriptions, and device operation.
8.2 RESET and Initialization Procedure
8.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 * VDD; all other inputs may be
undefined). RESET# needs to be maintained for minimum 200 µS with stable power. CKE is pulled
“Low” anytime before RESET# being de-asserted (min. time 10 nS). The power voltage ramp time
between 300 mV to VDD min. must be no greater than 200 mS; and during the ramp, VDD ≥ VDDQ
and (VDD - VDDQ) < 0.3 Volts.
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
In addition, VTT is limited to 0.95 V max once power ramp is finished, AND
VREF tracks VDDQ/2.
OR
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & VREF.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 µS until CKE becomes active. During this time,
the DRAM will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 tCK (which is larger)
before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to
clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time
to clock) before CKE goes active. Once the CKE is registered “High” after Reset, CKE needs to be
continuously registered “High” until the initialization sequence is finished, including expiration of
tDLLK and tZQinit.
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4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is
asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET#
deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS
before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be
statically held at either LOW or HIGH. If Rtt_Nom is to be enabled in MR1, the ODT input signal
must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the
first MRS command to load mode register. (tXPR=max (tXS ; 5 * tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2,
provide “Low” to BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3,
provide “Low” to BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL
Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to BA1-BA2).
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL
reset command, provide “High” to A8 and “Low” to BA0-2).
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
TIME BREAK DON'T CARE
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, CK#
VDD, VDDQ
RESET#
Command
BA
ODT
RTT
tCKSRX
T = 200 µs T = 500 µs
tDLLK
VALID
VALID
VALID
VALIDStatic LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
*1ZQCLMRS*1 MRSMRSMRS
MR2 MR3 MR1 MR0
tIS
tIS
tIS
tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
Tmin
CKE
10 ns
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 1 – Reset and Initialization Sequence at Power-on Ramping
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8.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be
undefined). RESET needs to be maintained for minimum 100 nS. CKE is pulled “LOW” before
RESET being de-asserted (min. time 10 nS).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
TIME BREAK DON'T CARE
Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK, CK#
VDD, VDDQ
RESET#
Command
BA
ODT
RTT
tCKSRX
T = 100 ns T = 500 µs
tDLLK
VALID
VALID
VALID
VALIDStatic LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
*1ZQCLMRS*1 MRSMRSMRS
MR2 MR3 MR1 MR0
tIS
tIS
tIS
tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
Tmin = 10 ns
CKE
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 2 – Reset Procedure at Power Stable Condition
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8.3 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode
Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed
via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not
defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after
power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by
re-executing the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after
power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the
mode register and is the minimum time required between two MRS commands shown in Figure 3.
TIME BREAK DON'T CARE
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2
CK#
CK
Command
ODT
CKE
VALID
Address
VALID
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALID
VALID VALID VALIDNOP/DESNOP/DESMRSNOP/DESNOP/DESMRS
VALID
ODT
Settings
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALIDVALID VALID
Old settings Updating Settings New Settings
tMRD tMOD
ODTLoff+1
Rtt_Nom DISABLED prior and/or after MRS command
Rtt_Nom ENABLED prior and/or after MRS command
Figure 3 – tMRD Timing
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The MRS command to Non-MRS command delay, tMOD is required for the DRAM to update the
features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS
command excluding NOP and DES shown in Figure 4.
TIME BREAK DON'T CARE
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2
CK#
CK
Command
ODT
CKE
VALID
Address
VALID
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALID
VALID VALID VALIDNOP/DESNOP/DESNOP/DESNOP/DESNOP/DESMRS
VALID
ODT
Settings
VALID VALID
VALID VALID VALID VALID VALID VALID VALID VALID VALIDVALID VALID
Old settings Updating Settings New Settings
tMOD
Rtt_Nom ENABLED prior and/or after MRS command
Rtt_Nom DISABLED prior and/or after MRS command
ODTLoff+1
Figure 4 – tMOD Timing
The mode register contents can be changed using the same command and timing requirements
during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state
with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register.
If the Rtt_Nom Feature is enabled in the Mode Register prior and/or after a MRS command, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state prior to the MRS
command. The ODT signal may be registered high after tMOD has expired. If the Rtt_Nom feature is
disabled in the Mode Register prior and after a MRS command, the ODT signal can be registered
either LOW or HIGH before, during and after the MRS command. The mode registers are divided into
various fields depending on the functionality and/or modes.
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8.3.1 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It
controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for
precharge Power Down, which include various vendor specific options to make DDR3 SDRAM useful
for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#,
BA0, BA1 and BA2, while controlling the states of address pins according to the Figure 5 below.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0*1 PPD WR DLL RBT
CL BLTM
0
1No
Yes
0 0
0 1
1 0
1 1
MR0
MR1
MR2
MR3
1
0 Slow exit (DLL off)
Fast exit (DLL on)
Burst Length
Address Field
Mode Register 0
Write recovery for Auto precharge CAS Latency
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
Reserved
7
8
9
11
10
Reserved
6
0
00
18 (Fixed)
BC4 or 8 (on the fly)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
16*2
5*2
6*2
7*2
8*2
10*2
14*2
12*2
0
1Normal
Test 0
1
Nibble Sequential
Interleave
0
0
A13
CL
0
0
0
0
1
1
1
1
1
10
1BC4 (Fixed)
Reserved
BA2
0*1
0
1
00
0
11
1
1Reserved
Reserved
13
0
0
0
0
10
11
1Reserved
Reserved
1
0
0
1
11
1
01
1
1Reserved
Reserved
Reserved
1
1
1
BA0
BA1 MRS mode
A8 DLL Reset
A12 DLL Control for Precharge PD
A9 WR(cycles)
A10
A11
A7 Mode A3 Read Burst Type
A6 A5 A2
A4 Latency
BL
A0
A1
Notes:
1. BA2 and A13 are reserved for future use and must be programmed to “0” during MRS.
2. WR (write recovery for Auto precharge)min in clock cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[nS] / tCK(avg)[nS]). The WR value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported CAS Latency, please refer to “Speed
Bins” tables for each frequency.
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 5 – MR0 Definition
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8.3.1.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type
is selected via bit A3 as shown in Figure 5. The ordering of accesses within a burst is determined by
the burst length, burst type, and the starting column address as shown in Table 1. The burst length is
defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8 and ‘on the fly’ which allows
BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#.
Table 1 – Burst Type and Burst Order
Burst
Length
READ/
WRITE
Starting Column Address
(A2, A1, A0)
Burst type = Sequential
(decimal)
A3 = 0
Burst type = Interleaved
(decimal)
A3 = 1
NOTES
4
Chop
READ
0 0 0
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3
0 0 1
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3
0 1 0
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3
0 1 1
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1, 2, 3
1 0 0
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1, 2, 3
1 0 1
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3
1 1 0
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3
1 1 1
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3
WRITE
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1, 2, 4, 5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5
8
READ
0 0 0
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
0 0 1
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
0 1 0
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
0 1 1
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
1 0 0
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
1 0 1
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
1 1 0
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
1 1 1
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being
selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation.
This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don't Care.
8.3.1.2 CAS Latency
The CAS Latency is defined by MR0 (bits A2, A4, A5 and A6) as shown in Figure 5. CAS Latency is
the delay, in clock cycles, between the internal Read command and the availability of the first bit of
output data. DDR3 SDRAM does not support any half-clock latencies. The overall Read Latency (RL)
is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. For more information on the
supported CL and AL settings based on the operating clock frequency, refer to section 10.15 “Speed
Bins” on page 134. For detailed Read operation refer to section 8.13 “READ Operation” on page 43.
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8.3.1.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values
shown in Figure 5. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only
used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified
if A7 = 1.
8.3.1.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL
can be used (i.e., Read commands or ODT synchronous operations).
8.3.1.5 Write Recovery
The programmed WR value MR0 (bits A9, A10 and A11) is used for the auto precharge feature along
with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by
dividing tWR (in nS) by tCK(avg) (in nS) and rounding up to the next integer: WRmin[cycles] =
Roundup(tWR[nS]/tCK(avg)[nS]). The WR must be programmed to be equal to or larger than tWR(min).
8.3.1.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power down mode. When MR0 (A12
= 0), or ‘slow-exit’, the DLL is frozen after entering precharge power down (for potential power savings)
and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or
‘fast-exit’, the DLL is maintained after entering precharge power down and upon exiting power down
requires tXP to be met prior to the next valid command.
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8.3.2 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength,
Rtt_Nom impedance, additive latency, Write leveling enable and Qoff. The Mode Register 1 is written
by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling
the states of address pins according to the Figure 6 below.
BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10*1Rtt_Nom BTRtt_Nom
Address Field
Mode Register 1
0 0
0
0
1
1
1 1
MR0
MR1
MR2
MR3
WRAL
Qoff 0*10*1Rtt_Nom D.I.C DLL
0
A0
1
Enable
Disable
Rtt_Nom disabled
RZQ/6
RZQ/12*4
RZQ/4
RZQ/2
1
0 0 0
0 0
0
1
10 0
1
0
1
0
1
0 Output buffer enabled
Output buffer disabled*2
1
0
Enabled
Disabled
BA0 A13
0D.I.C
Level
0*1
0
0
1
1
0
1
0
1
0 (AL disabled)
Reserved
CL-1
CL-2
Reserved
Reserved
RZQ/8*4
1 1 1
1
0
0
1
1
1
A5
0
0
1
1
A1
0
1
0
1
RZQ/6
Reserved
RZQ/7
Reserved
Note: RZQ = 240 ohms Note: RZQ = 240 ohms
BA2
0*1
Output Driver
Impedance Control
A9 A6 A2 Rtt_Nom*3
BA1 BA0 MR Select
A7 Write leveling enable
A12 Qoff*2
DLL Enable
A4 A3 Additive Latency
Notes:
1. BA2, A8, A10, A11 and A13 are reserved for future use and must be programmed to “0” during MRS.
2. Outputs disabled - DQs, DQSs, DQS#s.
3. In Write leveling Mode (MR1 A[7] = 1) with MR1 A[12]=1, all Rtt_Nom settings are allowed; in Write Leveling Mode (MR1 A[7]
= 1) with MR1 A[12]=0, only Rtt_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
4. If Rtt_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Figure 6 – MR1 Definition
8.3.2.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization,
and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on)
with MR1 (A0 = 0), the DLL is automatically disabled when entering Self Refresh operation and is
automatically re-enabled upon exit of Self Refresh operation. Any time the DLL is enabled and
subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK,
CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation,
except when Rtt_WR is enabled and the DLL is required for proper ODT operation. For more detailed
information on DLL Disable operation refer to section 8.6 “DLL-off Mode” on page 25.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
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The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set
Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally.
8.3.2.2 Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as
shown in Figure 6.
8.3.2.3 ODT RTT Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The
nominal termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be
programmed in MR2 to enable a unique RTT value when ODT is enabled during writes. The Rtt_WR
value can be applied during writes even when Rtt_Nom is disabled.
8.3.2.4 Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command
(either with or without auto-precharge) to be issued immediately after the active command. The
command is held for the time of the Additive Latency (AL) before it is issued inside the device. The
Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write
Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A
summary of the AL register options are shown in Table 2.
Table 2 – Additive Latency (AL) Settings
A4
A3
AL
0
0
0 (AL Disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
Note:
AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.
8.3.2.5 Write leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has the benefit of reducing the number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate
for skew. See section 8.9 “Write Leveling” on page 30 for more details.
8.3.2.6 Output Disable
The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 6. When
this feature is enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the
device, thus removing any loading of the output drivers. This feature may be useful when measuring
module power, for example. For normal operation, A12 should be set to ‘0’.
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8.3.3 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance,
and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#,
high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the
Figure 7 below.
BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Rtt_WR ASR
Address Field
Mode Register 2
BA1 BA0
0 0
0
0
1
1
1 1
MR0
MR1
MR2
MR3
5 (tCK(avg) ≥ 2.5nS)
8 (1.5nS > tCK(avg) ≥ 1.25nS)
9 (1.25nS > tCK(avg) ≥ 1.07nS)
6 (2.5nS > tCK(avg) ≥ 1.875nS)
7 (1.875nS > tCK(avg) ≥ 1.5nS)
A5 A4 A3
1
0 0 0
0 0
0
1
10 0
1
0
1
0
A7
1
0Normal operating temperature range
Extended operating temperature range
ASR enable
Manual SR Reference (SRT)
BA0 A13
100*1
Reserved
Reserved
Reserved
1 1 1
1
0
0
1
1
1
A10
0
0
1
1
A9
0
1
0
1
Dynamic ODT off
(Write does not affect Rtt value)
Reserved
RZQ/4
RZQ/2
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
1
0
Full array
1/8th Array (BA[2:0]=000)
3/4 Array (BA[2:0]=010,011,100,101,110 & 111)
1/8th Array (BA[2:0]=111)
Quarter Array (BA[2:0]=110 & 111)
Half Array (BA[2:0]=000,001,010 & 011)
Quarter Array (BA[2:0]=000 & 001)
Half Array (BA[2:0]=100,101,110 & 111)
0*1SRT CWL PASR
BA2
0*1
MR Select
A6
1
0
Auto Self Refresh (ASR)
Self Refresh Temperature (SRT) Range
Rtt_WR*2
Partial Array Self Refresh for 8 Banks
CAS write Latency (CWL)
Notes:
1. BA2, A8, A11~A13 are reserved for future use and must be programmed to “0” during MRS.
2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not
available. Figure 7 – MR2 Definition
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8.3.3.1 Partial Array Self Refresh (PASR)
If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified
address range shown in Figure 7 will be lost if Self Refresh is entered. Data integrity will be
maintained if tREFI conditions are met and no Self Refresh command is issued.
8.3.3.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 7. CAS Write Latency is
the delay, in clock cycles, between the internal Write command and the availability of the first bit of
input data.
DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as
Additive Latency (AL) + CAS Write Latency (CWL); WL = AL + CWL. For more information on the
supported CWL and AL settings based on the operating clock frequency, refer to section 10.15
“Speed Bins” on page 134. For detailed Write operation refer to section 8.14 “WRITE Operation” on
page 56.
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT)
DDR3 SDRAM must support Self Refresh operation at all supported temperatures. Applications
requiring Self Refresh operation in the Extended Temperature Range must use the ASR function or
program the SRT bit appropriately.
When ASR enabled, DDR3 SDRAM automatically provides Self Refresh power management functions
for all supported operating temperature values. If not enabled, the SRT bit must be programmed to
indicate TOPER during subsequent Self Refresh operation.
ASR = 0, Self Refresh rate is determined by SRT bit A7 in MR2.
ASR = 1, Self Refresh rate is determined by on-die thermal sensor. SRT bit A7 in MR2 is don't care.
8.3.3.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further
enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3
SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10
configure the Dynamic ODT settings. In Write leveling mode, only Rtt_Nom is available. For details on
Dynamic ODT operation, refer to section 8.19.3 “Dynamic ODT” on page 83.
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8.3.4 Mode Register MR3
The Mode Register MR3 controls Multi purpose registers. The Mode Register 3 is written by asserting
low on CS#, RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of
address pins according to the Figure 8 below.
BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
Mode Register 3
BA1 BA0
MR Select
0 0
0
0
1
1
1 1
MR0
MR1
MR2
MR3
Dataflow from MPR
Normal operation*3
BA0 A13
11MPR Loc
MPR
0*1
MPR Operation A1 A0
0 0
0
0
1
1
1 1
Predefined pattern*2
RFU
RFU
RFU
MPR Address
BA2
0*1
A2
0
1
MPR
MR Select MPR location
Notes:
1. BA2, A3~A13 are reserved for future use and must be programmed to “0” during MRS.
2. The predefined pattern will be used for read synchronization.
3. When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
Figure 8 – MR3 Definition
8.3.4.1 Multi Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration
bit sequence. To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3
Register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA
commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit
A2 = 0). Power Down mode, Self Refresh, and any other non-RD/RDA command is not allowed during
MPR enable mode. The RESET function is supported during MPR enable mode. For detailed MPR
operation refer to section 8.10 “Multi Purpose Register” on page 34.
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8.4 No OPeration (NOP) Command
The No OPeration (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP
(CS# LOW and RAS#, CAS#, and WE# HIGH). This prevents unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected.
8.5 Deselect Command
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR3
SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected.
8.6 DLL-off Mode
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent
operations until A0 bit is set back to “0”. The MR1 A0 bit for DLL control can be switched either during
initialization or later. Refer to section 8.8 “Input clock frequency change” on page 28.
The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock
frequency for DLL-off Mode is specified by the parameter tCK(DLL_OFF). There is no minimum
frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS
Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of
both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK), but not the Data
Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller
time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after
the Read command, the DLL-off mode tDQSCK starts (AL+CL - 1) cycles after the read command.
Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK)
and the difference between tDQSCK min and tDQSCK max is significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation is shown in the following Timing Diagram
(CL=6, BL=8):
TRANSITIONING DATA
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command READ
Address
NOP NOP NOP NOPNOPNOPNOPNOPNOPNOP
Bank
Col b
DON'T CARE
DQS,DQS# (DLL_on)
DQ (DLL_on)
DQS,DQS# (DLL_off)
DQ (DLL_off)
DQS,DQS# (DLL_off)
DQ (DLL_off)
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
RL (DLL_off) = AL + ( CL – 1 ) = 5 tDQSCK(DLL_off)_min
tDQSCK(DLL_on)_max
Dout
bDout
b+1 Dout
b+2 Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6 Dout
b+7
Dout
bDout
b+1 Dout
b+2 Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6 Dout
b+7
Dout
bDout
b+1 Dout
b+2 Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6 Dout
b+7
Note:
The tDQSCK is used here for DQS, DQS# and DQ to have a simplified diagram;
the DLL_off shift will affect both timings in the same way and the skew between
all DQ, and DQS, DQS# signals will still be tDQSQ.
Figure 9 – DLL-off mode READ Timing Operation
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8.7 DLL on/off switching procedure
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent
operations until A0 bit is set back to “0”.
8.7.1 DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh, as
outlined in the following procedure:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled, and DRAMs On-die Termination
resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL.)
2. Set MR1 bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) is satisfied.
5. Change frequency, in guidance with section 8.8 “Input clock frequency change” on page 28.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all
tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled
in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be
registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features
were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be
registered LOW or HIGH.
8. Wait tXS, then set Mode Registers with appropriate values (especially an update of CL, CWL and
WR may be necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, then DRAM is ready for next command.
TIME BREAK DON'T CARE
T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0
CK#
CK
CKE
Command SRE*3 NOP SRX*6 NOP MRS*7 NOP VALID*8
ODT
MRS*2 NOP
VALID*8
*1 tMOD tCKSRE *4 tXS tMOD
tCKESR
VALID8
ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High
Notes:
1. Starting with Idle state, RTT in Hi-Z state
2. Disable DLL by setting MR1 Bit A0 to 1
3. Enter SR
4. Change Frequency
5. Clock must be stable tCKSRX
6. Exit SR
7. Update Mode register with DLL off parameters setting
8. Any valid command
tCKSRX*5
Figure 10 – DLL Switch Sequence from DLL-on to DLL-off
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8.7.2 DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination
resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.)
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with section 8.8 “Input clock frequency change” on page 28.
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until
tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features
were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must
continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is
satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and
WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL
command may also be issued during or after tDLLK.)
9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset
before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a
ZQCL command was issued.
TIME BREAK DON'T CARE
T0 Ta0 Ta1 Tb0 Tc0 Td0 Te0 Tf1 Tg0 Th0
CK#
CK
CKE
Command NOP SRX*5 MRS*6 MRS*7 MRS*8 VALID*9
ODT
NOP SRE*2
VALID
*1 tCKSRE tCKSRX*4 tMRD tMRD
tCKESR
ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High
Notes:
1. Starting with idle state
2. Enter SR
3. Change Frequency
4. Clock must be stable tCKSRX
5. Exit SR
6. Set DLL on by MR1 A0 = 0
7. Update Mode registers
8. Any valid command
Tc1
tDLLK
tXS
*3ODTLoff + 1 x tCK
Figure 11 – DLL Switch Sequence from DLL Off to DLL On
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8.8 Input clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during
almost all states of normal operation. This means that, once the clock frequency has been set and is
to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by
the clock jitter and SSC (spread spectrum clocking) specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate
under two conditions: (1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these
two modes, it is illegal to change the clock frequency.
8.8.1 Frequency change during Self-Refresh
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode
and tCKSRE has been satisfied, the state of the clock becomes a don't care. Once a don't care,
changing the clock frequency is permissible, provided the new clock frequency is stable prior to
tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock
frequency, the Self-Refresh entry and exit specifications must still be met as outlined in see section
8.16 “Self-Refresh Operation” on page 67.
The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change below the
minimum operating frequency would require the use of DLL_on mode -> DLL_off mode transition
sequence; refer to section 8.7 “DLL on/off switching procedure” on page 26.
8.8.2 Frequency change during Precharge Power-down
The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit
mode or slow exit mode). If the Rtt_Nom feature was enabled in the mode register prior to entering
Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is
in an off state. If the Rtt_Nom feature was disabled in the mode register prior to entering Precharge
power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or
HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency
may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum
and maximum operating frequency specified for the particular speed grade. During the input clock
frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency
is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down
may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET
via MRS. Depending on the new clock frequency, additional MRS commands may need to be issued
to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock
period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is
ready to operate with new clock frequency. This process is depicted in Figure 12 on page 29.
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TIME BREAK DON'T CARE
T0 T1 T2 Ta0 Tb0 Tc1 Td0 Td1 Te0 Te1
CK#
CK
CKE
Command NOP NOP NOP MRS NOP VALID
ODT
NOP NOP
Tc0
DLL Reset VALID
Address
DQS, DQS#
DQ
DM
tCH tCL
tCK
tIH tIS
tCKSRE
tCKE
tCPDED
tIH
tIS
tCKb
tCHbtCLb
tCKb
tCHbtCLb
tCKb
tCHbtCLb
tXP tIH tIS
High-Z
High-Z
tAOFPD / tAOF
tDLLK
Exit PRECHARGE
Power-Down Mode
Frequency
Change
Enter PRECHARGE
Power-Down Mode
Previous clock frequency New clock frequency
tCKSRX
Notes:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements.
3. If the Rtt_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 9. If the Rtt_Nom feature was disabled in
the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case.
Figure 12 – Change Frequency during Precharge Power-down
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8.9 Write Leveling
For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate
for skew.
The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to
adjust the DQS - DQS# to CK - CK# relationship. The memory controller involved in the leveling must
have adjustable delay setting on DQS - DQS# to align the rising edge of DQS - DQS# with that of the
clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK#, sampled with the rising
edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays DQS - DQS# until a
transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would
ensure tDQSS specification.
Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to
combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS -
DQS# signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH
may have to be better than the absolute limits provided in section 10.16 “AC Characteristics” in
order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is shown in Figure 13.
CK#
CK
T0 T1 T2 T3 T4 T6 T7T5
T0 T1 T2 T3 T4 T6T5
Tn
CK#
CK
Diff_DQS
Diff_DQS
Diff_DQS
DQ
DQ
0 or 1 0 0 0
0 or 1 1 1 1
Source
Destination
Push DQS to capture 0-1
transition
Figure 13 – Write Leveling Concept
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on
ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM
configurations x4, x8 and x16. On a x16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The upper data
bits should provide the feedback of the upper Diff_DQS(Diff_UDQS) to clock relationship whereas the
lower data bits would indicate the lower Diff_DQS(Diff_LDQS) to clock relationship.
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8.9.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ‘High’ and after finishing leveling, DRAM exits
from write leveling mode if A7 in MR1 set ‘Low’ (Table 3). Note that in write leveling mode, only
DQS/DQS# terminations are activated and deactivated via ODT pin, unlike normal operation (Table 4).
Table 3 – MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
Table 4 – DRAM termination function in the leveling mode
ODT pin @DRAM
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
Asserted
On
Off
Note:
In Write Leveling Mode with its output buffer disabled (MR1 A[7] = 1 with MR1 A[12] = 1) all Rtt_Nom settings are allowed; in
Write Leveling Mode with its output buffer enabled (MR1 A[7] = 1 with MR1 A[12] = 0) only Rtt_Nom settings of RZQ/2, RZQ/4
and RZQ/6 are allowed.
8.9.2 Write Leveling Procedure
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When
entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode,
only NOP or DESELECT commands are allowed, as well as an MRS command to change Qoff bit
(MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling mode,
the MRS command performing the exit (MR1[A7]=0) may also change MR1 bits of A12, A9, A6-A5,
and A2-A1. Since the controller levels one rank at a time, the output of other ranks must be disabled
by setting MR1 bit A12 to 1. The Controller may assert ODT after tMOD, at which time the DRAM is
ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM
has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a
single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller.
tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ
bits asynchronously after tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling
feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure.
There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is
defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming DQ and
decides to increment or decrement DQS - DQS# delay setting and launches the next DQS/DQS#
pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the
controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 14
describes the timing diagram and parameters for the overall Write Leveling procedure.
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TIME BREAK DON'T CARE
CK#*5
ODT
Command
Diff_DQS*4
Prime DQ*1
One Prime DQ:
Late Remaining DQs
Early Remaining DQs
Late Prime DQs*1
Early Prime DQs*1
All DQs are Prime:
MRS*2 NOP*3 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
tMOD
tWLDQSEN
tWLMRD
tWLMRD
tDQSL*6 tDQSH*6 tDQSL*6 tDQSH*6
tWLO
tWLO
tWLOE
tWLO
tWLO tWLOE
tWLO
tWLOE
tWLO
tWLO
tWLO
T1
tWLS
tWLH
T2
tWLS
tWLH
UNDEFINED DRIVING MODE
CK
Notes:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the
remaining DQs must be driven low, as shown in above Figure, and maintained at this state through out the leveling
procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. Diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with
solid line, DQS# is shown with dotted line.
5. CK, CK#: CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the
max pulse width is system dependent.
Figure 14 – Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low at
T1 and CK - CK# high at T2]
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8.9.3 Write Leveling Mode Exit
The following sequence describes how the Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From
now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the
respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and continue registering low. (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be
issued after tMRD (Td1).
TIME BREAK DON'T CARE
CK#
CK
Command NOP NOP NOP NOP NOP NOP NOP MRS NOP VALID NOP VALID
T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1
MR1 VALID VALID
tWLO + tWLOE
result = 1
tAOFmax
tAOFmin
tIS tMOD
TRANSITIONING
Address
ODT
RTT_DQS_DQS#
DQS_DQS#
RTT_DQ
DQ*1
tMRD
ODTLoff
Rtt_Nom
UNDEFINED DRIVING MODE
Note:
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
Figure 15 – Timing details of Write leveling exit
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8.10 Multi Purpose Register
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration
bit sequence. The basic concept of the MPR is shown in Figure 16.
Multipurpose register
Pre-defined data for Reads
MR3 [A2]
DQ, DM, DQS, DQS#
Memory Core
(all banks precharged)
Figure 16 – MPR Block Diagram
To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 Register with bit
A2 = 1, as shown in Table 5. Prior to issuing the MRS command, all banks must be in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command
is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown in Table 6. When the
MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued
with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a
READ command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-
Refresh, and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET
function is supported during MPR enable mode.
Table 5 – MPR Functional Description of MR3 Bits
MR3 A[2]
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
don't care
(0b or 1b)
Normal operation, no MPR transaction
All subsequent Reads will come from DRAM array
All subsequent Write will go to DRAM array
1b
See Table 6
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]
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8.10.1 MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read:
— DQL[0] and DQU[0] drive information from MPR.
— DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.
Addressing during for Multi Purpose Register reads for all MPR agents:
— BA[2:0]: Don't care
— A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
— A[2]: A[2] selects the burst order
For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *)
For Burst Chop 4 cases, the burst order is switched on nibble base
A[2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
— A[9:3]: Don't care
— A10/AP: Don't care
— A12/BC#: Selects burst chop mode on-the-fly, if enabled within MR0
— A11, A13: Don't care
Regular interface functionality during register reads:
— Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
— Support of read burst chop (MRS and on-the-fly via A12/BC#)
— All other address bits (remaining column address bits including A10, all bank address bits) will
be ignored by the DDR3 SDRAM.
— Regular read latencies and AC timings apply.
— DLL must be locked prior to MPR Reads.
Note: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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8.10.2 MPR Register Address Definition
Table 6 provides an overview of the available data locations, how they are addressed by MR3 A[1:0]
during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi
Purpose Register Read.
Table 6 – MPR Readouts and Burst Order Bit Mapping
MR3 A[2]
MR3 A[1:0]
Function
Burst
Length
Read
Address
A[2:0]
Burst Order and Data Pattern
1b
00b
Read Pre-defined Pattern
for System Calibration
BL8
000b
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
1b
01b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
10b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
1b
11b
RFU
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
8.10.3 Relevant Timing Parameters
The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD,
tMOD, and tMPRR. For more details refer to section 10.16 “AC Characteristics” on page 138.
8.10.4 Protocol Example
Protocol Example (This is one example):
Read out pre-determined read-calibration pattern.
Description: Multiple reads from Multi Purpose Register, in order to do system level read timing
calibration based on pre-determined and standardized pattern.
Protocol Steps:
Precharge All.
Wait until tRP is satisfied.
Set MRS, “MR3 A[2] = 1b” and “MR3 A[1:0] = 00b”.
This redirects all subsequent reads and load pre-defined pattern into Multi Purpose Register.
Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the
period MR3 A[2] =1, no data write operation is allowed.
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Read:
A[1:0] = ‘00’b (Data burst order is fixed starting at nibble, always 00b here)
A[2] = ‘0’b (For BL=8, burst order is fixed as 0,1,2,3,4,5,6,7)
A12/BC# = 1 (use regular burst length of 8)
All other address pins (including BA[2:0] and A10/AP): don't care
After RL = AL + CL, DRAM bursts out the pre-defined Read Calibration Pattern.
Memory controller repeats these calibration reads until read data capture at memory controller is
optimized.
After end of last MPR read burst, wait until tMPRR is satisfied.
Set MRS, “MR3 A[2] = 0b” and “MR3 A[1:0] = don't care” to the normal DRAM state.
All subsequent read and write accesses will be regular reads and writes from/to the DRAM array.
Wait until tMRD and tMOD are satisfied.
Continue with “regular” DRAM commands, like activate a memory bank for regular read or write
access,...
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CK#
CK
Command PREA MRS READ*1 NOP NOP NOP NOP NOP NOP NOP NOP MRS
T0 Ta Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
BA
NOP NOP VALID
3 3
0 0*2 VALID
1 0*2 0
00 00
0 0
0 0
0 0
1
A[1:0]
A[2]
A[9:3]
A10/AP
A[11]
A12/BC#
DQS, DQS#
DQ
RL
tRP tMOD
VALID*1
VALID
VALID
VALID
VALID
tMPRR tMOD
Tc8 Tc9 Td
NOTES: 1. RD with BL8 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[2:0]. TIME BREAK DON'T CARE
Figure 17 – MPR Readout of pre-defined pattern, BL8 fixed burst order, single readout
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CK#
CK
Command PREA MRS READ*1 NOP NOP NOP NOP NOP NOP NOP NOP
T0 Ta Tb0 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
BA
NOP MRS VALID
3
0 0*2
1 0*2
00
0
0
0
1
A[1:0]
A[2]
A[9:3]
A10/AP
A[11]
A12/BC#
DQS, DQS#
DQ
RL
VALID*1
VALID
VALID
VALID
VALID
tMPRR
Tc8 Tc9 TdT10
3
VALID
VALID
0
00
VALID
0
VALID
0
VALID
0
VALID*1
RL
0*2
0*2
READ*1
TIME BREAK DON'T CARE
NOTES: 1. RD with BL8 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[2:0].
tMODtCCDtMODtRP
Figure 18 – MPR Readout of pre-defined pattern, BL8 fixed burst order, back-to-back readout
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TIME BREAK DON'T CARE
CK#
CK
Command PREA MRS READ*1 NOP NOP NOP NOP NOP NOP NOP MRS
T0 Ta Tb0 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
BA
NOP NOP VALID
3
0 0*2
1 0*3
00
0
0
0
1
A[1:0]
A[2]
A[9:3]
A10/AP
A[11]
A12/BC#
DQS, DQS#
DQ
RL
VALID*1
VALID
VALID
VALID
VALID
tMPRR tMOD
Tc8 Tc9 TdT10
VALID
VALID
VALID
VALID
VALID*1
RL
0*2
1*4
READ*1
3
VALID
0
00
0
0
0
NOTES: 1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
tCCD
tMOD
tRP
Figure 19 – MPR Readout pre-defined pattern, BC4, lower nibble then upper nibble
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TIME BREAK DON'T CARE
CK#
CK
Command PREA MRS READ*1 NOP NOP NOP NOP NOP NOP NOP MRS
T0 Ta Tb0 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
BA
NOP NOP VALID
3
0 0*2
1 1*4
00
0
0
0
1
A[1:0]
A[2]
A[9:3]
A10/AP
A[11]
A12/BC#
DQS, DQS#
DQ
RL
VALID*1
VALID
VALID
VALID
VALID
tMPRR tMOD
Tc8 Tc9 TdT10
VALID
VALID
VALID
VALID
VALID*1
RL
0*2
0*3
READ*1
3
VALID
0
00
0
0
0
NOTES: 1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
tCCD
tMOD
tRP
Figure 20 – MPR Readout of pre-defined pattern, BC4, upper nibble then lower nibble
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8.11 ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent
access. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0-
A13 selects the row. This row remains active (or open) for accesses until a precharge command is
issued to that bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
8.12 PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after
the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a
READ or WRITE command to a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing parameters. Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However, the precharge
period will be determined by the last PRECHARGE command issued to the bank.
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8.13 READ Operation
8.13.1 READ Burst Operation
During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12
during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
A12 = 1, BL8
A12 is used only for burst length control, not as a column address.
TRANSITIONING DATA
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3READ
Address*4
NOP NOP NOP NOPNOPNOPNOP
Bank
Col n
DON'T CARE
DQS, DQS#
DQ*2
CL = 6
Dout
nDout
n+1
RL = AL + CL
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tRPST
NOPNOPNOP
Notes:
1. BL8, RL = 6, AL = 0, CL = 6.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
Figure 21 – READ Burst Operation RL = 6 (AL = 0, CL = 6, BL8)
TRANSITIONING DATA
T0 T1 T5 T6 T10 T11 T12 T13 T14 T15 T16
CK#
CK
Command*3READ
Address*4
NOP NOP NOP NOPNOPNOPNOP
Bank
Col n
DON'T CARE
DQS, DQS#
DQ*2
CL = 6
Dout
nDout
n+1
RL = AL + CL
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tRPST
NOPNOPNOP
AL = 5
TIME BREAK
Notes:
1. BL8, RL = 11, AL = (CL - 1), CL = 6.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
Figure 22 – READ Burst Operation RL = 11 (AL = 5, CL = 6, BL8)
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8.13.2 READ Timing Definitions
Read timing is shown in Figure 23 and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK#.
tQSH describes the DQS, DQS# differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS, DQS# differential output low time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined.
CK#
CK
DQS#
DQS
tQSH tQSL
tDQSCK
tDQSCK
tDQSCK(min)
tDQSCK(max)
tDQSCK(min)
tDQSCK(max)
Rising Strobe
Region
tQH tQH
tDQSQ
Associated
DQ Pins
tDQSQ
Rising Strobe
Region
Figure 23 – READ Timing Definition
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8.13.2.1 READ Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in Figure 24 and is applied when the DLL is enabled and
locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK#.
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
tLZ(DQS), tHZ(DQS) for preamble/postamble (see section 8.13.2.3 and Figure 26).
CK/CK#
tRPRE
tLZ(DQS)min
tDQSCK(min) tDQSCK(min) tDQSCK(min) tDQSCK(min) tHZ(DQS)min
tQSH tQSL tQSH tQSL tQSH tQSL
tQSH tQSL tQSH tQSL tQSH tQSL
tRPST
tDQSCK(max) tDQSCK(max) tDQSCK(max) tDQSCK(max)
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tLZ(DQS)max
tHZ(DQS)max
DQS, DQS#
Erly Strobe
DQS, DQS#
Late Strobe
tRPRE
RL Measured
to this point
tRPST
Notes:
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe
edge can vary between tDQSCK(min) and tDQSCK(max).
2. Not with standing note 1, a rising strobe edge with tDQSCK(max) at T(n) can not be immediately followed by a rising strobe
edge with tDQSCK(min) at T(n+1). This is because other timing relationships (tQSH, tQSL) exist:
if tDQSCK(n+1) < 0:
tDQSCK(n) < 1.0 tCK - (tQSHmin + tQSLmin) - | tDQSCK(n+1) |
3. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by
tQSL.
4. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCK,min (early strobe case) and tLZ(DQS)max and tHZ(DQS)max
are not tied to tDQSCK,max (late strobe case).
5. The minimum pulse width of read preamble is defined by tRPRE(min).
6. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
7. The minimum pulse width of read postamble is defined by tRPST(min).
8. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
Figure 24 – Clock to Data Strobe Relationship
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8.13.2.2 READ Timing; Data Strobe to Data relationship
The Data Strobe to Data relationship is shown in Figure 25 and is applied when the DLL is enabled
and locked.
Rising data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3READ
Address*4
NOP NOP NOP NOPNOPNOPNOP
Bank
Col n
DQS, DQS#
DQ*2 (Last data valid)
Dout
n
tRPRE
tRPST
NOPNOPNOP
RL = AL + CL
Dout
nDout
n+1 Dout
n+2 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
Dout
n+1 Dout
n+2 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
Dout
n+1 Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tQH
tDQSQ(max) tDQSQ(max)
tQH
DQ*2 (first data no longer valid)
All DQs collectively
TRANSITIONING DATA DON'T CARE
Dout
n
Dout
n+3
Dout
n+3
Notes:
1. BL = 8, RL = 6 (AL = 0, CL = 6).
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL on for locking.
6. tDQSQ defines the skew between DQS, DQS# to Data and does not define DQS, DQS# to Clock.
7. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within
a burst.
Figure 25 – Data Strobe to Data Relationship
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8.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are
referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS)
and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). Figure 26 shows a method to calculate the point when
the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ), by measuring
the signal at two different voltages. The actual voltage measurement points are not critical as long as
the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as
singled ended.
VTT + 2x mV
VTT + x mV
VTT - x mV
VTT - 2x mV T1
T2
tLZ
CK
CK#
tLZ(DQS), tLZ(DQ)
tLZ(DQS): CK – CK# rising crossing at RL - 1
tLZ(DQ): CK – CK# rising crossing at RL
tHZ
CK
CK#
tHZ(DQS), tHZ(DQ) with BL8: CK – CK# rising crossing at RL + 4 nCK
tHZ(DQS), tHZ(DQ) with BC4: CK – CK# rising crossing at RL + 2 nCK
VOH - x mV
VOH - 2x mV
T2
T1
tHZ(DQS), tHZ(DQ)
VOL + 2x mV
VOL + x mV
tHZ(DQS), tHZ(DQ) end point = 2 * T1 - T2tLZ(DQS), tLZ(DQ) begin point = 2 * T1 - T2
Figure 26 – tLZ and tHZ method for calculating transitions and endpoints
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8.13.2.4 tRPRE Calculation
The method for calculating differential pulse widths for tRPRE is shown in Figure 27.
CK
CK#
Single ended signal, provided
as background information
DQS
DQS#
Single ended signal, provided
as background information
DQS - DQS#
Resulting differential signal,
relevant for tRPRE specification
tAtB
tCtD
t2
t1
tRPRE
tRPRE_end
tRPRE_begin
VTT
0
VTT
VTT
Figure 27 – Method for calculating tRPRE transitions and endpoints
8.13.2.5 tRPST Calculation
The method for calculating differential pulse widths for tRPST is shown in Figure 28.
CK
CK#
Single ended signal, provided
as background information
DQS
DQS#
Single ended signal, provided
as background information
DQS - DQS#
Resulting differential signal,
relevant for tRPST specification
VTT
tA
tB
tD
tC
t1
tRPST
tRPST_begin t2
tRPST_end
VTT
VTT
0
Figure 28 – Method for calculating tRPST transitions and endpoints
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPREADNOP
Bank
Col n
DQS, DQS#
DQ*2 RL = 6 Dout
nDout
n+1
RL = 6
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tRPST
NOPNOPNOP
T11 T12 T13 T14
NOP
Bank
Col b
NOP NOP NOP NOP
Dout
bDout
b+1 Dout
b+2 Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6 Dout
b+7
tCCD
TRANSITIONING DATA DON'T CARE
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ commands at T0 and T4.
Figure 29 – READ (BL8) to READ (BL8)
T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPREADNOP
Bank
Col n
DQS, DQS#*5
DQ*2 RL = 6
RL = 6
tRPRE tRPST
NOPNOPNOP
T12 T13 T14 T15
NOP
Bank
Col b
NOP NOP NOP NOP
tCCD = 5
TRANSITIONING DATA DON'T CARE
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0), tCCD = 5.
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ commands at T0 and T5.
5. DQS-DQS# is held logic low at T10.
Dout
nDout
n+1 Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7 Dout
bDout
b+1 Dout
b+2 Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6 Dout
b+7
TIME BREAK
Figure 30 – Nonconsecutive READ (BL8) to READ (BL8), tCCD=5
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPREADNOP
Bank
Col n
DQS, DQS#
DQ*2 RL = 6
Dout
nDout
n+1
RL = 6
tRPRE
Dout
n+2 Dout
n+3
tRPST
NOPNOPNOP
T11 T12 T13 T14
NOP
Bank
Col b
NOP NOP NOP NOP
tRPRE
Dout
bDout
b+1 Dout
b+2 Dout
b+3
tRPST
tCCD
TRANSITIONING DATA DON'T CARE
NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0)
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by either MR0 A[1:0] = 10 or MR0 A[1:0] = 01 and A12 = 0 during READ commands at T0 and T4.
Figure 31 – READ (BC4) to READ (BC4)
T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPNOP
Bank
Col n
DQS, DQS#
DQ*2
RL = 6
Dout
nDout
n+1 WL = 5
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tWPST
NOPNOPWRITE
T12 T13 T14 T15
Bank
Col b
NOP NOP NOP NOP
Din
bDin
b+1 Din
b+2 Din
b+3 Din
b+4 Din
b+5 Din
b+6 Din
b+7
T16
NOPNOPNOP
tRPST tWPRE
4 clocks tWR
tWTR
TRANSITIONING DATA DON'T CARE
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0 and WRITE command at T7.
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
TIME BREAK
Figure 32 – READ (BL8) to WRITE (BL8)
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T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPWRITENOP
DQS, DQS#
DQ*2
RL = 6 Dout
nDout
n+1
WL = 5
tRPRE
Dout
n+2 Dout
n+3
tWPST
NOPNOPNOP
T12 T13 T14 T15
NOP NOP NOP NOP
Din
bDin
b+1 Din
b+2 Din
b+3
T16
NOPNOPNOP
tRPST tWPRE
4 clocks tWR
tWTR
TRANSITIONING DATA DON'T CARE
NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0 and WRITE command at T5.
Bank
Col n Bank
Col b
READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
TIME BREAK
Figure 33 – READ (BC4) to WRITE (BC4) OTF
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPREADNOP
Bank
Col n
DQS, DQS#
DQ*2 RL = 6 Dout
nDout
n+1
RL = 6
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tRPST
NOPNOPNOP
T11 T12 T13 T14
NOP
Bank
Col b
NOP NOP NOP NOP
Dout
bDout
b+1 Dout
b+2 Dout
b+3
tCCD
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 6 (CL = 6, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T4.
Figure 34 – READ (BL8) to READ (BC4) OTF
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RL = 6
Dout
nDout
n+1
RL = 6
tRPRE
Dout
n+2 Dout
n+3
tRPST
tRPRE
Dout
bDout
b+1 Dout
b+2 Dout
b+7
tRPST
Dout
b+3 Dout
b+4 Dout
b+5 Dout
b+6
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPNOPREADNOP
Bank
Col n
DQS, DQS#
DQ*2
NOPNOPNOP
T11 T12 T13 T14
NOP
Bank
Col b
NOP NOP NOP NOP
tCCD
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 6 (CL = 6, AL = 0)
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T4.
Figure 35 – READ (BC4) to READ (BL8) OTF
T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPWRITENOP
DQS, DQS#
DQ*2 RL = 6 Dout
nDout
n+1
WL = 5
tRPRE
Dout
n+2 Dout
n+3
tWPST
NOPNOPNOP
T12 T13 T14 T15
NOP NOP NOP NOP
Din
bDin
b+1 Din
b+6 Din
b+7
T16
NOPNOPNOP
tRPST tWPRE
4 clocks tWR
tWTR
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T5.
Bank
Col n Bank
Col b
Din
b+2 Din
b+3 Din
b+4 Din
b+5
TIME BREAK
READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
Figure 36 – READ (BC4) to WRITE (BL8) OTF
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T0 T1 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Command*3 READ
Address*4
NOP NOP NOPREADNOP
Bank
Col n
DQS, DQS#
DQ*2
RL = 6
Dout
nDout
n+1 WL = 5
tRPRE
Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tWPST
NOPNOPWRITE
T12 T13 T14 T15
Bank
Col b
NOP NOP NOP NOP
Din
bDin
b+1 Din
b+2 Din
b+7
T16
NOPNOPNOP
tRPST tWPRE
4 clocks tWR
tWTR
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T7.
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
TIME BREAK
Figure 37 – READ (BL8) to WRITE (BC4) OTF
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8.13.2.6 Burst Read Operation followed by a Precharge
The minimum external Read command to Precharge command spacing to the same bank is equal to AL + tRTP with tRTP being the Internal Read
Command to Precharge Command Delay. Note that the minimum ACT to PRE timing, tRAS.MIN must be satisfied as well. The minimum value for the
Internal Read Command to Precharge Command Delay is given by tRTP.MIN = max(4 × nCK, 7.5 nS). A new bank active command may be issued to the
same bank if the following two conditions are satisfied simultaneously:
1. The minimum RAS precharge time (tRP.MIN) has been satisfied from the clock at which the precharge begins.
2. The minimum RAS cycle time (tRC.MIN) from the previous bank activation has been satisfied.
Examples of Read commands followed by Precharge are show in Figure 38 and Figure 39.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command NOP
Address
READ NOP ACTPRENOPNOP
Bank a,
Col n
DQS, DQS#
DQ
NOPNOPNOP
T11 T12 T13 T14
NOP
Bank a,
(or all)
NOP NOP NOP NOP
Dout
nDout
n+1 Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
tRTP
Dout
nDout
n+1 Dout
n+2 Dout
n+3
DQS, DQS#
DQ
BL4 Operation:
BL8 Operation:
tRP
RL = AL + CL = 9
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 9 (CL = 9, AL = 0)
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T14).
Bank a,
Row b
T15
NOP
Figure 38 – READ to PRECHARGE (RL = 9, AL = 0, CL = 9, tRTP = 4, tRP = 9)
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T0 T1 T2 T10 T11 T16 T18 T19 T20 T21 T22
CK#
CK
Command NOP
Address
READ NOP ACTPRENOPNOP
Bank a,
Col n
DQS, DQS#
DQ
NOPNOPNOP
T23 T24 T25 T27
NOP
Bank a,
(or all)
NOP NOP NOP NOP
Dout
nDout
n+1 Dout
n+2 Dout
n+3 Dout
n+4 Dout
n+5 Dout
n+6 Dout
n+7
CL = 11
Dout
nDout
n+1 Dout
n+2 Dout
n+3
DQS, DQS#
DQ
BL4 Operation:
BL8 Operation:
tRP
AL = CL - 2 = 9
T26
NOP
tRTP
Bank a,
Row b
TRANSITIONING DATA DON'T CARE
NOTES: 1. RL = 20 (CL = 11, AL = CL - 2)
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T16) and that tRC.MIN is satisfied at the next Active command time (T27). TIME BREAK
RL = 20
Figure 39 – READ to PRECHARGE (RL = 20, AL = CL-2, CL = 11, tRTP = 6, tRP = 11)
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8.14 WRITE Operation
8.14.1 DDR3 Burst Operation
During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12
during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
A12 = 1, BL8
A12 is used only for burst length control, not as a column address.
8.14.2 WRITE Timing Violations
8.14.2.1 Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be
initiated to make sure that the DRAM works properly. However, it is desirable; for certain minor
violations, that the DRAM is guaranteed not to “hang up”, and that errors are limited to that particular
operation.
For the following, it will be assumed that there are no timing violations with regards to the Write
command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned
below.
8.14.2.2 Data Setup and Hold Violations
Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges
associated with a write burst, and then wrong data might be written to the memory location addressed
with this WRITE command.
In the example (Figure 40 on page 57), the relevant strobe edges for write burst A are associated with
the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5.
Subsequent reads from that location might result in unpredictable read data, however the DRAM will
work properly otherwise.
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing
requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst,
then wrong data might be written to the memory location addressed with the offending WRITE
command. Subsequent reads from that location might result in unpredictable read data, however the
DRAM will work properly otherwise.
In the example (Figure 48 on page 61) the relevant strobe edges for Write burst n are associated with
the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements
starting or ending on one of these strobe edges need to be fulfilled for a valid burst. For Write burst b
the relevant edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges
are associated withboth bursts.
8.14.2.4 Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a Write burst. No
actual timing violations are shown here. For a valid burst all timing parameters for each edge of a
burst need to be satisfied (not only for one edge - as shown).
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TRANSITIONING DATA
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3
Address*4
DON'T CARE
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3 Din
n+4 Din
n+6 Din
n+7
tDQSS (min)
Bank
Col n
WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
WL = AL + CWL
Din
nDin
n+2 Din
n+3 Din
n+4 Din
n+6 Din
n+7
Din
nDin
n+2 Din
n+3 Din
n+4 Din
n+6 Din
n+7
DM
DQS, DQS#
DQ*2
DM
DQS, DQS#
DQ
DM
tDQSS (nominal)
tWPRE(min) tDQSS tDSH tDSH tDSH tDSH tWPST(min)
tDQSL tDQSHtDQSH(min) tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSS tDSS tDSS tDSS tDSS
tWPRE(min)
tDQSH(min)
tDSH tDSH tDSH tDSH tWPST(min)
tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSStDSStDSStDSStDSS
tWPRE(min) tDSH
tDQSS
tDSH tDSH tDSH tWPST(min)
tDQSH(min)
tDSS tDSS tDSS tDSS tDSS
tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDQSS (max)
Notes:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
Figure 40 – Write Timing Definition and Parameters
8.14.3 Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs,
consistent with the implementation on DDR2 SDRAMs. It has identical timings on write operations as
the data bits as shown in Figure 40, and though used in a unidirectional manner, is internally loaded
identically to data bits to ensure matched system timing. DM is not used during read cycles.
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8.14.4 tWPRE Calculation
The method for calculating differential pulse widths for tWPRE is shown in Figure 41.
CK
CK#
DQS - DQS#
Resulting differential signal,
relevant for tWPRE specification
VTT
0 V
t1
tWPRE
tWPRE_begin
t2
tWPRE_end
Figure 41 – Method for calculating tWPRE transitions and endpoints
8.14.5 tWPST Calculation
The method for calculating differential pulse widths for tWPST is shown in Figure 42.
CK
CK#
DQS - DQS#
Resulting differential signal,
relevant for tWPST specification t1
tWPST
tWPST_begin
t2
tWPST_end
0 V
VTT
Figure 42 – Method for calculating tWPST transitions and endpoints
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3 Din
n+4 Din
n+6 Din
n+7
Bank
Col n
WRITE NOP NOP NOP NOP
tWPRE
Din
n+1 Din
n+5
tWPST
NOP NOP NOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
WL = AL + CWL
Notes:
1. BL8, WL = 5; AL = 0, CWL = 5.
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
Figure 43 – WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8)
T0 T1 T5 T6 T9 T10 T11 T12 T13 T14 T15
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3 Din
n+4 Din
n+6 Din
n+7
Bank
Col n
WRITE NOP NOP NOP NOP
AL = 5
tWPRE
Din
n+1 Din
n+5
tWPST
NOP NOP NOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
CWL = 5
WL = AL + CWL
TIME BREAK
Notes:
1. BL8, WL = 10; AL = CL - 1, CL = 6, CWL = 5.
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
Figure 44 – WRITE Burst Operation WL = 10 (AL = CL-1, CWL = 5, BL8)
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3
Bank
Col n
WRITE NOP NOP NOP NOP NOP NOP NOP READ
WL = 5
tWPRE
Din
n+1
tWPST
NOP NOP
tWTR*5
Bank
Col b
RL = 6
TIME BREAK TRANSITIONING DATA DON'T CARE
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data
shown at T7. Figure 45 – WRITE (BC4) to READ (BC4) Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3
Bank
Col n
WRITE NOP NOP NOP NOP NOP NOP NOP PRE
WL = 5
tWPRE
Din
n+1
tWPST
NOP NOP
tWR*5
TIME BREAK TRANSITIONING DATA DON'T CARE
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies
the last burst write cycle until the precharge command can be issued to the same bank.
Figure 46 – WRITE (BC4) to PRECHARGE Operation
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3
Bank
Col n
WL = 5
tWPRE
Din
n+1
tWPST
4 clocks
VALID
Ta0T11 Ta1 T14
tWR*5
NOTES: 1. BC4 on the fly, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 on the fly setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
5. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).
WRITE NOP NOP NOPNOPNOPNOP NOPNOPNOP NOPNOP NOP NOP PRE
TRANSITIONING DATA DON'T CARE
TIME BREAK
Figure 47 – WRITE (BC4) OTF to PRECHARGE Operation
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2 Din
nDin
n+2 Din
n+3
Bank
Col n
WL = 5
tWPRE
Din
n+1
tWPST
4 clocks
Bank
Col b
T12T11 T13 T14
tWR
tWTR
WL = 5
tCCD
Din
n+5 Din
n+6
Din
n+4 Din
bDin
b+1
Din
n+7 Din
b+3 Din
b+4
Din
b+2 Din
b+6 Din
b+7
Din
b+5
NOTES: 1. BL8, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.
WRITE NOP NOP NOPNOPWRITENOP NOPNOPNOP NOPNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Figure 48 – WRITE (BL8) to WRITE (BL8)
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Din
nDin
n+2 Din
n+3
WL = 5
tWPRE
Din
n+1
tWPST
WL = 5
Din
bDin
b+1 Din
b+3
Din
b+2
tWPRE
tWPST
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
4 clocks
T12T11 T13 T14
tWR
tWTR
tCCD
NOTES: 1. BC4, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge at T13 (4 clocks from T9).
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPWRITENOP NOPNOPNOP NOPNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
Figure 49 – WRITE (BC4) to WRITE (BC4) OTF
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Din
nDin
n+2 Din
n+3
WL = 5
tWPRE
Din
n+1
tWPST
tWTR
T12T11 T13 T14
Din
n+5 Din
n+6
Din
n+4 Din
n+7 RL = 6
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 A[1:0] and A12 status at T13.
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPNOPNOP NOPNOPNOP READNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
Figure 50 – WRITE (BL8) to READ (BC4/BL8) OTF
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Din
nDin
n+2
WL = 5
tWPRE
Din
n+1
tWPST
tWTR
T12T11 T13 T14
Din
n+3 RL = 6
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 A[1:0] and A12 status at T13.
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPNOPNOP NOPNOPNOP READNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
4 clocks
Figure 51 – WRITE (BC4) to READ (BC4/BL8) OTF
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Din
nDin
n+2
WL = 5
tWPRE
Din
n+1
tWPST
tWTR
T12T11 T13 T14
Din
n+3 RL = 6
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL =5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10.
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPNOPNOP NOPNOPNOP NOPNOP NOP READ NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
Figure 52 – WRITE (BC4) to READ (BC4)
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Din
nDin
n+2 Din
n+3
WL = 5
tWPRE
Din
n+1
tWPST
4 clocks
T12T11 T13 T14
Din
n+5 Din
n+6
Din
n+4 Din
b+3
tWTR
NOTES: 1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T4.
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPWRITENOP NOPNOPNOP NOPNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
Din
n+7 Din
b+1 Din
b+2
Din
b
tWR
WL = 5
tCCD
Figure 53 – WRITE (BL8) to WRITE (BC4) OTF
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Din
nDin
n+2 Din
n+3
WL = 5
tWPRE
Din
n+1
tWPST
4 clocks
T12T11 T13 T14
Din
b+1 Din
b+2
Din
bDin
b+7
tWTR
NOTES: 1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T4.
CK#
CK
Command*3
Address*4
DQS, DQS#
DQ*2
WRITE NOP NOP NOPNOPWRITENOP NOPNOPNOP NOPNOP NOP NOP NOP
TRANSITIONING DATA DON'T CARE
Bank
Col b
Bank
Col n
Din
b+3 Din
b+5 Din
b+6
Din
B+4
tWR
WL = 5
tCCD
tWPRE
tWPST
Figure 54 – WRITE (BC4) to WRITE (BL8) OTF
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8.15 Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command
is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires
Refresh cycles at an average periodic interval of tREFI. When CS#, RAS# and CAS# are held Low and
WE# High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM
must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh
Command can be applied. The refresh addressing is generated by the internal refresh controller. This
makes the address bits “Don't Care” during a Refresh command. An internal address counter supplies
the addresses during the refresh cycle. No control of the external address bus is required once this
cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the
precharged (idle) state. A delay between the Refresh Command and the next valid command, except
NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in
Figure 55. Note that the tRFC timing parameter depends on memory density.
In general, a Refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during
operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 Refresh
commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row,
the resulting maximum interval between the surrounding Refresh commands is limited to 9 × tREFI
(see Figure 56). A maximum of 8 additional Refresh commands can be issued in advance (“pulled in”),
with each one reducing the number of regular Refresh commands required later by one. Note that
pulling in more than 8 Refresh commands in advance does not further reduce the number of regular
Refresh commands required later, so that the resulting maximum interval between two surrounding
Refresh commands is limited to 9 × tREFI (see Figure 57). At any given time, a maximum of 16 REF
commands can be issued within 2 x tREFI. Self-Refresh Mode may be entered with a maximum of
eight Refresh commands being postponed. After exiting Self-Refresh Mode with one or more Refresh
commands postponed, additional Refresh commands may be postponed to the extent that the total
number of postponed Refresh commands (before and after the Self-Refresh) will never exceed eight.
During Self-Refresh Mode, the number of postponed or pulled-in REF commands does not change.
TIME BREAK DON'T CARE
DRAM must be idle
DRAM must be idle
NOTES: 1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3
CK#
Command REF NOP NOP REF NOP VALID NOP
Tc1Tc0 Tc2 Tc3
NOP
tRFC
VALIDREF VALID VALIDVALID VALID VALID VALID
tRFC(min)
tREFI (max. 9 x tREFI)
CK
Figure 55 – Refresh Command Timing
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tRFC
8 REF-Commands pulled-in
tREFI
9 x tREFI
t
Figure 56 – Postponing Refresh Commands (Example)
tRFC
8 REF-Commands pulled-in
tREFI
9 x tREFI
t
Figure 57 – Pulling-in Refresh Commands (Example)
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8.16 Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the
system is powered down. When in the Self-Refresh mode, the DDR3 SDRAM retains data without
external clocking. The DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh
operation. The Self-Refresh-Entry (SRE) Command is defined by having CS#, RAS#, CAS#, and CKE
held low with WE# high at the rising edge of the clock.
Before issuing the Self-Refresh-Entry command, the DDR3 SDRAM must be idle with all bank
precharge state with tRP satisfied. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc.
satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are
satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) Also, on-die termination must be turned off
before issuing Self-Refresh-Entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior
to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry
command is registered, CKE must be held low to keep the device in Self-Refresh mode. During
normal operation (DLL on), MR1 (A0 = 0), the DLL is automatically disabled upon entering Self-
Refresh and is automatically enabled (including a DLL-Reset) upon exiting Self-Refresh.
When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, except
CKE and RESET#, are “don't care.” For proper Self-Refresh operation, all power supply and reference
pins (VDD, VDDQ, VSS, VSSQ, VREFCA and VREFDQ) must be at valid levels. VREFDQ supply may be
turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh operation,
provided that VREFDQ is valid and stable prior to CKE going back High and that first Write operation or
first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. The
DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters Self-
Refresh mode.
The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that
the DDR3 SDRAM must remain in Self-Refresh mode is tCKESR. The user may change the external
clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered, however, the
clock must be restarted and stable tCKSRX before the device can exit Self-Refresh operation.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable
prior to CKE going back HIGH. Once a Self-Refresh Exit command (SRX, combination of CKE going
high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be
satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for
any internal refresh in progress. Before a command that requires a locked DLL can be applied, a delay
of at least tXSDLL must be satisfied.
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration
commands may be required to compensate for the voltage and temperature drift as described in
section 8.18 “ZQ Calibration Commands” on page 77. To issue ZQ calibration commands,
applicable timing requirements must be satisfied (See Figure 72 - “ZQ Calibration Timing” on page
78).
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for
Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3 SDRAM can be put back into Self-
Refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of
tRFC). NOP or deselect commands must be registered on each positive clock edge during the Self-
Refresh exit interval tXS. ODT must be turned off during tXSDLL.
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The use of Self-Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3
SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh
Mode.
T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0
CK#
CK
Command
Tf0Te0
VALID VALID
VALID
NOP SRE NOP NOP*1 VALID*2 VALID*3
SRX
VALID VALID
tRP
ODTL
tXSDLL
tXS
tIS
tIS tCPDED
tCKESR
tCKSRE tCKSRX
Enter Self Refresh Exit Self Refresh
CKE
ODT
Address
TIME BREAK DON'T CARE
Notes:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
Figure 58 – Self-Refresh Entry/Exit Timing
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8.17 Power-Down Modes
8.17.1 Power-Down Entry and Exit
Power-down is synchronously entered when CKE is registered low (along with NOP or Deselect
command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL
operations, DLL locking or read / write operation are in progress. CKE is allowed to go low while any
of other operations such as row activation, precharge or auto-precharge and refresh are in progress,
but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are
shown in Figure 59 through Figure 71 with details for entry and exit of Power-Down.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode
for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC
timing and voltage specification as well as proper DLL operation with any CKE intensive operations as
long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in-progress commands are completed, the
device will be in precharge Power-Down mode; if any bank is open after in-progress commands are
completed, the device will be in active Power-Down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, CKE and
RESET#. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or
Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are
defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED
has expired. Table 7 – Power-Down Entry Definitions
Status of DRAM
MRS bit A12
DLL
PD Exit
Relevant Parameters
Active
(A bank or more Open)
Don't Care
On
Fast
tXP to any valid command
Precharged
(All banks Precharged)
0
Off
Slow
tXP to any valid command. Since it is in precharge state,
commands here will be ACT, REF, MRS, PRE or PREA.
tXPDLL to commands that need the DLL to operate, such
as RD, RDA or ODT control line.
Precharged
(All banks Precharged)
1
On
Fast
tXP to any valid command
Also, the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept
enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode,
CKE low, RESET# high, and a stable clock signal must be maintained at the inputs of the DDR3
SDRAM, and ODT should be in a valid state, but all other input signals are “Don't Care.” (If RESET#
goes low during Power-Down, the DRAM will be out of PD mode and into reset state.) CKE low must
be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the
device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or
Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable
command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-
down exit latency is defined in section 10.16 “AC Characteristics” on page 138.
Active Power Down Entry and Exit timing diagram example is shown in Figure 59. Timing Diagrams
for CKE with PD Entry, PD Exit with Read and Read with Auto Precharge, Write, Write with Auto
Precharge, Activate, Precharge, Refresh, and MRS are shown in Figure 60 through Figure 68.
Additional clarifications are shown in Figure 69 through Figure 71.
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T0 T1 T2 Ta0 Tb0 Tb1 Tc0
CK#
CK
VALID NOP NOP
tIS
Ta1
NOP NOP NOP VALID
VALID VALID
VALIDVALID
tIH
tIH
tIS
tXP
tCKE
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
tPD
Command
CKE
Address
TIME BREAK DON'T CARE
Note:
1. VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining open after completion of the precharge
command. Figure 59 – Active Power-Down Entry and Exit Timing Diagram
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8
CK#
CK
Command
Address
DQS, DQS#
DQ BL8 Dout
bDout
b+2 Dout
b+3
VALID
RD or
RDA NOP NOP NOP NOP
Dout
b+1
tCPDED
Tb1Tb0
NOP NOP VALID
Dout
b+5 Dout
b+6
Dout
b+4 Dout
b+7
NOP
Dout
b+1 Dout
b+2
Dout
bDout
b+3
NOP NOPNOP NOP
VALID
VALID
tIS
tPD
RL = AL + CL
tRDPDEN
DQ BC4
TIME BREAK TRANSITIONING DATA DON'T CARE
Power-Down
Entery
CKE
Figure 60 – Power-Down Entry after Read and Read with Auto Precharge
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T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb2
CK#
CK
Command
Address
Din
bDin
b+2 Din
b+3
Bank
Col n
WRITE NOP NOP NOP NOP
Din
b+1
tCPDED
Tb1Tb0
NOP NOP NOP
Din
b+5 Din
b+6
Din
b+4 Din
b+7
NOP
Din
b+1 Din
b+2
Din
bDin
b+3
NOP NOPNOP NOP
tIS
tPD
WL = AL + CWL
tWRAPDEN
Tc0 Tc1
NOP
WR*1
VALID
VALID
VALID
TIME BREAK TRANSITIONING DATA DON'T CARE
Power-Down
Entery
DQS, DQS#
DQ BL8
DQ BC4
Start Internal
Precharge
A10
CKE
Note:
1. tWR is programmed through MR0.
Figure 61 – Power-Down Entry after Write with Auto Precharge
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb2
CK#
CK
Command
Address
Din
bDin
b+2 Din
b+3
Bank
Col n
WRITE NOP NOP NOP NOP
Din
b+1
tCPDED
Tb1Tb0
NOP NOP NOP
Din
b+5 Din
b+6
Din
b+4 Din
b+7
NOP
Din
b+1 Din
b+2
Din
bDin
b+3
NOP NOPNOP NOP
tIS
tPD
WL = AL + CWL
tWRPDEN
Tc0 Tc1
NOP
tWR
VALID
VALID
VALID
TIME BREAK TRANSITIONING DATA DON'T CARE
Power-Down
Entery
DQS, DQS#
DQ BL8
DQ BC4
A10
CKE
Figure 62 – Power-Down Entry after Write
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T0 T1 T2 Ta0 Tb0 Tb1 Tc0
CK#
CK
NOP NOP
tIS
Ta1
NOP NOP NOP VALID
VALID VALID
tIH
tIS tXP
tCKEtCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
tPD
Command
CKE
TIME BREAK DON'T CARE
VALID
Figure 63 – Precharge Power-Down (Fast Exit Mode) Entry and Exit
T0 T1 T2 Ta0 Tb0 Tb1 Tc0
CK#
CK
NOP NOP
tIS
Ta1
NOP NOP NOP
VALID VALID
tIH
tIS tXP
tCKE
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
tPD
Command
CKE
VALIDVALID
VALID
tXPDLL
Td0
TIME BREAK DON'T CARE
VALID
Figure 64 – Precharge Power-Down (Slow Exit Mode) Entry and Exit
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T0 T1 T2 Ta0
CK#
REF NOP
Ta1
NOP VALID
VALID
tPD
tREFPDEN
tIS
tCPDED
Command
Address VALID
NOP
T3
VALID
CKE
CK
TIME BREAK DON'T CARE
VALID
VALID
Figure 65 – Refresh Command to Power-Down Entry
T0 T1 T2 Ta0
CK#
ACTIVE NOP
Ta1
NOP VALID
VALID
tPD
tACTPDEN
tIS
tCPDED
Command
Address VALID
NOP
T3
VALID
CKE
CK
TIME BREAK DON'T CARE
VALID
VALID
Figure 66 – Active Command to Power-Down Entry
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T0 T1 T2 Ta0
CK#
PRE or
PREA NOP
Ta1
NOP VALID
VALID
tPD
tPREPDEN
tIS
tCPDED
Command
Address VALID
NOP
T3
VALID
CKE
CK
TIME BREAK DON'T CARE
VALID
VALID
Figure 67 – Precharge / Precharge all Command to Power-Down Entry
T0 T1 Ta0 Tb0
MRS NOP
Tb1
NOP VALID
VALID
tPD
tMRSPDEN
tIS
tCPDED
Command
Address VALID
NOP
Ta1
VALID
CKE
CK#
CK
TIME BREAK DON'T CARE
Figure 68 – MRS Command to Power-Down Entry
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8.17.2 Power-Down clarifications - Case 1
When CKE is registered low for power-down entry, tPD(min) must be satisfied before CKE can be
registered high for power-down exit. The minimum value of parameter tPD(min) is equal to the
minimum value of parameter tCKE(min) as shown in section 10.16 “AC Characteristics” on page 138.
A detailed example of Case 1 is shown in Figure 69.
T0 T1 T2 Ta0 Tb0 Tb1 Tb2
CK#
CK
VALID NOP NOP
tIS
Ta1
NOP NOP NOP VALID
VALID
tIH
tIH
tIS
tCPDED
tCKE
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
tPD
Command
CKE
Address
TIME BREAK DON'T CARE
tIS
Enter
Power-Down
Mode
Figure 69 – Power-Down Entry/Exit Clarifications - Case 1
8.17.3 Power-Down clarifications - Case 2
For certain CKE intensive operations, for example, repeated ‘PD Exit - Refresh - PD Entry’ sequences,
the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL
updated. Therefore, the following conditions must be met in addition to tCKE in order to maintain
proper DRAM operation when the Refresh command is issued between PD Exit and PD Entry. Power-
down mode can be used in conjunction with the Refresh command if the following conditions are met:
1) tXP must be satisfied before issuing the command.
2) tXPDLL must be satisfied (referenced to the registration of PD Exit) before the next power-down can
be entered. A detailed example of Case 2 is shown in Figure 70.
T0 T1 T2 Ta1
CK#
CK
VALID NOP
Tb0
NOP NOP NOP
tXPDLL
Command NOP
Ta0
CKE
Tb1 Tc0
REF
Address VALID tCPDED
Exit
Power-Down
Mode
Enter
Power-Down
Mode
tIH
tIS tIH
tIS
tPD
Tc1 Td0
NOP NOP
tXP
tCKE
Enter
Power-Down
Mode
TIME BREAK DON'T CARE
Figure 70 – Power-Down Entry/Exit Clarifications - Case 2
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8.17.4 Power-Down clarifications - Case 3
If an early PD Entry is issued after a Refresh command, once PD Exit is issued, NOP or DES with
CKE High must be issued until tRFC(min) from the Refresh command is satisfied. This means CKE can
not be registered low twice within a tRFC(min) window. A detailed example of Case 3 is shown in
Figure 71.
T0 T1 T2 Ta1
CK#
CK
REF NOP
Tb0
NOP NOP NOP
tRFC(min)
Command NOP
Ta0
CKE
Tb1 Tc0
NOP
Address tCPDED
Exit
Power-Down
Mode
Enter
Power-Down
Mode
tIH
tIS tIH
tIS
tPD
Tc1 Td0
NOP NOP
tXP
tCKE
Enter
Power-Down
Mode
TIME BREAK DON'T CARE
Figure 71 – Power-Down Entry/Exit Clarifications - Case 3
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8.18 ZQ Calibration Commands
8.18.1 ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM RON & ODT values over PVT (process, voltage
and temperature). An external resistor (RZQ) between the DRAM ZQ pin and ground is used as a
calibration reference. DDR3 SDRAM needs longer time to calibrate output driver and on-die
termination circuits after power-up and/or any reset, medium time for a full calibration during normal
operation (e.g. after self-refresh exit) and relatively smaller time to perform periodic update calibrations.
ZQCL (ZQ Calibration Long) command is used to perform the initial calibration during power-up
initialization sequence. This command may be issued at any time by the controller depending on the
system environment. ZQCL command triggers the calibration engine inside the DRAM and, once
calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM IO,
which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full
calibration and the transfer of values. All other ZQCL commands except the first ZQCL command
issued after RESET are allowed a timing period of tZQoper.
ZQCS (ZQ Calibration Short) command is used to perform periodic calibrations to account for voltage
and temperature variations. A shorter timing window is provided to perform the calibration and transfer
of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a
minimum of 0.5 % (ZQ Correction) of RON and RTT impedance error within 64 nCK for all speed bins
assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature
Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval
between ZQCS commands can be determined from these tables and other application-specific
parameters. One method for calculating the interval between ZQCS commands, given the temperature
(Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is
illustrated. The interval could be defined by the following formula:
)Vdriftrate × (VSens+)Tdriftrate × (TSens onZQCorrecti
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15 mV/sec,
then the interval between ZQCS commands is calculated as:
15) × (0.15+1) × (1.5 0.5
= 0.133 ≈ 128mS
No other activities should be performed on the DRAM channel by the controller for the duration of
tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output
driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable
ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the
controller. See section 9.1 “Command Truth Table” on page 94 for a description of the ZQCL and
ZQCS commands.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self
refresh. Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit
ZQ calibration command. The earliest possible time for ZQ Calibration command (ZQCS or ZQCL)
after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of
tZQoper, tZQinit, or tZQCS between the devices.
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8.18.2 ZQ Calibration Timing
T0 T1 Ta1
CK#
CK
ZQCL NOP
Ta3
NOP VALID ZQCS
Command VALID
Ta0
A10
Tb1 Tc0
NOP
Address
tZQinit or tZQoper
Tc1 Tc2
NOP NOP
Ta2 Tb0
VALIDNOP
VALIDVALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
ODT
Hi-Z
ACTIVITIES
Hi-Z
VALID
VALID
VALID
VALID
ACTIVITIES
DQ Bus
tZQCS
TIME BREAK DON'T CARE
*1
*2
*3
*1
*2
*3
Notes:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
Figure 72 – ZQ Calibration Timing
8.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ Calibration function, a 240 ohm ± 1% tolerance external resistor must be
connected between the ZQ pin and ground. The single resistor can be used for each SDRAM or one
resistor can be shared between two SDRAMs if the ZQ calibration timings for each SDRAM do not
overlap. The total capacitive loading on the ZQ pin must be limited (See section 10.11 “Input/Output
Capacitance” on page 120).
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8.19 On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off
termination resistance for each DQU, DQL, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal via
the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the DRAM controller to independently turn on/off termination resistance for any or all
DRAM devices. More details about ODT control modes and ODT timing modes can be found further
down in this document:
The ODT control modes are described in section 8.19.1
The ODT synchronous mode is described in section 8.19.2
The dynamic ODT feature is described in section 8.19.3
The ODT asynchronous mode is described in section 8.19.4
The transitions between ODT synchronous and asynchronous are described in section 8.19.4.1
through section 8.19.4.4
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure 73.
VDDQ / 2
Swtich
ODT
RTT
To other
circuitry
like
RCV,…
DQ, DQS, DM
Figure 73 – Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other
control information, see below. The value of RTT is determined by the settings of Mode Register bits
(see Figure 6 - MR1 Definition on page 20 and Figure 7 - MR2 Definition on page 22). The ODT pin
will be ignored if the Mode Registers MR1 and MR2 are programmed to disable ODT, and in self-
refresh mode.
8.19.1 ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if any of MR1 {A9, A6, A2} or MR2 {A10, A9} are non zero. In this case, the
value of RTT is determined by the settings of those bits (see Figure 6 - MR1 Definition on page 20).
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (unless ODT is disabled by MR).
DRAM does not use any write or read command decode information.
The Termination Truth Table is shown in Table 8.
Table 8 – Termination Truth Table
ODT pin
DRAM Termination State
0
OFF
1
ON, (OFF, if disabled by MR1 {A9, A6, A2} and MR2 {A10, A9} in general)
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8.19.2 Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-
down definition, these modes are:
Any bank active with CKE high
Refresh with CKE high
Idle mode with CKE high
Active power down mode (regardless of MR0 bit A12)
Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must
be disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by
a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock
edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL - 2.
8.19.2.1 ODT Latency and Posted ODT
In Synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also
applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles
defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2;
ODTLoff = CWL + AL - 2. For more details refer to the ODT timing parameters in section 10.16 “AC
Characteristics” on page 138. Table 9 – ODT Latency
Symbol
Parameter
DDR3-1333, DDR3-1600 & DDR3-1866
Unit
ODTLon
ODT turn on Latency
WL - 2 = CWL + AL - 2
nCK
ODTLoff
ODT turn off Latency
WL - 2 = CWL + AL - 2
8.19.2.2 Timing Parameters
In synchronous ODT mode, the following timing parameters apply (see also Figures 74):
ODTLon, ODTLoff, tAON,min,max, tAOF,min,max.
Minimum RTT turn-on time (tAONmin) is the point in time when the device leaves high impedance and
ODT resistance begins to turn on. Maximum RTT turn on time (tAONmax) is the point in time when the
ODT resistance is fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (tAOFmin) is the point in time when the device starts to turn off the ODT
resistance. Maximum RTT turn off time (tAOFmax) is the point in time when the on-die termination has
reached high impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered
by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8)
after the Write command (see Figure 75). ODTH4 and ODTH8 are measured from ODT registered
high to ODT registered low or from the registration of a Write command until ODT is registered low.
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL =
4) or ODTH8 (BL = 8) after Write command (T7). ODTH is measured from ODT first registered high to
ODT first registered low, or from registration of Write command with ODT high to ODT registered low.
Note that although ODTH4 is satisfied from ODT registered high at T6, ODT must not go low before
T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.
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T0 T1 T2 T4
CK#
CK
T5T3
ODT
T6 T7
tAONmin
T8 T9 T10 T12 T13 T14 T15T11
AL = 3
ODTH4min
ODTLon = CWL + AL - 2
tAONmax
Rtt_Nom
tAOFmin
tAOFmax
ODTLoff = CWL + AL - 2
AL = 3 CWL - 2
CKE
DRAM_RTT
TRANSITIONING DON'T CARE
Figure 74 – Synchronous ODT Timing (AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0 T1 T2 T4
CK#
CK
T5T3
ODT
T6 T7
tAONmin
T8 T9 T10 T12 T13 T14 T15T11
tAONmax
Rtt_Nom tAOFmin
tAOFmax
CKE
DRAM_RTT
NOP NOP WRS4NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T16
tAONmax
tAONmin
tAOFmin
tAOFmax
Command
ODTH4 ODTH4min
ODTH4
ODTLon = WL - 2 ODTLon = WL - 2
ODTLoff = WL - 2 ODTLoff = WL - 2
TRANSITIONING DON'T CARE
T17
Figure 75 – Synchronous ODT (BL = 4, WL = 7)
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8.19.2.3 ODT during Reads
As the DDR3 SDRAM can not terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving
the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the example below. As shown in Figure 76 below, at
cycle T15, DRAM turns on the termination when it stops driving, which is determined by tHZ. If DRAM stops driving early (i.e., tHZ is early), then tAONmin
timing may apply. If DRAM stops driving late (i.e., tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the
Read and enabled later after the Read than shown in this example in Figure 76.
T0 T1 T2 T4
CK#
CK
T5T3
ODT
T6 T7 T8 T9 T10 T12 T13 T14 T15T11
READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T16
tAOFmin
Command
ODTTLoff = CWL + AL - 2
ODTLon = CWL + AL - 2
RL = AL + CL
VALID
Rtt_Nom
NOP
T17
NOP NOP NOP
Dout
bDout
b+2 Dout
b+3
Dout
b+1 Dout
b+5 Dout
b+6
Dout
b+4 Dout
b+7
tAOFmax tAONmax
Rtt_Nom
NOP NOP
RTT
DQS, DQS#
DQ
TRANSITIONING DON'T CARE
Address
Figure 76 – ODT must be disabled externally during Reads by driving ODT low.
(CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8)
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8.19.3 Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that
the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command.
This requirement is supported by the “Dynamic ODT” feature as described as follows:
8.19.3.1 Functional Description:
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described
as follows:
Two RTT values are available: Rtt_Nom and Rtt_WR.
− The value for Rtt_Nom is preselected via bits A[9,6,2] in MR1.
− The value for Rtt_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
− Nominal termination strength Rtt_Nom is selected.
− Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if
Dynamic ODT is enabled, the termination is controlled as follows:
− A latency ODTLcnw after the write command, termination strength Rtt_WR is selected.
− A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by
MRS or selected OTF) after the write command, termination strength Rtt_Nom is selected.
− Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
Table 10 shows latencies and timing parameters which are relevant for the on-die termination control
in Dynamic ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set
Rtt_WR, MR2{A10, A9}={0,0}, to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered
by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8)
after the Write command (see Figure 77). ODTH4 and ODTH8 are measured from ODT registered
high to ODT registered low or from the registration of a Write command until ODT is registered low.
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Table 10 – Latencies and timing parameters relevant for Dynamic ODT
Name and Description
Abbr.
Defined from
Defined to
Definition for all DDR3
speed bins
Unit
ODT turn-on Latency
ODTLon
Registering external
ODT signal high
Turning termination on
ODTLon = WL - 2
tCK
ODT turn-off Latency
ODTLoff
Registering external
ODT signal low
Turning termination off
ODTLoff = WL - 2
tCK
ODT Latency for changing
from Rtt_Nom to Rtt_WR
ODTLcnw
Registering external
write command
Change RTT strength from
Rtt_Nom to Rtt_WR
ODTLcnw = WL - 2
tCK
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 4)
ODTLcwn4
Registering external
write command
Change RTT strength from
Rtt_WR to Rtt_Nom
ODTLcwn4 = 4 + ODTLoff
tCK
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 8)
ODTLcwn8
Registering external
write command
Change RTT strength from
Rtt_WR to Rtt_Nom
ODTLcwn8 = 6 + ODTLoff
tCK(avg)
Minimum ODT high time after
ODT assertion
ODTH4
Registering ODT
high
ODT registered low
ODTH4 = 4
tCK(avg)
Minimum ODT high time after
Write (BL = 4)
ODTH4
Registering Write
with ODT high
ODT registered low
ODTH4 = 4
tCK(avg)
Minimum ODT high time after
Write (BL =8)
ODTH8
Registering Write
with ODT high
ODT registered low
ODTH4 = 6
tCK(avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min) = 0.3 * tCK(avg)
tADC(max) = 0.7 * tCK(avg)
tCK(avg)
Note: tAOFnom and tADCnom are 0.5 tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw and ODTLcwn)
8.19.3.2 ODT Timing Diagrams
The following pages provide exemplary timing diagrams as described in Table 11:
Table 11 – Timing Diagrams for “Dynamic ODT”
Figure and Page
Description
Figure 77 on page 85
Figure 77, Dynamic ODT: Behavior with ODT being asserted before and after the write
Figure 78 on page 86
Figure 78, Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
Figure 79 on page 86
Figure 79, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles
Figure 80 on page 87
Figure 80, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
Figure 81 on page 87
Figure 81, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 4 clock cycles
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T0 T1 T2 T4
CK#
CK
T5T3
ODT
T6 T7 T8 T9 T10 T12 T13 T14 T15T11
NOP NOP NOP
T16
tADCmin
Address
ODTLoff
ODTH4
ODTLcnw
Rtt_Nom
NOP
T17
Din
bDin
b+2 Din
b+3
Din
b+1
tADCmax
VALID
ODTH4
tAONmin
tAONmax
ODTLon ODTLcwn4
tADCmax
tADCmin
tAOFmax
tAOFmin
WL
WRS4 NOP NOP NOP NOP NOP NOP NOP NOPNOP NOP NOPNOP NOP
RTT
DQ
DQS, DQS#
Rtt_WR Rtt_Nom
TRANSITIONING DON'T CARE
NOTES: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
Figure 77 – Dynamic ODT: Behavior with ODT being asserted before and after the write
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tAOFmax
T0 T1 T2 T4
CK#
CK
DON'T CARE
T5T3
ODT
T6 T7 T8 T9 T10 T11
VALID
TRANSITIONING
tAOFmin
Address
Rtt_Nom
ODTH4
tAONmin
tAONmax
RTT
ODTLoff
VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
Command
DQ
DQS, DQS#
ODTLon
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 78 – Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
T0 T1 T2 T4
CK#
CK
DON'T CARE
T5T3
ODT
T6 T7 T8 T9 T10 T11
NOP
TRANSITIONING
tAOFmin
Address
Rtt_WR
tAOFmax
ODTH8
tAONmin
tADCmax
RTT
ODTLoff
WRS8 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Command
DQ
DQS, DQS#
Din
bDin
b+2 Din
b+3
Din
b+1 Din
b+5 Din
b+6
Din
b+4 Din
b+7
WL
ODTLcwn8
ODTLon
VALID
ODTLcnw
Note:
1. Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
Figure 79 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles
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T0 T1 T2 T4
CK#
CK
DON'T CARE
T5T3
ODT
T6 T7 T8 T9 T10 T11
NOP
TRANSITIONING
Address
RTT
WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Command
DQ
DQS, DQS#
VALID
ODTLcnw
Rtt_WR
Din
bDin
b+2 Din
b+3
Din
b+1
WL
ODTLcwn4
Rtt_Nom
tADCmax
tADCmin tAOFmin
tAOFmax
ODTH4
tAONmin
tADCmax
ODTLoff
ODTLon
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 80 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
T0 T1 T2 T4
CK#
CK
DON'T CARE
T5T3
ODT
T6 T7 T8 T9 T10 T11
NOP
TRANSITIONING
Address
RTT
WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Command
DQ
DQS, DQS#
VALID
ODTLcnw
Rtt_WR
Din
bDin
b+2 Din
b+3
Din
b+1
WL
ODTLcwn4 tAOFmax
tAOFmin
ODTH4
tAONmin
tADCmax
ODTLoff
ODTLon
Note:
1. Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
Figure 81 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 4 clock cycles
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8.19.4 Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit
A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0
bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT command.
In asynchronous ODT mode, the following timing parameters apply (see Figure 82): tAONPD,min,max, tAOFPD,min,max.
Minimum RTT turn-on time (tAONPDmin) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to
turn on. Maximum RTT turn on time (tAONPDmax) is the point in time when the ODT resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn
off time (tAOFPDmax) is the point in time when the on-die termination has reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT
being sampled low.
T0 T1 T2 T4
CK#
CK
T5T3
ODT
T6 T7 T8 T9 T10 T12 T13 T14 T15T11 T16 T17
tAONPDmin
tIH
RTT
tIS
tAONPDmax RTT
tAOFPDmin
tAOFPDmax
tIH tIS
CKE
TRANSITIONING DON'T CARE
Figure 82 – Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored
In Precharge Power Down, ODT receiver remains active, however no Read or Write command can be issued, as the respective ADD/CMD receivers may
be disabled. Table 12 – Asynchronous ODT Timing Parameters for all Speed Bins
Symbol
Description
Min.
Max.
Unit
tAONPD
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
2
8.5
nS
tAOFPD
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
2
8.5
nS
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8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions
Table 13 – ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period
Description
Min.
Max.
ODT to RTT turn-
on delay
min{ ODTLon * tCK(avg) + tAONmin; tAONPDmin }
max{ ODTLon * tCK(avg) + tAONmax; tAONPDmax }
min{ (WL - 2) * tCK(avg) + tAONmin; tAONPDmin }
max{ (WL - 2) * tCK(avg) + tAONmax; tAONPDmax }
ODT to RTT turn-
off delay
min{ ODTLoff * tCK(avg) +tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK(avg) + tAOFmax; tAOFPDmax }
min{ (WL - 2) * tCK(avg) +tAOFmin; tAOFPDmin }
max{ (WL - 2) * tCK(avg) + tAOFmax; tAOFPDmax }
tANPD
WL -1
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”,
there is a transition period around power down entry, where the DDR3 SDRAM may show either
synchronous or asynchronous ODT behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL -1)
and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min)
starts with the clock cycle where CKE is first registered low. The transition period begins with the
starting point of tANPD and terminates at the end point of tCPDED(min), as shown in Figure 83. If there
is a Refresh command in progress while CKE goes low, then the transition period ends at the later one
of tRFC(min) after the Refresh command and the end point of tCPDED(min), as shown in Figure 84.
Please note that the actual starting point at tANPD is excluded from the transition period, and the actual
end points at tCPDED(min) and tRFC(min), respectively, are included in the transition period.
ODT assertion during the transition period may result in an RTT change as early as the smaller of
tAONPDmin and (ODTLon*tCK(avg) + tAONmin) and as late as the larger of tAONPDmax and (ODTLon*
tCK(avg) + tAONmax). ODT de-assertion during the transition period may result in an RTT change as
early as the smaller of tAOFPDmin and (ODTLoff* tCK(avg) + tAOFmin) and as late as the larger of
tAOFPDmax and (ODTLoff* tCK(avg) + tAOFmax). See Table 13.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. Figure 83
shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state
change during the transition period; ODT_C shows a state change after the transition period.
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T0 T1 T2 T4
CK#
CK
T5T3
Last sync, ODT
T6 T7 T8 T9 T10 T12
NOP
tAOFmin
RTT tAOFmax
NOP NOP NOP NOPCommand
T11
RTT
tAOFPDmin
RTT
tAOFPDmax
NOP NOP NOP NOPNOP NOP
tCPDED
tCPDEDmin
tANPD
ODTLoff
PD entry transition period
tAOFPDmax
ODTLoff + tAOFmin
ODTLoff + tAOFmax
PD entry transition period
tAOFPDmin
CKE
RTT
Sync or async, ODT
RTT
First async, ODT
RTT
TRANSITIONING DATA DON'T CARE
Figure 83 – Synchronous to asynchronous transition during Precharge Power Down
(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
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T0 T1 T2 T4
CK#
CK
T5T3
Command
T6 T7 T8 T9 T10 T12 T13 Ta0 Ta1T11 Ta2 Ta3
RTT
CKE
NOP NOP NOP NOP NOP NOP NOPREF NOP
RTT
RTT
tAOFPDmax
Last sync, ODT
RTT
Sync or async, ODT
RTT
First async, ODT
tAOFPDmin
ODTLoff + tAOFPDmax
tAOFPDmin
tRFC(min)
ODTLoff + tAOFPDmin
PD entry transition period
tCPDEDmin
tANPD
ODTLoff tAOFmax
tAOFmin
TRANSITIONING DON'T CARE
tAOFPDmax
TIME BREAK
RTT
Figure 84 – Synchronous to asynchronous transition after Refresh command (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
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8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition period around power down
exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL - 1) and is
counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK(avg) + tAONmin) and as late
as the larger of tAONPDmax and (ODTLon*tCK(avg) + tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the
smaller of tAOFPDmin and (ODTLoff*tCK(avg) + tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK(avg) + tAOFmax). See Table 13.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_C,
asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the
transition period with synchronous response.
T0 T1 T2 Ta1
CK#
CK
Ta2Ta0
Command
Ta3 Ta4 Ta5 Ta6 Tb0 Tb2 Tc0 Tc1 Tc2Tb1 Td0 Td1
RTT
CKE
NOP NOP NOP NOP NOP NOP NOP
NOP NOP
RTT
RTT
RTT
Last sync, ODT
RTT
Sync or async, ODT
RTT
First async, ODT tAOFmin
ODTLoff + tAOFmax
tAOFPDmin
ODTLoff + tAOFmin
PD exit transition period
tXPDLL
tAOFPDmax
tAOFPDmin
NOP NOP NOP NOP NOP
tAOFmax
ODTLoff
tAOFPDmax
TRANSITIONING DON'T CARE
tANPD
TIME BREAK
Figure 85 – Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
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8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap (see Figure 86). In
this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD
entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case the response of the DDR3 SDRAMs RTT
to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD exit transition period to the end of the PD entry
transition period. Note that in the bottom part of Figure 86 it is assumed that there was no Refresh command in progress when Idle state was entered.
T0 T1 T2 T4
CK#
CK
T5T3
Command
T6 T7 T8 T9 T10 T12 T13 T14T11
CKE
NOP NOP NOP NOP NOP NOP NOPNOP NOP NOP NOPNOP NOPNOPREF
CKE
tRFC(min)
tANPD
PD entry transition period
PD exit transition period
tANPD
short CKE low transition period
tANPD short CKE high transition period tXPDLL
TIME BREAK TRANSITIONING DON'T CARE
tXPDLL
Figure 86 – Transition period for short CKE cycles, entry and exit period overlapping (AL = 0, WL = 5, tANPD = WL - 1 = 4)
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9. OPERATION MODE
9.1 Command Truth Table
Notes 1, 2, 3 and 4 apply to the entire Command Truth Table.
Note 5 Applies to all Read/Write commands.
[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don't Care, V=Valid]
Table 14 – Command Truth Table
COMMAND
Abbr.
CKE
CS#
RAS#
CAS#
WE#
BA0-
BA2
A13
A12/
BC#
A10/
AP
A0-
A9,
A11
NOTES
Previous
Cycle
Current
Cycle
Mode Register Set
MRS
H
H
L
L
L
L
BA
OP Code
Refresh
REF
H
H
L
L
L
H
V
V
V
V
V
Self Refresh Entry
SRE
H
L
L
L
L
H
V
V
V
V
V
7,9,12
Self Refresh Exit
SRX
L
H
H
X
X
X
X
X
X
X
X
7,8,9,12
L
H
H
H
V
V
V
V
V
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Row Address (RA)
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
5
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
5
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
5
Write with Auto Precharge
(Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
5
Write with Auto Precharge
(BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
RFU
L
H
CA
5
Write with Auto Precharge
(BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
RFU
H
H
CA
5
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
5
Read (BC4, on the Fly)
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
5
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
5
Read with Auto Precharge
(Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
5
Read with Auto Precharge
(BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
5
Read with Auto Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
5
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
Power Down Exit
PDX
L
H
L
H
H
H
V
V
V
V
V
6,12
H
X
X
X
X
X
X
X
X
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
X
L
X
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Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
The MSB of BA, RA and CA are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any
function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ supply may be turned OFF
and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VREFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the
No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between
operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or
write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
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9.2 CKE Truth Table
Notes 1-7 apply to the entire CKE Truth Table.
For Power-down entry and exit parameters See 8.17 “Power-Down Modes” on page 69.
CKE low is allowed only if tMRD and tMOD are satisfied.
Table 15 – CKE Truth Table
CURRENT
STATE2
CKE
COMMAND (N) 3
RAS#, CAS#, WE#, CS#
ACTION (N) 3
NOTES
Previous Cycle 1
(N-1)
Current Cycle 1
(N)
Power Down
L
L
X
Maintain Power Down
14,15
L
H
DESELECT or NOP
Power Down Exit
11,14
Self Refresh
L
L
X
Maintain Self Refresh
15,16
L
H
DESELECT or NOP
Self Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power Down Entry
11
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry
11,13,14,18
H
L
REFRESH
Self Refresh
9,13,18
Any other state
Refer to section 9.1 “Command Truth Table” on page 94 for more detail with all command signals
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained until 1nCK prior to
tCKEmin being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period.
Read or ODT commands may be issued only after tXSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered during Read or Write operations. For a detailed list of restrictions See section 8.16 “Self-
Refresh Operation” on page 67 and See section 8.17 “Power-Down Modes” on page 69.
14. The Power Down does not perform any refresh operations.
15. “X” means “don't care” (including floating around VREF) in Self Refresh and Power Down. It also applies to Address pins.
16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ supply may be turned OFF
and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VREFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered,
otherwise Active Power Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self Refresh
exit and Power Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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9.3 Simplified State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and
the commands to control them. In particular, situations involving more than one bank, the enabling or
disabling of on-die termination, and some other events are not captured in full detail.
Power
on Reset
Procedure Initialization MRS, MPR,
Write
Leveling
Self
Refresh
ZQ
Calibration Idle Refreshing
Active
Power
Down Activating Precharge
Power
Down
Bank
Active
Writing
Writing Reading
Reading
Precharging
From any state RESET
ZQCL MRS
SRE
SRX
REF
PDE
PDX
ACT
ZQCL, ZQCS
PDX
PDE
Write Read
Read AWrite A
Write A Read A
PRE, PREA
PRE, PREAPRE, PREA
Write A
Read
Write
Write Read
CKE_L
CKE_L
CKE_ L
Automatic sequence
Command sequence
Power
Applied
Figure 87 – Simplified State Diagram
Table 16 – State Diagram Command Definitions
Abbreviation
Function
Abbreviation
Function
Abbreviation
Function
ACT
Active
Read
RD, RDS4, RDS8
PDE
Enter Power-down
PRE
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Exit Power-down
PREA
Precharge All
Write
WR, WRS4, WRS8
SRE
Self-Refresh entry
MRS
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Self-Refresh exit
REF
Refresh
RESET
Start RESET Procedure
MPR
Multi-Purpose Register
ZQCL
ZQ Calibration Long
ZQCS
ZQ Calibration Short
-
-
NOTE: See “Command Truth Table” on page 94 for more details
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10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on VDD pin relative to VSS
VDD
-0.4 ~ 1.975
V
1, 3
Voltage on VDDQ pin relative to VSS
VDDQ
-0.4 ~ 1.975
V
1, 3
Voltage on any pin relative to VSS
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage Temperature
TSTG
-55 ~ 150
°C
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times. VREFDQ and VREFCA must not greater than 0.6 x VDDQ.
When VDD and VDDQ are less than 500 mV, VREFDQ and VREFCA may be equal to or less than 300 mV.
10.2 Operating Temperature Condition
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Commercial Operating Temperature Range (for -11/-12/-15)
TOPER
0 ~ 85
°C
1, 2
0 ~95
°C
1, 2, 4
Industrial Operating Temperature Range (for -12I/15I)
TOPER
-40 ~ 85
°C
1, 3
-40 ~ 95
°C
1, 3, 4
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement
conditions, please refer to the JEDEC document JESD51-2.
2. During operation, the DRAM case temperature must be maintained between 0 to 95°C for Commercial parts under all
specification parameters.
3. During operation, the DRAM case temperature must be maintained between -40 to 95°C for Industrial parts under all
specification parameters
4. Some applications require operation of the 85°C < TCASE ≤ 95°C operating temperature. Full specifications are provided in
this range, but the following additional conditions apply:
(a) Refresh commands have to be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µS.
(b) If Self-Refresh operation is required in 85°C < TCASE ≤ 95°C operating temperature range, than it is mandatory to either
use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or
enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
10.3 DC & AC Operating Conditions
10.3.1 Recommended DC Operating Conditions
SYM.
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
Supply Voltage
1.425
1.5
1.575
V
1, 2
VDDQ
Supply Voltage for Output
1.425
1.5
1.575
V
1, 2
RZQ
External Calibration Resistor connected
from ZQ ball to ground
237.6
240.0
242.4
Ω
3
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The external calibration resistor RZQ can be time-shared among DRAMs in special applications.
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10.4 Input and Output Leakage Currents
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTES
IIL
Input Leakage Current
(0V ≤ VIN ≤ VDD)
-2
2
µA
1
IOL
Output Leakage Current
(Output disabled, 0V ≤ VOUT ≤ VDDQ)
-5
5
µA
2
Notes:
1. All other balls not under test = 0 V.
2. All DQ, DQS and DQS# are in high-impedance mode.
10.5 Interface Test Conditions
Figure 88 represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of
the actual load presented by a production tester. System designers should use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers
correlate to their production test conditions, generally one or more coaxial transmission lines
terminated at the tester electronics.
DQ
DQS
DQS#
Timing reference point
VTT = VDDQ/2
25Ω
VDDQ
DUT
CK, CK#
Figure 88 – Reference Load for AC Timings and Output Slew Rates
The Timing Reference Points are the idealized input and output nodes / terminals on the outside of the
packaged SDRAM device as they would appear in a schematic or an IBIS model.
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g.
DQSL, DQSU) and the complement (e.g. DQSL#, DQSU#) signal.
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10.6 DC and AC Input Measurement Levels
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals
Table 17 – Single-Ended DC and AC Input Levels for Command and Address
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600
DDR3-1866
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
DC input logic high
VIH.CA(DC100)
VREF + 0.100
VDD
VREF + 0.100
VDD
V
1, 5
DC input logic low
VIL.CA(DC100)
VSS
VREF - 0.100
VSS
VREF - 0.100
V
1, 6
AC input logic high
VIH.CA(AC175)
VREF + 0.175
Note 2
-
-
V
1, 2, 7
AC input logic low
VIL.CA(AC175)
Note 2
VREF - 0.175
-
-
V
1, 2, 8
AC input logic high
VIH.CA(AC150)
VREF + 0.150
Note 2
-
-
V
1, 2, 7
AC input logic low
VIL.CA(AC150)
Note 2
VREF - 0.150
-
-
V
1, 2, 8
AC input logic high
VIH.CA(AC135)
-
-
VREF + 0.135
Note 2
V
1, 2, 7
AC input logic low
VIL.CA(AC135)
-
-
Note 2
VREF - 0.135
V
1, 2, 8
AC input logic high
VIH.CA(AC125)
-
-
VREF + 0.125
Note 2
V
1, 2, 7
AC input logic low
VIL.CA(AC125)
-
-
Note 2
VREF - 0.125
V
1, 2, 8
Reference Voltage
for ADD, CMD inputs
VREFCA(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Notes:
1. For input only pins except RESET#. VREF = VREFCA(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 121.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ± 1% VDD (for reference: approx.
± 15 mV).
4. For reference: approx. VDD/2 ± 15 mV.
5. VIH(DC) is used as a simplified symbol for VIH.CA(DC100).
6. VIL(DC) is used as a simplified symbol for VIL.CA(DC100).
7. VIH(AC) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175)
value is used when VREF + 0.175V is referenced, VIH.CA(AC150) value is used when VREF + 0.150V is referenced,
VIH.CA(AC135) value is used when VREF + 0.135V is referenced, and VIH.CA(AC125) value is used when VREF + 0.125V is
referenced.
8. VIL(AC) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175)
value is used when VREF - 0.175V is referenced, VIL.CA(AC150) value is used when VREF - 0.150V is referenced,
VIL.CA(AC135) value is used when VREF - 0.135V is referenced, and VIL.CA(AC125) value is used when VREF - 0.125V is
referenced.
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10.6.2 DC and AC Input Levels for Single-Ended Data Signals
Table 18 – Single-Ended DC and AC Input Levels for DQ and DM
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600
DDR3-1866
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
DC input logic high
VIH.DQ(DC100)
VREF + 0.100
VDD
VREF + 0.100
VDD
V
1, 5
DC input logic low
VIL.DQ(DC100)
VSS
VREF - 0.100
VSS
VREF - 0.100
V
1, 6
AC input logic high
VIH.DQ(AC150)
VREF + 0.150
Note 2
-
-
V
1, 2, 7
AC input logic low
VIL.DQ(AC150)
Note 2
VREF - 0.150
-
-
V
1, 2, 8
AC input logic high
VIH.DQ(AC135)
VREF + 0.135
Note 2
VREF + 0.135
Note 2
V
1, 2, 7
AC input logic low
VIL.DQ(AC135)
Note 2
VREF - 0.135
Note 2
VREF - 0.135
V
1, 2, 8
Reference Voltage
for DQ, DM inputs
VREFDQ(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Notes:
1. VREF = VREFDQ(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 121.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ(DC) by more than ± 1% VDD (for reference:
approx. ± 15 mV).
4. For reference: approx. VDD/2 ± 15 mV.
5. VIH(DC) is used as a simplified symbol for VIH.DQ(DC100).
6. VIL(DC) is used as a simplified symbol for VIL.DQ(DC100).
7. VIH(AC) is used as a simplified symbol for VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC150) value is used when VREF +
0.150V is referenced, and VIH.DQ(AC135) value is used when VREF + 0.135V is referenced.
8. VIL(AC) is used as a simplified symbol for VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC150) value is used when VREF -
0.150V is referenced, and VIL.DQ(AC135) value is used when VREF - 0.135V is referenced.
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The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA and VREFDQ are
illustrated in Figure 89. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands
for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g., 1 sec). This average
has to meet the min/max requirements in Table 17. Furthermore VREF(t) may temporarily deviate from
VREF(DC) by no more than ± 1% VDD.
VREF(DC)max
VREF(DC)min
VDD/2
VDD
VSS
voltage
time
VREF(DC)
VREF(t)
VREF AC-noise
Figure 89 – Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are
dependent on VREF.
“VREF” shall be understood as VREF(DC), as defined in Figure 89.
This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a
valid high or low level and therefore the time to which setup and hold is measured. System timing and
voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-
eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time
and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up
to the specified limit (± 1% of VDD) are included in DRAM timings and their associated deratings.
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10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
Table 19 – Differential DC and AC Input Level
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600 & DDR3-1866
UNIT
NOTES
MIN.
MAX.
Differential input high
VIHDIFF
+0.200
Note 3
V
1
Differential input low
VILDIFF
Note 3
-0.200
V
1
Differential input high AC
VIHDIFF(AC)
2 x (VIH(AC) - VREF)
Note 3
V
2
Differential input low AC
VILDIFF(AC)
Note 3
2 x (VIL(AC) - VREF)
V
2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH.CA(AC)/VIL.CA(AC) of ADD/CMD and VREFCA; for DQSL, DQSL#, DQSU , DQSU# use
VIH.DQ(AC)/VIL.DQ(AC) of DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the
reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to be within
the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to section 10.12 “Overshoot and Undershoot Specifications” on page 121.
tDVAC
tDVAC
Half cycle
VIHDIFF(AC)min
VIHDIFFmin
0
VILDIFFmax
VILDIFF(AC)max
Differential Input Voltage (i.e. DQS – DQS#, CK - CK# )
time
Figure 90 – Definition of differential ac-swing and “time above AC-level” tDVAC
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Table 20 – Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
Slew Rate
[V/nS]
DDR3-1333/1600
DDR3-1866
tDVAC [pS]
@ VIH/LDIFF(AC) =
350mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
(CK - CK#) only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
> 4.0
75
-
175
-
134
-
139
-
4.0
57
-
170
-
134
-
139
-
3.0
50
-
167
-
112
-
118
-
2.0
38
-
119
-
67
-
77
-
1.8
34
-
102
-
52
-
63
-
1.6
29
-
81
-
33
-
45
-
1.4
22
-
54
-
9
-
23
-
1.2
Note
-
19
-
Note
-
Note
-
1.0
Note
-
Note
-
Note
-
Note
-
< 1.0
Note
-
Note
Note
-
Note
-
Note:
Rising input differential signal shall become equal to or greater than VIHDIFF(AC) level and Falling input differential signal shall
become equal to or less than VILDIFF(AC) level.
10.6.4 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQSL, DQSU, CK#, DQSL#, DQSU#) has also
to comply with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the AC-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
DQSL, DQSU, DQSL#, DQSU# have to reach VSEHmin / VSELmax (approximately the AC-levels
(VIH.DQ(AC) / VIL.DQ(AC) ) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these AC-levels apply also for the
single-ended signals CK and CK#.
Table 21 – Single-ended levels for CK, DQSL, DQSU, CK#, DQSL# or DQSU#
PARAMETER
SYM.
DDR3-1333, DDR3-1600 & DDR3-1866
UNIT
NOTES
MIN.
MAX.
Single-ended high level for strobes
VSEH
(VDD/2) + 0.175
Note 3
V
1, 2
Single-ended high level for CK, CK#
(VDD/2) + 0.175
Note 3
V
1, 2
Single-ended low level for strobes
VSEL
Note 3
(VDD/2) - 0.175
V
1, 2
Single-ended low level for CK, CK#
Note 3
(VDD/2) - 0.175
V
1, 2
Notes:
1. For CK, CK# use VIH.CA(AC) / VIL..CA(AC) of ADD/CMD; for strobes (DQSL, DQSL#, DQSU, DQSU#) use VIH.DQ(AC) /
VIL.DQ(AC) of DQs.
2. VIH.DQ(AC) / VIL.DQ(AC) for DQs is based on VREFDQ; VIH.CA(AC) / VIL.CA(AC) for ADD/CMD is based on VREFCA; if a
reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to be within
the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to section 10.12 “Overshoot and Undershoot Specifications” on page 121.
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VDD or VDDQ
VSEHmin
VDD/2 or VDDQ/2
VSELmax
VSS or VSSQ
VSEH
VSEL
CK or DQS
time
Figure 91 – Single-ended requirement for differential signals
Note that, while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the
same. The transition of single-ended signals through the AC-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
10.6.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the
requirements in Table 22. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS.
VIX
VIX
VIX
VDD/2
CK#, DQS#
CK, DQS
VDD
VSS
VSEH VSEL
Figure 92 – VIX Definition
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Table 22 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
SYMBOL
DDR3-1333, DDR3-1600 & DDR3-1866
UNIT
NOTES
MIN.
MAX.
Differential Input Cross Point Voltage
VIX(CK)
- 150
150
mV
2
relative to VDD/2 for CK, CK#
- 175
175
mV
1
Differential Input Cross Point Voltage
VIX(DQS)
-150
150
mV
2
relative to VDD/2 for DQS, DQS#
Note:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with
a single-ended swing VSEL/VSEH of at least VDD/2 ± 250 mV, and when the differential slew rate of CK - CK# is larger
than 3 V/nS. Refer to Table 21 for VSEL and VSEH standard values.
2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX (Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX (Max)) ≥ 25mV
10.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 10.16.4 “Address / Command Setup, Hold and Derating” on page 149 for single-
ended slew rate definitions for address and command signals.
See section 10.16.5 “Data Setup, Hold and Slew Rate Derating” on page 156 for single-ended slew
rate definitions for data signals.
10.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 23 and Figure 93.
Table 23 – Differential Input Slew Rate Definition
Description
Measured
Defined by
from
to
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
VIL.DIFFmax
VIH.DIFFmin
[VIH.DIFFmin - VIL.DIFFmax] / ΔTR.DIFF
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
VIH.DIFFmin
VIL.DIFFmax
[VIH.DIFFmin - VIL.DIFFmax] / ΔTF.DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
VIH.DIFFmin
0
VIL.DIFFmax
ΔTF.DIFF
ΔTR.DIFF
Differential input voltage (DQS - DQS#; CK - CK#)
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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10.7 DC and AC Output Measurement Levels
Table 24 – Single-ended DC and AC Output Levels
PARAMETER
SYMBOL
VALUE
UNIT
NOTES
DC output high measurement level (for IV curve linearity)
VOH(DC)
0.8 x VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.5 x VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.2 x VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
VTT + 0.1 x VDDQ
V
1
AC output low measurement level (for output slew rate)
VOL(AC)
VTT - 0.1 x VDDQ
V
1
Note:
1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 25 – Differential DC and AC Output Levels
PARAMETER
SYMBOL
VALUE
UNIT
NOTES
MIN.
MAX.
AC differential output high measurement level (for output
slew rate)
VOH.DIFF(AC)
+0.2 x VDDQ
V
1
AC differential output low measurement level (for output
slew rate)
VOL.DIFF(AC)
-0.2 x VDDQ
V
1
Note:
1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
10.7.1 Output Slew Rate Definition and Requirements
The slew rate definition depends if the signal is single-ended or differential. For the relevant AC output
reference levels see above Table 24 and Table 25.
Table 26 – Output Slew Rate
PARAMETER
SYMBOL
DDR3-1333,
DDR3-1600
DDR3-1866
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
Single-ended Output Slew Rate
SRQse
2.5
5
2.5
5*1
V/nS
1, 2, 3
Differential Output Slew Rate
SRQdiff
5
10
5
12
V/nS
2, 3
Notes:
1. In two cases, a maximum slew rate of 6 V/nS applies for a single DQ signal within a byte lane.
- Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 5 V/nS applies.
2. Background for Symbol Nomenclature: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-
Output); se: Single-ended Signals; diff: Differential Signals.
3. For RON = RZQ/7 settings only.
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10.7.1.1 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is
defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 27
and Figure 94. Table 27 – Single-ended Output Slew Rate Definition
Description
Measured
Defined by
from
to
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] / ΔTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)] / ΔTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VTT
VOL(AC)
ΔTFse
ΔTRse
Single-ended Output Voltage (i.e. DQ)
Figure 94 –Single-ended Output Slew Rate Definition
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10.7.1.2 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is
defined and measured between VOL.DIFFAC) and VOH.DIFF(AC) for differential signals as shown in Table
28 and Figure 95.
Table 28 – Differential Output Slew Rate Definition
Description
Measured
Defined by
from
to
Differential output slew rate for rising edge
VOL.DIFF(AC)
VOH.DIFF(AC)
[VOH.DIFF(AC) - VOL.DIFF(AC)] / ΔTRdiff
Differential output slew rate for falling edge
VOH.DIFF(AC)
VOL.DIFF(AC)
[VOH.DIFF(AC) - VOL.DIFF(AC)] / ΔTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH.DIFF(AC)
0
VOL.DIFF(AC)
ΔTFdiff
ΔTRdiff
Differential Outut Voltage (DQS - DQS#)
Figure 95 – Differential Output Slew Rate Definition
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10.8 34 ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown in Figure 96. Output driver impedance RON is
selected by bits “D.I.C” A1 and A5 in the MR1 Register. Two different values can be selected via MR1
settings:
RON34 = RZQ / 7 (nominal 34.3 Ω ±10% with nominal RZQ = 240 Ω)
RON40 = RZQ / 6 (nominal 40.0 Ω ±10% with nominal RZQ = 240 Ω)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu =
Out
OutDDQ
I
V-V
under the condition that RONPd is turned off
RONPd =
Out
Out
I
V
under the condition that RONPu is turned off
VSSQ
DQ
VDDQ
Vout
Output Driver
Ipd
RONpd
RONpu
Ipu
To other
circuitry
like RCV, ... Iout
Chip in Drive Mode
Figure 96 – Output Driver: Definition of Voltages and Currents
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Table 29 – Output Driver DC Electrical Characteristics, assuming RZQ = 240 Ω; entire operating
temperature range; after proper ZQ calibration
RONNom
Resistor
VOUT
MIN.
NOM.
MAX.
UNIT
NOTES
34 Ω
RON34Pd
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
RON34Pu
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
40 Ω
RON40Pd
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/6
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/6
1, 2, 3
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/6
1, 2, 3
RON40Pu
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/6
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/6
1, 2, 3
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/6
1, 2, 3
Mismatch between pull-up and pull-down,
MMPuPd
VOMDC = 0.5 × VDDQ
-10
+10
%
1, 2, 4
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 × VDDQ. Other calibration
schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 * VDDQ:
MMPuPd =
Nom
PdPu
RONRON-RON
x 100%
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10.8.1 Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 30
and Table 31.
ΔT = T - T(@calibration); ΔV= VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Table 30 – Output Driver Sensitivity Definition
MIN.
MAX.
UNIT
RONPU@ VOHDC
0.6 - dRONdTH*|ΔT| - dRONdVH*|ΔV|
1.1 + dRONdTH*|ΔT| + dRONdVH*|ΔV|
RZQ/7
RON@ VOMDC
0.9 - dRONdTM*|ΔT| - dRONdVM*|ΔV|
1.1 + dRONdTM*|ΔT| + dRONdVM*|ΔV|
RZQ/7
RONPD@ VOLDC
0.6 - dRONdTL*|ΔT| - dRONdVL*|ΔV|
1.1 + dRONdTL*|ΔT| + dRONdVL*|ΔV|
RZQ/7
Table 31 – Output Driver Voltage and Temperature Sensitivity
Speed Bin
DDR3-1333
DDR3-1600 & DDR3-1866
UNIT
MIN.
MAX.
MIN.
MAX.
dRONdTM
0
1.5
0
1.5
%/°C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/°C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/°C
dRONdVH
0
0.15
0
0.13
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
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10.9 On-Die Termination (ODT) Levels and Characteristics
10.9.1 ODT Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register.
ODT is applied to the DQ, DM and DQS/DQS# pins.
A functional representation of the on-die termination is shown in Figure 97. The individual pull-up and
pull-down resistors (RTTPu and RTTPd) are defined as follows:
RTTPu =
Out
OutDDQ
I
VV -
under the condition that RTTPd is turned off
RTTPd =
Out
Out
I
V
under the condition that RTTPu is turned off
VSSQ
DQ
VDDQ
Vout
ODT
Ipd
RTTpd
RTTpu
Ipu
To other
circuitry
like RCV, ... Iout
Chip in Termination Mode
Iout = IPd - IPu
Figure 97 – On-Die Termination: Definition of Voltages and Currents
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10.9.2 ODT DC Electrical Characteristics
An overview about the specification requirements for RTT and ΔVM is provided in Table 32.
Table 32 – ODT DC Impedance and Mid-Level Requirements
MR1 A9, A6, A2
RTT
Resistor
Vout
Min.
Nom.
Max.
Unit
Notes
0, 1, 0
120 Ω
RTT120
0.9
1.0
1.6
RZQ/2
1, 2, 3, 4
0, 0, 1
60 Ω
RTT60
0.9
1.0
1.6
RZQ/4
1, 2, 3, 4
0, 1, 1
40 Ω
RTT40
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/6
1, 2, 3, 4
1, 0, 1
30 Ω
RTT30
0.9
1.0
1.6
RZQ/8
1, 2, 3, 4
1, 0, 0
20 Ω
RTT20
0.9
1.0
1.6
RZQ/12
1, 2, 3, 4
Deviation of VM with respect to VDDQ/2, ΔVM
-5
+5
%
1, 2, 3, 4, 5
Notes:
1. With RZQ = 240 Ω.
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the following section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
4. Measurement definition for RTT :
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current
I(VIL(AC)) respectively. Calculate RTT as follows:
RTT = [VIH(AC) - VIL(AC)] / [I (VIH(AC)) - I (VIL(AC))]
5. Measurement definition for VM and ΔVM:
Measure voltage (VM) at test pin (midpoint) with no load. Calculate ΔVM as follows:
ΔVM = (2 × VM / VDDQ - 1) × 100%.
10.9.3 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 33
and Table 34. The following definitions are used:
ΔT = T - T (@calibration);ΔV = VDDQ- VDDQ (@calibration); VDD = VDDQ
Table 33 – ODT Sensitivity Definition
SYMBOL
MIN.
MAX.
UNIT
RTT
0.9 - dRTTdT × |ΔT| - dRTTdV × |ΔV|
1.6 + dRTTdT × |ΔT| + dRTTdV × |ΔV|
RZQ/2,4,6,8,12
Table 34 – ODT Voltage and Temperature Sensitivity
SYMBOL
MIN.
MAX.
UNIT
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization
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10.9.4 Design guide lines for RTTPU and RTTPD
Table 35 provides an overview of the ODT DC electrical pull-up and pull-down characteristics. The
values are not specification requirements, but can be used as design guide lines.
Table 35 – ODT DC Electrical Pull-Down and Pull-Up Characteristics, assuming RZQ = 240 Ω ± 1%
entire operating temperature range; after proper ZQ calibration
MR1 A9, A6, A2
RTT
Resistor
Vout
Min.
Nom.
Max.
Unit
Notes
0, 1, 0
120 Ω,
RTT120PD240,
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/TISFPUPD
1, 2, 3, 4, 5
0, 0, 1
60 Ω,
RTT60PD120,
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/TISFPUPD
1, 2, 3, 4, 5
0, 1, 1
40 Ω,
RTT40PD80,
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/TISFPUPD
1, 2, 3, 4, 5
1, 0, 1
30 Ω,
RTT30PD60,
1, 0, 0
20 Ω
RTT20PD40
RTT120PU240,
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/TISFPUPD
1, 2, 3, 4, 5
RTT60PU120,
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/TISFPUPD
1, 2, 3, 4, 5
RTT40PU80,
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/TISFPUPD
1, 2, 3, 4, 5
RTT30PU60,
RTT20PU40
Notes:
1. TISFPUPD: Termination Impedance Scaling Factor for Pull-Up and Pull-Down path:
TISFPUPD = 1 for RTT120PU/PD240
TISFPUPD = 2 for RTT60PU/PD120
TISFPUPD = 3 for RTT40PU/PD80
TISFPUPD = 4 for RTT30PU/PD60
TISFPUPD = 6 for RTT20PU/PD40
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the above section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
4. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 × VDDQ. Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ.
5. Not a specification requirement, but a design guide line.
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10.10 ODT Timing Definitions
10.10.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 98.
DQ, DM
DQS, DQS#
Timing reference point
VTT = VSSQ
RTT = 25Ω
VDDQ
DUT
CK, CK#
VSSQ
Figure 98 – ODT Timing Reference Load
10.10.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 36 and subsequent figures.
Measurement reference settings are provided in Table 37.
Table 36 – ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figure
tAON
Rising edge of CK - CK# defined by the end
point of ODTLon
Extrapolated point at VSSQ
Figure 99
tAONPD
Rising edge of CK - CK# with ODT being first
registered high
Extrapolated point at VSSQ
Figure 100
tAOF
Rising edge of CK - CK#defined by the end
point of ODTLoff
End point: Extrapolated point at VRtt_Nom
Figure 101
tAOFPD
Rising edge of CK - CK# with ODT being first
registered low
End point: Extrapolated point at VRtt_Nom
Figure 102
tADC
Rising edge of CK - CK# defined by the end
point of ODTLcnw, ODTLcwn4 or ODTLcwn8
End point: Extrapolated point at VRtt_WR and
VRtt_Nom respectively
Figure 103
Table 37 – Reference Settings for ODT Timing Measurements
Measured Parameter
Rtt_Nom Setting
Rtt_WR Setting
VSW1 [V]
VSW2 [V]
tAON
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAONPD
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAOF
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tAOFPD
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
tADC
RZQ/12
RZQ/2
0.20
0.30
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CK
CK#
tAON
VSSQ
VSW2
VSW1
TSW1
TSW2
End point: Extrapolated point at VSSQ
DQ, DM
DQS, DQS#
Begin point: Rising edge of CK – CK#
defined by the end point of ODTL on
VTT
VSSQ
Figure 99 – Definition of tAON
CK
CK#
tAONPD
VSSQ
VSW2
VSW1
TSW1
TSW2
End point: Extrapolated point at VSSQ
DQ, DM
DQS, DQS#
Begin point: Rising edge of CK - CK# with
ODT being first registered high
VTT
VSSQ
Figure 100 – Definition of tAONPD
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CK
CK#
tAOF
VSW2
VSW1
TSW1
TSW2
End point: Extrapolated point at VRtt_Nom
DQ, DM
DQS, DQS#
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLoff
VTT
VSSQ
VRtt_Nom
Figure 101 – Definition of tAOF
CK
CK#
tAOFPD
VSW2
VSW1
TSW1
TSW2
End point: Extrapolated point at VRtt_Nom
DQ, DM
DQS, DQS#
Begin point: Rising edge of CK – CK# with
ODT being first registered low
VTT
VSSQ
VRtt_Nom
Figure 102 – Definition of tAOFPD
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CK
CK#
tADC
VSW2
VSW1
TSW1
TSW21
End point: Extrapolated point at VRtt_Nom
DQ, DM
DQS, DQS#
Begin point: Rising edge of CK – CK#
defined by the end point of ODTLcnw
VRtt_Nom
tADC
TSW1
TSW2
End point: Extrapolated point at VRtt_WR
Begin point: Rising edge of CK – CK# defined by
the end point of ODTLcwn4 or ODTLcwn8
VTT
VRtt_Nom
VRtt_WR
VSSQ
Figure 103 – Definition of tADC
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10.11 Input/Output Capacitance
PARAMETER
SYMBOL
DDR3-1333
DDR3-1600
DDR3-1866
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Input/output capacitance
(DQ, DM, DQS, DQS#)
CIO
1.4
2.5
1.4
2.3
1.4
2.2
pF
1, 2, 3
Input capacitance
(CK and CK#)
CCK
0.8
1.4
0.8
1.4
0.8
1.3
pF
2, 3
Delta of input capacitance
(CK and CK#)
CDCK
0
0.15
0
0.15
0
0.15
pF
2, 3, 4
Delta of Input/Output capacitance
(DQS and DQS#)
CDDQS
0
0.15
0
0.15
0
0.15
pF
2, 3, 5
Input capacitance
(CTRL, ADD, CMD input-only pins)
CI
0.75
1.3
0.75
1.3
0.75
1.2
pF
2, 3, 6
Delta of input capacitance
(All CTRL input-only pins)
CDI_CTRL
-0.4
0.2
-0.4
0.2
-0.4
0.2
pF
2, 3, 7, 8
Delta of input capacitance
(All ADD/CMD input-only pins)
CDI_ADD_CMD
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF
2, 3, 9, 10
Delta of Input/output capacitance
(DQ, DM, DQS, DQS#)
CDIO
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2, 3, 11
Input/output capacitance of ZQ signal
CZQ
3
3
3
pF
2, 3, 12
Notes:
1. Although the DM signals have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured
according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD, VDDQ,
VSS, VSSQ applied and all other pins floating (except the ball under test, CKE, RESET# and ODT as necessary).
VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here.
4. Absolute value of CCK-CCK#.
5. Absolute value of CIO(DQS)-CIO(DQS#).
6. CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#, CAS#, WE#.
7. CDI_CTRL applies to ODT, CS# and CKE.
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK#)).
9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, RAS#, CAS# and WE#.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)).
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)).
12. Maximum external load capacitance on ZQ signal: 5 pF.
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10.12 Overshoot and Undershoot Specifications
10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins:
Applies to A0-A13, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT
PARAMETER
DDR3-1333
DDR3-1600
DDR3-1866
UNIT
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.4
0.33
0.28
V-nS
Maximum undershoot area below VSS
0.4
0.33
0.28
V-nS
10.12.2 AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:
Applies to CK, CK#, DQ, DQS, DQS#, DM
PARAMETER
DDR3-1333
DDR3-1600
DDR3-1866
UNIT
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
0.4
0.4
V
Maximum overshoot area above VDDQ
0.15
0.13
0.11
V-nS
Maximum undershoot area below VSSQ
0.15
0.13
0.11
V-nS
Maximum Amplitude
Maximum Amplitude Overshoot Area
Undershoot Area
VDD/VDDQ
Volts (V)
Time (nS)
VSS/VSSQ
Figure 104 – AC Overshoot and Undershoot Definition
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10.13 IDD and IDDQ Specification Parameters and Test Conditions
10.13.1 IDD and IDDQ Measurement Conditions
In this section, IDD and IDDQ measurement conditions such as test load and patterns are defined.
Figure 105 shows the setup and test load for IDD and IDDQ measurements.
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the
DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM.
They can be used to support correlation of simulated IO power to actual IO power as
outlined in Figure 106. In DRAM module application, IDDQ cannot be measured separately
since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
“0” and “LOW” is defined as VIN ≤ VILAC(max).
“1” and “HIGH” is defined as VIN ≥ VIHAC(min).
“MID-LEVEL” is defined as inputs are VREF = VDD / 2.
Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 38.
Basic IDD and IDDQ Measurement Conditions are described in Table 39.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 40 through Table 47.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not
limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0b (Output Buffer enabled in MR1);
Rtt_Nom = RZQ/6 (40 Ohm in MR1);
Rtt_WR = RZQ/2 (120 Ohm in MR2);
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS#, RAS#, CAS#, WE# } := {HIGH, LOW, LOW, LOW}
Define D# = {CS#, RAS#, CAS#, WE# } := {HIGH, HIGH, HIGH, HIGH}
Table 38 – Timings used for IDD and IDDQ Measurement-Loop Patterns
Speed Bin
DDR3-1333
DDR3-1600
DDR3-1866
Unit
CL-nRCD-nRP
9-9-9
11-11-11
13-13-13
Part Number Extension
-15/15I
-12/12I
-11
tCK
1.5
1.25
1.07
nS
CL
9
11
13
nCK
nRCD
9
11
13
nCK
nRC
33
39
45
nCK
nRAS
24
28
32
nCK
nRP
9
11
13
nCK
nFAW
30
32
33
nCK
nRRD
5
6
6
nCK
nRFC 2 Gb
107
128
150
nCK
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RESET#
CK/CK#
CKE
CS#
RAS#, CAS#, WE#
A, BA
ODT
ZQ
VSS VSSQ
DQS, DQS#, DQ, DM
DDR3
SDRAM
VDD VDDQ
IDD IDDQ(optional)
VDDQ / 2
RTT = 25 Ω
NOTE: DIMM level Output test load condition may be different from above.
Figure 105 – Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
Application specific
memory channel
environment
Channel IO
Power
simulation
Correlation
Correlation
Channel IO Power
Number
IDDQ Test Load
IDDQ
Simulation IDDQ
Measurement
Figure 106 – Correlation from simulated Channel IO Power to actual Channel IO Power
supported by IDDQ Measurement
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Table 39 – Basic IDD and IDDQ Measurement Conditions
SYM.
DESCRIPTION
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 38; BL: 8(1); AL: 0; CS#: High
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according
to Table 40; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 40); Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pattern Details: see Table 40
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 38; BL: 8(1,6); AL: 0; CS#:
High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling according to Table 41; DM: stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,... (see Table 41); Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pattern Details: see Table 41
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 42; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 42
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 43; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: toggling according to Table 43; Pattern Details: see Table 43
IDDQ2NT
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pecharge Power Down Mode: Slow Exit(3)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pecharge Power Down Mode: Fast Exit(3)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 42; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 42
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0
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Publication Release Date: Dec. 03, 2015
Revision: A06
- 125 -
Basic IDD and IDDQ Measurement Conditions, continued
SYM.
DESCRIPTION
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1,6); AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 44; Data IO:
seamless read data burst with different data between one burst and the next one according to Table
44; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,... (see Table 44); Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal:
stable at 0; Pattern Details: see Table 44
IDDQ4R
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 38; BL: 8(1); AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 45; Data IO:
seamless write data burst with different data between one burst and the next one according to
Table 45; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... (see Table 45); Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal:
stable at HIGH; Pattern Details: see Table 45
IDD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 38; BL: 8(1); AL: 0; CS#: High between
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 46; Data
IO: MID-LEVEL; DM: stable at 0; Bank Activity: REF command every nRFC (see Table 46);
Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Pattern Details:
see Table 46
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):
Normal(5); CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 38; BL: 8(1); AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MID-
LEVEL
IDD6ET
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):
Extended(5); CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 38; BL: 8(1); AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers(2); ODT Signal: MID-LEVEL
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 38; BL:
8(1,6); AL: CL-1; CS#: High between ACT and RDA; Command, Address, Bank Address Inputs:
partially toggling according to Table 47; Data IO: read data bursts with different data between one
burst and the next one according to Table 47; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1, ...7) with different addressing, see Table 47; Output Buffer and RTT:
Enabled in Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 47
IDD8
RESET# Low Current
RESET#: Low; External clock: Off; CK and CK#: Low; CKE: FLOATING; CS#, Command,
Address, Bank Address, Data IO: FLOATING; ODT Signal: FLOATING
RESET# Low current reading is valid once power is stable and RESET has been Low for at least
1mS
Notes:
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00b.
2. Output Buffer Enable: set MR1 A[12] = 0b; set MR1 A[5,1] = 01b; Rtt_Nom enable: set MR1 A[9,6,2] = 011b; Rtt_WR
enable: set MR2 A[10,9] = 10b.
3. Pecharge Power Down Mode: set MR0 A12=0b for Slow Exit or MR0 A12=1b for Fast Exit.
4. Auto Self-Refresh (ASR): set MR2 A6 = 0b to disable or 1b to enable feature.
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0b for normal or 1b for extended temperature range.
6. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0b.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 126 -
Table 40 – IDD0 Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
3, 4
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
...
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
0
0
0
0
0
-
...
Repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
1*nRC+1, 2
D, D
1
0
0
0
0
0
0
0
0
F
0
-
1*nRC+3, 4
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
...
Repeat pattern nRC + 1,...,4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS
PRE
0
0
1
0
0
0
0
0
0
F
0
-
...
Repeat pattern nRC + 1,...,4 until 2*nRC - 1, truncate if necessary
1
2*nRC
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 127 -
Table 41 – IDD1 Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
3, 4
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
...
Repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD
RD
0
1
0
1
0
0
0
0
0
0
0
00000000
...
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
0
0
0
0
0
-
...
Repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
1*nRC+1, 2
D, D
1
0
0
0
0
0
0
0
0
F
0
-
1*nRC+3, 4
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
...
Repeat pattern nRC + 1,...,4 until nRC + nRCD - 1, truncate if necessary
1*nRC+nRCD
RD
0
1
0
1
0
0
0
0
0
F
0
00110011
...
Repeat pattern nRC + 1,...,4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS
PRE
0
0
1
0
0
0
0
0
0
F
0
-
...
Repeat pattern nRC + 1,...,4 until 2*nRC - 1, truncate if necessary
1
2*nRC
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 128 -
Table 42 – IDD2N and IDD3N Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D#
1
1
1
1
0
0
0
0
0
F
0
-
3
D#
1
1
1
1
0
0
0
0
0
F
0
-
1
4-7
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-27
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Table 43 – IDD2NT and IDDQ2NT Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D#
1
1
1
1
0
0
0
0
0
F
0
-
3
D#
1
1
1
1
0
0
0
0
0
F
0
-
1
4-7
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-27
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 129 -
Table 44 – IDD4R and IDDQ4R Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
RD
0
1
0
1
0
0
0
0
0
0
0
00000000
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2, 3
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
4
RD
0
1
0
1
0
0
0
0
0
F
0
00110011
5
D
1
0
0
0
0
0
0
0
0
F
0
-
6, 7
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
1
8-15
Repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
Repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
Repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
Repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
Repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
Repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
Repeat Sub-Loop 0, but BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 45 – IDD4W Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
WR
0
1
0
0
1
0
0
0
0
0
0
00000000
1
D
1
0
0
0
1
0
0
0
0
0
0
-
2, 3
D#, D#
1
1
1
1
1
0
0
0
0
0
0
-
4
WR
0
1
0
0
1
0
0
0
0
F
0
00110011
5
D
1
0
0
0
1
0
0
0
0
F
0
-
6, 7
D#, D#
1
1
1
1
1
0
0
0
0
F
0
-
1
8-15
Repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
Repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
Repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
Repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
Repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
Repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
Repeat Sub-Loop 0, but BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 130 -
Table 46 – IDD5B Measurement-Loop Pattern1
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
3, 4
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
5...8
Repeat cycles 1...4, but BA[2:0] = 1
9...12
Repeat cycles 1...4, but BA[2:0] = 2
13...16
Repeat cycles 1...4, but BA[2:0] = 3
17...20
Repeat cycles 1...4, but BA[2:0] = 4
21...24
Repeat cycles 1...4, but BA[2:0] = 5
25...28
Repeat cycles 1...4, but BA[2:0] = 6
29...32
Repeat cycles 1...4, but BA[2:0] = 7
2
33...nRFC - 1
Repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 131 -
Table 47 – IDD7 Measurement-Loop Pattern1
ATTENTION: Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
CK, CK#
CKE
Sub-Loop
Cycle
Number
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[13:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2
toggling
Static High
0
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1
RDA
0
1
0
1
0
0
0
1
0
0
0
00000000
2
D
1
0
0
0
0
0
0
0
0
0
0
-
...
Repeat above D Command until nRRD - 1
1
nRRD
ACT
0
0
1
1
0
1
0
0
0
F
0
-
nRRD+1
RDA
0
1
0
1
0
1
0
1
0
F
0
00110011
nRRD+2
D
1
0
0
0
0
1
0
0
0
F
0
-
...
Repeat above D Command until 2 * nRRD -1
2
2*nRRD
Repeat Sub-Loop 0, but BA[2:0] = 2
3
3*nRRD
Repeat Sub-Loop 1, but BA[2:0] = 3
4
4*nRRD
D
1
0
0
0
0
3
0
0
0
F
0
-
Assert and repeat above D Command until nFAW - 1, if necessary
5
nFAW
Repeat Sub-Loop 0, but BA[2:0] = 4
6
nFAW+nRRD
Repeat Sub-Loop 1, but BA[2:0] = 5
7
nFAW+2*nRRD
Repeat Sub-Loop 0, but BA[2:0] = 6
8
nFAW+3*nRRD
Repeat Sub-Loop 1, but BA[2:0] = 7
9
nFAW+4*nRRD
D
1
0
0
0
0
7
0
0
0
F
0
-
Assert and repeat above D Command until 2 * nFAW - 1, if necessary
10
2*nFAW+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
2*nFAW+1
RDA
0
1
0
1
0
0
0
1
0
F
0
00110011
2*nFAW+2
D
1
0
0
0
0
0
0
0
0
F
0
-
Repeat above D Command until 2 * nFAW + nRRD - 1
11
2*nFAW+nRRD
ACT
0
0
1
1
0
1
0
0
0
0
0
-
2*nFAW+nRRD+1
RDA
0
1
0
1
0
1
0
1
0
0
0
00000000
2*nFAW+nRRD+2
D
1
0
0
0
0
1
0
0
0
0
0
-
Repeat above D Command until 2 * nFAW + 2 * nRRD -1
12
2*nFAW+2*nRRD
Repeat Sub-Loop 10, but BA[2:0] = 2
13
2*nFAW+3*nRRD
Repeat Sub-Loop 11, but BA[2:0] = 3
14
2*nFAW+4*nRRD
D
1
0
0
0
0
3
0
0
0
0
0
-
Assert and repeat above D Command until 3 * nFAW - 1, if necessary
15
3*nFAW
Repeat Sub-Loop 10, but BA[2:0] = 4
16
3*nFAW+nRRD
Repeat Sub-Loop 11, but BA[2:0] = 5
17
3*nFAW+2*nRRD
Repeat Sub-Loop 10, but BA[2:0] = 6
18
3*nFAW+3*nRRD
Repeat Sub-Loop 11, but BA[2:0] = 7
19
3*nFAW+4*nRRD
D
1
0
0
0
0
7
0
0
0
0
0
-
Assert and repeat above D Command until 4 * nFAW - 1, if necessary
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
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10.13.2 IDD Current Specifications
Speed Bin
DDR3-1333
DDR3-1600
DDR3-1866
SYM.
Part Number Extension
-15/15I
-12/12I
-11
UNIT
DEFINITION
MAX.
MAX.
MAX.
IDD0
Operating One Bank Active-Precharge Current
100
105
115
mA
IDD1
Operating One Bank Active-Read-Precharge Current
125
130
140
mA
IDD2N
Precharge Standby Current
65
70
80
mA
IDD2NT
Precharge Standby ODT Current
100
105
110
mA
IDD2P0
Precharge Power Down Current Slow Exit
19
19
19
mA
IDD2P1
Precharge Power Down Current Fast Exit
48
50
55
mA
IDD2Q
Precharge Quiet Standby Current
65
70
75
mA
IDD3N
Active Standby Current
70
75
80
mA
IDD3P
Active Power Down Current
55
60
65
mA
IDD4R
Operating Burst Read Current
235
250
280
mA
IDD4W
Operating Burst Write Current
200
220
250
mA
IDD5B
Burst Refresh Current
145
150
155
mA
IDD6
Self-Refresh Current, TOPER = 0 - 85°C
19
19
19
mA
IDD6ET
Self-Refresh Current, TOPER = 0 - 95°C
21
21
21
mA
IDD7
Operating Bank Interleave Read Current
370
380
400
mA
IDD8
RESET# Low Current
19
19
19
mA
Notes:
1. Max. values for IDD currents consider worst case conditions of process, temperature and voltage.
2. The IDD values must be derated (increased) when operated outside the range 0°C ≤ TCASE ≤ 85°C:
(a) When TCASE < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and
IDD6, IDD6ET and IDD7 must be derated by 7%.
(b) When TCASE > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by
2%; and IDD2P0, IDD2P1 must be derated by 30%.
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10.14 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the
min/max values may result in malfunction of the DDR3 SDRAM device.
Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where
each clock period is calculated from rising edge to rising edge.
tCK(avg) =
N
jj
tCK
1
/ N
where N = 200
Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
consecutive rising edge. tCK(abs) is not subject to production test.
Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
tCH(avg) =
N
jj
tCH
1
/ (N × tCK(avg))
where N = 200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low
pulses.
tCL(avg) =
N
jj
tCL
1
/ (N × tCK(avg))
where N = 200
Definition for tJIT(per) and tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
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Definition for tJIT(cc) and tJIT(cc,lck)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
tJIT(cc) = Max of |{tCKi +1 - tCKi}|.
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not
subject to production test.
10.15 Speed Bins
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRC and tRAS for each corresponding bin.
10.15.1 DDR3-1333 Speed Bin and Operating Conditions
Speed Bin
DDR3-1333
UNIT
NOTES
CL-nRCD-nRP
9-9-9
Part Number Extension
-15/15I
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
667
MHz
Internal read command to first data
tAA
13.5
(13.125) *9
20
nS
ACT to internal read or write delay time
tRCD
13.5
(13.125) *9
nS
PRE command period
tRP
13.5
(13.125) *9
nS
ACT to ACT or REF command period
tRC
49.5
(49.125) *9
nS
ACT to PRE command period
tRAS
36
9 * tREFI
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
nS
1, 2, 3, 4, 6
CWL = 6, 7
tCK(AVG)
Reserved
nS
5
CL = 7
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
1.875
< 2.5
nS
1, 2, 3, 4, 6
(Optional) *9
nS
CWL = 7
tCK(AVG)
Reserved
nS
5
CL = 8
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
1.875
< 2.5
nS
1, 2, 3, 4, 6
CWL = 7
tCK(AVG)
Reserved
nS
5
CL = 9
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
1.5
< 1.875
nS
1, 2, 3, 4, 6
CL = 10
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
1.5
< 1.875
nS
1, 2, 3, 4, 6
Supported CL Settings
Sup_CL
6, (7), 8, 9, 10
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7
nCK
Note:
Field value contents in blue font or parentheses are optional AC parameter and CL setting. Detail descriptions refer to note 9.
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10.15.2 DDR3-1600 Speed Bin and Operating Conditions
Speed Bin
DDR3-1600
UNIT
NOTES
CL-nRCD-nRP
11-11-11
Part Number Extension
-12/12I
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
800
MHz
Internal read command to first data
tAA
13.75
(13.125) *9
20
nS
ACT to internal read or write delay time
tRCD
13.75
(13.125) *9
nS
PRE command period
tRP
13.75
(13.125) *9
nS
ACT to ACT or REF command period
tRC
48.75
(48.125) *9
nS
ACT to PRE command period
tRAS
35
9 * tREFI
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
nS
1, 2, 3, 4, 7
CWL = 6, 7, 8
tCK(AVG)
Reserved
nS
5
CL = 7
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
1.875
< 2.5
nS
1, 2, 3, 4, 7
(Optional) *9
nS
5
CWL = 7, 8
tCK(AVG)
Reserved
nS
5
CL = 8
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
1.875
< 2.5
nS
1, 2, 3, 4, 7
CWL = 7, 8
tCK(AVG)
Reserved
nS
5
CL = 9
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
1.5
< 1.875
nS
5
(Optional) *9
nS
1, 2, 3, 4, 7
CWL = 8
tCK(AVG)
Reserved
nS
5
CL =10
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
1.5
< 1.875
nS
1, 2, 3, 4, 7
CWL = 8
tCK(AVG)
Reserved
nS
5
CL =11
CWL = 5, 6, 7
tCK(AVG)
Reserved
nS
5
CWL = 8
tCK(AVG)
1.25
< 1.5
nS
1, 2, 3, 4, 7
Supported CL Settings
Sup_CL
6, (7), 8, (9), 10, 11
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 8
nCK
Note:
Field value contents in blue font or parentheses are optional AC parameter and CL setting. Detail descriptions refer to note 9.
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10.15.3 DDR3-1866 Speed Bin and Operating Conditions
Speed Bin
DDR3-1866
UNIT
NOTES
CL-nRCD-nRP
13-13-13
Part Number Extension
-11
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
933
MHz
Internal read command to first data
tAA
13.91
20
nS
ACT to internal read or write delay time
tRCD
13.91
nS
PRE command period
tRP
13.91
nS
ACT to ACT or REF command period
tRC
47.91
nS
ACT to PRE command period
tRAS
34
9 * tREFI
nS
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
nS
1, 2, 3, 4, 8
CWL = 6, 7, 8, 9
tCK(AVG)
Reserved
nS
5
CL = 8
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
1.875
< 2.5
nS
1, 2, 3, 4, 8
CWL = 7, 8, 9
tCK(AVG)
Reserved
nS
5
CL =10
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
1.5
< 1.875
nS
1, 2, 3, 4, 8
CWL = 8, 9
tCK(AVG)
Reserved
nS
5
CL =13
CWL = 5, 6, 7, 8
tCK(AVG)
Reserved
nS
5
CWL = 9
tCK(AVG)
1.07
< 1.25
nS
1, 2, 3, 4, 8
Supported CL Settings
Sup_CL
6, 8, 10, 13
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 9
nCK
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10.15.4 Speed Bin General Notes
The absolute specification for all speed bins is TOPER and VDD = VDDQ = 1.5V ± 0.075V. In addition
the following general notes apply.
1. Max. limits are exclusive. E.g. if tCK(AVG).MAX value is 2.5 nS, tCK(AVG) needs to be < 2.5 nS.
2. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making
a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
3. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An
application should use the next smaller standard tCK(AVG) value (2.5, 1.875, 1.5, 1.25 nS or 1.07 nS)
when calculating CL [nCK] = tAA [nS] / tCK(AVG) [nS], rounding up to the next ‘Supported CL’.
4. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3nS or 2.5nS or 1.875 nS or 1.25 nS). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
5. ‘Reserved’ settings are not allowed. User must program a different value.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125
nS or lower. SPD settings must be programmed to match. For example, DDR3-1333 (9-9-9) devices
supporting down binning to DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11) devices supporting
down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes
for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to
13.125 nS, tRCmin (Byte 21, 23) also should be programmed accodingly. For example, 49.125nS
(tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333 (9-9-9) and 48.125 nS (tRASmin + tRPmin =
35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
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10.16 AC Characteristics
10.16.1 AC Timing and Operating Condition for -11 speed grade
SYMBOL
SPEED GRADE
DDR3-1866 (-11)
UNITS
NOTES
PARAMETER
MIN.
MAX.
Common Notes
1, 2, 3, 4
Clock Input Timing
tCK(DLL-off)
Minimum clock cycle time (DLL-off mode)
8
nS
45
tCK(avg)
Average Clock Period
See “Speed Bin” on page 136
pS
tCH(avg)
Average CK/CK# high pulse width
0.47
0.53
tCK(avg)
tCL(avg)
Average CK/CK# low pulse width
0.47
0.53
tCK(avg)
tCK(abs)
Absolute Clock Period
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
pS
37
tCH(abs)
Absolute CK/CK# high pulse width
0.43
tCK(avg)
38
tCL(abs)
Absolute CK/CK# low pulse width
0.43
tCK(avg)
39
tJIT(per)
Clock Period Jitter
-60
60
pS
tJIT(per,lck)
Clock Period Jitter during DLL locking period
-50
50
pS
tJIT(cc)
Cycle to Cycle Period Jitter
120
pS
tJIT(cc,lck)
Cycle to Cycle Period Jitter during DLL locking
period
100
pS
tJIT(duty)
Clock Duty Cycle Jitter
Already included in tCH(abs) and
tCL(abs)
pS
tERR(2per)
Cumulative error across 2 cycles
-88
88
pS
tERR(3per)
Cumulative error across 3 cycles
-105
105
pS
tERR(4per)
Cumulative error across 4 cycles
-117
117
pS
tERR(5per)
Cumulative error across 5 cycles
-126
126
pS
tERR(6per)
Cumulative error across 6 cycles
-133
133
pS
tERR(7per)
Cumulative error across 7 cycles
-139
139
pS
tERR(8per)
Cumulative error across 8 cycles
-145
145
pS
tERR(9per)
Cumulative error across 9 cycles
-150
150
pS
tERR(10per)
Cumulative error across 10 cycles
-154
154
pS
tERR(11per)
Cumulative error across 11 cycles
-158
158
pS
tERR(12per)
Cumulative error across 12 cycles
-161
161
pS
tERR(nper)
Cumulative error across n = 13, 14...49, 50
cycles
Min.: tJIT(per)min * (1 + 0.68 * ln(n))
Max.: tJIT(per)max * (1 + 0.68 * ln(n))
pS
7
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AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
DDR3-1866 (-11)
UNITS
NOTES
PARAMETER
MIN.
MAX.
Data Timing
tDQSQ
DQS, DQS# to DQ skew, per group, per access
85
pS
23
tQH
DQ output hold time from DQS, DQS#
0.38
tCK(avg)
18, 23
tLZ(DQ)
DQ low impedance time from CK, CK#
-390
195
pS
17, 23, 24
tHZ(DQ)
DQ high impedance time from CK, CK#
195
pS
17, 23, 24
tDS(AC135)
Data setup time to
DQS, DQS#
Base specification @ 2 V/nS
68
pS
11, 40
VREF @ 2 V/nS
135.5
pS
11, 40, 42
tDH(DC100)
Data hold time from
DQS, DQS#
Base specification @ 2 V/nS
70
pS
11, 40
VREF @ 2 V/nS
120
pS
11, 40, 42
tDIPW
DQ and DM Input pulse width for each input
320
pS
10
Data Strobe Timing
tRPRE
DQS,DQS# differential READ Preamble
0.9
Note 21
tCK(avg)
18, 21, 23
tRPST
DQS,DQS# differential READ Postamble
0.3
Note 22
tCK(avg)
18, 22, 23
tQSH
DQS,DQS# differential output high time
0.4
tCK(avg)
18, 23
tQSL
DQS,DQS# differential output low time
0.4
tCK(avg)
18, 23
tWPRE
DQS,DQS# differential WRITE Preamble
0.9
tCK(avg)
46
tWPST
DQS,DQS# differential WRITE Postamble
0.3
tCK(avg)
46
tDQSCK
DQS,DQS# rising edge output access time from
rising CK, CK#
-195
195
pS
17, 23
tLZ(DQS)
DQS and DQS# low-impedance time from CK,
CK# (Referenced from RL - 1)
-390
195
pS
17, 23, 24
tHZ(DQS)
DQS and DQS# high-impedance time from CK,
CK# (Referenced from RL + BL/2)
195
pS
17, 23, 24
tDQSL
DQS,DQS# differential input low pulse width
0.45
0.55
tCK(avg)
12, 14
tDQSH
DQS,DQS# differential input high pulse width
0.45
0.55
tCK(avg)
13, 14
tDQSS
DQS,DQS# rising edge to CK,CK# rising edge
-0.27
0.27
tCK(avg)
16
tDSS
DQS,DQS# falling edge setup time to CK,CK#
rising edge
0.18
tCK(avg)
15, 16
tDSH
DQS,DQS# falling edge hold time from CK,CK#
rising edge
0.18
tCK(avg)
15, 16
Command and Address Timing
tAA
Internal read command to first data
See “Speed Bin” on page 136
nS
8
tRCD
ACT to internal read or write delay time
nS
8
tRP
PRE command period
nS
8
tRC
ACT to ACT or REF command period
nS
8
tRAS
ACT to PRE command period
nS
8
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AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
DDR3-1866 (-11)
UNITS
NOTES
PARAMETER
MIN.
MAX.
Command and Address Timing
tDLLK
DLL locking time
512
nCK
tRTP
Internal READ Command to PRECHARGE
Command delay
max(4nCK, 7.5nS)
8
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK, 7.5nS)
8, 26
tWR
WRITE recovery time
15
nS
8, 26
tMRD
Mode Register Set command cycle time
4
nCK
tMOD
Mode Register Set command update delay
max(12nCK, 15nS)
tCCD
CAS# to CAS# command delay
4
nCK
tDAL(min)
Auto precharge write recovery + precharge time
WR + roundup(tRP(min)/ tCK(avg))
nCK
6
tMPRR
Multi-Purpose Register Recovery Time
1
nCK
29
tRRD
ACTIVE to ACTIVE command period for 2KB page
size
max(4nCK, 6nS)
8
tFAW
Four activate window for 2KB page size
35
nS
8
tIS(AC135)
Command and Address
setup time to CK, CK#
Base specification
65
pS
9, 41
VREF @ 1 V/nS
200
pS
9, 41, 42
tIS(AC125)
Command and Address
setup time to CK, CK#
Base specification
150
pS
9, 41
VREF @ 1 V/nS
275
pS
9, 41, 42
tIH(DC100)
Command and Address
hold time from CK, CK#
Base specification
100
pS
9, 41
VREF @ 1 V/nS
200
pS
9, 41, 42
tIPW
Control and Address input pulse width for each
input
535
pS
10
Calibration Timing
tZQinit
Power-up and RESET calibration time
max(512nCK, 640nS)
tZQoper
Normal operation Full calibration time
max(256nCK, 320nS)
tZQCS
Normal operation Short calibration time
max(64nCK, 80nS)
33
Reset Timing
tXPR
Exit Reset from CKE HIGH to a valid command
max(5nCK, 170nS)
Self Refresh Timing
tXS
Exit Self Refresh to commands not requiring a
locked DLL
max(5nCK, 170nS)
34
tXSDLL
Exit Self Refresh to commands requiring a locked
DLL
tDLLK(min)
nCK
35
tCKESR
Minimum CKE low width for Self Refresh entry to
exit timing
tCKE(min) + 1nCK
tCKSRE
Valid Clock Requirement after Self Refresh Entry
(SRE)
max(5 nCK, 10nS)
tCKSRX
Valid Clock Requirement before Self Refresh Exit
(SRX)
max(5 nCK, 10nS)
Refresh Timing
tRFC
REF command to ACT or REF command time
160
nS
36
tREFI
Average periodic
refresh Interval
0°C ≤ TCASE ≤ 85°C
7.8
μS
85°C < TCASE ≤ 95°C
3.9
μS
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 141 -
AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
DDR3-1866 (-11)
UNITS
NOTES
PARAMETER
MIN.
MAX.
Power Down Timing
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK, 6nS)
34
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK, 24nS)
35
tCKE
CKE minimum pulse width
max(3nCK, 5nS)
tCPDED
Command pass disable delay
2
nCK
tPD
Power Down Entry to Exit Timing
tCKE(min)
9 * tREFI
25
tACTPDEN
Timing of ACT command to Power Down entry
1
nCK
27
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
1
nCK
27
tRDPDEN
Timing of RD/RDA command to Power Down entry
RL + 4 + 1
nCK
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + WR + 1
Max.:
nCK
19
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 + WR + 1
Max.:
nCK
19
tREFPDEN
Timing of REF command to Power Down entry
1
nCK
27, 28
tMRSPDEN
Timing of MRS command to Power Down entry
tMOD(min)
ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4
nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6
nCK
31
tAONPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
2
8.5
nS
32
tAOFPD
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
nS
32
tAON
RTT turn-on
-195
195
pS
17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
tCK(avg)
17, 44
tADC
RTT dynamic change skew
0.3
0.7
tCK(avg)
17
Write Leveling Timing
tWLMRD
First DQS/DQS# rising edge after write leveling
mode is programmed
40
nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25
nCK
5
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
140
pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
140
pS
tWLO
Write leveling output delay
0
7.5
nS
tWLOE
Write leveling output error
0
2
nS
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 142 -
10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades
SYMBOL
SPEED GRADE
DDR3-1600
(-12/12I)
DDR3-1333
(-15/15I)
UNITS
NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
Common Notes
1, 2, 3, 4
Clock Input Timing
tCK(DLL-off)
Minimum clock cycle time (DLL-off mode)
8
8
nS
45
tCK(avg)
Average Clock Period
See “Speed Bin” on
page 135
See “Speed Bin” on
page 134
pS
tCH(avg)
Average CK/CK# high pulse width
0.47
0.53
0.47
0.53
tCK(avg)
tCL(avg)
Average CK/CK# low pulse width
0.47
0.53
0.47
0.53
tCK(avg)
tCK(abs)
Absolute Clock Period
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
pS
37
tCH(abs)
Absolute CK/CK# high pulse width
0.43
0.43
tCK(avg)
38
tCL(abs)
Absolute CK/CK# low pulse width
0.43
0.43
tCK(avg)
39
tJIT(per)
Clock Period Jitter
-70
70
-80
80
pS
tJIT(per,lck)
Clock Period Jitter during DLL locking period
-60
60
-70
70
pS
tJIT(cc)
Cycle to Cycle Period Jitter
140
160
pS
tJIT(cc,lck)
Cycle to Cycle Period Jitter during DLL locking
period
120
140
pS
tJIT(duty)
Clock Duty Cycle Jitter
Already included in tCH(abs) and tCL(abs)
pS
tERR(2per)
Cumulative error across 2 cycles
-103
103
-118
118
pS
tERR(3per)
Cumulative error across 3 cycles
-122
122
-140
140
pS
tERR(4per)
Cumulative error across 4 cycles
-136
136
-155
155
pS
tERR(5per)
Cumulative error across 5 cycles
-147
147
-168
168
pS
tERR(6per)
Cumulative error across 6 cycles
-155
155
-177
177
pS
tERR(7per)
Cumulative error across 7 cycles
-163
163
-186
186
pS
tERR(8per)
Cumulative error across 8 cycles
-169
169
-193
193
pS
tERR(9per)
Cumulative error across 9 cycles
-175
175
-200
200
pS
tERR(10per)
Cumulative error across 10 cycles
-180
180
-205
205
pS
tERR(11per)
Cumulative error across 11 cycles
-184
184
-210
210
pS
tERR(12per)
Cumulative error across 12 cycles
-188
188
-215
215
pS
tERR(nper)
Cumulative error across n = 13, 14...49, 50
cycles
Min.: tJIT(per)min * (1 + 0.68 * ln(n))
Max.: tJIT(per)max * (1 + 0.68 * ln(n))
pS
7
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 143 -
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SYMBOL
SPEED GRADE
DDR3-1600
(-12/12I)
DDR3-1333
(-15/15I)
UNITS
NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
Data Timing
tDQSQ
DQS, DQS# to DQ skew, per group, per access
100
125
pS
23
tQH
DQ output hold time from DQS, DQS#
0.38
0.38
tCK(avg)
18, 23
tLZ(DQ)
DQ low impedance time from CK, CK#
-450
225
-500
250
pS
17, 23, 24
tHZ(DQ)
DQ high impedance time from CK, CK#
225
250
pS
17, 23, 24
tDS(AC150)
Data setup time to
DQS, DQS#
Base specification
10
30
pS
11, 40
VREF @ 1 V/nS
160
180
11, 40, 42
tDH(DC100)
Data hold time from
DQS, DQS#
Base specification
45
65
pS
11, 40
VREF @ 1 V/nS
145
165
11, 40, 42
tDIPW
DQ and DM input pulse width for each input
360
400
pS
10
Data Strobe Timing
tRPRE
DQS,DQS# differential READ Preamble
0.9
Note 21
0.9
Note 21
tCK(avg)
18, 21, 23
tRPST
DQS,DQS# differential READ Postamble
0.3
Note 22
0.3
Note 22
tCK(avg)
18, 22, 23
tQSH
DQS,DQS# differential output high time
0.4
0.4
tCK(avg)
18, 23
tQSL
DQS,DQS# differential output low time
0.4
0.4
tCK(avg)
18, 23
tWPRE
DQS,DQS# differential WRITE Preamble
0.9
0.9
tCK(avg)
46
tWPST
DQS,DQS# differential WRITE Postamble
0.3
0.3
tCK(avg)
46
tDQSCK
DQS,DQS# rising edge output access time from
rising CK, CK#
-225
225
-255
255
pS
17, 23
tLZ(DQS)
DQS and DQS# low-impedance time from
CK, CK# (Referenced from RL - 1)
-450
225
-500
250
pS
17, 23, 24
tHZ(DQS)
DQS and DQS# high-impedance time from
CK, CK# (Referenced from RL + BL/2)
225
250
pS
17, 23, 24
tDQSL
DQS,DQS# differential input low pulse width
0.45
0.55
0.45
0.55
tCK(avg)
12, 14
tDQSH
DQS,DQS# differential input high pulse width
0.45
0.55
0.45
0.55
tCK(avg)
13, 14
tDQSS
DQS,DQS# rising edge to CK,CK# rising edge
-0.27
0.27
-0.25
0.25
tCK(avg)
16
tDSS
DQS,DQS# falling edge setup time to CK,CK#
rising edge
0.18
0.2
tCK(avg)
15, 16
tDSH
DQS,DQS# falling edge hold time from CK,CK#
rising edge
0.18
0.2
tCK(avg)
15, 16
Command and Address Timing
tAA
Internal read command to first data
See “Speed Bin” on
page 135
See “Speed Bin” on
page 134
nS
8
tRCD
ACT to internal read or write delay time
nS
8
tRP
PRE command period
nS
8
tRC
ACT to ACT or REF command period
nS
8
tRAS
ACT to PRE command period
nS
8
tDLLK
DLL locking time
512
512
nCK
tRTP
Internal READ Command to PRECHARGE
Command delay
max(4nCK,
7.5nS)
max(4nCK,
7.5nS)
8
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK,
7.5nS)
max(4nCK,
7.5nS)
8, 26
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 144 -
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SYMBOL
SPEED GRADE
DDR3-1600
(-12/12I)
DDR3-1333
(-15/15I)
UNITS
NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
Command and Address Timing
tWR
WRITE recovery time
15
15
nS
8, 26
tMRD
Mode Register Set command cycle time
4
4
nCK
tMOD
Mode Register Set command update delay
max(12nCK,
15nS)
max(12nCK,
15nS)
tCCD
CAS# to CAS# command delay
4
4
nCK
tDAL(min)
Auto precharge write recovery + precharge
time
WR + roundup(tRP(min)/ tCK(avg))
nCK
6
tMPRR
Multi-Purpose Register Recovery Time
1
1
nCK
29
tRRD
ACTIVE to ACTIVE command period for 2KB
page size
max(4nCK,
7.5nS)
max(4nCK,
7.5nS)
8
tFAW
Four activate window for 2KB page size
40
45
nS
8
tIS(AC175)
Command and Address
setup time to CK, CK#
Base specification
45
65
pS
9, 41
VREF @ 1 V/nS
220
240
pS
9, 41, 42
tIS(AC150)
Command and Address
setup time to CK, CK#
Base specification
170
190
pS
9, 41
VREF @ 1 V/nS
320
340
pS
9, 41, 42
tIH(DC100)
Command and Address
hold time from CK, CK#
Base specification
120
140
pS
9, 41
VREF @ 1 V/nS
220
240
pS
9, 41, 42
tIPW
Control, address and control input pulse width
for each input
560
620
pS
10
Calibration Timing
tZQinit
Power-up and RESET calibration time
max(512nCK,
640nS)
max(512nCK,
640nS)
tZQoper
Normal operation Full calibration time
max(256nCK,
320nS)
max(256nCK,
320nS)
tZQCS
Normal operation Short calibration time
max(64nCK,
80nS)
max(64nCK,
80nS)
33
Reset Timing
tXPR
Exit Reset from CKE HIGH to a valid
command
max(5nCK,
170nS)
max(5nCK,
170nS)
Self Refresh Timing
tXS
Exit Self Refresh to commands not requiring a
locked DLL
max(5nCK,
170nS)
max(5nCK,
170nS)
34
tXSDLL
Exit Self Refresh to commands requiring a
locked DLL
tDLLK(min)
tDLLK(min)
nCK
35
tCKESR
Minimum CKE low width for Self Refresh entry
to exit timing
tCKE(min) +
1nCK
tCKE(min) +
1nCK
tCKSRE
Valid Clock Requirement after Self Refresh
Entry (SRE)
max(5 nCK,
10nS)
max(5 nCK,
10nS)
tCKSRX
Valid Clock Requirement before Self Refresh
Exit (SRX)
max(5 nCK,
10nS)
max(5 nCK,
10nS)
Refresh Timing
tRFC
REF command to ACT or REF command time
160
160
nS
36
tREFI
Average periodic
refresh Interval
-40°C ≤ TCASE ≤ 85°C*
7.8
7.8
μS
0°C ≤ TCASE ≤ 85°C
7.8
7.8
μS
85°C < TCASE ≤ 95°C
3.9
3.9
μS
* -40°C ≤ TCASE ≤ 85°C is for 12I and 15I grade only.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 145 -
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SYMBOL
SPEED GRADE
DDR3-1600
(-12/12I)
DDR3-1333
(-15/15I)
UNITS
NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
Power Down Timing
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
6nS)
max(3nCK,
6nS)
34
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24nS)
max(10nCK,
24nS)
35
tCKE
CKE minimum pulse width
max(3nCK,
5nS)
max(3nCK,
5.625nS)
tCPDED
Command pass disable delay
1
1
nCK
tPD
Power Down Entry to Exit Timing
tCKE(min)
9 * tREFI
tCKE(min)
9 * tREFI
25
tACTPDEN
Timing of ACT command to Power Down entry
1
1
nCK
27
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
1
1
nCK
27
tRDPDEN
Timing of RD/RDA command to Power Down entry
RL + 4 + 1
RL + 4 + 1
nCK
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + WR + 1
Max.:
nCK
19
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 + WR + 1
Max.:
nCK
19
tREFPDEN
Timing of REF command to Power Down entry
1
1
nCK
27, 28
tMRSPDEN
Timing of MRS command to Power Down entry
tMOD(min)
tMOD(min)
ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4
4
nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6
6
nCK
31
tAONPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
2
8.5
2
8.5
nS
32
tAOFPD
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
2
8.5
nS
32
tAON
RTT turn-on
-225
225
-250
250
pS
17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
0.3
0.7
tCK(avg)
17, 44
tADC
RTT dynamic change skew
0.3
0.7
0.3
0.7
tCK(avg)
17
Write Leveling Timing
tWLMRD
First DQS/DQS# rising edge after write leveling
mode is programmed
40
40
nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25
25
nCK
5
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
165
195
pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
165
195
pS
tWLO
Write leveling output delay
0
7.5
0
9
nS
tWLOE
Write leveling output error
0
2
0
2
nS
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 146 -
10.16.3 Timing Parameter Notes
1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.
For example, tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) +
tERR(4per),min (which is smaller than 4 x tCK(avg)).
2. Timing that is not specified is illegal and after such an event, in order to provide proper operation, the
DRAM must be resetted or powered down and then restarted through the specified initialization
sequence before normal operation can continue.
3. The CK/CK# input reference level (for timing reference to CK / CK#) is the point at which CK and CK#
cross.
The DQS/DQS# input reference level is the point at which DQS and DQS# cross;
The input reference level for signals other than CK/CK#, DQS/DQS# and RESET# is VREFCA and
VREFDQ respectively.
4. Inputs are not recognized as valid until VREFCA stabilizes within specified limits.
5. The max values are system dependent.
6. tCK(avg) refers to the actual application clock period. WR refers to the WR parameter stored in mode
register MR0.
7. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
8. For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [nS] / tCK(avg)
[nS] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR3-1333 (9-9-9), of which tRP = 13.5nS, the device will
support tnRP = RU{tRP / tCK(avg)} = 9, as long as the input clock jitter specifications are met, i.e.
Precharge command at Tm and Active command at Tm+9 is valid even if (Tm+9 - Tm) is less than
13.5nS due to input clock jitter.
9. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are
not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are
relative to the clock signal crossing that latches the command/address. That is, these parameters
should be met whether clock jitter is present or not.
10. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the
consecutive crossing of VREF(DC).
11. These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition
edge to its respective data strobe signal (DQS(L/U), DQS(L/U)#) crossing.
12. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from
one falling edge to the next consecutive rising edge.
13. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured
from one rising edge to the next consecutive falling edge.
14. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
15. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
16. These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)#) crossing to its
respective clock signal (CK, CK#) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these
parameters should be met whether clock jitter is present or not.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 147 -
17. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 ≤ m ≤ 12. (output deratings are relative to the actual SDRAM
input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has tERR(mper),act,min = - 138 pS and
tERR(mper),act,max = + 155 pS, then
tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 255 pS - 155 pS = - 410 pS and
tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 255 pS + 138 pS = + 393 pS.
Similarly, tLZ(DQ) for DDR3-1333 derates to tLZ(DQ),min(derated) = - 500 pS - 155 pS = - 655 pS and
tLZ(DQ),max(derated) = 250 pS + 138 pS = + 388 pS. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 ≤ n ≤ 12, and
tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 ≤ n ≤ 12.
18. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has tCK(avg),act = 1500 pS,
tJIT(per),act,min = - 58 pS and tJIT(per),act,max = + 74 pS, then
tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 1500
pS - 58 pS = + 1292 pS.
Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x
1500 pS - 58 pS = + 512 pS. (Caution on the min/max usage!).
19. WR in clock cycles as programmed in mode register MR0.
20. tWR(min) is defined in nS, for calculation of tWRPDEN it is necessary to round up tWR(min)/tCK(avg) to the
next integer value.
21. The maximum read preamble is bound by tLZ(DQS)min on the left side and tDQSCK(max) on the right side.
See Figure 24 - “READ Timing; Clock to Data Strobe relationship” on page 45.
22. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max
on the right side. See Figure 24 - “READ Timing; Clock to Data Strobe relationship” on page 45.
23. Value is only valid for RON34.
24. Single ended signal parameter.
25. tREFI depends on TOPER.
26. Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
27. CKE is allowed to be registered low while operations such as row activation, precharge, auto-precharge
or refresh are in progress, but power down IDD spec will not be applied until finishing those operations.
28. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is
satisfied, there are cases where additional time such as tXPDLL(min) is also required. See section 8.17.3
“Power-Down clarifications - Case 2” on page 75.
29. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
30. ODTH4 is measured from ODT first registered high (without a Write command) to ODT first registered
low, or from ODT registered high together with a Write command with burst length 4 to ODT registered
low.
31. ODTH8 is measured from ODT registered high together with a Write command with burst length 8 to
ODT registered low.
32. This parameter applies upon entry and during precharge power down mode with DLL frozen.
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33. One ZQCS command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and RTT
impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the
‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’
tables. The appropriate interval between ZQCS commands can be determined from these tables and
other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate)
and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The
interval could be defined by the following formula:
)Vdriftrate × (VSens+)Tdriftrate × (TSens onZQCorrecti
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
For example, if TSens = 1.5% / C, VSens = 0.15% / mV, Tdriftrate = 1 C / sec and Vdriftrate = 15
mV/sec, then the interval between ZQCS commands is calculated as:
15) × (0.15+1) × (1.5 0.5
= 0.133 ≈ 128mS
34. Commands not requiring a locked DLL are all commands except Read, Read with Auto-Precharge and
Synchronous ODT.
35. Commands requiring a locked DLL are Read, Read with Auto-Precharge and Synchronous ODT.
36. A maximum of one regular plus eight posted refresh commands can be issued to any given DDR3
SDRAM device meaning that the maximum absolute interval between any refresh command and the
next refresh command is 9 ×tREFI.
37. Parameter tCK(avg) is specified per its average value. However, it is understood that the relationship
between the average timing tCK(avg) and the respective absolute instantaneous timing tCK(abs) holds
all times.
38. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the
following falling edge.
39. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the
following rising edge.
40. tDS(base) and tDH(base) values are for a single-ended 1V/nS slew rate DQs (DQs are at 2V/nS for
DDR3-1866) and 2V/nS DQS, DQS# differential slew rate. Note for DQ and DM signals, VREF(DC) =
VREFDQ(DC). For input only pins except RESET#, VREF(DC) = VREFCA(DC). See section 10.16.5 “Data
Setup, Hold and Slew Rate Derating” on page 156.
41. tIS(base) and tIH(base) values are for 1V/nS CMD/ADD single-ended slew rate and 2V/nS CK, CK#
differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except
RESET#, VREF(DC) = VREFCA(DC). See section 10.16.4 “Address / Command Setup, Hold and
Derating” on page 149.
42. The setup and hold times are listed converting the base specification values (to which derating tables
apply) to VREF when the slew rate is 1 V/nS (DQs are at 2V/nS for DDR3-1866). These values, with a
slew rate of 1 V/nS (DQs are at 2V/nS for DDR3-1866), are for reference only.
43. For definition of RTT turn-on time tAON See 8.19.2.2 “Timing Parameters” on page 80.
44. For definition of RTT turn-off time tAOF See 8.19.2.2 “Timing Parameters” on page 80.
45. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
46. Actual value dependant upon measurement level definitions See Figure 41 - “Method for calculating
tWPRE transitions and endpoints” on page 58 and See Figure 42 - “Method for calculating tWPST
transitions and endpoints” on page 58.
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10.16.4 Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the
datasheet tIS(base) and tIH(base) value (see Table 48) to the ΔtIS and ΔtIH derating value (see Table 49
to Table 52) respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(DC) to AC
region’, use nominal slew rate for derating value (see Figure 107). If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to VREF(DC) level is used for derating value (see Figure 109).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual
signal is always later than the nominal slew rate line between shaded ‘DC to VREF(DC) region’, use
nominal slew rate for derating value (see Figure 108). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a tangent line to the
actual signal from the DC level to VREF(DC) level is used for derating value (see Figure 110).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 53).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached VIH/IL(AC) at the time of the rising clock transition, a valid input signal is still required to
complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization. Table 48 – ADD/CMD Setup and Hold Base-Values for 1V/nS
Symbol
Reference
DDR3-1333
DDR3-1600
DDR3-1866
Unit
tIS(base) AC175
VIH/L(AC)
65
45
-
pS
tIS(base) AC150
VIH/L(AC)
190
170
-
pS
tIS(base) AC135
VIH/L(AC)
-
-
65
pS
tIS(base) AC125
VIH/L(AC)
-
-
150
pS
tIH(base) DC100
VIH/L(DC)
140
120
100
pS
Notes:
1. (AC/DC referenced for 1V/nS Address/Command slew rate and 2 V/nS differential CK-CK# slew rate)
2. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 100pS for
DDR3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mV and another 25 pS to account for
the earlier reference point [(175 mV - 150 mV) / 1 V/nS].
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75pS for
DDR3-1866 of derating to accommodate for the lower alternate threshold of 125 mV and another 10 pS to account for the
earlier reference point [(135 mV - 125 mV) / 1 V/nS].
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Table 49 – Derating values DDR3-1333/1600 tIS/tIH - AC/DC based AC175 Threshold
CMD/
ADD
Slew
rate
(V/nS)
ΔtIS, ΔtIH derating in [pS] AC/DC based
AC175 Threshold -> VIH(AC)=VREF(DC)+175mV, VIL(AC)=VREF(DC)-175mV
CK, CK# Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
88
50
88
50
88
50
96
58
104
66
112
74
120
84
128
100
1.5
59
34
59
34
59
34
67
42
75
50
83
58
91
68
99
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-2
-4
-2
-4
-2
-4
6
4
14
12
22
20
30
30
38
46
0.8
-6
-10
-6
-10
-6
-10
2
-2
10
6
18
14
26
24
34
40
0.7
-11
-16
-11
-16
-11
-16
-3
-8
5
0
13
8
21
18
29
34
0.6
-17
-26
-17
-26
-17
-26
-9
-18
-1
-10
7
-2
15
8
23
24
0.5
-35
-40
-35
-40
-35
-40
-27
-32
-19
-24
-11
-16
-2
-6
5
10
0.4
-62
-60
-62
-60
-62
-60
-54
-52
-46
-44
-38
-36
-30
-26
-22
-10
Table 50 – Derating values DDR3-1333/1600 tIS/tIH - AC/DC based - Alternate AC150 Threshold
CMD/
ADD
Slew
rate
(V/nS)
ΔtIS, ΔtIH derating in [pS] AC/DC based
Alternate AC150 Threshold -> VIH(AC)=VREF(DC)+150mV, VIL(AC)=VREF(DC)-150mV
CK, CK# Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
0
-4
0
-4
0
-4
8
4
16
12
24
20
32
30
40
46
0.8
0
-10
0
-10
0
-10
8
-2
16
6
24
14
32
24
40
40
0.7
0
-16
0
-16
0
-16
8
-8
16
0
24
8
32
18
40
34
0.6
-1
-26
-1
-26
-1
-26
7
-18
15
-10
23
-2
31
8
39
24
0.5
-10
-40
-10
-40
-10
-40
-2
-32
6
-24
14
-16
22
-6
30
10
0.4
-25
-60
-25
-60
-25
-60
-17
-52
-9
-44
-1
-36
7
-26
15
-10
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Table 51 – Derating values DDR3-1866 tIS/tIH - AC/DC based Alternate AC135 Threshold
CMD/
ADD
Slew
rate
(V/nS)
ΔtIS, ΔtIH derating in [pS] AC/DC based
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
CK, CK# Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
68
50
68
50
68
50
76
58
84
66
92
74
100
84
108
100
1.5
45
34
45
34
45
34
53
42
61
50
69
58
77
68
85
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
-4
2
-4
2
-4
10
4
18
12
26
20
34
30
42
46
0.8
3
-10
3
-10
3
-10
11
-2
19
6
27
14
35
24
43
40
0.7
6
-16
6
-16
6
-16
14
-8
22
0
30
8
38
18
46
34
0.6
9
-26
9
-26
9
-26
17
-18
25
-10
33
-2
41
8
49
24
0.5
5
-40
5
-40
5
-40
13
-32
21
-24
29
-16
37
-6
45
10
0.4
-3
-60
-3
-60
-3
-60
6
-52
14
-44
22
-36
30
-26
38
-10
Table 52 – Derating values DDR3-1866 tIS/tIH - AC/DC based Alternate AC125 Threshold
CMD/
ADD
Slew
rate
(V/nS)
ΔtIS, ΔtIH derating in [pS] AC/DC based
Alternate AC125 Threshold -> VIH(AC)=VREF(DC)+125mV, VIL(AC)=VREF(DC)-125mV
CK, CK# Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
63
50
63
50
63
50
71
58
79
66
87
74
95
84
103
100
1.5
42
34
42
34
42
34
50
42
58
50
66
58
74
68
82
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
4
-4
4
-4
4
-4
12
4
20
12
28
20
36
30
44
46
0.8
6
-10
6
-10
6
-10
14
-2
22
6
30
14
38
24
46
40
0.7
11
-16
11
-16
11
-16
19
-8
27
0
35
8
43
18
51
34
0.6
16
-26
16
-26
16
-26
24
-18
32
-10
40
-2
48
8
56
24
0.5
15
-40
15
-40
15
-40
23
-32
31
-24
39
-16
47
-6
55
10
0.4
13
-60
13
-60
13
-60
21
-52
29
-44
37
-36
45
-26
53
-10
Table 53 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid ADD/CMD transition
Slew Rate
[V/nS]
DDR3-1333/1600
DDR3-1866
tVAC @ 175mV [pS]
tVAC @ 150mV [pS]
tVAC @ 135mV [pS]
tVAC @ 125mV [pS]
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
> 2.0
75
-
175
-
168
-
173
-
2.0
57
-
170
-
168
-
173
-
1.5
50
-
167
-
145
-
152
-
1.0
38
-
130
-
100
-
110
-
0.9
34
-
113
-
85
-
96
-
0.8
29
-
93
-
66
-
79
-
0.7
22
-
66
-
42
-
56
-
0.6
Note
-
30
-
10
-
27
-
0.5
Note
-
Note
-
Note
-
Note
-
< 0.5
Note
-
Note
Note
-
Note
-
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or
less than VIL(AC) level.
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CK
CK#
DQS#
DQS
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
tIS tIH tIS tIH
tVAC
nominal
slew rate
VREF to AC
region
nominal
slew rate
VREF to AC
region
tVAC
ΔTF ΔTR
Setup Slew Rate
Falling Signal =VREF(DC) – VIL(AC)max
ΔTF Setup Slew Rate
Rising Signal =VIH(AC)min - VREF(DC)
ΔTR
tDS tDH tDS tDH
Note: Clock and Strobe are drawn
on a different time scale.
Figure 107 – Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to
strobe) and tIS (for ADD/CMD with respect to clock)
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VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
tIS tIH tIS tIH
nominal
slew rate
DC to VREF
region
nominal
slew rate
DC to VREF
region
ΔTF
ΔTR
tDS tDH tDS tDH
Note: Clock and Strobe are drawn
on a different time scale.
Hold Slew Rate
Rising Signal =VREF(DC) – VIL(DC)max
ΔTR Hold Slew Rate
Falling Signal =VIH(DC)min - VREF(DC)
ΔTF
CK
CK#
DQS#
DQS
Figure 108 – Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe)
and tIH (for ADD/CMD with respect to clock)
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VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
ΔTF
ΔTR
VREF to AC
region
VREF to AC
region
tangent
line
tangent
line
nominal
line
nominal
line
tVAC
tVAC
Setup Slew Rate
Rising Signal =tangent line [VIH(AC)min - VREF(DC)]
ΔTR
Setup Slew Rate
Falling Signal =tangent line [VREF(DC) - VIL(AC)max]
ΔTF
tIS tIH tIS tIH
tDS tDH tDS tDH
Note: Clock and Strobe are drawn
on a different time scale.
CK
CK#
DQS#
DQS
Figure 109 – Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
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VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
ΔTFΔTR
DC to VREF
region
tangent
line nominal
line
Hold Slew Rate
Rising Signal =tangent line [VREF(DC) - VIL(DC)max]
ΔTR
DC to VREF
region
tangent
line
nominal
line
Hold Slew Rate
Falling Signal =tangent line [VIH(DC)min - VREF(DC)]
ΔTF
tIS tIH tIS tIH
tDS tDH tDS tDH
Note: Clock and Strobe are drawn
on a different time scale.
CK
CK#
DQS#
DQS
VDDQ
Figure 110 – Illustration of tangent line for for hold time tDH (for DQ with respect to strobe) and
tIH (for ADD/CMD with respect to clock)
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10.16.5 Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the
data sheet tDS(base) and tDH(base) value (see Table 54) to the ΔtDS and ΔtDH (see Table 55 and Table
56) derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see Figure 107). If the actual signal is always earlier than the nominal slew rate line between shaded
‘VREF(DC) to AC region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to VREF(DC) level is used for derating value (see Figure 109).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see Figure 108). If the actual signal is always later than the nominal slew rate line between shaded
‘DC level to VREF(DC) region’, use nominal slew rate for derating value. If the actual signal is earlier
than the nominal slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to VREF(DC) level is used for derating value (see
Figure 110).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 57).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization. Table 54 – Data Setup and Hold Base-Values
Symbol
Reference
DDR3-1333
DDR3-1600
DDR3-1866
Unit
Notes
tDS(base) AC150
VIH/L(AC)
SR=1V/nS
30
10
-
pS
2
tDS(base) AC135
VIH/L(AC)
SR=2V/nS
-
-
68
pS
1
tDH(base) DC100
VIH/L(DC)
SR=1V/nS
65
45
-
pS
2
tDH(base) DC100
VIH/L(DC)
SR=2V/nS
-
-
70
pS
1
Notes:
1. (AC/DC referenced for 2V/nS DQ-slew rate and 4 V/nS DQS slew rate).
2. (AC/DC referenced for 1V/nS DQ-slew rate and 2 V/nS DQS slew rate).
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 157 -
Table 55 – Derating values for DDR3-1333/1600 tDS/tDH - (AC150)
DQ
Slew
rate
(V/nS)
ΔtDS, ΔtDH derating in [pS] AC/DC based*
DQS, DQS# Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
2.0
75
50
75
50
75
50
-
-
-
-
-
-
-
-
-
-
1.5
50
34
50
34
50
34
58
42
-
-
-
-
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
0
-4
0
-4
8
4
16
12
24
20
-
-
-
-
0.8
-
-
-
-
0
-10
8
-2
16
6
24
14
32
24
-
-
0.7
-
-
-
-
-
-
8
-8
16
0
24
8
32
18
40
34
0.6
-
-
-
-
-
-
-
-
15
-10
23
-2
31
8
39
24
0.5
-
-
-
-
-
-
-
-
-
-
14
-16
22
-6
30
10
0.4
-
-
-
-
-
-
-
-
-
-
-
-
7
-26
15
-10
Note: Cell contents ‘-’ are defined as not supported.
Table 56 – Derating values for DDR3-1866 tDS/tDH - (AC135)
DQ
Slew
rate
(V/nS)
ΔtDS, ΔtDH derating in [pS] AC/DC based*
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
Alternate DC100 Threshold -> VIH(DC)=VREF(DC)+100mV, VIL(DC)=VREF(DC)-100mV
DQS, DQS# Differential Slew Rate
8.0 V/nS
7.0 V/nS
6.0 V/nS
5.0 V/nS
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
4.0
34
25
34
25
34
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.5
29
21
29
21
29
21
29
21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
23
17
23
17
23
17
23
17
23
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.5
-
-
14
10
14
10
14
10
14
10
14
10
-
-
-
-
-
-
-
-
-
-
-
-
2.0
-
-
-
-
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
1.5
-
-
-
-
-
-
-23
-17
-23
-17
-23
-17
-23
-17
-15
-9
-
-
-
-
-
-
-
-
1.0
-
-
-
-
-
-
-
-
-68
-50
-68
-50
-68
-50
-60
-42
-52
-34
-
-
-
-
-
-
0.9
-
-
-
-
-
-
-
-
-
-
-66
-54
-66
-54
-58
-46
-50
-38
-42
-30
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-64
-60
-56
-52
-48
-44
-40
-36
-32
-26
-
-
0.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-53
-59
-45
-51
-37
-43
-29
-33
-21
-17
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-43
-61
-35
-53
-27
-43
-19
-27
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-39
-66
-31
-56
-23
-40
0.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-38
-76
-30
-60
Note: Cell contents ‘-’ are defined as not supported.
Table 57 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid DQ transition
Slew Rate [V/nS]
DDR3-1333/1600 (AC150)
DDR3-1866 (AC135)
tVAC [pS]
tVAC [pS]
Min.
Max.
Min.
Max.
> 2.0
105
-
93
-
2.0
105
-
93
-
1.5
80
-
70
-
1.0
30
-
25
-
0.9
13
-
Note
-
0.8
Note
-
Note
-
0.7
Note
-
-
-
0.6
Note
-
-
-
0.5
Note
-
-
-
< 0.5
Note
-
-
-
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than
VIL(AC) level.
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 158 -
11. PACKAGE SPECIFICATION
Package Outline WBGA96 (9x13 mm2, ball pitch: 0.8mm, Ø =0.45mm)
1
96xΦb
A1 A
SEATING PLANE
SYMBOL DIMENSION (MM)
MIN. NOM. MAX.
A
A1
b
D
E
D1
E1
eE
eD
aaa
bbb
ccc
ddd
--- ---
--- ---
--- --- 0.15
0.10
0.20
--- --- 0.15
0.80 BSC.
0.80 BSC.
6.40 BSC.
12.00 BSC.
1.20
0.40
0.50
13.10
9.10
9.00
13.00
8.90
12.90
0.40
0.25
D
eE
E1
eD
D1
237
89
E
---
---
---
---
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Cccc
C
A
C
aaa
B
C
bbb
//
Pin A1 index Pin A1 index
eee --- --- 0.08
SOLDER BALL DIAMETER REFERS.
TO POST REFLOW CONDITION.
THE WINDOW-SIDE
ENCAPSULANT
T
eee C A
CB
M
ddd M
4X
BALL LAND
BALL OPENING
Note:
1. Ball land: 0.5mm, Ball opening: 0.4mm, PCB Ball land
suggested ≤ 0.4mm
1
W632GG6KB
Publication Release Date: Dec. 03, 2015
Revision: A06
- 159 -
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A01
Feb. 18, 2013
All
Initial formally datasheet
A02
Feb. 27, 2013
97
Revise storage temperature up to 150°C
138, 147, 155
Revise -11 speed grade DDR3-1866 data setup/hold
time AC parameters tDS/tDH spec
139,143
Revise all speed grades tXPR, tXS min. AC
parameters spec
103
Update allowed time before ringback (tDVAC) for CK -
CK# and DQS - DQS# spec (Table 20)
103
Update single-ended levels for CK, DQSL, DQSU,
CK#, DQSL# or DQSU# spec (Table 21)
150
Update required time tVAC above VIH(AC) {below
VIL(AC)} for valid ADD/CMD transition spec (Table 53)
156
Update derating values for DDR3-1866 tDS/tDH -
(AC135) (Table 56)
156
Update required time tVAC above VIH(AC) {below
VIL(AC)} for valid DQ transition spec (Table 57)
A03
Dec. 09, 2013
11
Added block diagram
7, 134, 135,
137
Added CL = 7, CWL = 6 support for DDR3-1600 and
DDR3 1333 speed bins
5~7, 98, 122,
132, 135,
142~145
Added 12A and 12K automotive grade parts
A04
Dec. 08, 2014
5~7, 98, 122,
132, 134, 135,
142~145
Removed 12A, 12K, 15A and 15K automotive grade
parts
98
Revise storage temperature
6, 98
Commercial operating temperature range change
from 0°C ≤ TCASE ≤ 85°C to 0°C ≤ TCASE ≤ 95°C
A05
Jul. 20, 2015
7
Revise typo of DDR3-1333 @ CL=10 tCK(AVG) max.
value
A06
Dec. 03, 2015
98
Revise storage temperature maximum value from
100°C to 150°C
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
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Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.