ANALOG DEVICES FEATURES Complete A/D Converter with Reference and Clock Fast Successive Approximation Conversion - 25ys No Missing Codes Over Temperature 0 ta +70C AD571K 55C to +125C AD571S Digital Multiplexing 3 State Outputs 18 Pin Ceramic DIP Low Cost Monolithic Construction PRODUCT DESCRIPTION The AD571 is a 10-bit successive approximation A/D con- verter consisting of a DAC, voltage reference, clock, com- parator, successive approximation register and output buffers all fabricated on a single chip. No external components are required to perform a full accuracy 10-bit conversion in 25ps. The AD71 incorporates the most advanced integrated cir- cuit design and processing technology available today. It is the first complete converter to employ I? L (integrated in- jection logic) processing in the fabrication of the SAR function. Laser trimming of the high stability SiCr thin film resistor ladder network at the wafer stage (LWT) insures high accuracy, which is maintained with a temperature compensated, sub- surface Zener reference. Operating on supplies of +5V to +15V and -15V, the ADS571 will accept analog inputs of 0 to +10V, unipolar or 5V bipolar, externally selectable. As the BLANK and CONVERT input is driven low, the three state outputs will be open and a conversion will commence. Upon completion of the conversion, the DATA READY line will go low and the data will appear at the output. Pulling the BLANK and CON- VERT input high blanks the outputs and readies the device for the next conversion. The AD571 executes a true 10-bit conversion with no missing codes in approximately 25ys. The AD571 is available in two versions for the 0 to +70C temperature range, the AD571J and K. The AD571S guarantees 10-bit accuracy and no missing codes from -55C to +125C. All three grades are packaged in an 18-pin hermetically-sealed ceramic DIP. *Coverecd by Patent No. 3,940,760, other patents pending. Integrated Circuit 10-Bit Analog to Digital Converter 40 BIT CURRENT OUTPUT Ba PRODUCT HIGHLIGHTS 1. The AD571 is a complete 10-bit A/D converter. No external components are required to perform a con- version. Full scale calibration accuracy of 0.3% is achieved without external trims. . The AD571 is a single chip device employing the most advanced IC processing techniques. Thus, the user has at his disposal a truly precision component with the relia- bility and low cost inherent in monolithic construction. . The AD571 accepts either unipolar (O to +10V) or bipolar (-5V to +5V) analog inputs by simply grounding or opening a single pin. . The device offers true 10-bit accuracy and exhibits no missing codes over its entire operating temperature range. Operation is guaranteed with -15V and +5V to +15V sup- plies. The device will also operate with a -12V supply. . The AD5715S is also available with full processing to MIL-STD-883A, Class B. The single chip construction and functional completeness make the AD571 especially attractive for high reliability applications. Every AD571 is subjected to long-term stabilization bakes, given a powered burn-in at +125C, and tempera- ture cycled ten times from -65C to +150C prior to final test to insure reliability and long-term stability. In addition, all units are tested 100% at the extremes of their respective temperature ranges for all parameters to guarantee full performance. A/D CONVERTERS 2078SPECIFICATIONS (typical @ +25C with V+ = +5V, V- = -15V, all voltages measured with respect to digital common, unless otherwise indicated) MODEL AD571JD AD571KD AD571SD/AD571SD-883B* RESOLUTION 10 Bits * * RELATIVE ACCURACY @ 25C! +1 LSB max 1/2LSB max t1LSB max Tmin to Tmax +1LSB max +1/2LSB max +1LSB max FULL SCALE CALIBRATION? (With 1522 Resistor In Series With Analog Input +2LSB (typ) * * UNIPOLAR OFFSET (max) +1LSB +1/2LSB * BIPOLAR OFFSET (max) +1LSB +1/2LSB * DIFFERENTIAL NONLINEARITY (Resolution for Which no Missing Codes are Guaranteed) +25C 10 Bits * * Tmin to Tmax 9 Bits 10 Bits 10 Bits TEMPERATURE RANGE 0 to +70C * -55C to +125C TEMPERATURE COEFFICIENTS Guaranteed max Change Tmin tO Tmax Unipolar Offset +2LSB (44ppm/C) +1LSB (22ppm/C) +2LSB (20ppm/*C) Bipolar Offset +2LSB (44ppm/C) +1LSB (22ppm/C) +2LSB (20ppm/C) Full Scale Calibration +4LSB (88ppm/C) +2LSB (44ppm/C) +5LSB (50ppm/C) (With 15Q Fixed Resistor or 50Q Trimmer) POWER SUPPLY REJECTION Max Change In Full Scale Calibration CMOS Positive Supply (K only) +13.5V<V+5+16.5V N.A. +1LSB max N.A. TTL Positive Supply +4.5V5V+54+5.5V +2LSB max 1LSB max * Negative Supply -16.5V<V+<-13.5V :++2LSB max +1LSB max * ANALOG INPUT RESISTANCE 3kQ min * * 5kQ typ * * 7kQ max * * ANALOG INPUT RANGES (Analog Input to Analog Common) Unipolar to +10V * * Bipolar -5V to +5V * * OUTPUT CODING Unipolar Positive True Binary * * Bipolar Positive True Offset Binary * * LOGIC OUTPUT? Bit Outputs and Data Ready Output Sink Current 3.2mA min * * (Vour = 0.4V max, Tmin to Tmax) (2TTL Loads) * * Output Source Current (Bit Outputs)* (Vour = 2.4V min, Tmin to Tmax) 0.5mA min * * Output Leakage When Blanked +40uA max * * LOGIC INPUT Blank and Convert Input 0<Vin<V+ 440A max . . Blank Logic 1 2.0V min * * Convert Logic 0 0.8V max * * CONVERSION TIME 15s min * * a5ps typ * * 3Ous max * * 208S A/D CONVERTERSMODEL AD571JD AD571KD AD571SD/AD571SD-883B POWER SUPPLY Absolute Maximum V+ +7V +16.5V v- -16.5V * Specified Operating Rated Performance V+ +5V +5V to +15V V- ~15V * Operating Range V+ +4.5V to +5.5V +4.5V to+16.5V * V- -12V to -16.5V * * Operating Current Blank Mode Vt=45V 2mA typ (10mA max) * V+=415V 5mA typ (L0mA max) * * V-=-15V 9mA typ (15mA max) * Convert Mode V+t=+5V 5SmA * * V+=+15V 10mA * V-=-15V 10mA . *Specifications same as AD571J **Specifications same as AD571K Specifications subject to change without notice. NOTES: 1 Relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. ? Full scale calibration is guaranteed trimmable to zero with an external 50Q potentiometer in place of the 15 fixed resistor, Full scale is defined as 10 volts minus 1LSB, or 9.990 volts. 3 Logic Input and Output Thresholds and Levels are a function of V+. They are guaranteed TTL compatible at V+ = +5V, CMOS compatible at V+ = 15V for the AD571K. _ * The Data output lines have active pull-ups to source 0,5mA, The DATA READY line is open collector with a nominal 6kQ internal pull-up resistor. 5 The AD571S is available fully processed and screened to the requirements of MIL-STD-883A, Class B. A complete list of tests is given further. When ordering, specify the AD571SD-883B. ABSOLUTE MAXIMUM RATINGS V+ to Digital Common AD571J,S..... ADS571K....... V- to Digital Common.............. Analog Common to Digital Common... . . Analog Input to Analog Common........ Control Inputs ...............0008. tee ee Oto +7V -+-+ Oto +16.5V wee 0 to -16.5V see eee t15V sete 0 to V+ Digital Outputs (Blank Mode)............ Power Dissipation. ..............-2+05- OUTLINE DIMENSIONS Dimensions shown in inches and (mm). |. 0.9 0.01 (22.86 20.25)-= 0.085 oot ) (2.06) 0.01 0.002 0.032 R (0.81) ow rae + | (0.26 0.06) os t oor 0.3 REF (7.87) (7.32) (7.62) tl eter ed PIN #1 IDENTIFIER | = 0.095 (2.4n 0.185 (4.7) T 0.036 (0.89) 0.032 (0.81) 0.018 0.140.005 0.054 (0.46) (2.54 0.13} (1.37) 0.8 0.008 - (20.32 +0.2) Figure 1. 18-Lead Ceramic Dual-in-Line Package A/D CONVERTERS 2098CIRCUIT DESCRIPTION The AD571 is a complete 10-bit A/D converter which requires no external components to provide the cornplete successive- approximation analog-to-digital conversion function. A block diagram of the AD571 is shown in Figure 2. Upon receipt of the CONVERT command, the internal 10-bit current out- put DAC is sequenced by the I? L successive-approximation register (SAR) from its most-significant bit (MSB) to least- significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5kQ input resistor. The comparator determines whether the ad- dition of each successively-weighted bit current causes the DAC current surn to be greater or less than the put current; if the sum is less the bit is left on, if more, the bit is turned off. After testing all the bits, the SAR contains a 10-bit binary code which accurately represents the input signal to within +4%LSB (0.05%). DIGITAL BLANK & veo COMMON CONVERT CONTROL W ANALOG IN ANALOG COMMON {14 19 BIT CURRENT 10 BIT ouTPUT SAR DAC BIT OUTPUTS BIPOLAR OFFSET CONTROL STATE 3S AUTO BLANK CONTAC L. 7 BURIED ZENER REFERENCE Figure 2, AD571 Functional Block Diagram Upon completion of the sequence, the SAR sends out a DATA READY signal (active low), which also brings the three-state buffers out of their open state, making the bit output lines become active high or low, depending on the code in the SAR. When the BLANK and CONVERT line is brought high, the output buffers again go open, and the BIT2 BITS BITS BITS BIT6 BIT? BITS o o o Qo 9 COMMON BIPOLAR OFFSET CONTROL, QO ANALOG COMMON | ANALOG IN 151 | THE ADS571 IS ALSO AVAILABLE IN A LASER. TRIMMED PASSIVATI:D CHIP FORM GUARANTEED TO J SPECIFICATIONS. CONSULT FACTORY FOR PRICING AND APPLICATION PARTICULARS. FIGURE 3 SHOWS THE CHIP METAL LIZATION LAYOUT AND BONDING PAOS. Figure 3. Chip Bonding Diagram 2108S A/D CONVERTERS SAR is prepared for another conversion cycle. Details of the timing are given further. The temperature compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and tempera- ture. The bipolar offset input controls a switch which allows the positive bipolar offset current (exactly equal to the value of the MSB less %LSB) to be injected into the summing (+) node of the comparator to offset the DAC output. Thus the nominal 0 to +10V unipolar input range becomes a5V to +5V range. The 5k&2 thin film input resistor is trimmed so that with a full scale input signal, an input current will be generated which exactly matches the DAC output with all bits on. (The input resistor is trimmed slightly low to facilitate user trimming, as discussed on the next page.) POWER SUPPLY SELECTION The AD$71 is designed for optimum performance using a +5V and -15V supply, for which the AD571J and AD571S are specified. AD571K will also operate with up to a +15V supply, which allows direct interface to CMOS logic. The input logic threshold is a function of V+ as shown in Figure 4. The supply current drawn by the device is a function of both V+ and the operating mode (BLANK or CONVERT). These supply current variations are shown in Figure 5. The supply currents change only moderately over temperature as shown in Figure 9. Vin Volts V+, Volts Figure 4. Logic Threshold (AD571K Only) I-, CONVERT MODE Ain * Oto +10 -, BLANK MODE Vin = OV CONVEAT MODE e supery 7 =+10V CURRENT mA BLANK MODE ra 45 50 6.0 70 ao 90 = 10.0 W000:1200.D 1416180 Vt or V- Volta Figure 5. Supply Currents vs Supply Levels and Operating ModesCONNECTING THE AD571 FOR STANDARD OPERATION The AD571 contains all the active components required to perform a complete A/D conversion. Thus, for most situa- tions, all that is necessary is connection of the power sup- ply (+5 and -15), the analog input, and the conversion start pulse. But, there are some features and special con- nections which should be considered for achieving optimum performance. The functional pin-out is shown in Figure 6. BIT 9] 1 TOENTIFIER [8] art 10 LSB BITS] 2 17 |DATA READY BIT? E [16] DIGITAL COM BITS J ADS71 a BIPOLAR OFF BITS (=| [+4] ANALOG COM BIT 4 Ce] [13] ANALOG IN BIT3 EI [a2] we art 2[e | [11 Jou a conv. G MSB BIT 1} 9 wolve Figure 6. AD571 Pin Connections FULL SCALE CALIBRATION The 5kQ thin film input resistor is laser trimmed to produce a current which matches the full scale current of the internal DACplus about 0.3%when a full scale analog input voltage of 9.990 volts (10 volts 1 LSB) is applied at the input. The input resistor is trimmed in this way so that if a fine trimming potentiometer is inserted in series with the input signal, the input current at the full scale input voltage can be trimmed down to match the DAC full scale current as precisely as desired. However, for many applications the nominal 9.99 volt full scale can be achieved to sufficient accuracy by simply inserting a 15Q resistor in series with the analog input to pin 13. Typical full scale calibration error will then be about +2LSB or +0.2%. If the more precise calibration is desired, a 5082 trimmer should be used instead. Set the analog input at 9.990 volts, and set the trimmer so that the output code is just at the transition between 1111111110 and 1111111111. Each LSB will then have a weight of 9.766mV. If a nominal full scale of 10.24 voits is desired (which makes the LSB have weight of exactly 10.00mV), a 10022 resistor in series with a 100Q trimmer (or a 200Q trimmer with good resolution) should be used. Of course, larger full scale ranges can be ar- ranged by using a larger input resistor, but linearity and full scale temperature coefficient may be compromised if the external resistor becomes a sizeable percentage of 5kQ. Sc NT e fare 2 feo .sB vo on ADS7I 6 feo OIGITAL COM as] BIPOLAR (Shont TO COMMON FOR ) ba CONTROL\ UNIPOLAR, OPEN FOR BIPOLAR 1 fe ANALOG COMMON TOLERATES 206mV jp 0 ( TO DIGITAL COMMON ANALOG IN. a} p gor Bins 12}-0 18 1682 FIXED OR 502 VARIABLE W } Bat {SEE TEXT) MSE [ 9 [e}o-s Figure 7. Standard AD571 Connections PLEL e111 1) Fi BIPOLAR OPERATION The standard unipolar 0 to +10V range is obtained by shorting the bipolar offset control pin to digital common. If the pin is left open, the bipolar offset current will be switched into the comparator summing node, giving a-5V to +5V range with an offset binary output code. (-5.00 volts in will give a 10-bit code of 0000000000; an input of 0.00 volts results in an out- put code of 1000000000 and 4.99 volts at the input yeilds the 1111111111 code). The bipolar offset control input is not di- rectly TTL compatible, but a TTL interface for logic control can be constructed as shown in Figure 8. +5V m4 | Bac + Aw OR} $4 Accom ADS71 oF 1 BIPOLAR | | OFFSET BVCOM. {| [CONTROL ~ 1 Data | 10BITS ( Deom FAK ev com Figure 8. Bipolar Offset Contralled by Logic Gate Gate Output = 1 Unipolar 0- 10V Input Range Gate Output=0 Bipolar +5V Input Range COMMON MODE RANGE The AD571 provides separate Analog and Digital Common connections. The circuit will operate properly with as much as t200mV of common mode range between the two commons. This permits more flexible control of system common bussing and digital and analog returns. In normal operation the Analog Common terminal may gener- ate transient currents of up to 2mA during a conversion. In addition, a static current of about 2mA will flow into Analog Common in the unipolar mode after a conversion is complete. An additional 1mA will flow in during a blank interval with zero analog input. The Analog Common current will be modu- lated by the variations in input signal. The absolute maximum voltage rating between the two com- mons is t1 volt. We recommend the connection of a parallel pair of back-to-back protection diodes between the commons if they are not connected locally. C CONVERT MODE B- BLANK MODE 4-18, C 1 +16, 4-158 7. SUPPLY CURRENTS mA tris, @ b4By, C. 1+6V.B -50 +26 0 a 50 70 00 125 TEWIPERATURE - C Figure 9. AD571 Power Supply Current vs Temperature A/D CONVERTERS 2171SZERO OFFSET The apparent zero point of the AD571 can be adjusted by inserting an offset voltage between the Analog Common of the device and the actual signal return or signal common. Figure 10 illustrates two methods of providing this offset. Figure 10A shows how the converter zero may be offset by up to +3 bits to correct the device initial offset and/or input signal offsets. As shown, the circuit gives approximately syrametrical ad- justment in unipolar mode. In bipolar mode R2 should be omitted to obtain a symmetrical range. Au INPUT SIGNAL iAAD571 Acom gm $100 $ SIGNAL COMMON +15V -15V ZERO OFFSET ADJ +3 BIT RANGE Figure 10.(A) mt AlN A,) INPUT 4} SIGNAL AD571 Ry AAA 2.72 OR 52 POT. Acom SIGNAL COMMON % BIT ZERO OFFSET Figure 10.(8} Figure 11 shows the nominal transfer curve near zero for an AD571 in unipolar mode. The code transitions are at the edges of the nominal bit weights. In some applications it will be pre- ferable to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics. This offset can easily be accomplished as shown in Figure 10B. At balance (after a conversion) approximately 2mA flows into the Analog Common terminal. A 2.722 resistor in series with this terminal will result in approximately the desired % bit off- set of the transfer characteristics. The nominal 2mA Analog Common current is not closely controlled in manufacture. If high accuracy is required, a 51 potentiometer (connected as a rheostat) can be used as R2. Additional negative offset range may be obtained by using larger values of R2. Of course, if the zero transition point is changed, the full scale transition point will also move. Thus, if an offset of 4L5B is introduced, full scale trimming as described on previous page should be done with an analog input of 9.985 volts. NOTE: During a conversion transient currents from the Analog Common terminal will disturb the offset voltage. Capacitive decoupling should not be used around the offset network. These transients will settle as appropriate during a conversion. Capacitive decoupling will pump up and fail to settle re- sulting in conversion errors. Power supply decoupling which returns to analog signal common, should go to the signal input side of the resistive offset network. 2128S A/D CONVERTERS OUTPUT co CODE ' 0000000100 0000000011 90000000010 0000000001 0000000000 OV 10mVv 30mV 50mV INPUT VOLTAGE NOMINAL CHARACTERISTICS REFERRED TO ANALOG COMMON OUTPUT CODE 00900000100 0000000011 0000000010 0000000001 a +-+ + OV 10mV 30mV 50mV INPUT VOLTAGE OFFSET CHARACTERISTICS WITH 2.79 IN SERIES WITH ANALOG COMMON 4 + Figure 11. AD&71 Transfer Curve - Unipolar Operation (Approximate Bit Weights Shown for I/lustration, Nominal Bit Weights ~ 9.766mV) MIL-STD-883 The rigors of the military/aerospace environment, temperature extremes, humidity, mechanical stress, etc., demand the utmost in electronic circuits. The AD571, with the inherent reliability of integrated circuit construction, was designed with these applications in mind. The hermetically-sealed, low profile DIP package takes up a fraction of the space required by equivalent modular designs and protects the chip from hazardous environ- ments. To further insure reliability, the AD571 is offered with 100% screening to MIL-STD-883B, method 5004. Table | details the test procedures of MIL-STD-883. Analog Devices subjects each part ordered with 883B screening to these tests on a 100% basis. TABLE I TEST METHOD 1) Internal Visual (Pre cap) 2) Stabilization Bake 2010, Test Condition B Method 1008, 24 hours @ +150C Method 1010, Test Condition C, 10 Cycles, -65C to +150C Method 2001, Test Condition E, Y1 plane, 30kg Method 1014, Test Condition A and C Method 1015, Test Condition B, 168 hours @ +125C Performed 190% to all min and max specifications on data pages Method 2009 3) Temperature Cycling 4) Constant Acceleration 5) Seal, Fine and Gross 6) Burn-in Test 7) Final Electrical Tests 8) External VisualCONTROL AND TIMING OF THE AD571 There are several important timing and control features on the AD571 which must be understood precisely to allow optimal interfacing to microprocessor or other types of con- trol systems. All of these features are shown in the timing diagram in Figure 12. The normal stand-by situation is shown at the left end of the drawing. The BLANK and CONVERT (B & C) line is held high, the output lines will be open, and the DATA READY (DR) line will be high. This mode is the lowest power state of the device (typically 150mW). When the (B & C) line is brought low, the conversion cycle is initiated; but the DR and Data lines do not change state. When the conversion cycle is complete (typically 25us), the DR line goes low, and within 500ns, the Data lines become active with the new data. About 1.5ps after the B & C line is again brought high, the DR line will go high and the Data lines will go open. When the B & C line is again brought low, a new conversion will begin. The minimum pulse width for the B & C line to blank previous data and start a new conversion is 2s. If the B & C line is brought high during a conversion, the conversion will stop, and the DR and Data lines will not change. If a 2us or longer pulse is applied to the B & C line during a conversion, the converter will clear and start a new conversion cycle. PULSE BLANKS AND STAATS CONVERSION ON FALLING EDGE BLANKS DATA OUTPUTS HOLDS DATA START OUTPUTS Bat input CONVERSION 2us min CONVERSION GONY ERSION | fea 25 | maa 1.5us: t- \ START STOP START CONVERSION NEW CONVERSION of our 500ns | INDICATES NI READY imaxh DATA READY EW DATA DATA BLANK " one x (ONE NO, our Loren) > ZERO ze RRR x Figure 12. AD&71 Timing and Control Sequence AKX BLANK (OPEN) CONTROL MODES WITH BLANK AND CONVERT The timing sequence of the AD571 discussed above allows the device to be easily operated in a variety of systems with differ- ing control modes. The two most common control modes, the Convert Pulse Mode, and the Multiplex Mode, are illustrated here. Convert Pulse Mode In this mode, data is present at the out- put of the converter at all times except when conversion is taking place. Figure 13 illustrates the timing of this mode. The BLANK and CONVERT line is normally low and conversions are triggered by a positive pulse. A typical application for this timing mode is shown in Figure 16, in which uP bus interfacing is easily accomplished with three-state buffers. Multiplex Mode In this mode the outputs are blanked except when the device is selected for conversion and readout; this timing shown in Figure 14. A typical AD571 multiplexing ap- plication is shown in Figure 17. This operating mode allows multiple AD571 devices to drive common data lines. All BLANK and CONVERT lines are held high to keep theoutputs blanked. A single AD571 is selected, its BLANK and CONVERT line is driven low and at the end of SNe conversion, which is indicated by DATA READY going low, the conversion result will be present at the outputs. When this data has been read from the 10-bit bus, BLANK and CONVERT is restored to the blank mode to clear the data bus for other converters. When several AD571s are multiplexed in sequence, a new conversion may be started in one AD571 while data is being read from another. As long as the data is read and the first AD571 is cleared within 15ps after the start of conversion of the second AD571, no data overlap will occur. CONVERT PULSE CONVERT INTERVAL BR PREVIOUS ane NEW OUTPUTS DATA {QREN}OO___ DATA Figure 13. Convert Pulse Mode pec uae STARTS j CONVERSION ENDS on ~ wt END DATA READOUT ar BEAD OUT DATA OUTPUTS COX AN RY para DATA RK ERR Figure 14. Multiplex Mode SAMPLE-HOLD AMPLIFIER CONNECTION TO THE AD571 Many situations in high-speed acquisition systems or digitizing of rapidly changing signals require a sample-hold amplifier (SHA) in front of the A-D converter. The SHA can acquire and hold a signal faster than the converter can perform a conver- sion. A SHA can also be used to accurately define the exact point in time at which the signal is sampled. For the AD571, a SHA can also serve as a high input impedance buffer. Figure 15 shows the AD571 connected to the AD582 monoli- thic SHA for high speed signal acquisition. In this configuration, the AD582 will acquire a 10 volt signal in less than 10s with a droop rate less than 1004V/ms. The control signals are arranged so that when the control line goes low, the AD582 is put into the hold mode, and the AD571 will begin its conversion cycle. (The AD582 settles to final value well in advance of the +15 +5V + Zh. o CONTROL IN o Bat Ne 9 AIN OATA READY v4] 3 psa frto_to 6 VOLT com ADS82 | AD571 5 ~ : 300pF - 0 COM y az 3 ja 6 fe |? ne Ne DATA |108ITS NULL ANALOG IN 7 o ACOM ) -15V 18 VOLT com Figure 15. Sample-Hold Interface to the AD571 A/D CONVERTERS 2138first comparator decision inside the AD571), The DATA READY line is fed back to the other side of the differential input control gate so that the AD582 cannot come out of the hold mode during the conversion cycle. At the end of the conversion cycle, the DATA READY line goes low, auto- matically placing the AD582 back into the sample mode. This feature allows simple control of both the SHA and the A-D converter with a single line. Observe carefully the ground, sup- ply, and bypass capacitor connections between the two de- vices. This will minimize ground noise and iriterference during the conversion cycle to give the most accurate measurements. INTERFACING THE AD571 TO A MICROPROCESSOR The AD571 can easily be arranged to be driven from standard microprocessor control lines and to present data to any standard microprocessor bus (4-, 8-, 12-or 16-bit) with a mini- mum of additional control components. The configuration shown in Figure 16 is designed to operate with an 8-bit bus and standard 8080 control signals. The input control circuitry shown is required to insure that the AD571 receives a sufficiently long B & C input pulse. When the converter is ready to start a new conversion, the B & C line is low, and DR is low. To command a conversion, the start address decode line goes low, followed by WR. The B & C line will now go high, followed about 1.5ys later by DR. This resets the external flip-flop and brings B & C back to low, which initiates the conversion cycle. At the end of the conversion cycle, the DR line goes low, the data outputs will become active with the new data and the control lines wiil return to the stand-by state. The new data will remain active until a new conversion is commanded. The self-pulsing nature of this circuit guarantees a sufficient convert pulse width. This new data can now be presented to the data bus by en- abling the three-state buffers when desired. .4 data word (8-bit or 2-bit) is loaded onto the bus when its decoded ad- dress goes low and the RD line goes low. This arrangement presents data to the bus left-justified, wita highest bits in the 8-bit word; a right-justified data arrangement can be set ANALOG IN D97 ul DATA BUS ANALOG COM 14 START ADDRESS FROM DECODER FROM sys WA HL BYTE ADDRESS FROM DECODER LO BYTE ADDRESS FROM DECODER FROM SYS RO Figure 16. Interfacing AD571 to an 8-Bit Bus (8080 Control Structure) 214S A/D CONVERTERS up by a simple re-wiring. Polling the converter to determine if conversion is complete can be done by addressing the gate which buffers the DR line, as shown. In this configuration, there is no need for additional buffer register storage since the data can be held indefinitely in the AD571, since the B & Cc line is continually held low. BUS INTERFACING WITH A PERIPHERAL INTERFACE CIRCUIT An improved technique for interfacing to a uP bus involves the use of special peripheral interfacing circuits (or I/O devices), such as the MC6820 Peripheral Interface Adapter (PIA). Shown in Figure 17 is a straightforward application of a PIA to multiplex up to 8 AD571 circuits. The AD571 has 3-state outputs, hence the data bit outputs can be paralleled, provided that only one converter at a time is permitted to be the active state. The DATA READY output of the AD571 is an open collector with resistor pull-up, thus several DR lines can be wire-ored to allow indication of the status of the selected device. One of the 8-bit ports of the PIA is combined with 2-bits from the other port and programmed as a 10-bit input port. The remaining 6-bits of the second port are programmed as outputs and along with the 2 control bits (which act as outputs), are used to control the 8 AD571s. When a control line is in the 1 or high state, the ADC will be automatically blanked. That is, its outputs will be in the inactive open state. If a single control line is switched low, its ADC will convert and the outputs will automatically go active when the conversion is complete. The result can be read from the two peripheral ports; when the next conversion is desired, a different control line can be switched to zero, blanking the previously active port at the same time. Subsequently, this second device can be read by the microprocessor, and so-forth. The status lines are wire-ored in 2 groups and connected to the two remaining control pins. This allows a conversion status check to be made after a convert command, if necessary. The ADCs are divided into two groups to minimize the loading effect of the internal pull-up resistors on the DATA READY buffers. See the MC6820 data sheet for more application detail. ANALOG IN. DA a mse ADB7T $ : LT) LsB STATUS bat GROUP 1 T - ae CAT TRO : ~ MsB rm + PORTA ROE Aos7i 3 t~ +2 FROM : Lr oo 8 Bp. DB7 kK _ Us MC6820 Q Bac PERIPHERAL Ast pe9 Ip! T INTERFACE ast e413 > ADAPTER 3 >| (Play os JF iz = BALANCE 5 " oR OF PORT bod wel MsB 8 aw ke ADS71 3 y UU ENABLE [a4 3 BEE : RES us8 ce2___cBt lJ Bact {TO ONE MORE IN GROUP 1) _. Ait = 1 (TO THREE MORE IN GAouP 2h || STATUS GROUP 2 oR : ~ Msa aps74 \ _ ts8 LJ aac Figure 17. Multiplexing 8 AD571s Using Single PIA for uP Interface. No Other Logic Required (6800 Control Structure)