19-0123; Aev. 4; 8/96 me is KIT General Description The MAX186/MAX188 are 12-bit data-acquisition sys- tems that combine an 8-channel multiplexer, high-band- width track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual +5V supplies. The analog inputs are software contig- urable for unipclar/bipolar and single-ended/ditferential operation. The 4-wire serial interface directly connects to SPI, QSPI" and Microwire devices without external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX186/MAX188 use either the internal clock or an external serial-interface clock to perform successive-ap proximation A/D conver- sions. The serial interface can operate beyond 4MHz when the internal clock is used. The MAX186 has an internal 4.096V reference while the MAX188 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim . The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10,/A at reduced sampling rates. The MAX186/MAX188 are available in 20-pin DIP and SO packages, and in a shrink small-outline package (SSOP), that occupies 30% less area than an 8-pin DIP. For applications that call for a parallel interface, see the MAX180/MAX181 data sheet. For anti-aliasing filters, consult the MAX274/MAX275 data sheet. Applications Portable Data Logging Data-Acquisition High-Accuracy Process Control Automatic Testing Robotics Battery-Powered Instruments Medical Instruments SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor. MAAXLAA MAXIM Low-Power, 8-Channel, Serial 12-Bit ADCs Features + 8-Channel Single-Ended or 4-Channel Differential Inputs # Single +5V or t5V Operation # Low Power: 1.5mA (operating mode) 2A (power-down mode) 4 Internal Track/Hold, 133kHz Sampling Rate + Internal 4.086V Reference (MAX1 86) + SPI-, QSPI-, Microwire-, TMS320-Com patible 4-Wire Serial Interface # Software-Configurable Unipolar or Bipolar Inputs # 20-Pin DIP, SO, SSOP Packages Evaluation Kit Available Ordering Information * PART* TEMP. RANGE PIN-PACKAGE MAX186_CPP 0 to +70C 20 Plastic DIP MAX186_CWP OT to +70 20 SO MAX186_CAP OT to +70 20 SSOP MAX186DC/D OT to +70C Dice* MAX186_EPP -40C to +85C 20 Plastic DIP MAX186_EWP -40C to +85C 20 SO MAX186_EAP 40 to +85C 20 SSOP MAX186_MJP -55C to +125C 20 CERDIP* Ordering Information continued on last page. + NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. Contact factory for availability of A-grade in SSOP package. * Dice are specified at +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883. Pin Configuration TOP VIEW eno [1 cn [2] ow | Anaxim cus [4 | cra [5 | cus [6 | cre [7] cu7 [e | Ys [s | sHoW fo MAX186 MAX188 DIP /SO/SSOP Maxim iniegraited Producis 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 S8LXVW/ISLXVNLow-Power, 8-Channel, Serial 12-Bit ADCs ABSOLUTE MAXIMUM RATINGS MAX186/MAX188 Vop to AGND.. cece ceeceeecseeesereteennnnnnee -0.3V to +6V Continuous Power Dissipation (Ta = +70C) Vss to AGND oo. eceeceeceseeeneneteeennneeee +0.3V to -6V Plastic DIP (derate 11.11mW/C above +70C)} ........... e8omw Vp to VSS... cece cee cee tee secrete tneteteetnneneeennes -0.3V to +12V SO (derate 10.00mMW/C above +70C) 0. ee AGND to DGND. cece cee eeteceetnteeeneeees -0.3V to +0.3V SSOP (derate 8.00mWi'C above +70C) we CHO-CH7 to AGND, DGND........ (Vg - 0.3) to (Vpp + 0.3V) CERDIP (derate 11.11mW/C above +70C)...0..0......889mW CHO-CH7 Total Input Current 2.00... cece eeereeeeeeees +20mA Operating Temperature Ranges: VREF to AGND -0.3 to (Vpp + 0.3V) MAX186_C/MAX188_ 0 oe cette tees O to +70C REFADJ to AGND -0.3 to (Vpp + 0.8M) MAX186_E/MAX188 E..ecceeereeeeeneeees -40C to +85C Digital Inputs to DGND. oes -0.3 to (Vpp + 0.38V) MAX186_M/MAX1 88M o.oo. eres -55C to +125C Digital Outputs to DGND....... ve -0.3 to (VpD + 0.3) Storage Temperature Range.......... ee -60C to +150C Digital Output Sink Current 0000.00 ee eee eeeeeeees 25mA Lead Temperature (soldering, 10sec)... +300C Siresses beyond those listed under Absolute Maximum Aalings may cause penmanent damage to the device. These are siress ratings only, and functional operation of the device al these or any other condilions beyond those indicated in ihe operational sections of the specifications is nol implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V 45%; Vsg = OV or -5V; foLk = 2.0MHz, external clock (50% duly cycle); 15 clocks/conversion cycle (133ksps); MAX186 4.7uF capacitor at VREF pin; MAX188external reference, VREF = 4.096 applied to VREF pin; Ta = Tmin to Tmax, unless otherwise noted.) | PARAMETER | SYMBOL CONDITIONS MIN TYP MAX | UNITS De ACCURACY (Note 1) Resolution 12 Bits MAX186A/MAX1 88A +0.5 MAX186B/MAX1 88B +0.5 Relative Accuracy (Note 2) MAX186C +1.0 LSB MAX1886 +0.75 MAX186D/MAX188D +1.0 Differential Nonlinearity DNL No missing codes over temperature +1 LSB MAX1 86A/MAX1 88A +2.0 MAX186B/MAX1 88B +3.0 Offset Error LSB MAX186C/MAX188C +3.0 MAX186D/MAX188D +3.0 MAX186 (all grades) +3.0 MAX1 88A +1.5 Gain Error (Note 3) External reference MAX1 88B +2.0 LSB 4.096V (MAX188) MAX1 88C +2.0 MAX1 88D +3.0 Gain Temperature Coefficient External reference, 4.096V +0.8 ppm Serer 201 Ls DYNAMIC SPECIFICATIONS (19kKHz sine wave input, 4.096Vp_p, 133ksps, 2.0MHz external clock, bipolar input mode) Signal-to-Noise + Distortion Ratio | SINAD 70 dB (citar | THO 20 | a8 Spurious-Free Dynamic Range SFDR 80 dB Channel-to-Channel Crosstalk 65kHz, Vin = 4.096Vp-p (Note 4) -85 dB 2 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V +5%; Vss = OV or -5V; fcLk = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186 4.7uF capacitor at VREF pin; MAX188external reference, VREF = 4.096V applied to VREF pin; Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small-Signal Bandwidth -3dB rolloff 45 MHz Full-Power Bandwidth 800 kHz CONVERSION RATE . . Internal clock 5.5 10 Conversion Time (Note 5) t conv - [ls External clock, 2MHz, 12 clocks/conversion 6 Track/Hold Acquisition Time tAz 1.5 [ls Aperture Delay 10 ns Aperture Jitter <50 ps Internal Clock Frequency 1.7 MHz External compensation, 4.7 UF 0.1 2.0 External Clock Frequency Range Internal compensation (Note 6) 0.1 0.4 MHz Used for data transfer only 10 ANALOG INPUT Input Voltage Range, Unipolar, Vss= OV VALE Single-Ended and Differential Vv (Note 9) Bipolar, Vg = -5V +VREF/2 Multiplexer Leakage Current On/off leakage current, Viy = +5V +0.01 +1 pA Input Capacitance (Note 6) 16 pF INTERNAL REFERENCE (MAX186 only, reference buffer enabled) VREF Output Voltage Ta = +25C 4076 4096 4.116 V VREF Short-Circuit Current 30 mA MAX186A, MAX186B MAES 6 80 a VREF Tempco MAXI B6C | MAX186_E +30 +60 ppmiC MAX186_M +30 +80 MAX186D +30 Load Regulation (Note 7) OmA to 0.5mA output load 2.5 mv .. Internal compensation 0 Capacitive Bypass at VREF - LF External compensation A7 .. Internal compensation 0.01 Capacitive Bypass at REFADJ - LF External compensation 0.01 REFADJ Adjustment Range 41.5 % EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V) Input Voltage Range 2.50 Yo V Input Current 200 350 LA Input Resistance 12 20 ko) Shutdown VREF Input Current 1.5 10 LA Buffer Disable Threshold REFADJ voD V MA AXLAA 3 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V +5%; Vss = OV or -5V; fcLk = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186 4.7uF capacitor at VREF pin; MAX188external reference, VREF = 4.096V applied to VREF pin; Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Internal compensation mode 0 uF External compensation mode 47 Reference-Buffer Gain MAX1 86 1878 VN MAX188 1.638 REFADJ Input Current MAXI86 50 pA MAX188 +5 DIGITAL INPUTS (DIN, SCLK, GS, SHDN) DIN, SCLK, CS Input High Voltage VINH 2.4 Vv DIN, SCLK, CS Input Low Voltage | VINL 0.8 V DIN, SCLK, CS Input Hysteresis VHYST 0.15 V DIN, SCLK, CS Input Leakage lIN Vin = OVor Vop +1 LA DIN, SCLK, CS Input Capacitance CIN (Note 6) 15 pF SHDN Input High Voltage VINH Vpp - 0.5 V SHDN Input Low Voltage VINL 0.5 V SHDN Input Current, High liNH SHDN = Vpp 4.0 LA SHDN Input Current, Low line SHDN = 0V -4.0 LA SHDN Input Mid Voltage Vim 1.5 Vpp -1.5 V SHDN Voltage, Floating VeLt | SHDN = open 2.75 V Mid Input Allowed Leakage, SHDN = open -100 100 nA DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low VoL Isink = 5mA 04 V ISINK = 16mA 0.3 Output Voltage High VoH ISOURCE = 1mA 4 V Three-State Leakage Current I CS = 5V +10 pA Three-State Outp ut Capacitance Cout | CS= 5V (Note 6) 15 pF POWER REQUIREMENTS Positive Supply Voltage Vpb 5 +5% Vv Negative Supply Voltage Vss 5 ey Vv Operating mode 1.5 2.5 mA Positive Supply Current Ipb Fast power-down 30 70 Full power-down 2 10 HA . Operating mode and fast power-down 50 Negative Supply Current Iss Full power-down 10 HA 4 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V +5%; Vss = OV or -5V; fcLk = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186 4.7uF capacitor at VREF pin; MAX188external reference, VREF = 4.096V applied to VREF pin; Ta = TmIN to Tmax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Positive Supply Rejection PSR Vpp = SY 45%; external reference, 4.096V; +0.06 +05 my (Note 8) full-scale input Negative Supply Rejection PgR Vss = 5V +5%; external reference, 4.096V: +0.01 405 my (Note 8) full-scale input Note 1: Tested at Vpp = 5.0V; Vgg = OV; unipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX186 internal reference, offset nulled; MAX188 external reference (VREF = +4.096)}, offset nulled. Note 4: Ground on-channel; sine wave applied to all off channels. Note S: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing. Note 7: External load should not change during conversion for specified accuracy. Note 8: Measured at Vsypp_y +5% and Voyppy -5% only. Note 9: The common-mode range for the analog inputs is from Vss to Vpp. TIMING CHARACTERISTICS (Vpp = 5V 45%: Veg =OV or -5V, Ta = Tryin to Tax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time taz 1.5 us DIN to SCLK Setup Ips 100 ns DIN to SCLK Hold tou 6) ns MAX18 C/E 20 150 ns SCLK Fall to Output Data Valid t Cc = 100pF = NPE NEN pe LoaD = ee MAX18__M 20 200 ns CS Fall to Output Enable tpv CLoap = 100pF 100 ns CS Rise to Output Disable tr CLoap = 100pF 100 ns CS to SCLK Rise Setup less 100 ns CS ta SCLK Rise Hold tesy 0 ns SCLK Pulse Width High tcH 200 ns SCLK Pulse Width Low te 200 ns SCLK Fall to SSTRB tsstRB CLoap = 100pF 200 ns (Note 8) SSTRB Ouiput Enable tspv External clock mode only, CLoap = 100pF 200 ns (Note 8) to SSTRB Output Disable tsta External clock made only, CLoap = 100pF 200 ns SSTRB Rise to SCLK Rise tsck Internal clock mode only 0 ns (Note 6) MA AXLAA 5 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs Typical Operating Characteristics POWER-SUPPLY REJECTION INTERNAL REFERENCE VOLTAGE CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEM PERATURE vs. TEMPERATURE vs. TEMPERATURE 0.30 0.16 gg = Ov or - e 2 0.42 0.20 2.485 = os > S 010 to 0.15 = = = 22.454 Ee 0.08 2 0.19 ti = g = 0.06 2.453 ing 0.05 0.04 0.00 2.450 0.02 -0.05 0 60 -40-20 0 20 40 60 80 100120140 40-20 0 20 40 60 80 100120 60-40 -20 0 20 40 60 80.100 120 140 TEMPERATURE ( C) TEMPERATURE ( Cj TEM PERATURE ( GC) M AX186/MAX188 FFT PLOT -- 133kHz 20 0 SB -40 -- odie wee el fee 199kKHZ4.. ws : : cTa=t25C | 5 -60 bese cetetsbeeceteeediee = 80 <= 100 120 4140 0 93.25kHz 66.5kHz FREQUENCY Pin Description PIN NAME FUNCTION 1-8 CHO-CH7 Sampling Analog Inputs 9 Vss Negative Supply Voltage. Tie to -5V +5% or AGND Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10pA (max) 10 SHDN supply current, otherwise the MAX186/MAX1 88 are fully operational. Pulling SHDN high puts the ref- erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier 11 VREF (4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7yF capacitor to ground when using external compensation mode. Also functions as an input when used with a precision external reference. MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs Pin Description (continued) PIN NAME FUNCTION 12 REFADJ ve to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to 13 AGND Analog Ground. Also IN- Input for single-ended conversions. 14 DGND Digital Ground 15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the 16 SSTRB A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external mede). 17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK. 18 os Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 19 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.) 20 Vbp Positive Supply Voltage, +5V+5% +5V 3k _ DOUT DOUT : cs co > T 0 So T oO SCLK 3k CLoap CLoan BIN SHIFT L L o | REGISTER [peo = = DGND SHDN a. High-Z to Vou and Vo. 10 You b. High-Z ta Vg. and Vou to cHO OUTPUT OUT . o OL 10 Vo Hig OL on 10 Vo. cHt SHIFT _ CH2 EGISTER STRB Figure 1. Load Circuits for Enable Time CH3 ANALOG an Moe CLOCK INy>. +5 CHE eal CH? ADC QUT 3k AGND DOUT DOUT A 1.65 o . o 2 REFERENCE ren L L MAK AAaUM 3 3k CLoap CLoao REFAD J MAX 86 L L VREF fA0OGV] Maxi a8 = oagysp = = DGND a Von to High-z b Vou to High-Z Figure 2. Load Circuits for Disabled Time Figure 3. Block Diagram MA AXLAA S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs Detailed Description The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuit- ry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188. Pseudo-Differential Input The sampling architecture of the ADCs analog com- parator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CHO-GH/ and IN- is switched to AGND. In differential mode, IN+ and IN- are selected from pairs of CHO/GH1, GH2/CH8, CH4/CH5 and CH6/CH7. Configure the channels with Table 3 and Table 4. In differential mode, IN- and IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain sta- ble within +0.5LSB (+0.1L5B for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1yF capacitor from AIN- (the select- ed analog input, respectively) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHyo_p. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acqui- sition interval, the T/H switch opens, retaining charge on CHo_p as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching Cyo_p from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is sim- ply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to OV within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x [(Vint) - (Vin-)] from Cyuo_p te the binary-weighted capacitive DAC, which in turn forms a digital represen- tation of the analog input signal. Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mede on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for 12-BIT CAP ACITIVE DAC VREF4 INPUT = CHoLD COMPARATOR MUX CHO O cHio 16pF CH2 O CH3 O CH4 O CHS O cH O CHT O AGND AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN-- CHANNEL. SINGLE-ENDED MODE: IN+ = CHO-CH?, IN-- = AGND. DIFFERENTIAL MODE: IN+ AND IN-- SELECTED FROM PAIRS OF CHO/CH1, CH2/CH3, CH4/CHS, CHE/CH?. SWITCH Figure 4. Equivalent input Circuit single-ended inputs, IN- is connected to AGND, and the converter samples the + input. If the converter is set up for differential inputs, IN- connects to the - input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and Cyo_p charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signals source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is cal- culated by: taz = 9 x (Rg + Rin) x 16pF, where Riy = &kQ, Rg = the source impedance of the input signal, and taz is never less than 1.5us. Note that source impedances below SkQ do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is con- nected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADCs signal bandwidth. Input Bandwidth The ADC's input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure pericdic sig- nals with bandwidths exceeding the ADCs sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs Vop 4 59 2M Hz OSCILLATOR OSCILLOSCOPE SCLK SSTRB DOUT* OGND AGND MAX 4 3 MAXT86 8 ovT MAX184 4.096V rs ANALOG 9 gy F INPUT I = SCLK DIN fa- +5 +5 ot DOUT 1N4148 roo REFADJ SSTRE I I z VREF SHDN FN.C. 1 & Ct pO.01F TO ark I =- = th Loe ee Le LN 42.5V] 42.5 REFERENCE * FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) **REQUIRED FOR MAX188 ONLY. APOTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES. Figure 5. Quick-Look Circuit Analog Input Range and Input Protection Internal protection diodes, which clamp the analog input to Vpp and Ves, allow the channel input pins to swing from Veg - 0.3V to Vpp + 0.38V without damage. However, for accurate conversions near full scale, the inputs must not exceed Vpp by more than 50mMY, cr be lower than Ves by 50mvV. If the analog input exceeds 50mV beyond the sup- plies, do not forward bias the protection diodes of off-channels over two milliamperes, as excessive current will degrade the conversion accuracy of the on-channel. The full-scale input voltage depends on the voltage at VREF. See Tables 1a and 1b. Quick Look To evaluate the analog performance of the MAX186/MAX188 quickly, use the circuit of Figure 5. The MAX186/MAX188 require a control byte to be writ ten to DIN before each conversion. Tying DIN to +5V feeds in control bytes of $FF (HEX), which trigger MA AXLAA Table 1a. Unipolar Full Seale and Zero Scale Zero Reference Full Scale Scale Internal Reference (MAX186 only) OV +4,096V External Reference * at REFADJ OV | Vrerapu x A at VREF OV VREF *A = 1.678 tor the MAX186, 1.638 for the MAX188 Table 1b. Bipolar Full Seale, Zero Scale, and Negative Full Scale Negative Zero Reference Full Scale Scale Full Scale Internal Reference (MAX186 only) -4.096V/2 OV +4.096V/2 External Reference -1/2VperADS OV +1/2VperAD, at REFADJ x A* x A* at VREF -1/2 VREF OV +1/2 VREF *A = 7.678 for the MAX186, 1.638 jor the MAX188& S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs single-ended unipolar conversions on CH7 in external clock mode without powering down between conver- sions. In external clock made, the SSTRB output pulses high for one clock period before the most significant bit of the 12-bit conversion result comes out of DOUT. Varying the analog input to CH? should alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK. How to Start a Conversion A conversion is started on the MAX186/MAX188 by clocking a control byte into DIN. Each rising edge on SCLK, with CS low, clocks a bit from DIN into the MAX186/MAX188s internal shift register. After CS falls, the first arriving logic 1 bit defines the MSB of the control byte. Until this first start bit arrives, any num- ber of logic 0 bits can be clocked into DIN with no effect. Table 2 shows the control-byte format. Table 2. Control-Byte Format The MAX186/MAX188 are fully compatible with Microwire and SPI devices. For SPI, select the correct clock polarity and sampling edge in the SPI control reg- isters: set CPOL = 0 and CPHA = 0. Microwire and SPI both transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). Example: Simple Software Interface Make sure the GPUs serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode, call it TB1. TB1 should be of the format: 1XXXxXxX11 Binary, where the Xs denote the particular channel and conversion-mede selected. Bit 7 Bit 6 Bits Bit 4 Bit3 Bit2 Bit 1 Bit o (MSB) (LSB) START SEL2 SEL1 SELO UNI/BIP SGL/DIF PD1 PDO Bit Name Description 7(MSB) START The first logic 1 bit after CS goes low defines the beginning of the control byte. 6 SEL2 These three bits select which of the eight channels are used for the conversion. 5 SEL1 See Tables 3 and 4. 4 SELO 3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from OV to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VWREF/2. 2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mede, input signal voltages are referred to AGND. In differential mode, the voltage difference between two channels is measured. See Tables 3 and 4. 1 PD1 Selects clock and power-down modes. O(LSB) PDO PD1 PDO Mode 0 0 Full power-down (lg = 2A) 0 1 Fast power-down (lq = 30UA) 1 0 Internal clock mede 1 1 External clock mode 10 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs Table 3. Channel Selection in Single-Ended Mode (SGL/DIFF = 1) SEL2 SEL1 SELO CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND 0 0 0 + - 1 0 0 + - 0 0 1 + 1 0 1 + - 0 1 0 + - 1 1 0 + 0 1 1 + - 1 1 1 + - Table 4. Channel Selection in Differential Mode (SGL/DIFF = 0) SEL2 SEL1 SELO CHO CH1 CH2 CH3 CcH4 CH5 CH6 CH7 0 0 0 + - 0 0 1 + 0 1 0 + 0 1 1 + - 1 0 0 - + 1 0 1 + 1 1 0 - + 1 1 1 - + 2) Use a general-purpose I/O line on the CPU to pull CS on the MAX186/MAX188 low. 3) Transmit TB1 and simultaneously receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 HEX) and simulta- neously receive byte RB2. 5) Transmit a byte of all zeros (600 HEX) and simulta- neously receive byte RB3. 6) Pull CS on the MAX186/MAX188 high. MA AXLAA Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 will contain the result of the conversion padded with one leading zero and three trailing zeros. The total conversion time is a function of the serial clock frequency and the amount of dead time between 8-bit transfers. Make sure that the total conversion time does not exceed 120s, to avoid excessive T/H droop. Digital Output In unipolar input mode, the output is straight binary (see Figure 15). For bipolar inputs, the output is twos-complement (see Figure 16). Data is clocked out at the falling edge of SCLK in MSB-first format. 11 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs 1.58 (CLK = 2MHz2) cs [ ft taco. >} SCLK 1 4 8 2 6 bo ea DIN braatfsece|sets fsero | UM | Sl pp: | eno | SSTRE ] [ }#_- FB2 mt RBS >| RB4 a boul [Fuleo[=lelalel=| [xlelea lola A/D STATE IDLE et CONVERSION }a inte Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible) ~ DOUT "*" I l l Il ' ! I 1 icss pt I ha tcu rm tsH I Be tcl A I I I I I I I SCLK ) \ } \ y \ eee I ise | l | Ptipy pe I ri-- tcsh - 7 ---J_- | Figure 7. Detailed Serial-interface Timing internal and External! Clock Modes The MAX186/MAX188 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1 86/MAX188. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PDO of the control byte program the clock mode. Figures 7 through 10 show the timing characteristics common to both medes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con- 12 version steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approxi- mation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (see Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB will output a logic low. Figure 8 shows the SSTRB timing in external clack mode. The conversion must complete in some minimum time, cr else droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mede if the clock period exceeds 10s, or if serial-clock interruptions could cause the conversion interval to exceed 120us. MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs cs eee I i tspv l ae SSTRB now! he ~~ | I I SCLK too CLOCKED IN Tol fens I l 1 il * m testas l -tsstaB Figure 8. External Clock Mode SSTRB Detailed Timing =] 4 SCLK +f fel fal det fet jel fet fe 1.58 (CLK = 2MHz) DIN brant|sev2 | set: IseLo j UAL | SCL] PD }poo | a Kc SSTRB | EB it ft tconv >| mur - yee Te TT Te Ti zeros A/D STATE IDLE ACQUISITION thos > IDLE Figure 9. internal Clock Mode Timing internal Clock In internal clock mode, the MAX186/MAX188 generate their own conversion clock internally. This frees the microprocessor from the burden of running the SAR con- version clock, and allows the conversion results to be read back at the processors convenience, at any clock rate from Zero to typically 1OMHz. SSTRB goes low at the start of the conversion and then goes high when the con- version is complete. SSTRB will be low for a maximum of 10ps, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out at this register at any time after the conversion is com- plete. After SSTRB goes high, the next falling clock edge MA AXLAA will produce the MSB of the conversion at DOUT, fol- lowed by the remaining bits in MSB-first format (see Figure 9). CS does not need to be held low once a con- version is started. Pulling CS high prevents data from being clocked into the MAX186/MAX188 and three- states DOUT, but it does not adversely effect an internal clock-mode conversion already in progress. When inter- nal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 10 shows the SSTRB timing in internal clock mode. In internal clock mode, data can be shifted in and out of the MAX186/MAX188 at clock rates exceeding 4.0MHz, provided that the minimum acquisition time, taz, is kept above 1.5us. 13 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CS eee I _'! ! eT pt cs l I SSTRB #ee I I I l l + IgsTaB l I l SCLK #e6 PDO CLOCK IN NOTE: FOR BEST NOISE PERFORM ANCE, KEEP SCLK LOW DURING CONVERSION. Figure 10. Internal Clock Mode SSTRB Deiailed Timing Data Framing The falling edge of CS does net start a conversion on the MAX186/MAX188. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PDO bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low any- time the converter is idle, e.g. after Voc is applied. OR The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto the DOUT pin. If a falling edge on CS forces a start bit before bit 5 (B5) becomes available, then the current conversion will be terminated and a new one started. Thus, the fastest the MAX186/MAX188 can run is 15 clocks per conversion. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can drive the MAX186/MAX188. Figure 11b shows the serial-interface timing necessary to perform a conver- sion every 16 SCLK cycles in external clock mode. 14 Applications Information Power-On Reset When power is first applied and if SHDN is not pulled low, internal power-on reset circuitry will activate the MAX186/MAX188 in internal clock mode, ready to con- vert with SSTRB = high. After the power supplies have been stabilized, the internal reset time is 100ps and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN will be interpreted as a start bit. Until a conversion takes place, DOUT will shift out zeros. Reference-Buffer Compensation In addition to its shutdown function, the SHDN pin also selects internal or external compensation. The compen- sation affects both power-up time and maximum conver- sion speed. Compensated or not, the minimum clock rate is 100kHz due to droop on the sample-and-hold. To select external compensation, float SHDN. See the Typical Operating Circuit, which uses a 4.7UF capacitor at VREF. A value of 4.7uF or greater ensures stability and allows operation of the converter at the full clock speed of 2MHz. External compensation increases power-up time (see the Choosing Power-Down Mode section, and Table 5). Internal compensation requires no external capacitor at VREF, and is selected by pulling SHDN high. Internal com- pensation allows for shortest power-up times, but is only available using an external clock and reduces the maxi- mum clock rate to 400kHz. MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs DIN XXXN s | CONTROL BYTE 0 | $ | CONTROL BYTE 1 | $ | CONTROL BYTE 2 boul nl SSTRB }B11 B10 B9 BS B7 BG BS B4 BS B2 Bt BO| CONVERSION RESULT 0 }B11 B10 B9 B8 B7 B6 BS B4B3 B2 Bt BO | CONVERSION RESULT 1 Figure fa. External Clock Mode, 15 Clocks/Conversion Timing cs XXX DIN XK s | CONTROL BYTE 0 [s | CONTROL BYTE 1 eee boul mxxxm | 811 B10 Bo BS B7 BG BS B4 BS B2 BI BO | CONVERSION RESULT O BOCOCR | Bii Bit BO B eee CONVERSION RESULT 1 Figure 17b. Extemal Clock Mode, 16 Clocks/Conversion Timing Power-Down Choosing Power-Down Mode You can save power by placing the converter in a low-current shutdown state between conversions. Select full power-down or fast power-down mode via bits 7 and 8 of the DIN control byte with SHDN high or floating (see Tables 2 and 6). Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 7 and 8 of DIN word (see Table 7). Full power-down mode turns off all chip functions that draw quiescent current, reducing Ipp and Iss typically to 2yA. Fast power-down mode turns off all circuitry except the bandgap reference. With the fast power-down mode, the supply current is 830A. Power-up time can be shortened to 5ys in internal compensation mode. In both software shutdown modes, the serial interface remains operational, however, the ADC will not convert. Table 5 illustrates how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, the power-up time is 20ms with a 4.7UF compensation capacitor (200ms with a S3uF capacitor) when the capacitor is fully discharged. In fast power-down, you can eliminate start-up time by MA AXLAA using low-leakage capacitors that will not discharge more than 1/2LSB while shut down. In shutdown, the capacitor has to supply the current into the reference (1.5/A typ) and the transient currents at power-up. Figures 12a and 12b illustrate the various power-down sequences in both external and internal clock modes. Software Power-Down Software power-down is activated using bits PD1 and PDO cf the control byte. As shown in Table 6, PD1 and PDO also specify the clock mode. When software shut- down is asserted, the ADC will continue to operate in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quies- cent-current state. In internal clock mode, the interface remains active and conversion results may be clocked out while the MAX186/MAX188 have already entered a software power-down. The first logical 1 on DIN will be interpreted as a start bit, and powers up the MAX186/MAX188. Following the start bit, the data input word or control byte also deter- mines clock and power-down modes. For example, if the DIN word contains PD1 = 1, then the chip will remain powered up. If PD1 = 0, a power-down will resume after one conversion. 15 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs CLOCK INTERNAL EXTERNAL rat EXTERNAL MODE 1 1 ! I ! I SHON T | df 1 SETS EXTERNAL ___ SETS FAST SETSEXTERNAL I #1 CLOCK MODE POWER-DOWN CLOCK MODE y! I 1 . MODE = I DIN [s[eleDee ih i shhkbh bh] [shih Al i \ 1 I I I DOUT | DATA VALID | DATA VALID | I fiatioloatainvatio! | (12 DATA BITS} (12DATABITS) | 4 ! 1 FULL POWERED MODE . POWERED UP Pr gr hat POWERED uP ae uP POWER-DOWN Figure 12a. Timing Diagram Power-Down Modes, External Clock Table . Typical Power-Up Delay Times Reference Reference- VREF Power- Power-Up Maximum Buffer Buffer Capacitor Down Delay Sampling Compensation (uF) Mode (sec) Rate (ksps) Mode Enabled Internal Fast SU 26 Enabled Internal Full 300 26 Enabled External 47 Fast See Figure 14c 133 Enabled External 47 Full See Figure 14c 133 Disabled Fast 2u 133 Disabled Full ey 133 Table 6. Software Shutdown and Clock Mode Table 7. Hard-Wired Shutdown and Compensation Mode PD1 PDO Device Mode SHDN Device Reference-Bu ffer 1 1 External Clock Mode State Mode Compensation 1 0 Internal Clock Mode 1 Enabled Internal Compensation 0 1 Fast Power-Down Mode Floating Enabled External Compensation 0 0 Full Power-Down Mode 0 Full Power-Down N/A 16 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs CLOCK MODE __ SETS INTERNAL CLOCK MODE cs DIN bs [ef feelih To] DOUT | DATA VALID I ee INTERNAL CLOCK MODE Fel xls eof] __ SETS FULL POWER-DOWN cD DATA VALID SSTRB CONVERSION MODE POWERED UP CONVERSION I I FULL \ POWER -DOWN I I 1 POWERED UP Figure 12b. Timing Diagram Power-Down Modes, internal Clock Hardware Power-Down The SHDN pin places the converter into the full power-down mode. Unlike with the software shut-down modes, conversion is not completed. It stops coinci- dentally with SHDN being brought low. There is no power-up delay if an external reference is used and is not shut down. The SHDN pin alse selects internal or external reference compensation (see Table 7). Power-Down Sequencing The MAX186/MAX188 auto power-down modes can save considerable power when operating at less than maximum sample rates. The following discussion illus- trates the various power-down sequences. Lowest Power at up to 500 Conversions/Channel/Second The following examples illustrate two different power-down sequences. Other combinations of clock rates, compen- sation modes, and power-down modes may give lowest power consumption in other applications. Figure 14a depicts the MAX186 power consumption for one or eight channel conversions utilizing full power-down mode and internal reference compensation. A 0.01pF bypass capacitor at REFADJ forms an RC filter with the internal 20kQ reference resistor with a 0.2ms time constant. To achieve full 12-bit accuracy, 10 time constants or 2ms are required after power-up. Waiting 2ms in FASTPD mode instead of full power-up will reduce the power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 13. ow ELITE} FULLPD 2.5 FASTPD REFADJ ov 4V VREF ov COMPLETE CONVERSION SEQUENCE ai 2ms Wall CCE} 4-H t= RC = 20kQ x Crerapy CHi CH? (ZEROS) NOPD FULLPD FASTPD > IguFFeN = 15 8 MK Figure 13. MAX{186 FULLPD/FASTPD Power-Up Sequence MA AXLAA 17 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs MAX186 FULL POWER-DOWN 1000 WAMBEHaA 2ms FASTPD WAIT 400kKHZ EXTERNAL CLOCK INTERNAL GOM PENS ATION CHANNELS 00 1 CHANNEL AVG. SUPPLY CURRENT { A} 1 O 50 100 150 200 250 300 350 400 450 500 CONVERSIONS PER CHANNEL PER SECOND MAX1B6/MAX188 FAST POWER-DOWN 10,000 CHANNELS 1000 1 CHANNEL oo o Hz EXTERNAL CLOCK NAL COMPENSATION 8 WAIT AVG. SUPPLY CURRENT ( A} G 2k 4k GR KOK 612k 614k 16k 18k CONVERSIONS PER CHANNEL PER SECOND Figure 14a. MAXT86 Supply Current vs. Sample Raie/Second, FULLPD, 400kHz Clock Lowest Power at Higher Throughputs Figure 14b shows the power consumption with external-reference compensation in fast power-down, with one and eight channels converted. The external 4.7UF compensation requires a 50us wait after power-up, accomplished by 75 idle clocks after a dummy conver- sion. This circuit combines fast multi-channel conversion with lowest power consumption possible. Full power-down mode may provide increased power sav- ings in applications where the MAX186/MAX188 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. External and Internal References The MAX186 can be used with an internal or external reference, whereas an external reference is required for the MAX188. Dicde D1 shown in the Typical Operating Circuit ensures correct start-up. Any standard signal diode can be used. For both parts, an external refer- ence can either be connected directly at the VREF ter- minal or at the REFADJ pin. An internal buffer is designed to provide 4.096V at VREF for both the MAX186 and MAX188. The MAX186's internally trimmed 2.46V reference is buffered with a gain of 1.678. The MAX188's buffer is trimmed with a buffer gain of 1.638 to scale an external 2.5V reference at REFADJ to 4.096V at VREF. MAX186 Internal Reference The full-scale range of the MAX186 with internal reference is 4.096V with unipolar inputs, and +2.048 with bipolar inputs. The internal reference voltage is adjustable to +1.5% with the Reference-Adjust Circuit of Figure 17. 18 Figure 14b. MAX186/MAX188 Supply Current vs. Sample Rate/Second, FASTPD, 2MHz Clock 3.0 2.5 2.0 POWER-UP DELAY (ms} in 0.0001 0.001 0.01 0.41 1 10 TIME IN SHUTDOWN (sec) Figure f4c. Typical Power-Up Delay vs. Time in Shuidown External Reference With both the MAX186 and MAX188, an external refer- ence can be placed at either the input (REFADJ) or the output (VREF} of the internal buffer amplifier. The REFADJ input impedance is typically 20kQ for the MAX186 and higher than 100k for the MAX188, where the internal reference is omitted. At VREF, the input impedance is a minimum of 12k for DC currents. During conversion, an external reference at VREF must be able to deliver up to 850A DC load current and have an output impedance of 100 or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7yF capacitor. MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs OUTPUT CODE FULL-SCALE 11...111 TRANSITION 11...110 ~ I ! ! ! ! I ! y FS = +4.096V Pd 1 1LSB=_F& , I 4996 # I I I OO...011 I Oo...010 ' oo... 004 ' oo...000 LL} - - ------ ly 0 4 2 93 t FS INPUT VOLTAGE (LSBs) FS -32LSB O11. 144 Ott... 110 FS = 44.096 1 = 2 ' haa] I 1LSB = 44,096 1 Ooo... 010 7 4096 I o00...001 + ; 000...000 P------------,J------- t-- I 404th oP ' 1 I 114...110 ; 1 144.0 .401 1 I I I 1 I = ! ; 100...001 \ ; 100... 000 ' 1 ' L i | FS ov +FS - 1L SB INPUT VOLTAGE (LSBs) Figure 15. MAX186A4AX188 Unipolar Transfer Function, 4.096V = Full Scale Using the buffered REFADJ input avoids external buffering of the reference. To use the direct VREF input, disable the internal buffer by tying REFADJ to Vpp. Transfer Function and Gain Adjust Figure 15 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 16 shows the bipolar input/output transfer function. Code transitions occur halfway between successive integer LSB values. Output coding is binary with 1 LSB = 1.00mV (4.096V/4096) for unipolar operation and 1 LSB = 1.00mV ((4.096V/2 - -4.096/2)/4096) for bipolar operation. Figure 17, the MAX186 Reterence-Adjust Circuit, shows how to adjust the ADC gain in applications that use the internal reference. The circuit provides +1.5% (+65LSBs) of gain adjustment range. Layout, Grounding, Bypassing For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the ADG package. Figure 18 shows the recommended system ground connections. A single-point analog ground (star ground point) should be established at AGND, sepa- rate from the logic ground. All other analeg grounds MA AXLAA Figure 16. MAX186/MAX18& Bipolar Transfer Function, +4.096V/2 = Full Scale +8 MAXIAA MAX186 510k 100k an a REFADJ 12 0.01 F 24k 1 Figure 17. MAX186 Reference-Adjust Circuit and DGND should be connected to this ground. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low imped- ance and as short as possible for noise-free operation. High-frequency noise in the Vpp power supply may affect the high-speed comparator in the ADC. Bypass these supplies to the single-point analog ground with 0.1uF and 4.7uF bypass capacitors close to the MAX186/MAX188. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a low- pass filter, as shown in Figure 18. 19 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs SUPPLIES +3 3 GND R*=108 + AE : Yop AGND Veg DGND +3 DGND MAXLAN DIGITAL MAXT BBM AX1 88 CIRCUITRY * OPTIONAL Figure 18. Power-Supply Grounding Connection High-Speed Digital Interfacing with QSPI The MAX186/MAX188 can interface with QSPI at high throughput rates using the circuit in Figure 19. This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in mem- ory without taxing the CPU since QSPI incorporates its own micro-sequencer. Figure 19 depicts the MAX186, but the same circuit could be used with the MAX188 by adding an external reference to VREF and connecting REFADJ to Vpp. Figure 20 details the code that sets up QSPI for autonomous operation. In external clock mode, the MAX186/MAX188 perform a single-ended, unipolar con- version on each of their eight analog input channels. Figure 21, QSPI Assembly-Code Timing, shows the tim- ing associated with the assembly code cf Figure 20. The first byte clocked inte the MAX186/MAX188 is the control byte, which triggers the first conversion on GHO. The last two bytes clocked into the MAX186/MAX188 are all zero and clock out the results of the CH7 conversion. 2 F Voor Vope Voosyn Veray ar O41 F cHO Yoo 20 | aa = CH2 ef} MAXIAN H3 DI MAX BE CH4 SSTRB 7 z= uv. cr AG Am ont SCLK wt T = = SCK PCSO N 17 | | ie | MOSI Y. MC68HC16 CHS DouT p15 CHE DGND CH7 AGND Veg REFADJ atheachtachheh | pee 13 12 eunn Q. 11 Seon eer tae ak T vssi_ W998 MISO O1F * CLOCK CONNECTIONS NOT SHOWN Figure 19. MAX186 QSP! Connection 20 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs *Title : MAX186.ASM * Description : * This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM provided in the Motorola 68HC16 Evaluation Kit. Roger J.A. Chen, Applications Engineer MAXIM Integrated Products November 20, 1992 * oF + FF FF INCLUDE EQUATES.ASM ;Equates for common reg addrs INCLUDE ORGOO00G.ASM initialize reset vector INCLUDE ORGOO008. ASM <initialize interrupt vectors ORG $0200 :start program after interrupt vectors INCLUDE INITSYS.ASM set EK=F,XK=0, YK=0, 7K=0 set sys clock at 16.78 MHz, COP off INCLUDE INITRAM.ASM :turn on internal SRAM at $10000 :sel stack (SK=1, SP=03FE) MAIN: JSR INITQSPI MAINLOCP: JSR READ186 WAIT: LDAA SPSR ANDA #$80 BEQ WAIT wait for QSPI to finish BRA MAINLOOP ENDPROGRAM: INITQSPI: This routine sets up the QSPI microsequencer to operate on its own. The sequencer will read all eight channels of a MAX186/MAX1 88 each time it is triggered. The A/D converter results will be left in the receive data RAM. Each 16 bit receive data RAM lecation will shave a leading zero, 12 bits of conversion result and three zeros. Receive RAM Bits 151413 1211 10 09 08 07 06 05 04 03 02 01 00 A/D Result 0 MSB LSBO0 0 0 ~* Initialize the QSFI Registers ****** PSHA PSHB LDAA #%01111000 STAA GQPDR idle state for PCSO-3 = high LDAA #%01111011 STAA QPAR assign port D to be QSPI LDAA #%01111110 STAA OQDDR ;only MISO is an input LDD #$8008 STD SPCRO master mode, 16 bits/transfer, -GPOL=CPHA=0,1MHz Ser Clock LBD #$0000 STD SPCRI :set delay between PCSO and SCK, is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software Figure 20. MAX186/MAX1 88 Assembly-Code Listing MA AXLAA 21 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs set delay between transfers LDD #$0800 STD SPCR2 set ENDOP to $8 for 9 transfers ***** Initialize QSPI Command RAM ***** LDAA #$80 CCONT=1,BITSE=0,DT=0, DSCK=0,PCS0=ACTIVE STAA $FD40 store first byte in COMMAND RAM LDAA #$CO CCONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE STAA $FD41 STAA $FD42 STAA $FD43 STAA $FD44 STAA $FD45 STAA $FD46 STAA $FD47 LDAA #$40 CONT=0,BITSE=1,DT=-0,DSCK=0,PCSO=ACTIVE STAA $FD48 *ee** Initialize QSPI Transmit RAM ***** LDD #$008F STD $FD20 LBD #$00CF STD $FD22 LDD = #$009F STD $FD24 LDD #$00DF STD $FD26 LBD #$00AF STD $FD28 LDD #$00EF STD $FD2A LDD = #$00BF STD $FD2c LDD = #$00FF STD $FD2E LDD #$0000 STD $FD30 PULB PULA RTS READ186: ;This routine triggers the QSPI microsequencer to autonomously trigger conversions on all 8 channels of the MAX186. Each conversion result is stored in the receive data RAM. PSHA LDAA #$80 ORAA SPCRI STAA SPCRI1 just set SPE PULA RIS KkRKE weex Interrupts/Exceptions BDM: BGND exception vectors point here Figure 20. MAX186/MAX1 88 Assembly-Code Listing (continued) 22 MA AXLAALow-Power, 8-Channel, Serial 12-Bit ADCs Figure 21. QSP! Assembly-Coda Timing TMS320C3x to MAX186 Interface Figure 22 shows an application circuit to interface the MAX186/MAX188 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 23. Use the following steps to initiate a conversion in the MAX186/MAX188 and to read the results: 1} The TMS320 should be configured with CLKX (trans- mit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR of the TMS320 are tied together with the SCLK input of the MAX186/MAX188. 2) The MAX186/MAX188 CS is driven low by the XF_ I/O port of the TMS320 to enable data to be clocked into DIN of the MAX1 86/MAX188. 3) An 8-bit word (1XXXXX11) should be written to the MAX186/MAX188 to initiate a conversion and place the device into external clock mode. Refer to Table 2 to select the proper XXXXX bit values for your spe- cific application. 4) The SSTRB output of the MAX186/MAX188 is moni- tored via the FSR input of the TMS320. A falling edge on the SSTRB output indicates that the conver- sion is in progress and data is ready to be received from the MAX186/MAX188. MA AXLAA XF ee) CS OLKX SCLK TM S320C3x | SA AXLAA CLKR MAX1 66 MAX1 68 Dx pe! DIN DR ia DOUT FSR ha $STRB Figure 22. MAX186/MAX188 to TMS320 Serial interface 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits rep- resent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX186/MAX188 until the next conversion is initiated. 23 S8LXVW/ISLXVNMAX186/MAX188 Low-Power, 8-Channel, Serial 12-Bit ADCs cs \ SCLK fo a PP IPS DIN __fstant \ seve J seus sev Junvair fsa. air} PDI | PDO \ - TRB $8 7 DOUT 7 HF r_\ HIGH PIMPED ANCE A Fuse (er Yuse | HIGH MSB B10 Bt LSB IMPEDANCE a Typical Operating Circuit Figure 23. TMS320 Serial interface Timing Diagram +5 ha CHO Yoo ' | Von == 03 ov to DGND 0.4 F wane C4 ANAL INPUTS AGND Jor \ AAAXLM ae CPU woiCH? MAXI8G Ves = cs 1/0 SCLK + SCK (SK)* ; VREF DIN f+ MO8I ($0) are DOUT + M180 (SI) = REFADJ SSTREF ca oc) suny Le Veg 0.01 FL. SHDN L _Ordering Information (continued) PART? TEMP. RANGE PIN-PACKAGE MAX188 CPP OT to+70T 20 Plastic DIP MAX188_CWP OT to+70T 2080 MAX188 CAP 6 to+70T 20 SSOP MAX188DC/D OT to+70T Dice* MAX188 EPP -40C to +85 C Plastic DIP MAX188 EWP -40C to +85 C 2080 MAX188_EAP -40C to +85 C 20 SSOP MAX188 MJP -55C to +125 20 CERDIP** PART TEMP. RANGE BOARD TYPE MAX1 86EVKIT-DIP OC to +70C Through-Hole Chip Topography CGH1 GHO Voo SCLK 0.151" (3.84 mm) sg SHDN __ VREF REFADJ AGND o.417" Pa (2.97 mm) MAX186/MAX188 TRANSISTOR COUNT: 2278; SUBSTRATE CONNECTED TO Vpp + NOTE: Parts are offered in grades A, B, C and D (grades defined in Glecirical Characieristics). When ordering, piease specify grade. * Dice are specified at +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1996 Maxim Integrated Products Printed USA AAAXLAMA js a registered trademark of Maxim Integrated Products.