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®
VSP3000
12-Bit, 6MHz
CCD/CIS SIGNAL PROCESSOR
FEATURES
●
12-BIT, 6MHZ A/D CONVERTER
●GUARANTEED NO MISSING CODES
●3 CHANNEL, 2MHz COLOR SCAN MODE:
Correlated Double Samplers
8-Bit Offset Adjustment DACs
0dB to +13dB PGAs
●A/D INPUT MONITOR
●INTERNAL VOLTAGE REFERENCE
●SINGLE +5V SUPPLY
●3V OR 5V DIGITAL OUTPUT
●LOW POWER: 475mW typ (3-CH Mode)
DESCRIPTION
The VSP3000 is a complete, three-channel image
signal processor for Charge Coupled Device (CCD)
or Contact Image Sensor (CIS) systems. Each chan-
nel contains sensor signal sampling, Black Level
adjustment and a programmable gain amplifier. The
three inputs are multiplexed into a high speed, 12-bit
analog-to-digital converter. Input circuitry can be
configured, by digital command, for CCD or CIS
sensors. A Black Clamp and Correlated Double
Samplers (CDS) are provided for CCD sensors. For
CIS devices, the VSP3000 provides a single-ended
sampler and a reference input. The VSP3000 is
available in a 48-lead LQFP package and operates
from 0°C to +85°C with a single +5V supply.
TM
VSP3000
©1998 Burr-Brown Corporation PDS-1444B Printed in U.S.A. August, 1999
APPLICATIONS
●CCD AND CIS COLOR SCANNERS
●FAX AND MULTI-FUNCTION MACHINES
●INDUSTRIAL/ MEDICAL IMAGING SYSTEMS
85
RINP
RINN
Clamp
85
GINP
GINN
Clamp
8
5
5
8
8
3
8
12
CDS
CDS
CDS
PGA
PGA
PGA
BINP
BINN
Clamp
8-Bit
DAC
8-Bit
DAC
8-Bit
DAC
MUX
Timing
Bandgap
Reference
R
G
B
Offset
Register
R
G
B
Gain
Adjust
Register
Configuration
Register
Register
Port
M1 M2 M3
12-Bit
A/D
P/S
WRT
RD
SCLK
SD
CM
REFT
REFB
OE
V
DRV
B0-B11
(D0-D7, A0-A2)
VSP3000
CK1CLP CK2 STRT V
REF
ADCCK TP0
®
2
VSP3000
SPECIFICATIONS
At TA = full specified temperature range, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, and PGA gain = 1, unless otherwise specified.
VSP3000Y
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 12 Bits
SPECIFIED TEMPERATURE RANGE 0 to +85 °C
CONVERSION CHARACTERISTICS
3-Channel CDS Mode 6 MHz
3-Channel CIS Mode 6 MHz
ANALOG INPUTS
Full-Scale Input Range 0.5 3.5 Vp-p
Input Capacitance 10 pF
Input Limits GNDA – 0.3 VDDA + 0.3 V
DYNAMIC CHARACTERISTICS
Integral Non-Linearity (INL) ±1±2 LSB
Differential Non-Linearity (DNL) 0.3 0.75 LSB
No Missing Codes 12 Bits
Input-Referred Noise 0.3 LSBs rms
PSRR 0.04 % FSR
DIGITAL INPUTS
Logic Family CMOS
Convert Command Start Conversion Rising Edge of ADCCK
High Level Input Current (VIN = VDDD)10 µA
Low Level Input Current (VIN = 0V) 10 µA
High Level Input Voltage 3.5 V
Low Level Input Voltage 1V
Input Capacitance 5pF
DIGITAL OUTPUTS
Logic Family CMOS
Logic Coding Straight Binary
VDRV Supply Range +2.7 +5.3 V
Output Voltage, VDRV = +5V
Low Level IOL = 50µA +0.1 V
High Level IOH = 50µA +4.6 V
Low Level IOL = 1.6mA +0.4 V
High Level IOH = 0.5mA +2.4 V
Output Voltage, VDRV = +3
Low Level IOL = 50µA +0.1 V
High Level IOH = 50µA +2.5 V
3-State Enable Time OE = LOW 20 40 ns
3-State Enable Time OE = HIGH 2 10 ns
Output Capacitance 5pF
Data Latency 6 Clock Cycles
Data Output Delay CL = 15pF 12 ns
DC ACCURACY
Zero Error 0.8 % FS
Gain Error 1.5 % FS
Reference Input Resistance 800 Ω
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VSOperating 4.7 5 5.3 V
Supply Current: +ISOperating 95 102 mA
Power Dissipation Operating 475 510 mW
Thermal Resistance,
θ
JA 75 C/W
®
3VSP3000
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
VDDA, VDDD,VDRV ................................................................................... +6V
Analog Input....................................................... (–0.3V) to (+VDDA + 0.3V)
Logic Input ......................................................... (–0.3V) to (+VDDD + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature..................................................................... +150 °C
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PRODUCT PACKAGE
VSP3000Y DEM-VSP3000Y
DEMO BOARD ORDERING INFORMATION
PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA
VSP3000Y 48-Lead LQFP 340 0°C to +85°C VSP3000Y VSP3000Y 250-Piece Tray
"""""VSP3000Y/2K Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3000Y/2K” will get a single 2000-
piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
®
4
VSP3000
PIN DESCRIPTIONS
PIN DESIGNATOR TYPE DESCRIPTION PIN DESIGNATOR TYPE DESCRIPTION
1 CLP DI Clamp Enable
2 GNDAP Analog Ground
3 RINP AI Red-Channel Analog Input
4 RINN AI Red-Channel Reference Input
5 GNDAP Analog Ground
6 GINP AI Green-Channel Analog Input
7 GINN AI Green-Channel Reference Input
8 GNDAP Analog Ground
9 BINP AI Blue-Channel Analog Input
10 BINN AI Blue-Channel Reference Input
11 GNDAP Analog Ground
12 VDDA P Analog Power Supply, +5V
13 STRT DI Start Line Scanning
14 ADCCK DI A/D Converter Clock Input
15 CK1 DI Sample Reference Clock
16 CK2 DI Sample Data Clock
17 GNDDP Digital Ground
18 RD DI Read Signal for Registers
19 WRT DI Write Signal for Registers
20 P/S DI Parallel/Serial Port Select.
HIGH = Parallel, LOW = Serial
21 SD DI Serial Data Input
22 SCLK DI Serial Data Clock
23 VDDD P Digital Power Supply, +5V
24 OE DI A/D Converter Output Enable
25 B0 (D0) LSB DIO
A/D Output (Bit 0) and Register Data Port (Bit 0)
26 B1 (D1) DIO
A/D Output (Bit 1) and Register Data Port (Bit 1)
27 B2 (D2) DIO
A/D Output (Bit 2) and Register Data Port (Bit 2)
28 B3 (D3) DIO
A/D Output (Bit 3) and Register Data Port (Bit 3)
29 B4 (D4) DIO
A/D Output (Bit 4) and Register Data Port (Bit 4)
30 B5 (D5) DIO
A/D Output (Bit 5) and Register Data Port (Bit 5)
31 B6 (D6) DIO
A/D Output (Bit 6) and Register Data Port (Bit 6)
32 B7 (D7) DIO
A/D Output (Bit 7) and Register Data Port (Bit 7)
33 B8 (A0) DIO A/D Output (Bit 8) and Register Address (Bit 0)
34 B9 (A1) DIO A/D Output (Bit 9) and Register Address (Bit 1)
35 B10 (A2) DIO A/D Output (Bit 10) and Register Address (Bit 2)
36 B11 MSB DIO A/D Output (Bit 11)
37 VDRV P Output Driver Voltage Supply
38 VDDD P Digital Power Supply, +5V
39 GNDDP Digital Ground
40 TP0 AO A/D Converter Input Monitor Pin
41 GNDAP Analog Ground
42 VDDA P Analog Power Supply, +5V
43 VREF AIO Reference Input/Output
44 GNDAP Analog Ground
45 REFB AO Bottom Reference
46 CM AO Common-Mode Voltage
47 REFT AO Top Reference
48 VDDA P Analog Power Supply, +5V
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
B11 (MSB)
B10 (A2)
B9 (A1)
B8 (A0)
B7 (D7)
B6 (D6)
B5 (D5)
B4 (D4)
B3 (D3)
B2 (D2)
B1 (D1)
B0 (D0, LSB)
V
DDA
REFT
CM
REFB
GND
A
V
REF
V
DDA
GND
A
TP0
GND
D
V
DDD
V
DRV
STRT
ADCCK
CK1
CK2
GND
D
RD
WRT
P/S
SD
SCLK
V
DDD
OE
1
2
3
4
5
6
7
8
9
10
11
12
CLP
GND
A
RINP
RINN
GND
A
GINP
GINN
GND
A
BINP
BINN
GND
A
V
DDA
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
VSP3000Y
®
5VSP3000
TIMING SPECIFICATIONS
Timing Specifications = tMIN to tMAX with +5V power supply.
SYMBOL PARAMETER MIN TYP MAX UNITS
Clock Parameters
tCK1AP 3-Channel Conversion Rate 300 500 ns
tCK1BP 1-Channel Conversion Rate 100 166 ns
tCK1A CK1 Pulse Width 20 125 ns
tCK1B CK1 Pulse Width 20 40 ns
tCK2A CK2 Pulse Width 20 125 ns
tCK2B CK2 Pulse Width 20 40 ns
tCCK ADCCK Pulse Width 40 83 ns
tCKP ADCCK Period 100 166 ns
tSSampling Delay 10 ns
tCK12A CK1 Falling Edge to CK2 Rising Edge 15 ns
tCK12B CK1 Falling Edge to CK2 Rising Edge 15 ns
tCK21A CK2 Falling Edge to CK1 Rising Edge 70 ns
tCK21B CK2 Falling Edge to CK1 Rising Edge 40 ns
tCNV Conversion Delay 40 ns
tST Start Conversion Time 20 100 ns
tSET ADCCK Falling Edge to CK1 Rising Edge 10 ns
tADCCK2 ADCCK Falling Edge to CK2 Falling Edge 5 ns
tADCCK1 ADCCK Falling Edge to CK1 Falling Edge 5 ns
Read/Write Register
tWWRT Pulse Width 30 50 ns
tRW Address Setup Time 20 50 ns
tDA Data Setup Time 30 50 ns
tWD Data Valid Time 30 ns
tSD Data Ready Time 15 50 ns
tSCK Serial Clock Pulse Width 30 50 ns
tSCKP Serial Clock Period 60 100 ns
tSS Serial Ready Time 100 200 ns
tSW WRT Pulse Setup Time 50 ns
tPR Parallel Ready Time 20 ns
tRD Read Out Delay 20 ns
tRH Read Out Hold Time 1 ns
Data Output
tOES A/D Converter Output Enable Setup Time 20 ns
tOEW OE Pulse Width 100 ns
tOER Output Enable Time 20 40 ns
t3E 3-State Enable Time 2 10 ns
tACKD Data Output Delay 12 ns
tOEP Parallel Port Setup Time 10 ns
®
6
VSP3000
TIMING DIAGRAMS
3-Channel CIS Mode Timing
tCCK tCCK
t
CKP
t
CNV
t
ADCCK1
t
S
GRR1G1B1B
t
CK1A
t
SET
R1, G1, B1
t
CK1AP
t
ST
CIS
STRT
CK1
ADCCK
1-Channel CCD Mode Timing
t
CK1BP
t
CK2B
t
CNV
t
CK21B
t
S
t
S
t
CKP
t
CK12B
t
SET
t
CK1B
t
CCK
t
CCK
Pixel 1
CCD
STRT
CK1
CK2
ADCCK Pixel 1
t
CKP
t
CCK
t
CCK
t
CK12A
t
CK2A
t
SET
t
CK21A
t
ST
t
CK1AP
t
CK1A
t
S
t
S
t
CNV
t
ADCCK2
GRR1G1B1B
R1, G1, B1
CCD
STRT
CK1
CK2
ADCCK
3-Channel CCD Mode Timing
®
7VSP3000
TIMING DIAGRAMS (Cont)
1-Channel CIS Mode Timing
tCK1BP
tCKP
tCCK
tCCK
tCK1B
STRT
CIS
CK1
ADCCK
tS
tCNV
tSET
Pixel 1
Pixel 1
Valid
DOUT
OE
ADCCK
P/S
t
OEP
t
OES
t
OER
t
OEW
t
3E
t
ACKD
Timing for A/D Output
Timing for Parallel Port Writing Timing for Reading
Valid
Stable
Valid
t
DA
t
RW
t
RD
t
RH
Register
A2-A0
RD
D7-D0
P/S
t
PR
Valid
Stable
StableA2-A0
P/S
D7-D0
WRT
Register
tRW
tDA
tW
tPR
®
8
VSP3000
TIMING DIAGRAMS (Cont)
DOUT Timing Diagram—3-Channel CDS Mode
(N–3)
R
(N–3)
G
(N–3)
B
(N–2)
R
N
R, G, B
(N+1)
R, G, B
(N+2)
R,G, B
(N+3)
R, G, B
G
(N–2) (N–2)
B
(N–1)
RG
(N–1) (N–1)
B
N
RG
NN
B
(N+1)
RG
(N+1)
CCD
Start
CK1
CK2
ADCCK
DOUT
Timing for Serial Port Writing
t
SS
t
SCK
t
SCK
t
SCKP
t
SD
t
W
t
SW
t
WD
Valid
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
P/S
SCLK
SD
WRT
Data
®
9VSP3000
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDDA = +5V, VDDD = +5V, fADCCK = 6MHz, and fCK2 = 2MHz, unless otherwise specified.
4.70 4.80 4.90 5.00 5.10 5.20 5.30
600
500
400
300
200
100
Power Supply Voltage (V)
Power Dissipation (mV)
POWER DISSIPATION vs POWER SUPPLY VOLTAGE
3-CHANNEL MODE
4.70 4.80 4.90 5.00 5.10 5.20 5.30
600
500
400
300
200
100
Power Supply Voltage (V)
Power Dissipation (mV)
POWER DISSIPATION vs POWER SUPPLY VOLTAGE
1-CHANNEL MODE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Gain
PGA TRANSFER FUNCTION
Sample Quantity, N = 100
0 5 10 15
PGA Gain Setting
20 25 31
®
10
VSP3000
THEORY OF OPERATION
The VSP3000 can be operated in one of the following four
modes:
3-Channel CCD Mode
3-Channel CIS Mode
1-Channel CCD Mode
1-Channel CIS Mode
3-CHANNEL CCD MODE
In this mode, the VSP3000 can simultaneously process three
output CCD signals. These signals are AC-coupled to the
RINP, GINP, and BINP inputs. RINN, GINN, BINN are not
used in this mode and should be grounded. The CLP signal
enables internal biasing circuitry to clamp these inputs to a
proper voltage, enabling internal CDS circuitry to operate
properly. VSP3000 inputs may be applied as DC-coupled
inputs, which need to be level-shifted to a proper DC level.
The correlated double samplers take two samples of the
incoming CCD signals; the CCD reference levels are taken on
the falling edge of CK1 and the CCD information is taken on
the falling edge of CK2. These two samples are then sub-
tracted by the CDSs and the result is the CDS’ output.
Three channels are used to process three inputs simulta-
neously. Each consists of a 5-bit PGA (0dB to +13dB)
and an 8-bit offset digital-to-analog converter (+50mV to
–150mV). A 3-to-1 analog MUX follows the CDS chan-
nels and feeds a high performance 12-bit A/D converter.
The analog MUX can be programmed to cycle between
red, green, and blue or blue, green, and red.
When the STRT signal is HIGH, the conversion is initiated on
the rising edge of ADCCK. The STRT signal indicates the
first samples for a scan line. When STRT goes LOW, the
analog MUX is switched to the first sample of the sequence.
As specified in the “3-Channel CCD Mode” timing diagram,
the falling edge of CK2 must be in the LOW period of
ADCCK. If the falling edge of CK2 is in the HIGH period of
ADCCK (note: ADCCK is for sampling the B Channel), the
VSP3000 will not function properly.
3-CHANNEL CIS MODE
In this mode, the VSP3000 is operated as 3-channel samplers
and a digitizer. Unlike the CDS mode, VSP3000 takes only
one sample on the falling edge of CK1 for each input. Since
only one sample is taken, CK2 is grounded in this operation.
The input signal is DC-coupled in most cases. For example,
for the red channel, RINP is the CIS signal input, and RINN
is the CIS reference signal. The same applies to the green
channel (GINP and GINN) and blue channel (BINP and
BINN).
In this mode, three CDSs become CIS signal processing
circuits (acting like a track-and-hold) to process three inputs
simultaneously. Each CIS signal processing circuit consists
of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC
(+50mV to –150mV). A 3-to-1 analog MUX follows the
CIS signal processing circuits and feeds a high performance
12-bit A/D converter. The analog MUX can be programmed
to cycle between red, green, and blue or blue, green, and
red.
When the STRT signal is HIGH, the conversion is initiated
on the rising edge of ADCCK. The STRT signal indicates the
first sample for a scan line. When STRT goes LOW, the
analog MUX is switched to the first sample of the sequence.
As specified in the “3-Channel CIS Mode” timing diagram,
the falling edge of CK1 must be in the LOW period of
ADCCK. If the falling edge of CK1 is in the HIGH period of
ADCCK (note: ADCCK is for sampling the B Channel), the
VSP3000 will not function properly.
1-CHANNEL CCD MODE
In this mode, the VSP3000 processes only one CCD signal.
The CCD signal is AC-coupled to RINP, GINP, or BINP (as
selected by the data in the Configuration Register). RINN,
GINN, BINN are not used in this mode and should be
grounded. The CLP signal enables internal biasing circuitry
to clamp this input to a proper voltage so that internal CDS
circuitry can work properly. The VSP3000 input may be
applied as a DC-coupled input, which needs to be level-
shifted to a proper DC level.
The CDS takes two samples of the incoming CCD signal. The
CCD reference value is taken on the falling edge of CK1 and
the CCD information is taken on the falling edge of CK2.
These two samples are then subtracted by the CDS and the
result is the CDS’ output.
In this mode, only one of the three channels is enabled. Each
CDS consists of a 5-bit PGA (0dB to +13dB) and an 8-bit
offset DAC (+50mV to –150mV). A 3-to-1 analog MUX is
inserted between the CDSs and a high performance 12-bit A/
D converter. The analog MUX is not cycling between chan-
nels in this mode. Instead, the analog MUX is connected to
a specific channel, depending on the data in the Configuration
Register.
As specified in the “1-Channel CCD Mode” timing diagram,
both the active period of CK1 (tCK1B) and the active period of
CK2 (tCK2B) must be in the LOW period of ADCCK. If it is
in the HIGH period of ADCCK, the VSP3000 will not
function properly.
1-CHANNEL CIS MODE
In this mode, the VSP3000 is operated as a 1-channel sampler
and digitizer. Unlike the CDS mode, VSP3000 takes only one
sample on the falling edge of CK1. Since only one sample is
taken, CK2 is grounded in this operation. The input signal is
DC-coupled in most cases. Here, the VSP3000 inputs are
differential. For example, for the red channel, RINP is the
CIS signal input, and RINN is the CIS reference signal. The
same applies to the green channel (GINP and GINN) and blue
channel (BINP and BINN).
In this mode, the CDS becomes a CIS signal processing
circuit (acting like a track-and-hold). Each CIS signal pro-
cessing circuit consists of a 5-bit PGA (0dB to +13dB) and an
8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog
MUX follows the CIS signal processing circuits and feeds a
®
11 VSP3000
high performance 12-bit A/D converter. The analog MUX is
not cycling between channels in this mode. Instead, the
analog MUX is connected to a specific channel, depending on
the data in the Configuration Register.
As specified in the “1-Channel CIS Mode” timing diagram,
the active period of CK1 (tCK1B) must be in the LOW period
of ADCCK. If it is in the HIGH period of ADCCK, the
VSP3000 will not function properly.
ANALOG PGA
There is one analog PGA on each channel. Each analog PGA
is controlled by a 5-bit PGA gain register. The analog PGA
gain varies from 1 to 4.44 (0dB to +13dB). The transfer
function of the PGA is:
Gain = 4/(4 – 0.1 • X)
where X is the integer representation of the 5-bit PGA gain
register. Figure 1 shows the PGA transfer function plot.
VCLAMP, is derived from the reference. VCLAMP depends on
the value of VREF; if VREF is set to 1V, VCLAMP is 2.5V and
if VREF is set to 1.5V, VCLAMP is 3V. There are many factors
that determine the size of the input coupling capacitors
including CCD signal swing, voltage droop across the input
capacitor since the last clamp interval, leakage current of the
VSP3000 input circuitry, and the time period of CK1. Figure
2 shows a simplified equivalent circuit of the VSP3000
inputs. In this equivalent circuit, the input coupling capacitor,
CIN, and the sampling capacitor, C1, are constructed as a
capacitor divider (during CK1). For AC analysis, op amp
inputs are grounded. Therefore, the sampling voltage, VS
(during CK1) is:
VS = (CIN/CIN + C1)) • VIN
From this equation, we see that a larger value of CIN makes
VS closer to VIN. In other words, the input signal VIN will be
attenuated less if CIN is large. However, there is a disadvan-
tage to using a large value of CIN: the larger the CIN, the more
dummy or optical black pixels must be used to restore the DC
component of the input signal.
CHOOSING CMAX AND CMIN
As mentioned previously, a large CIN is preferable if there is
enough time for the CLP signal to charge up CIN. Typically,
0.01µF to 0.1µF of CIN can be used for most cases. In order
to optimize CIN, the following two equations can be used to
calculate CMAX and CMIN:
CMAX = ( tCK1 • N)/[RSW • ln (VD/VERROR)]
where, tCK1 is the time when both CK1 and CLP are HIGH
and N is the number of black pixels, RSW is the total switch
resistance, VD is the droop across CIN and VERROR is the
difference between VS and VCLAMP. The nominal value of
RSW is 4kΩ plus the driver’s impedance. 0.1V should be
tolerable for VERROR and still keep the VSP3000 working
properly.
CMIN = ( I/VERROR) • t
where, I is 10nA, the typical leakage current of the VSP3000
input circuitry and t is the time between clamp pulses.
FIGURE 1. PGA Transfer Function Plot.
PGA TRANSFER FUNCTION
0 5 10 15 20 25 31
0 5 10 15 20 25 31
Gain
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
PGA TRANSFER FUNCTION
PGA Gain Setting
PGA Gain Setting
Gain (dB)
14
12
10
8
6
4
2
0
C
1
4pF
C
2
4pF
C
IN
V
S
V
CLAMP
OP
AMP
CK1
CK2
CLP
V
IN
CK1
FIGURE 2. Equivalent Circuit of VSP3000 Inputs.
CHOOSING AC INPUT COUPLING CAPACITORS
The purpose of the input coupling capacitor is to isolate the
DC output of the CCD array from affecting the VSP3000. The
internal clamping circuitry restores the necessary DC compo-
nent to the CCD output signal. The internal clamp voltage,
®
12
VSP3000
PROGRAMMING THE VSP3000
The VSP3000 consists of three CCD or CIS channels and a 12-
bit A/D converter. Each channel (red, green, and blue) has its
own 8-bit offset and 5-bit gain adjustable registers to be
programmed by the user. There is also a 7-bit Configuration
Register on-chip to program the different operation modes.
These registers are as follows:
For this example, VREF will be 1V.
Bypass VREF with 10µF and 0.1µF capacitors when internal
reference mode is used.
Example:
A 1-channel CIS mode (red channel) with external 1.2V
reference:
= > D0 = ‘1’, D1 = X, D2 = ‘1’, D4 = ‘0’ and D5 = ‘0’
For this example, VREF will be an input pin, applied with
1.2V. This input will set the full-scale input of the VSP3000
at 2.4V.
Offset Registers
Offset registers control the analog offset input to the channel
prior to the PGA. There is an 8-bit Offset Register on each
channel. The offset range varies from –150mV to +50mV.
The Offset Register uses a Straight Binary code. All ‘0’s
correspond to –150mV and all ‘1’s correspond to +50mV of
the offset adjustment.
PGA Gain Registers
The PGA Gain Registers control the analog gain to the
channels prior to the A/D converter. There is a 5-bit PGA
Gain Register on each channel. The gain range varies from 1
to 4.44 (0dB to +13dB). The PGA Gain Register is a Straight
Binary code. All ‘0’s correspond to analog gain of 0dB and
all ‘1’s correspond to the analog gain of 13dB.
Offset and Gain Calibration Sequence
When the VSP3000 is powered on, it will be initialized as a
3-channel CDS, 1V internal (2V full scale) reference mode
with analog gain of 1. This mode is commonly used for CCD
scanner applications. The calibration procedure is done at the
very beginning of the scan. Once calibration is done, registers
on VSP3000 will keep this information (offset and gain for
each channel) during the operation.
To calibrate the VSP3000, use the following procedure:
Step 1: Set the VSP3000 to the proper mode.
Step 2: Set analog PGA gain to 1 (code: 00H) and offset to
0mV (code: C0H).
Step 3: Scan a dark line.
Step 4: Calculate the pixel offsets according to the ADC
output.
Step 5: Readjust input Offset Registers.
Step 6: Scan a white line.
Step 7: Calculate gain. It will be the ADC full scale divided
by the ADC output when the white line is scanned.
Step 8: Set the Gain Register. If the ADC output is not close
to full scale, go back to Step 3. The calibration is
complete if the output is close to full scale.
These Registers can be accessed by either the parallel or serial
port. In the parallel mode, the address and data port are
combined with the ADC data output pins. The data bus is
assigned as D0 to D7 (pin 25 to pin 32) and the address bus
is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data
(SD), serial clock (SCLK), and write signal (WRT pin for
both parallel and serial writing) are assigned. The following
table shows how to access these modes.
Configuration Register
The Configuration Register is designed as follows:
ADDRESS
A2 A1 A0 REGISTER
0 0 0 Configuration Register (7-Bit)
0 0 1 Red Channel Offset Register (8-Bit)
0 1 0 Green Channel Offset Register (8-Bit)
0 1 1 Blue Channel Offset Register (8-Bit)
1 0 0 Red Channel Gain Register (5-Bit)
1 0 1 Green Channel Gain Register (5-Bit)
1 1 0 Blue Channel Gain Reigster (5-Bit)
1 1 1 Reserved
OE P/S MODE
0 0 A/D Data Output Enabled, Serial Mode Enabled
0 1 Prohibit Mode
1 0 A/D Data Output Disabled, Serial Mode Enabled
1 1 A/D Data Output Disabled, Parallel Mode Enabled
BIT LOGIC ‘0’ LOGIC ‘1’
D0 CDS Mode CIS Mode
D1 VREF = 1V VREF = 1.5V
D2 Internal Reference External Reference
D3
3-Channel, D4 and D5 Disabled 1-Channel, D4 and D5 Enabled
D4 D5
0 0 Red Channel
0 1 Green Channel
1 0 Blue Channel
1 1 XXXXXXXX
D6 R > G > B MUX Sequence B > G > R MUX Sequence
D7 XXXXXXXX XXXXXXXX
For Reading/Writing to the Configuration Register, the ad-
dress will be:
A2 = ‘0’, A1 = ‘0’, and A0 = ‘0’
Example:
A 3-channel CDS with internal reference VREF = 1V (2V full-
scale input), the mode will be:
= > D0 = ‘0’, D1 = ‘0’and D3 = ‘0’
®
13 VSP3000
EVALUATION BOARD SCHEMATIC
36
35
34
33
32
31
30
29
28
27
26
25
10
9
8
7
6
5
4
3
2
1
1
3
5
7
9
11
13
15
B11 (MSB)
B10
B9
B8
B7
B6
B5
B4
17
19
21
23
B3
B2
B1
B0 (LSB)
33 ADCCK
39 OE
11
12
13
14
15
16
17
18
19
20
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
22
20
18
15
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38
13
BINN
14 15 16 17 18 19 20 21 22 23
37
24
VSP3000
C
8
0.1µF
C
7
10µF
C
5
0.1µF
C
1
0.1µFTP1
BNC1
BNC2
BNC3
R
1
50Ω
C
6
0.1µF
C
4
0.1µF
C
9
0.1µFC
10
0.1µFC
11
0.1µFC
12
0.1µF
+
C
18
10µF
C
17
0.1µF
V
DD
V
DRV
+
14
12
10
8
6
4
2
IDT74FCT541T
GINN
RINN
CLP
V
DDD
V
DDA
V
DRV
V
DDA
V
DDD
JP4
C
16
10µF
C
15
0.1µF
+
JP1
TP1
BNC4
STRT
TP2
TP3
C
2
0.1µF
R
2
50ΩJP2
C
3
0.1µF
R
3
50Ω
R
4
50ΩTP5
BNC5
ADCCK
R
5
50ΩTP6
RDWRTP/S SDSCLK
V
DD
C
13
0.1µF
R
9
1kΩ
R
8
1kΩ
R
10
1kΩ
OE
TP7
BNC6
CK1
R
6
50Ω
JP3
V
DDA
REFT
CM
REFB
GND
A
V
REF
V
DDA
GND
A
TP0
GND
D
V
DDD
V
DRV
STRT
ADCCK
CK1
CK2
GND
D
RD
WRT
P/S
SD
SCLK
V
DDD
OE
CLP
GND
A
RINP
RINN
GND
A
GINP
GINN
GND
A
BINP
BINN
GND
A
V
DDA
(MSB) B11
B10 (A2)
B9 (A1)
B8 (A0)
B7 (D7)
B6 (D6)
B5 (D5)
B4 (D4)
B3 (D3)
B2 (D2)
B1 (D1)
(LSB) B0 (D0)
BNC7
CK2
R
7
50Ω
TP0
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
IDT74FCT541T
C
14
0.1µF
R
11
1kΩ
