Integrated Video Decoder and HDMI Receiver ADV7482 Data Sheet FEATURES Component video processor Any-to-any 3 x 3 color space conversion (CSC) matrix Contrast/brightness/hue/saturation video adjustment Timing adjustments controls for horizontal sync (HS)/vertical sync (VS)/data enable (DE) timing Video mute function Serial digital audio output interface HDMI audio extraction support Advanced audio muting feature I2S-compatible, left justified and right justified audio output modes 8-channel TDM output mode available 2 Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) transmitters 4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing options for HDMI/SDP/digital input port sources 1-lane transmitter for standard definition processor (SDP) sources 8-bit digital input/output port General 2-wire serial microprocessor unit (MPU) interface (I2C compatible) -40C to +85C temperature grade 100-ball, 9 mm x 9 mm, RoHS-compliant CSP_BGA package Qualified for automotive applications Analog input Worldwide NTSC/PAL/SECAM color demodulation support with autodetection One 10-bit ADC, 4x oversampling for CVBS, Y/C, and YPbPr 8 analog video input channels with on-chip antialiasing filter Fully differential, pseudo differential, and single-ended CVBS video input support STB diagnostics on differential video inputs CVBS (composite), Y/C (S-Video), and YPbPr (component) video input support Fast switching capability between analog inputs Adaptive contrast enhancement (ACE) Excellent common-mode noise rejection capabilities Rovi (Macrovision) copy protection detection Up to 4 V common-mode input range solution Vertical blanking interval (VBI) data slicer High-Definition Multimedia Interface (HDMI) capable receiver HDCP authentication and decryption support 162 MHz maximum pixel clock frequency, allowing HDTV formats up to 1080p and display resolutions up to UXGA (1600 x 1200 at 60 Hz) HDCP repeater support, up to 25 KSVs supported Integrated CEC controller, CEC 1.4 compatible Adaptive TMDS equalizer 5 V detect and Hot Plug assert APPLICATIONS Portable devices Automotive infotainment (head unit and rear seat entertainment systems) HDMI repeaters and video switches FUNCTIONAL BLOCK DIAGRAM RX0P/RX0N RX1P/RX1N RX2P/RX2N ADV7482 HDMI RECEIVER INTERRUPTS CONTROLLER DDC_SCL DDC_SDA HPD CEC RX_5V LLC P0 TO P7 AIN1 TO AIN8 DIAG1 TO DIAG4 DDC CEC HPD EDID RAM HDCP AUDIO PROCESSOR CP CORE 8-BIT TTL INPUT/OUTPUT AFE I2C SLAVE ALSB SCLK SDATA INTRQ1 INTRQ2 AUDIO OUTPUT FORMATTER I2S_MCLK I2S_LRCLK I2S_SCLK I2S_SDATA 4-LANE MIPI CSI-2 TRANSMITTER CLKAP/CLKAN DA0P/DA0N TO DA3P/DA3N SD CORE 1-LANE MIPI CSI-2 TRANSMITTER DIAGNOSTIC CLKBP/CLKBN DB0P/DB0N 12047-001 RXCP/RXCN Figure 1. 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Technical Support www.analog.com ADV7482 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Recommendation .................................................. 16 Applications ....................................................................................... 1 Power-Up Sequence ................................................................... 16 Functional Block Diagram .............................................................. 1 Power-Down Sequence.............................................................. 16 Revision History ............................................................................... 2 Thoery of Operation ...................................................................... 17 General Description ......................................................................... 3 HDMI Receiver........................................................................... 17 Detailed Functional Block Diagram .............................................. 4 Component Processor ............................................................... 17 Specifications..................................................................................... 5 Analog Front End ....................................................................... 17 Electrical Characteristics ............................................................. 5 Short to Battery Diagnostics ..................................................... 18 Analog Video Specifications ....................................................... 7 Standard Definition Processor ................................................. 18 MIPI Video Output Specifications ............................................. 8 8-Bit Digital Input/Output Port ............................................... 19 Analog Specifications ................................................................... 8 Audio Processing ........................................................................ 19 Timing Specifications .................................................................. 9 MIPI CSI-2 Transmitters ........................................................... 19 Absolute Maximum Ratings .......................................................... 12 Interrupts ..................................................................................... 19 Thermal Resistance .................................................................... 12 Outline Dimensions ....................................................................... 20 ESD Caution ................................................................................ 12 Ordering Guide .......................................................................... 20 Pin Configuration and Function Descriptions ........................... 13 Automotive Products ................................................................. 20 REVISION HISTORY 6/14--Revision 0: Initial Version Rev. 0 | Page 2 of 20 Data Sheet ADV7482 GENERAL DESCRIPTION The ADV7482 is an integrated video decoder and HDMI(R) receiver, targeted at connectivity enabled head units requiring a wired, uncompressed digital audio/video link from smartphones, and other consumer electronics devices to support streaming and integration of cloud-based multimedia content and applications into an automotive infotainment system. The ADV7482 HDMI capable receiver supports a maximum pixel clock frequency of 162 MHz, allowing HDTV formats up to 1080p, and display resolutions up to UXGA (1600 x 1200 at 60 Hz). The device integrates a consumer electronics control (CEC) controller that supports the capability discovery and control (CDC) feature. The HDMI input port has dedicated 5 V detect and Hot PlugTM assert pins. The HDMI receiver includes an adaptive transition minimized differential signaling (TMDS) equalizer that ensures robust operation of the interface with long cables. The ADV7482 contains a component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness, and saturation adjustments, as well as free run and timing adjustment controls for HS/VS/DE timing. The ADV7482 analog front end (AFE) comprises a single high speed, 10-bit analog-to-digital converter (ADC) that digitizes the analog video signal before applying it to the SDP. The eight analog video inputs can accept single-ended, pseudo differential, and fully differential composite video signals, as well as S-Video and YPbPr video signals, supporting a wide range of consumer and automotive video sources. Short to battery (STB) events can be detected on differential input video signals. STB protection is provided by ac coupling the input video signals. The ADV7482, in combination with an external resistor divider, provides a common-mode input range of 4 V, enabling the removal of large signal common-mode transients present on the video lines. The automatic gain control (AGC) and clamp restore circuitry allow an input video signal up to 1.0 V p-p at the analog video input pins of the ADV7482. Alternatively, the AGC and clamp restore circuitry can be bypassed for manual settings. The SDP of the ADV7482 is capable of decoding a large selection of analog baseband video signals in composite, S-Video, and component formats. The SDP supports worldwide NTSC, PAL, and SECAM standards. The ADV7482 features an 8-bit digital input/output port, supporting input and output video resolutions up to 720p/1080i in both the 8-bit interleaved 4:2:2 SDR and DDR modes. To enable glueless interfacing of these video input sources to the latest generation of infotainment system on chips (SoCs), the ADV7482 features two MIPI(R) CSI-2 transmitters. The four-lane transmitter provides four data lanes, two data lanes, and one data lane muxing options, and can be used to output video from the HDMI receiver, the SDP, and the digital input port. The single-lane transmitter can be used to output video from the SDP only. The ADV7482 offers a flexible audio output port for audio data extracted from HDMI streams. The HDMI receiver has advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. Additionally, the ADV7482 can be set to output time division multiplexing (TDM) serial audio, which allows the transmission of eight multiplexed serial audio channels on a single audio output interface port. The ADV7482 is programmed via a 2-wire, serial, bidirectional port (I2C compatible). Fabricated in an advanced CMOS process, the ADV7482 is available in a 9 mm x 9 mm, RoHS-compliant, 100-ball CSP_BGA package and is specified over the -40C to +85C temperature range. The ADV7482 is offered in automotive and industrial versions. Rev. 0 | Page 3 of 20 ADV7482 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM ADV7482 SCLK SDATA ALSB RESET I2C SLAVE/ CONTROL HPD RX_5V 5V DETECT AND HPD PIN CONTROLLER CEC CEC CONTROLLER LLC P0 P1 P2 P3 P4 P5 P6 P7 HDCP KEYS EQUALIZER SAMPLER INTRQ1 INTRQ2 I2S_MCLK I2S_LRCLK I2S_SCLK I2S_SDATA AUDIO OUTPUT FORMATTER HDCP ENGINE PLL RXCP/RXCN RX0P/RX0N RX1P/RX1N RX2P/RX2N AUDIO PROCESSOR PACKET PROCESSOR EDID/ REPEATER CONTROLLER DDC_SDA DDC_SCL GENERAL INTERRUPTS CONTROLLER PACKET/ INFOFRAME MEMORY HDMI PROCESSOR COLOR SPACE CONVERSION COMPONENT PROCESSOR (CP) 8-BIT TO 6-BIT DITHER BLOCK MIPI CSI-2 TRANSMITTER A CSI-2 Tx D-PHY Tx 8-BIT DIGITAL INPUT/ OUTPUT PORT CLKAP/ CLKAN DA0P/DA0N DA1P/DA1N DA2P/DA2N DA3P/DA3N CLOCK PROCESSING BLOCK XTALP ADLLT PROCESSING PLL AA FILTER AA FILTER AA FILTER STANDARD DEFINITION PROCESSOR (SDP) 10-BIT ADC + SHA - ADC 2D COMB VBI SLICER COLOR DEMOD AA FILTER STANDARD AUTODETECTION DIAGNOSTICS MIPI CSI-2 TRANSMITTER B ACE DOWNDITHER CSI-2 Tx D-PHY Tx CLKBP/ CLKBN DB0P/ DB0N VREFP VREFN REFERENCE Figure 2. Rev. 0 | Page 4 of 20 12047-002 DIAG1 DIAG2 DIAG3 DIAG4 MUX BLOCK AFE AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 OUTPUT BLOCK FIFO XTALN Data Sheet ADV7482 SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS 1 Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance 2 CRYSTAL INPUT Input High Voltage Input Low Voltage DIGITAL OUTPUTS1 Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance2 POWER REQUIREMENTS Digital Power Supply HDMI Terminator Supply HDMI Comparator Supply PLL Power Supply MIPI Transmitters Power Supply Digital Input/Output Power Supply1 Analog Power Supply CURRENT CONSUMPTION1, 2, 3, 4 Digital Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input HDMI Terminator Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input Symbol N INL DNL VIH VIL IIN CIN VIH VIL VOH VOL ILEAK COUT DVDD TVDD CVDD PVDD MVDD DVDDIO AVDD Test Conditions/Comments CVBS mode CVBS mode SCLK, SDATA, RESET, ALSB, LLC, and P0 to P7 DVDDIO = 3.14 V to 3.46 V DVDDIO = 3.14 V to 3.46 V Min Typ Unit 10 Bits LSB LSB 2 0.6 2 -10 XTALP XTALP LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK, I2S_SDATA, SDATA, INTRQ1 and INTRQ2 (when configured to drive when active) DVDDIO = 3.14 V to 3.46 V and ISOURCE = 0.4 mA DVDDIO = 3.14 V to 3.46 V and ISINK = 3.2 mA Max 0.8 +10 10 V V A pF 0.4 V V 1.2 2.4 20 V V A pF 1.89 3.46 1.89 1.89 1.89 3.46 1.89 V V V V V V V 279 mA mA mA 0.4 10 3.3 V operation 1.71 3.14 1.71 1.71 1.71 3.14 1.71 1.8 3.3 1.8 1.8 1.8 3.3 1.8 IDVDD 74.5 74.7 71.3 72.8 68.1 32.5 0.7 0.7 mA mA mA mA mA mA mA 0.7 0.7 35 0.7 mA mA mA mA ITVDD 40 Rev. 0 | Page 5 of 20 ADV7482 Parameter HDMI Comparator Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input PLL Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input MIPI Transmitters Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input Digital Input/Output Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input Analog Supply Current Single-Ended CVBS Input Fully Differential and Pseudo Differential CVBS Input Y/C Input YPbPr Input HDMI Input 8-Bit Digital Input POWER-DOWN CURRENTS2, 5 Digital Supply HDMI Terminator Supply HDMI Comparator Supply PLL Supply MIPI Transmitters Supply Digital Input/Output Supply Analog Supply Total Power Dissipation in Power-Down Mode Data Sheet Symbol ICVDD Test Conditions/Comments Min Typ Max 92 0.1 0.1 0.1 0.1 63.9 0.1 IPVDD 52 37.5 37.5 37.7 37.7 29.2 27.9 IMVDD 77 23.3 23.3 23.2 23.2 45.7 38.1 IDVDDIO 78 0.2 0.2 0.2 0.2 3.6 0.2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 51.9 70 mA mA mA mA mA mA mA 63 78.5 0.1 0.1 mA mA mA mA 0.2 0.4 0.1 0.1 0.1 0.2 0.1 4 mA mA mA mA mA mA mA mW IAVDD 93 IDVDD_PD ITVDD_PD ICVDD_PD IPVDD_PD IMVDD_PD IDVDDIO_PD IAVDD_PD Unit mA mA mA The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V. Guaranteed by lab characterization. Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature. 4 Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), MoireX video pattern for analog inputs, pseudorandom test pattern for digital inputs, and at worst-case temperature. 5 Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature. 1 2 3 Rev. 0 | Page 6 of 20 Data Sheet ADV7482 ANALOG VIDEO SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted. Table 2. Parameter NONLINEAR SPECIFICATIONS 1, 2 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS Signal-to-Noise Ratio, Unweighted2 Analog Front-End Crosstalk 3 Common-Mode Rejection Ratio2, 4 LOCK TIME SPECIFICATIONS Horizontal Lock Range3 Vertical Lock Range3 Subcarrier Lock Range3 Color Lock-In Time3 Synchronization Depth Range3 Color Burst Range3 Fast Switch Speed2, 5 Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulated five-step CVBS input, modulated five-step CVBS input, five-step 0.9 0.5 2.0 Degrees % % SNR Luma ramp Luma flat field 57.1 58 60 73 dB dB dB dB CMRR Typ -5 40 fSC Max +5 70 1.3 60 20 5 200 200 100 Unit % Hz kHz Lines % % ms These specifications apply to all CVBS input types, as well as to single-ended and differential CVBS inputs. Guaranteed by lab characterization. 3 Guaranteed by design. 4 The CMRR of this circuit design is critically dependent on the external resistor matching its inputs. This measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 5 The time it takes the ADV7482 to switch from one analog input (single ended or differential) to another, for example, switching from AIN1 to AIN2. 1 2 Rev. 0 | Page 7 of 20 ADV7482 Data Sheet MIPI VIDEO OUTPUT SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted. The ADV7482 MIPI CSI-2 transmitters conform to the MIPI D-PHY Version 1.00.00 specification by characterization. The clock lane of the ADV7482 remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the ADV7482 operating with a nominal 1 Gbps output data rate. Table 3 Parameter UNIT INTERVAL 1 DATA LANE LP Tx DC SPECIFICATIONS 2 Thevenin Output High Level Low Level CLOCK LANE LP Tx DC SPECIFICATIONS2 Thevenin Output High Level Low Level DATA LANE HS Tx SIGNALING REQUIREMENTS High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level CLOCK LANE HS Tx SIGNALING REQUIREMENTS High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level HS Tx CLOCK TO DATA LANE TIMING REQUIREMENTS Data to Clock Skew 1 2 Symbol UI Min 1 Typ Max 12.5 Unit ns VOH VOL 1.1 -50 1.2 0 1.3 +50 V mV VOH VOL 1.1 -50 1.2 0 1.3 +50 V mV |V1| 140 200 150 200 270 10 360 250 mV p-p mV mV mV 140 200 150 200 270 10 360 250 mV p-p mV mV mV 0.65 x UI ns |V2| 0.35 x UI Guaranteed by design. These measurements were performed with CLOAD = 50 pF. ANALOG SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted. Table 4. Parameter CLAMP CIRCUITRY External Clamp Capacitor Large Clamp Source Current Sink Current Fine Clamp Source Current Sink Current Test Conditions/Comments Required by design Rev. 0 | Page 8 of 20 Min Typ Max Unit 0.1 F 0.32 0.32 mA mA 7 7 A A Data Sheet ADV7482 TIMING SPECIFICATIONS AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted. Table 5. Parameter CLOCK AND CRYSTAL Nominal Frequency 1 Frequency Stability1 Input LLC Clock Frequency Range 2, 3 Output LLC Clock Frequency Range2, 3 I2S_SCLK Frequency3 I2S_MCLK Frequency3 2 I C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time (Stop Condition) RESET FEATURE RESET Pulse Width1 8-BIT DIGITAL INPUT PORT2 LLC High Time3 Symbol Test Conditions Typ Max Unit MHz ppm MHz Required by design Required by design DVDDIO = 3.14 V to 3.46 V 13.5 50 148.5 DVDDIO = 3.14 V to 3.46 V 13.5 148.5 MHz 12.288 24.576 MHz MHz 400 kHz s s s s ns ns ns s t1 t2 t3 t4 t5 t6 t7 t8 28.63636 0.6 1.3 0.6 0.6 100 300 300 0.6 5 ms DVDDIO = 3.14 V to 3.46 V t21 LLC Low Time3 SDR and DDR Modes Setup Time SDR and DDR Modes Hold Time DDR Mode Setup Time DDR Mode Hold Time 8-BIT DIGITAL OUTPUT PORT2 LLC High Time Min t22 t23 t24 t25 Data latched on rising edge Data latched on rising edge Data latched on falling edge Data latched on falling edge DVDDIO = 3.14 V to 3.46 V t26 LLC Low Time SDR Modes Setup Time 4, 5 t36 SDR Modes Hold Time4, 5 t37 DDR Modes Setup Time4, 5 t27 DDR Modes Hold Time4, 5 t28 DDR Mode Setup TIme4, 5 t29 DDR Modes Hold Time4, 5 t30 At P0 to P7 output pin, data latched on rising edge At P0 to P7 output pin, data latched on rising edge At P0 to P7 output pin, data latched on rising edge At P0 to P7 output pin, data latched on rising edge At P0 to P7 output pin, data latched on falling edge At P0 to P7 output pin, data latched on falling edge Rev. 0 | Page 9 of 20 45 55 45 55 1 1 1 1 40 60 40 60 % duty cycle % duty cycle ns ns ns ns 1.98 % duty cycle % duty cycle ns 2.50 ns 1.66 ns 3.52 ns 1.71 ns 3.17 ns ADV7482 Data Sheet Parameter I2S PORT, MASTER MODE I2S_SCLK High Time Symbol Test Conditions Min t31 I2S_SCLK Low Time I2S_LRCLK Data Transition Time t32 t33 t34 t35 I2S_SDATA Data Transition Time Typ Max Unit 45 55 45 55 % duty cycle % duty cycle ns ns ns ns End of valid data to I2S_SCLK falling edge I2S_SCLK falling edge to start of valid data End of valid data to I2S_SCLK falling edge I2S_SCLK falling edge to start of valid data 10 10 5 5 Required by design. The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V. Guaranteed by design. 4 These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000. 5 Guaranteed by lab characterization. 1 2 3 Timing Diagrams t3 t5 t3 SDATA t1 t6 t2 t4 t7 12047-003 SCLK t8 2 Figure 3. I C Timing t22 t21 t23 LLC 12047-007 P7 TO P0 Figure 4. 8-Bit Digital Pixel Video Input, SDR Video Data Timing t21 LLC t24 t23 t25 12047-008 t22 P7 TO P0 Figure 5. 8-Bit Digital Pixel Video Input, DDR Video Data Timing t26 LLC t36 12047-009 t37 P7 TO P0 Figure 6. 8-Bit Digital Pixel Video Output, SDR Video Data Timing Rev. 0 | Page 10 of 20 Data Sheet ADV7482 t26 LLC t27 t29 t28 12047-010 t30 P7 TO P0 Figure 7. 8-Bit Digital Pixel Video Output, DDR Video Data Timing t31 I2S_SCLK t32 I2S_LRCLK t33 t34 MSB MSB - 1 t35 I2S_SDATA I2S MODE I2S_SDATA RIGHT JUSTIFIED MODE t34 MSB MSB - 1 t35 t34 MSB LSB t35 Figure 8. I2S Timing Rev. 0 | Page 11 of 20 12047-011 I2S_SDATA LEFT JUSTIFIED MODE ADV7482 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter TVDD, DVDDIO to GND AVDD, PVDD, MVDD, DVDD, CVDD to GND CVDD to DVDD MVDD to DVDD PVDD to DVDD AVDD to DVDD Digital Inputs Voltage to GND Digital Outputs Voltage to GND Analog Inputs to GND XTALN and XTALP to GND HDMI Digital Inputs Voltage to GND 5 V Tolerant Inputs Voltage to GND1, 2 Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V To reduce power consumption when using the ADV7482, turn off unused sections of the device. -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V GND - 0.3 V to DVDDIO + 0.3 V GND - 0.3 V to DVDDIO + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to PVDD + 0.3 V -0.3 V to CVDD + 0.3 V -0.3 V to +5.5 V Due to printed circuit board (PCB) metal variation, and, therefore, variation in PCB heat conductivity, the value of JA may differ for various PCBs. The most efficient measurement solution is achieved using the package surface temperature to estimate the die temperature. This eliminates the variance associated with the JA value. Do not exceed the maximum junction temperature (TJ max) of 125C. The following equation calculates the junction temperature (TJ) using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): TJ = TS + (JT xWTOTAL) where: TS is the package surface temperature (C). JT = 0.81C/W for the 100-ball CSP_BGA (based on 2s2p test board defined by JEDEC standards. 125C -65C to +150C 260C WTOTAL = (PVDD x IPVDD) + (TVDD x ITVDD) - PUpStream + (CVDD x ICVDD) + (AVDD x IAVDD) + (DVDD x IDVDD) + (DVDDIO x IDVDDIO) + (MVDD x IMVDD) The following inputs are 3.3 V inputs but are 5 V tolerant: DDC_SCL, DDC_SDA, HPD, RX_5V, and CEC. 2 The following inputs are 1.8 V inputs but are 5 V tolerant: DIAG1, DIAG2, DIAG3, and DIAG4. 1 where PUpStream is the quantity of TVDD power consumed on the upstream HDMI transmitter. PUpStream can be estimated to be around 110 mW for a nominal HDMI transmitter. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0 | Page 12 of 20 Data Sheet ADV7482 A 1 2 3 4 5 6 7 8 9 10 GND I2S_ SDATA GND RX2P RX1P RX0P RXCP DDC_SCL DNC GND A B MVDD I2S_ SCLK CVDD RX2N RX1N RX0N RXCN DDC_SDA HPD GND B C CLKAN CLKAP I2S_ LRCLK I2S_ MCLK TEST2 TVDD CEC RX_5V AIN7 AIN8 C D DA0N DA0P TEST3 DVDD GND GND GND DIAG4 AIN5 AIN6 D E DA1N DA1P INTRQ2 GND GND GND AVDD DIAG3 AIN3 AIN4 E F DA2N DA2P INTRQ1 GND GND GND GND VREFN AIN1 AIN2 F G DA3N DA3P TEST DVDD GND GND GND VREFP DIAG1 DIAG2 G H DB0N DB0P DVDDIO P1 P4 DNC DNC RESET PVDD GND H J CLKBN CLKBP MVDD P2 P5 P7 DNC SCLK XTALN XTALP J K GND MVDD P0 P3 P6 LLC DNC SDATA ALSB GND K 1 2 3 4 5 6 7 8 9 10 DNC = DO NOT CONNECT. LEAVE THIS PIN UNCONNECTED. 12047-012 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 9. Pin Configuration Table 7. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 Mnemonic GND I2S_SDATA GND RX2P RX1P RX0P RXCP DDC_SCL DNC GND MVDD I2S_SCLK CVDD Type Ground Output Ground HDMI HDMI HDMI HDMI HDMI Miscellaneous Ground Power Output Power B4 B5 B6 B7 B8 B9 B10 RX2N RX1N RX0N RXCN DDC_SDA HPD GND HDMI HDMI HDMI HDMI HDMI HDMI Ground Description Ground. I2S Audio Output. Ground. HDMI Digital Input Channel 2. HDMI Digital Input Channel 1. HDMI Digital Input Channel 0. HDMI Input Clock. HDCP Slave Serial Clock. Do Not Connect. Leave this pin unconnected. Ground. MIPI Supply Voltage (1.8 V). Audio Serial Clock. HDMI Comparator Supply Voltage (1.8 V). This is the supply for the HDMI sensitive analog circuitry. Blocks on this supply include the TMDS PLL and the equalizers. HDMI Digital Input Channel 2 Complement. HDMI Digital Input Channel 1 Complement. HDMI Digital Input Channel 0 Complement. HDMI Input Clock Complement. HDCP Slave Serial Data. HDMI Hot Plug Assert. Ground. Rev. 0 | Page 13 of 20 ADV7482 Data Sheet Pin No. C1 C2 C3 C4 C5 C6 C7 C8 Mnemonic CLKAN CLKAP I2S_LRCLK I2S_MCLK TEST2 TVDD CEC RX_5V Type Output Output Output Output Miscellaneous Power HDMI HDMI C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 AIN7 AIN8 DA0N DA0P TEST3 DVDD GND GND GND DIAG4 AIN5 AIN6 DA1N DA1P INTRQ2 GND GND GND AVDD DIAG3 AIN3 AIN4 DA2N DA2P INTRQ1 GND GND GND GND VREFN AIN1 AIN2 DA3N DA3P TEST DVDD GND GND GND VREFP DIAG1 DIAG2 Input Input Output Output Miscellaneous Power Ground Ground Ground Input Input Input Output Output Output Ground Ground Ground Power Input Input Input Output Output Output Ground Ground Ground Ground Output Input Input Output Output Miscellaneous Power Ground Ground Ground Output Input Input Description MIPI Transmitter A Negative Output Clock. MIPI Transmitter A Positive Output Clock. Audio Left/Right Clock. Audio Master Clock Output. Test Pin 2. Pull down via a large pull-down resistor to ground. HDMI Terminator Supply Voltage (3.3 V). CEC Channel. HDMI 5 V Detect. A large pull-down resistor (100 k, typical) to ground must be connected to this pin. Analog Video Input Channel. Analog Video Input Channel. MIPI Transmitter A Negative Data Output. MIPI Transmitter A Positive Data Output. Test Pin 3. Pull up to DVDDIO via a pull-up resistor (4.7 k). Digital Supply Voltage (1.8 V). Ground. Ground. Ground. Analog Video Diagnostic Input. This input is 5 V tolerant. Analog Video Input Channel. Analog Video Input Channel. MIPI Transmitter A Negative Data Output. MIPI Transmitter A Positive Data Output. Interrupt Request Output. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Analog Video Diagnostic Input. This input is 5 V tolerant. Analog Video Input Channel. Analog Video Input Channel. MIPI Transmitter A Negative Data Output. MIPI Transmitter A Positive Data Output. Interrupt Request Output. Ground. Ground. Ground. Ground. Internal Voltage Reference Output. Analog Video Input Channel. Analog Video Input Channel. MIPI Transmitter A Negative Data Output. MIPI Transmitter A Positive Data Output. Do Not Connect. Leave this pin unconnected. Digital Supply Voltage (1.8 V). Ground. Ground. Ground. Internal Voltage Reference Output. Analog Video Diagnostic Input. This input is 5 V tolerant. Analog Video Diagnostic Input. This input is 5 V tolerant. Rev. 0 | Page 14 of 20 Data Sheet ADV7482 Pin No. H1 H2 H3 H4 H5 H6 H7 H8 Mnemonic DB0N DB0P DVDDIO P1 P4 DNC DNC RESET Type Output Output Power Input/Output Input/Output Miscellaneous Miscellaneous Input H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 PVDD GND CLKBN CLKBP MVDD P2 P5 P7 DNC SCLK XTALN Power Ground Output Output Power Input/Output Input/Output Input/Output Miscellaneous Input Output J10 XTALP Input K1 K2 K3 K4 K5 K6 K7 K8 K9 GND MVDD P0 P3 P6 LLC DNC SDATA ALSB Ground Power Input/Output Input/Output Input/Output Input/Output Miscellaneous Input/Output Input K10 GND Ground Description MIPI Transmitter B Negative Data Output. MIPI Transmitter B Positive Data Output. Digital Input/Output Supply Voltage (3.3 V). Video Pixel Input/Output Port. Video Pixel Input/Output Port. Do Not Connect. Leave this pin unconnected. Do Not Connect. Leave this pin unconnected. System Reset Input, Active Low. A minimum low reset pulse of 5 ms is required to reset the chip. PLL Supply Voltage (1.8 V). Ground. MIPI Transmitter B Negative Output Clock. MIPI Transmitter B Positive Output Clock. MIPI Supply Voltage (1.8 V). Video Pixel Input/Output Port. Video Pixel Input/Output Port. Video Pixel Input/Output Port. Do Not Connect. Leave this pin unconnected. I2C Port Serial Clock Input. Crystal Output. This pin must be connected to the 28.63636 MHz crystal or not connected if an external 1.8 V, 28.63636 MHz clock oscillator is used. In crystal mode, the crystal must be a fundamental crystal. Crystal Input or External Clock Input. This pin must be connected to the 28.63636 MHz crystal or connected to an external 1.8 V, 28.63636 MHz clock oscillator if a clock oscillator is used. In crystal mode, the crystal must be a fundamental crystal. Ground. MIPI Supply Voltage (1.8 V). Video Pixel Input/Output Port. Video Pixel Input/Output Port. Video Pixel Input/Output Port. Line Locked Clock. Input/output clock for the pixel data. Do Not Connect. Leave this pin unconnected. I2C Port Serial Data Input/Output. Main I2C Address Selection Pin. This pin selects the main I2C address (IO Map I2C address) for the part. When ALSB is set to Logic 0, the IO Map I2C write address is 0xE0; when ALSB is set to Logic 1, the IO Map I2C write address is 0xE2. Ground. Rev. 0 | Page 15 of 20 ADV7482 Data Sheet POWER SUPPLY RECOMMENDATION POWER-UP SEQUENCE POWER-DOWN SEQUENCE Adhere to the absolute maximum ratings at all times during power-up (see Table 6). The power-up sequence for the ADV7482 is as follows: The ADV7482 power supplies can be deasserted simultaneously as long as a higher rated supply (for example, DVDDIO) does not fall to a voltage level less than a lower rated supply (for example, DVDD), and the absolute maximum ratings specifications are followed. 3. 4. 5. Assert RESET (pull the pin low). Power up the 3.3 V supplies (DVDDIO and TVDD). These supplies must be powered up simultaneously. Power up the 1.8 V supplies (DVDD, CVDD, PVDD, MVDD, and AVDD). These supplies must be powered up simultaneously. RESET can be deasserted (pulled high) 5 ms after all supplies are fully powered up. After all power supplies and the RESET pin are powered up and stable, wait an additional 5 ms before initiating I2C communication with the ADV7482. 3.3V RESET 0V 3.3V 3.3V SUPPLIES 0V 1.8V 1.8V SUPPLIES 0V RESET > 5ms Figure 10. Supply Power-Up Sequence Rev. 0 | Page 16 of 20 12047-017 1. 2. Data Sheet ADV7482 THOERY OF OPERATION * The HDMI receiver allows programmable equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. The receiver is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance. The HDMI interface of the ADV7482 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP 1.4 protocol. Dual extended display identification data (EDID) support is provided via an on-chip 512-byte EDID RAM. The EDID RAM must be programmed at power-up. It can be configured as two 256-byte EDIDs, or as a single 512-byte EDID. The ADV7482 has a synchronization regeneration block used to regenerate the data enable (DE) signal based on the measurement of the video format being displayed and to filter the horizontal and vertical synchronization signals to prevent glitches. The HDMI receiver also supports TMDS error reduction coding, 4-bit (TERC4) error detection, used for the detection of corrupted HDMI packets. The main HDMI receiver features include * * * * * * * * * * * 162.0 MHz (UXGA at 24 BPP) maximum TMDS clock frequency. Integrated fully adaptive equalizer for cable lengths up to 30 meters. HDCP 1.4 support. Internal HDCP keys. HDCP repeater support, up to 25 key selection vectors (KSVs) supported. PCM audio packet support. Support for 8-channel TDM output data up to 48 kHz. Repeater support. Internal EDID RAM (512-byte for single mode, and 256-byte for dual mode operation). Hot Plug assert output pin (HPD). CEC controller. * * * ANALOG FRONT END The ADV7482 AFE comprises a single high speed, 10-bit ADC that digitizes the analog video signal before applying it to the SDP. The AFE uses differential channels to the ADC to ensure high performance in mixed-signal applications and to enable differential CVBS to be connected directly to the ADV7482. Up to eight analog inputs can be connected to the AFE. The front end also includes an 8-channel input mux that enables different configurations of single-ended CVBS (up to eight), pseudo differential or fully differential CVBS (up to four), Y/C (up to four), and YPbPr (up to two) analog inputs. Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter. A resistor divider network is required before each analog input channel to ensure that the input signal is within the range of the ADC. Figure 11 shows a typical voltage divider network for single-ended inputs, Figure 12 shows a typical voltage divider network for pseudo differential inputs, and Figure 13 shows a typical voltage divider network for fully differential inputs. The choice of the resistor divider shown in Figure 13 provides a common-mode range of up to 4 V in fully differential CVBS input mode. Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7482. ANALOG INPUT 100nF 24 Figure 11. Typical Single-Ended Input Voltage Divider Network ANALOG INPUT CVBS_P 1.3k 100nF AINx 430 75 COMPONENT PROCESSOR The ADV7482 has one any-to-any 3 x 3 CSC matrix. The CSC block is located in the processing path before the CP section. CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions. Many other standards of color space can be implemented using the color space converter. AIN 51 12047-013 The HDMI receiver supports video formats ranging from 480i to 1080p, and display resolutions from VGA (640 x 480 at 60 Hz) to UXGA (1600 x 1200 at 60 Hz). Support for all video modes supported by the HDMI receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p, and display resolutions from VGA (640 x 480 at 60 Hz) to UXGA (1600 x 1200 at 60 Hz). Manual adjustments including gain (contrast), offset (brightness), hue, and saturation. Free run output mode that provides stable timing when no video input is present. Timing adjustments controls for HS/VS/DE timing. ANALOG INPUT CVBS_N 1.3k 430 100nF AINy 12047-014 HDMI RECEIVER Figure 12. Typical Pseudo Differential Input Resistor Divider Network CP features include Rev. 0 | Page 17 of 20 ADV7482 CVBS_P 1.3k 100nF R4 AINx DIAGx R5 430 ANALOG INPUT 150 CVBS_N 1.3k 430 100nF AINy 430 ANALOG INPUT CVBS_N The ADC features three clocking rates that allow 4x oversampling per channel for CVBS mode, Y/C mode, and YPbPr mode. The main AFE features include * * * * * 1.3k 100nF AINy Figure 14. Diagnostic Connection for Differential Inputs The fully differential AFE of the ADV7482 provides inherent small and large signal noise rejection, improved electromagnetic interference (EMI) protection, and the ability to absorb ground bounce. Support is provided for both true differential and pseudo differential signals. * AINx 75 OR 150 Figure 13. Typical Fully Differential Input Resistor Divider Network * 100nF 430 12047-015 ANALOG INPUT 1.3k CVBS_P 12047-016 ANALOG INPUT Data Sheet A single 172 MHz, 10-bit ADC that enables true 8-bit video decoding. 8-channel analog input mux that enables multiple source connections without the requirement of an external mux. A current clamp control loop that ensures that any dc offsets are removed from the video signal entering the SDP. Diagnostic capability on all differential inputs. Support for 4 V common-mode input range. Support for analog input signals up to 1 V p-p. Support for single-ended, pseudo differential, and fully differential inputs. SHORT TO BATTERY DIAGNOSTICS In differential mode, the ADV7482 is protected against STB events by ac coupling capacitors (see Figure 12 and Figure 13). The input network resistors are sized to reduce the current flow during an STB event, thus preventing damage to the resistors. Note that the input network resistors and the ac coupling capacitors must be chosen with ratings guaranteeing they are able to withstand the high voltage of STB events. The four diagnostic inputs of the ADV7482 provide diagnostic capability for all differential inputs. The ADV7482 can detect an STB event on either the positive or the negative composite input and trigger an interrupt. The 75 (pseudo differential) or 150 (fully differential) parallel termination resistor enables one DIAGx pin to sense an STB event on either input, because there is a minimal voltage drop across the resistor. Resistors R4 and R5 divide down the voltage at the input connector to protect the DIAGx pin from an STB event. The DIAGx pin circuitry compares this voltage to a programmable reference voltage, known as the diagnostic slice level. When the diagnostic slice level is exceeded, an STB event has occurred. R4 and R5 are sized to allow the use of low cost, small footprint resistors that are tolerant of STB events. Use the following equation to find the STB voltage for a selected diagnostic slice level. VSTB_TRIGGER = R5 + R4 x DIAGNOSTIC_SLICE_LEVEL R5 where: VSTB_TRIGGER is the minimum voltage required at the input connector to trigger the STB interrupt on the ADV7482. DIAGNOSTIC_SLICE_LEVEL is the programmable reference voltage. For example, with a diagnostic slice level programmed to 1.125 V, an R4 value of 9.1 k, and an R5 value of 1 k, the minimum voltage required at the input connector to trigger the STB interrupt is approximately 11.4 V. When the DIAGx pin voltage exceeds the diagnostic slice level voltage, a hardware interrupt is triggered and indicated by one of the interrupt pins. A readback register specifies the input on which the STB event occurred. STANDARD DEFINITION PROCESSOR The ADV7482 is capable of decoding a large selection of baseband video signals in composite (both single-ended and differential), S-Video, and component formats. The video standards supported by the video processor include * PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N, PAL Nc, and PAL 60 * NTSC J, NTSC M, and NTSC 4.43 * SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L The ADV7482 can automatically detect the video standard and process it accordingly. The ADV7482 has a five-line adaptive 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the Rev. 0 | Page 18 of 20 Data Sheet ADV7482 video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available with the ADV7482. The ADV7482 implements the patented Adaptive Digital Line Length Tracking (ADLLTTM) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7482 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7482 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ACE of the ADV7482 offers improved visual detail using an algorithm that automatically varies contrast levels to enhance picture detail. ACE allows the contrast of an image to increase depending on the content of the picture. Typically, this allows bright areas to be made brighter and dark areas to be made darker. However, the ADV7482 ACE feature also allows the contrast within dark areas to increase without significantly affecting the bright areas of the picture. This feature is particularly useful in automotive applications, where it is important to discern objects in shaded areas. Down dithering converts the output of the ADV7482 from an 8-bit to a 6-bit output, enabling ease of design for standard LCD panels. The SDP can process a variety of VBI data services, such as closed captioning (CCAP), wide screen signaling (WSS), and copy generation management system (CGMS). The ADV7482 is fully Rovi(R)(Macrovision(R)) compliant; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. 8-BIT DIGITAL INPUT/OUTPUT PORT The ADV7482 features an 8-bit digital bidirectional port. The following formats are supported both as input and output ports: * 8-bit interleaved 4:2:2 SDR input/output with embedded timing codes * 8-bit interleaved 4:2:2 DDR input/output with embedded timing codes The maximum input and output video resolution supported is 720p/1080i in both SDR and DDR modes. Video received on the 8-bit digital input port can be routed to the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit digital output port can be routed from either the SD core or the CP core. AUDIO PROCESSING conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, a 2-channel linear PCM audio signal can be ramped down to a mute state to prevent audio clicks or pops. The audio is output on a single flexible serial digital audio output port supporting I2S-compatible, left justified, and right justified audio output modes in master mode only. TDM is also supported, allowing up to eight audio channels with a sample rate up to 48 kHz to be transmitted over the single serial digital audio interface. MIPI CSI-2 TRANSMITTERS The ADV7482 features two MIPI CSI-2 transmitters: a fourlane transmitter (Transmitter A) and a single lane transmitter (Transmitter B). The four-lane transmitter consists of four differential data lanes (DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P), and a differential clock lane (CLKAN and CLKAP). It supports four data lanes, two data lanes, and one data lane muxing options, and can be used to transmit video received on either the HDMI receiver (processed through the CP), the 8-bit digital input port, or the AFE (processed through the SDP). The main features of the four-lane MIPI transmitter (Transmitter A) include * * * * Support for 8-bit and 10-bit YCbCr 4:2:2 video modes. Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4 (RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes. Support for video formats ranging from 480i to 1080p, and display resolutions from VGA to UXGA (certain restrictions apply to the muxing option, video mode, and video format that can be selected). Data lanes and clock lane remapping to ease PCB layout. The single lane transmitter consists of a single differential data lane (DB0N and DB0P) and a differential clock lane (CLKBN and CLKBP). It transmits video received on the AFE (processed through the SDP). The main features of the single lane MIPI transmitter (Transmitter B) include * * Support for 8-bit YCbCr 4:2:2 video mode. Support for 480i and 576i video formats. INTERRUPTS The ADV7482 features two interrupt request pins. INTRQ1 and INTRQ2 can be programmed to trigger interrupts based on various selectable events related to the HDMI receiver (video and audio related), the SDP, and the CP. The ADV7482 features an audio processor that handles the audio extracted from the HDMI stream by the HDMI receiver. It contains an audio mute controller that can detect a variety of Rev. 0 | Page 19 of 20 ADV7482 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 9.10 9.00 SQ 8.90 A1 BALL CORNER 10 9 8 7 6 5 4 3 2 1 A B C 7.20 BSC SQ D E F 0.80 BSC G H J K DETAIL A *1.400 1.253 1.173 BOTTOM VIEW 0.90 REF 0.383 0.343 0.303 0.26 REF SEATING PLANE DETAIL A 0.975 0.910 0.845 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 *COMPLIANT TO JEDEC STANDARDS MO-275-DDAB-1 WITH THE EXCEPTION TO PACKAGE HEIGHT 03-14-2013-A TOP VIEW Figure 15. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-4) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2, 3 ADV7482WBBCZ ADV7482WBBCZ-RL 1 2 3 Temperature Range -40C to +85C -40C to +85C Package Description 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Package Option BC-100-4 BC-100-4 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. This device is programmed with internal HDCP keys. Customer must have HDCP adopter status (consult Digital Protection, LLC, for licensing requirements) to purchase any components with internal HDCP keys AUTOMOTIVE PRODUCTS The ADV7482W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12047-0-6/14(0) Rev. 0 | Page 20 of 20