TLV75709PDBVR - TEXAS INSTRUMENTS

Integrated Video Decoder

and HDMI Receiver

Data Sheet

ADV7482

FEATURES

Analog input

Worldwide NTSC/PAL/SECAM color demodulation support

with autodetection

One 10-bit ADC, 4× oversampling for CVBS, Y/C, and YPbPr

8 analog video input channels with on-chip antialiasing

filter

Fully differential, pseudo differential, and single-ended

CVBS video input support

STB diagnostics on differential video inputs

CVBS (composite), Y/C (S-Video), and YPbPr (component)

video input support

Fast switching capability between analog inputs

Adaptive contrast enhancement (ACE)

Excellent common-mode noise rejection capabilities

Rovi (Macrovision) copy protection detection

Up to 4 V common-mode input range solution

Vertical blanking interval (VBI) data slicer

High-Definition Multimedia Interface (HDMI) capable

receiver

HDCP authentication and decryption support

162 MHz maximum pixel clock frequency, allowing HDTV

formats up to 1080p and display resolutions up to UXGA

(1600 × 1200 at 60 Hz)

HDCP repeater support, up to 25 KSVs supported

Integrated CEC controller, CEC 1.4 compatible

Adaptive TMDS equalizer

5 V detect and Hot Plug assert

Component video processor

Any-to-any 3 × 3 color space conversion (CSC) matrix

Contrast/brightness/hue/saturation video adjustment

Timing adjustments controls for horizontal sync

(HS)/vertical sync (VS)/data enable (DE) timing

Video mute function

Serial digital audio output interface

HDMI audio extraction support

Advanced audio muting feature

I2S-compatible, left justified and right justified audio

output modes

8-channel TDM output mode available

2 Mobile Industry Processor Interface (MIPI) Camera Serial

Interface 2 (CSI-2) transmitters

4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing

options for HDMI/SDP/digital input port sources

1-lane transmitter for standard definition processor (SDP)

sources

8-bit digital input/output port

General

2-wire serial microprocessor unit (MPU) interface (I2C

compatible)

−40°C to +85°C temperature grade

100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package

Qualified for automotive applications

APPLICATIONS

Portable devices

Automotive infotainment (head unit and rear seat

entertainment systems)

HDMI repeaters and video switches

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

RXCP/RXCN

DDC_SCL

DDC_SDA

HPD

RX_5V

CEC

HDMI

RECEIVER

CORE

AUDIO

PROCESSOR

C SLAVE

INTERRUPTS

CONTROLLER

AUDIO OUTPUT

FORMATTER

DIAGNOSTIC

8-BI T TTL

INPUT/OUTPUT

AFE

CEC

HPD

EDID RAM

HDCP

DDC

SCLK

SDATA

ALSB

INTRQ1

INTRQ2

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

CLKAP/CLKAN

CLKBP/CLKBN

DB0P/DB0N

AIN1 TO

AIN8

P0 TO P7

LLC

DIAG1 TO

DIAG4

DA0P/DA0N TO

DA3P/DA3N

4-LANE

MIPI CSI-2

TRANSMITTER

1-LANE

MIPI CSI-2

TRANSMITTER

ADV7482

CORE

12047-001

Rev. 0 Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

ADV7482 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications ..................................................................................... 5

Electrical Characteristics ............................................................. 5

Analog Video Specifications ....................................................... 7

MIPI Video Output Specifications ............................................. 8

Analog Specifications ................................................................... 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution ................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Power Supply Recommendation .................................................. 16

Power-Up Sequence ................................................................... 16

Power-Down Sequence .............................................................. 16

Thoery of Operation ...................................................................... 17

HDMI Receiver ........................................................................... 17

Component Processor ............................................................... 17

Analog Front End ....................................................................... 17

Short to Battery Diagnostics ..................................................... 18

Standard Definition Processor ................................................. 18

8-Bit Digital Input/Output Port ............................................... 19

Audio Processing ........................................................................ 19

MIPI CSI-2 Transmitters ........................................................... 19

Interrupts ..................................................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

Automotive Products ................................................................. 20

REVISION HISTORY

6/14—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

Data Sheet ADV7482

GENERAL DESCRIPTION

The ADV7482 is an integrated video decoder and HDMI®

receiver, targeted at connectivity enabled head units requiring a

wired, uncompressed digital audio/video link from smartphones,

and other consumer electronics devices to support streaming

and integration of cloud-based multimedia content and

applications into an automotive infotainment system.

The ADV7482 HDMI capable receiver supports a maximum

pixel clock frequency of 162 MHz, allowing HDTV formats up

to 1080p, and display resolutions up to UXGA (1600 × 1200 at

60 Hz). The device integrates a consumer electronics control

(CEC) controller that supports the capability discovery and

control (CDC) feature. The HDMI input port has dedicated 5 V

detect and Hot Plug™ assert pins.

The HDMI receiver includes an adaptive transition minimized

differential signaling (TMDS) equalizer that ensures robust

operation of the interface with long cables.

The ADV7482 contains a component processor (CP) that

processes the video signals from the HDMI receiver. It provides

features such as contrast, brightness, and saturation

adjustments, as well as free run and timing adjustment controls

for HS/VS/DE timing.

The ADV7482 analog front end (AFE) comprises a single high

speed, 10-bit analog-to-digital converter (ADC) that digitizes

the analog video signal before applying it to the SDP.

The eight analog video inputs can accept single-ended, pseudo

differential, and fully differential composite video signals, as

well as S-Video and YPbPr video signals, supporting a wide

range of consumer and automotive video sources.

Short to battery (STB) events can be detected on differential

input video signals. STB protection is provided by ac coupling

the input video signals. The ADV7482, in combination with an

external resistor divider, provides a common-mode input range

of 4 V, enabling the removal of large signal common-mode

transients present on the video lines.

The automatic gain control (AGC) and clamp restore circuitry

allow an input video signal up to 1.0 V p-p at the analog video

input pins of the ADV7482. Alternatively, the AGC and clamp

restore circuitry can be bypassed for manual settings.

The SDP of the ADV7482 is capable of decoding a large

selection of analog baseband video signals in composite, S-Video,

and component formats. The SDP supports worldwide NTSC,

PAL, and SECAM standards.

The ADV7482 features an 8-bit digital input/output port,

supporting input and output video resolutions up to 720p/1080i

in both the 8-bit interleaved 4:2:2 SDR and DDR modes.

To enable glueless interfacing of these video input sources to the

latest generation of infotainment system on chips (SoCs), the

ADV7482 features two MIPI® CSI-2 transmitters. The four-lane

transmitter provides four data lanes, two data lanes, and one

data lane muxing options, and can be used to output video from

the HDMI receiver, the SDP, and the digital input port. The

single-lane transmitter can be used to output video from the

SDP only.

The ADV7482 offers a flexible audio output port for audio data

extracted from HDMI streams. The HDMI receiver has

advanced audio functionality, such as a mute controller that

prevents audible extraneous noise in the audio output.

Additionally, the ADV7482 can be set to output time division

multiplexing (TDM) serial audio, which allows the transmission

of eight multiplexed serial audio channels on a single audio

output interface port.

The ADV7482 is programmed via a 2-wire, serial, bidirectional

port (I2C compatible).

Fabricated in an advanced CMOS process, the ADV7482 is

available in a 9 mm × 9 mm, RoHS-compliant, 100-ball

CSP_BGA package and is specified over the −40°C to +85°C

temperature range.

The ADV7482 is offered in automotive and industrial versions.

Rev. 0 | Page 3 of 20

ADV7482 Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

Figure 2.

INTRQ1

INTRQ2

I2S_MCLK

I2S_LRCLK

I2S_SCLK

I2S_SDATA

CLKAP/

CLKAN

DA0P/DA0N

DA1P/DA1N

DA2P/DA2N

DA3P/DA3N

ADV7482

GENERAL

INTERRUPTS

CONTROLLER

C SLAVE/

CONTROL

SCLK

SDATA

ALSB

RESET

MIPI CSI-2

TRANSMITTER A

AUDIO OUT P UT

FORMATTER

RX0P/RX0N

RX1P/RX1N

RX2P/RX2N

RXCP/RXCN

5V DET E CT AND

HPD PI N

CONTROLLER

CEC

CONTROLLER

EQUALIZER

OUTPUT BLOCK FIFO

PLL

EDID/

REPEATER

CONTROLLER

8-BIT

DIGITAL

INPUT/

OUTPUT

PORT

LLC

SAMPLER

HDCP

ENGINE

HDCP

KEYS

HDMI

PROCESSOR COMPONENT

PROCESSOR

(CP)

PACKET

PROCESSOR AUDIO

PROCESSOR

PACKET/

INFOFRAME

MEMORY

8-BIT

6-BIT

DITHER

BLOCK

ACE

DOWN-

DITHER

COLOR

SPACE

CONVERSION

CSI- 2 Tx D-PHY Tx

CLKBP/

CLKBN

DB0P/

DB0N

MIPI CSI-2

TRANSMITT E R B

VREFP

VREFN

CSI- 2 Tx D-PHY Tx

DDC_SDA

DDC_SCL

HPD

RX_5V

CEC

DIAGNOSTICS

CLO CK P ROCES S ING BLO CK

PLLADLLT PROCESSING

REFERENCE

AIN7

AIN8

AFE

MUX BLOCK

–

SHA ADC

10-BIT ADC

FILTER

XTALP

XTALN

STANDARD DEF INI TI ON

PROCESSOR (SDP)

2D COM B

VBI SLICER

COLOR DEMOD

STANDARD

AUTODETECTION

DIAG1

DIAG2

DIAG3

DIAG4

AIN5

AIN6

AIN3

AIN4

AIN1

AIN2

12047-002

Rev. 0 | Page 4 of 20

Data Sheet ADV7482

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

STATIC PERFORMANCE

Resolution (Each ADC) N 10 Bits

Integral Nonlinearity INL CVBS mode 2 LSB

Differential Nonlinearity DNL CVBS mode ±0.6 LSB

DIGITAL INPUTS

SCLK, SDATA, RESET, ALSB, LLC, and P0 to P7

Input High Voltage VIH DVDDIO = 3.14 V to 3.46 V 2 V

Input Low Voltage VIL DVDDIO = 3.14 V to 3.46 V 0.8 V

Input Leakage Current IIN −10 +10 µA

Input Capacitance2 CIN 10 pF

CRYSTAL INPUT

Input High Voltage VIH XTALP 1.2 V

Input Low Voltage VIL XTALP 0.4 V

DIGITAL OUTPUTS1 LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,

I2S_SDATA, SDATA, INTRQ1 and INTRQ2 (when

configured to drive when active)

Output High Voltage VOH DVDDIO = 3.14 V to 3.46 V and ISOURCE = 0.4 mA 2.4 V

Output Low Voltage

DVDDIO = 3.14 V to 3.46 V and I

SINK

= 3.2 mA

0.4

High Impedance Leakage Current ILEAK 10 µA

Output Capacitance2 COUT 20 pF

POWER REQUIREMENTS

Digital Power Supply DVDD 1.71 1.8 1.89 V

HDMI Terminator Supply

VDD

3.14

3.3

3.46

HDMI Comparator Supply CVDD 1.71 1.8 1.89 V

PLL Power Supply PVDD 1.71 1.8 1.89 V

MIPI Transmitters Power Supply MVDD 1.71 1.8 1.89 V

Digital Input/Output Power Supply1 DVDDIO 3.3 V operation 3.14 3.3 3.46 V

Analog Power Supply AVDD 1.71 1.8 1.89 V

CURRENT CONSUMPTION1, 2, 3, 4

Digital Supply Current IDVDD 279 mA

Single-Ended CVBS Input 74.5 mA

Fully Differential and Pseudo Differential

CVBS Input

74.7

Y/C Input 71.3 mA

YPbPr Input 72.8 mA

HDMI Input 68.1 mA

8-Bit Digital Input

32.5

HDMI Terminator Supply Current ITVDD 40 mA

Single-Ended CVBS Input 0.7 mA

Fully Differential and Pseudo Differential

CVBS Input

0.7 mA

Y/C Input 0.7 mA

YPbPr Input 0.7 mA

HDMI Input 35 mA

8-Bit Digital Input

0.7

Rev. 0 | Page 5 of 20

ADV7482 Data Sheet

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

HDMI Comparator Supply Current ICVDD 92 mA

Single-Ended CVBS Input 0.1 mA

Fully Differential and Pseudo Differential

CVBS Input

0.1 mA

Y/C Input 0.1 mA

YPbPr Input 0.1 mA

HDMI Input 63.9 mA

8-Bit Digital Input

0.1

PLL Supply Current IPVDD 52 mA

Single-Ended CVBS Input 37.5 mA

Fully Differential and Pseudo Differential

CVBS Input

37.5 mA

Y/C Input

37.7

YPbPr Input 37.7 mA

HDMI Input 29.2 mA

8-Bit Digital Input 27.9 mA

MIPI Transmitters Supply Current IMVDD 77 mA

Single-Ended CVBS Input 23.3 mA

Fully Differential and Pseudo Differential

CVBS Input

23.3 mA

Y/C Input 23.2 mA

YPbPr Input 23.2 mA

HDMI Input 45.7 mA

8-Bit Digital Input 38.1 mA

Digital Input/Output Supply Current IDVDDIO 78 mA

Single-Ended CVBS Input

0.2

Fully Differential and Pseudo Differential

CVBS Input

0.2 mA

Y/C Input 0.2 mA

YPbPr Input 0.2 mA

HDMI Input 3.6 mA

8-Bit Digital Input 0.2 mA

Analog Supply Current IAVDD 93 mA

Single-Ended CVBS Input 51.9 mA

Fully Differential and Pseudo Differential

CVBS Input

70 mA

Y/C Input 63 mA

YPbPr Input 78.5 mA

HDMI Input 0.1 mA

8-Bit Digital Input 0.1 mA

POWER-DOWN CURRENTS2, 5

Digital Supply IDVDD_PD 0.2 mA

HDMI Terminator Supply ITVDD_PD 0.4 mA

HDMI Comparator Supply ICVDD_PD 0.1 mA

PLL Supply IPVDD_PD 0.1 mA

MIPI Transmitters Supply IMVDD_PD 0.1 mA

Digital Input/Output Supply IDVDDIO_PD 0.2 mA

Analog Supply

AVDD_PD

0.1

Total Power Dissipation in Power-Down

Mode

4 mW

1 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

2 Guaranteed by lab characterization.

3 Typical current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V), Philips test pattern, and at room temperature.

4 Maximum current consumption values are recorded with maximum rated voltage supply levels (including DVDDIO = 3.46 V), MoireX video pattern for analog inputs,

pseudorandom test pattern for digital inputs, and at worst-case temperature.

5 Typical power-down current consumption values are recorded with nominal voltage supply levels (including DVDDIO = 3.3 V) at room temperature.

Rev. 0 | Page 6 of 20

Data Sheet ADV7482

ANALOG VIDEO SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

NONLINEAR SPECIFICATIONS1, 2

Differential Phase DP CVBS input, modulated five-step 0.9 Degrees

Differential Gain DG CVBS input, modulated five-step 0.5 %

Luma Nonlinearity LNL CVBS input, five-step 2.0 %

NOISE SPECIFICATIONS

Signal-to-Noise Ratio, Unweighted2 SNR Luma ramp 57.1 dB

Luma flat field 58 dB

Analog Front-End Crosstalk

Common-Mode Rejection Ratio

2, 4

CMRR

LOCK TIME SPECIFICATIONS

Horizontal Lock Range3 −5 +5 %

Vertical Lock Range3 40 70 Hz

Subcarrier Lock Range3 fSC ±1.3 kHz

Color Lock-In Time3 60 Lines

Synchronization Depth Range3 20 200 %

Color Burst Range3 5 200 %

Fast Switch Speed2, 5 100 ms

1 These specifications apply to all CVBS input types, as well as to single-ended and differential CVBS inputs.

2 Guaranteed by lab characterization.

3 Guaranteed by design.

4 The CMRR of this circuit design is critically dependent on the external resistor matching its inputs. This measurement was performed with 0.1% tolerant resistors, a

common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.

5 The time it takes the ADV7482 to switch from one analog input (single ended or differential) to another, for example, switching from AIN1 to AIN2.

Rev. 0 | Page 7 of 20

ADV7482 Data Sheet

MIPI VIDEO OUTPUT SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

The ADV7482 MIPI CSI-2 transmitters conform to the MIPI D-PHY Version 1.00.00 specification by characterization. The clock lane of

the ADV7482 remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some

measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements

were performed with the ADV7482 operating with a nominal 1 Gbps output data rate.

Table 3

Parameter Symbol Min Typ Max Unit

UNIT INTERVAL1 UI 1 12.5 ns

DATA LANE LP Tx DC SPECIFICATIONS2

Thevenin Output

High Level VOH 1.1 1.2 1.3 V

Low Level

−50

+50

CLOCK LANE LP Tx DC SPECIFICATIONS2

Thevenin Output

High Level VOH 1.1 1.2 1.3 V

Low Level VOL −50 0 +50 mV

DATA LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing

140

200

270

mV p-p

Differential Voltage Mismatch 10 mV

Single-Ended Output High Voltages 360 mV

Static Common-Mode Voltage Level 150 200 250 mV

CLOCK LANE HS Tx SIGNALING REQUIREMENTS

High Speed Differential Voltage Swing |V2| 140 200 270 mV p-p

Differential Voltage Mismatch 10 mV

Single-Ended Output High Voltages 360 mV

Static Common-Mode Voltage Level 150 200 250 mV

HS Tx CLOCK TO DATA LANE TIMING REQUIREMENTS

Data to Clock Skew 0.35 × UI 0.65 × UI ns

1 Guaranteed by design.

2 These measurements were performed with CLOAD = 50 pF.

ANALOG SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor Required by design 0.1 µF

Large Clamp

Source Current

0.32

Sink Current 0.32 mA

Fine Clamp

Source Current 7 µA

Sink Current 7 µA

Rev. 0 | Page 8 of 20

Data Sheet ADV7482

TIMING SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 5.

Parameter Symbol Test Conditions Min Typ Max Unit

CLOCK AND CRYSTAL

Nominal Frequency1 Required by design 28.63636 MHz

Frequency Stability1 Required by design ±50 ppm

Input LLC Clock Frequency

Range2, 3

DVDDIO = 3.14 V to 3.46 V 13.5 148.5 MHz

Output LLC Clock Frequency

Range2, 3

DVDDIO = 3.14 V to 3.46 V 13.5 148.5 MHz

I2S_SCLK Frequency3 12.288 MHz

I2S_MCLK Frequency3 24.576 MHz

I2C PORT

SCLK Frequency 400 kHz

SCLK Minimum Pulse Width High t1 0.6 µs

SCLK Minimum Pulse Width Low t2 1.3 µs

Hold Time (Start Condition) t3 0.6 µs

Setup Time (Start Condition) t4 0.6 µs

SDATA Setup Time t5 100 ns

SCLK and SDATA Rise Times t6 300 ns

SCLK and SDATA Fall Times t7 300 ns

Setup Time (Stop Condition) t8 0.6 µs

RESET FEATURE

RESET Pulse Width1 5 ms

8-BIT DIGITAL INPUT PORT2 DVDDIO = 3.14 V to 3.46 V

LLC High Time3 t21 45 55 % duty

cycle

LLC Low Time3 45 55 % duty

cycle

SDR and DDR Modes Setup Time t22 Data latched on rising edge 1 ns

SDR and DDR Modes Hold Time t23 Data latched on rising edge 1 ns

DDR Mode Setup Time t24 Data latched on falling edge 1 ns

DDR Mode Hold Time t25 Data latched on falling edge 1 ns

8-BIT DIGITAL OUTPUT PORT2 DVDDIO = 3.14 V to 3.46 V

LLC High Time t26 40 60 % duty

cycle

LLC Low Time 40 60 % duty

cycle

SDR Modes Setup Time4, 5 t36 At P0 to P7 output pin, data latched on rising

edge

1.98 ns

SDR Modes Hold Time4, 5 t37 At P0 to P7 output pin, data latched on rising

edge

2.50 ns

DDR Modes Setup Time

4, 5

At P0 to P7 output pin, data latched on rising

edge

1.66

DDR Modes Hold Time4, 5 t28 At P0 to P7 output pin, data latched on rising

edge

3.52 ns

DDR Mode Setup TIme4, 5 t29 At P0 to P7 output pin, data latched on falling

edge

1.71 ns

DDR Modes Hold Time4, 5 t30 At P0 to P7 output pin, data latched on falling

edge

3.17 ns

Rev. 0 | Page 9 of 20

ADV7482 Data Sheet

Parameter Symbol Test Conditions Min Typ Max Unit

I2S PORT, MASTER MODE

I2S_SCLK High Time t31 45 55 % duty

cycle

I2S_SCLK Low Time 45 55 % duty

cycle

I2S_LRCLK Data Transition Time t32 End of valid data to I2S_SCLK falling edge 10 ns

t33 I2S_SCLK falling edge to start of valid data 10 ns

I2S_SDATA Data Transition Time t34 End of valid data to I2S_SCLK falling edge 5 ns

t35 I2S_SCLK falling edge to start of valid data 5 ns

1 Required by design.

2 The 8-bit digital input/output port is only available when the DVDDIO supply is between 3.14 V and 3.46 V.

3 Guaranteed by design.

4 These specifications only apply when the LLC_DLL_PHASE[4:0] (IO Map, Register 0x0C[4:0]) is set to 00000.

5 Guaranteed by lab characterization.

Timing Diagrams

Figure 3. I2C Timing

Figure 4. 8-Bit Digital Pixel Video Input, SDR Video Data Timing

Figure 5. 8-Bit Digital Pixel Video Input, DDR Video Data Timing

Figure 6. 8-Bit Digital Pixel Video Output, SDR Video Data Timing

SDATA

SCLK

t3t5t3

t4t8

12047-003

LLC

P7 TO P0

12047-007

t25

t24

t23

t22

LLC

P7 TO P0

t21

12047-008

12047-009

LLC

P7 TO P0

t36 t37

Rev. 0 | Page 10 of 20

Data Sheet ADV7482

Figure 7. 8-Bit Digital Pixel Video Output, DDR Video Data Timing

Figure 8. I2S Timing

12047-010

LLC

P7 TO P0

I2S_SCLK

I2S_LRCLK

I2S_SDATA

LEFT JUSTIFIED

MODE

I2S_SDATA

RIGHT JUSTIFIED

MODE

I2S_SDATA

S MODE

MSB MSB – 1

LSBMSB

12047-011

Rev. 0 | Page 11 of 20

ADV7482 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

TVDD, DVDDIO to GND 4 V

AVDD, PVDD, MVDD, DVDD, CVDD

to GND

2.2 V

CVDD to DVDD −0.3 V to +0.3 V

MVDD to DVDD −0.3 V to +0.3 V

PVDD to DVDD −0.3 V to +0.3 V

AVDD to DVDD −0.3 V to +0.3 V

Digital Inputs Voltage to GND

GND − 0.3 V to DVDDIO +

0.3 V

Digital Outputs Voltage to GND GND − 0.3 V to DVDDIO +

0.3 V

Analog Inputs to GND −0.3 V to AVDD + 0.3 V

XTALN and XTALP to GND −0.3 V to PVDD + 0.3 V

HDMI Digital Inputs Voltage to

GND

−0.3 V to CVDD + 0.3 V

5 V Tolerant Inputs Voltage to

GND1, 2

−0.3 V to +5.5 V

Maximum Junction Temperature

(TJ max)

125°C

Storage Temperature Range −65°C to +150°C

Infrared Reflow Soldering

(20 sec)

260°C

1 The following inputs are 3.3 V inputs but are 5 V tolerant: DDC_SCL,

DDC_SDA, HPD, RX_5V, and CEC.

2 The following inputs are 1.8 V inputs but are 5 V tolerant: DIAG1, DIAG2,

DIAG3, and DIAG4.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

To reduce power consumption when using the ADV7482, turn

off unused sections of the device.

Due to printed circuit board (PCB) metal variation, and,

therefore, variation in PCB heat conductivity, the value of θJA

may differ for various PCBs.

The most efficient measurement solution is achieved using the

package surface temperature to estimate the die temperature.

This eliminates the variance associated with the θJA value.

Do not exceed the maximum junction temperature (TJ max) of

125°C. The following equation calculates the junction

temperature (TJ) using the measured package surface

temperature and applies only when no heat sink is used on the

device under test (DUT):

TJ = TS + (ΨJT ×WTOTAL)

where:

TS is the package surface temperature (°C).

ΨJT = 0.81°C/W for the 100-ball CSP_BGA (based on 2s2p test

board defined by JEDEC standards.

WTOTAL = (PVDD × IPVDD) + (TVDD × ITVDD) − PUpStream +

(CVDD × ICVDD) + (AVDD × IAVDD) + (DVDD × IDVDD) +

(DVDDIO × IDVDDIO) + (MVDD × IMVDD)

where PUpStream is the quantity of TVDD power consumed on the

upstream HDMI transmitter. PUpStream can be estimated to be

around 110 mW for a nominal HDMI transmitter.

ESD CAUTION

Rev. 0 | Page 12 of 20

Data Sheet ADV7482

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 9. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Description

A1 GND Ground Ground.

A2 I2S_SDATA Output I2S Audio Output.

A3 GND Ground Ground.

A4 RX2P HDMI HDMI Digital Input Channel 2.

A5 RX1P HDMI HDMI Digital Input Channel 1.

A6 RX0P HDMI HDMI Digital Input Channel 0.

A7 RXCP HDMI HDMI Input Clock.

A8 DDC_SCL HDMI HDCP Slave Serial Clock.

A9 DNC Miscellaneous Do Not Connect. Leave this pin unconnected.

A10 GND Ground Ground.

MVDD

Power

MIPI Supply Voltage (1.8 V).

B2 I2S_SCLK Output Audio Serial Clock.

B3 CVDD Power HDMI Comparator Supply Voltage (1.8 V). This is the supply for the

HDMI sensitive analog circuitry. Blocks on this supply include the

TMDS PLL and the equalizers.

B4 RX2N HDMI HDMI Digital Input Channel 2 Complement.

B5 RX1N HDMI HDMI Digital Input Channel 1 Complement.

B6 RX0N HDMI HDMI Digital Input Channel 0 Complement.

B7 RXCN HDMI HDMI Input Clock Complement.

B8 DDC_SDA HDMI HDCP Slave Serial Data.

B9 HPD HDMI HDMI Hot Plug Assert.

B10 GND Ground Ground.

1 2 3 4 5 6 7 8 9 10

AGND I2S_

SDATAGND RX2PRX1PRX0PRXCPDDC_SCLDNC GND A

BMVDD I2S_

SCLK CVDD RX2N RX1N RX0N RXCN DDC_SDAHPD GND B

CCLKAN CLKAPI2S_

LRCLK I2S_

MCLK TEST2 TVDD CEC RX_5V AIN7 AIN8 C

DDA0N DA0PTEST3 DVDD GND GND GND DIAG4 AIN5 AIN6 D

EDA1N DA1PINTRQ2 GND GND GND AVDD DIAG3 AIN3 AIN4 E

FDA2N DA2PINTRQ1 GND GND GND GND VREFN AIN1 AIN2 F

GDA3N DA3PTEST DVDD GND GND GND VREFPDIAG1 DIAG2 G

HDB0N DB0PDVDDIO P1 P4 DNC DNC RESET PVDD GND H

JCLKBN CLKBPMVDD P2 P5 P7 DNC SCLK XTALN XTALPJ

KGND MVDD P0 P3 P6 LLC DNC SDATAALSB GND K

1 2 3 4 5 6 7 8 9 10

12047-012

DNC = DO NOT CONNEC T. LEAVE THI S P IN UNCO NNE CTED.

Rev. 0 | Page 13 of 20

ADV7482 Data Sheet

Pin No. Mnemonic Type Description

C1 CLKAN Output MIPI Transmitter A Negative Output Clock.

C2 CLKAP Output MIPI Transmitter A Positive Output Clock.

C3 I2S_LRCLK Output Audio Left/Right Clock.

C4 I2S_MCLK Output Audio Master Clock Output.

TEST2

Miscellaneous

Test Pin 2. Pull down via a large pull-down resistor to ground.

C6 TVDD Power HDMI Terminator Supply Voltage (3.3 V).

C7 CEC HDMI CEC Channel.

C8 RX_5V HDMI HDMI 5 V Detect. A large pull-down resistor (100 kΩ, typical) to

ground must be connected to this pin.

C9 AIN7 Input Analog Video Input Channel.

C10

AIN8

Input

Analog Video Input Channel.

D1 DA0N Output MIPI Transmitter A Negative Data Output.

D2 DA0P Output MIPI Transmitter A Positive Data Output.

D3 TEST3 Miscellaneous Test Pin 3. Pull up to DVDDIO via a pull-up resistor (4.7 kΩ).

D4 DVDD Power Digital Supply Voltage (1.8 V).

D5 GND Ground Ground.

D6 GND Ground Ground.

D7 GND Ground Ground.

D8 DIAG4 Input Analog Video Diagnostic Input. This input is 5 V tolerant.

D9 AIN5 Input Analog Video Input Channel.

D10 AIN6 Input Analog Video Input Channel.

E1 DA1N Output MIPI Transmitter A Negative Data Output.

E2 DA1P Output MIPI Transmitter A Positive Data Output.

E3 INTRQ2 Output Interrupt Request Output.

E4 GND Ground Ground.

E5 GND Ground Ground.

E6 GND Ground Ground.

E7 AVDD Power Analog Supply Voltage (1.8 V).

E8 DIAG3 Input Analog Video Diagnostic Input. This input is 5 V tolerant.

E9 AIN3 Input Analog Video Input Channel.

E10 AIN4 Input Analog Video Input Channel.

F1 DA2N Output MIPI Transmitter A Negative Data Output.

F2 DA2P Output MIPI Transmitter A Positive Data Output.

F3 INTRQ1 Output Interrupt Request Output.

F4 GND Ground Ground.

F5 GND Ground Ground.

F6 GND Ground Ground.

F7 GND Ground Ground.

F8 VREFN Output Internal Voltage Reference Output.

F9 AIN1 Input Analog Video Input Channel.

F10 AIN2 Input Analog Video Input Channel.

G1 DA3N Output MIPI Transmitter A Negative Data Output.

G2 DA3P Output MIPI Transmitter A Positive Data Output.

G3 TEST Miscellaneous Do Not Connect. Leave this pin unconnected.

G4 DVDD Power Digital Supply Voltage (1.8 V).

G5 GND Ground Ground.

G6 GND Ground Ground.

G7 GND Ground Ground.

VREFP

Output

Internal Voltage Reference Output.

G9 DIAG1 Input Analog Video Diagnostic Input. This input is 5 V tolerant.

G10 DIAG2 Input Analog Video Diagnostic Input. This input is 5 V tolerant.

Rev. 0 | Page 14 of 20

Data Sheet ADV7482

Pin No. Mnemonic Type Description

H1 DB0N Output MIPI Transmitter B Negative Data Output.

H2 DB0P Output MIPI Transmitter B Positive Data Output.

H3 DVDDIO Power Digital Input/Output Supply Voltage (3.3 V).

H4 P1 Input/Output Video Pixel Input/Output Port.

Input/Output

Video Pixel Input/Output Port.

H6 DNC Miscellaneous Do Not Connect. Leave this pin unconnected.

H7 DNC Miscellaneous Do Not Connect. Leave this pin unconnected.

H8 RESET Input System Reset Input, Active Low. A minimum low reset pulse of

5 ms is required to reset the chip.

H9 PVDD Power PLL Supply Voltage (1.8 V).

H10

GND

Ground

Ground.

J1 CLKBN Output MIPI Transmitter B Negative Output Clock.

J2 CLKBP Output MIPI Transmitter B Positive Output Clock.

J3 MVDD Power MIPI Supply Voltage (1.8 V).

J4 P2 Input/Output Video Pixel Input/Output Port.

J5 P5 Input/Output Video Pixel Input/Output Port.

J6 P7 Input/Output Video Pixel Input/Output Port.

J7 DNC Miscellaneous Do Not Connect. Leave this pin unconnected.

J8 SCLK Input I2C Port Serial Clock Input.

J9 XTALN Output Crystal Output. This pin must be connected to the 28.63636 MHz

crystal or not connected if an external 1.8 V, 28.63636 MHz clock

oscillator is used. In crystal mode, the crystal must be a

fundamental crystal.

J10 XTALP Input Crystal Input or External Clock Input. This pin must be connected

to the 28.63636 MHz crystal or connected to an external 1.8 V,

28.63636 MHz clock oscillator if a clock oscillator is used. In crystal

mode, the crystal must be a fundamental crystal.

K1 GND Ground Ground.

K2 MVDD Power MIPI Supply Voltage (1.8 V).

K3 P0 Input/Output Video Pixel Input/Output Port.

K4 P3 Input/Output Video Pixel Input/Output Port.

K5 P6 Input/Output Video Pixel Input/Output Port.

LLC

Input/Output

Line Locked Clock. Input/output clock for the pixel data.

K7 DNC Miscellaneous Do Not Connect. Leave this pin unconnected.

K8 SDATA Input/Output I2C Port Serial Data Input/Output.

K9 ALSB Input Main I2C Address Selection Pin. This pin selects the main I2C

address (IO Map I2C address) for the part. When ALSB is set to

Logic 0, the IO Map I2C write address is 0xE0; when ALSB is set to

Logic 1, the IO Map I2C write address is 0xE2.

K10 GND Ground Ground.

Rev. 0 | Page 15 of 20

ADV7482 Data Sheet

Rev. 0 | Page 16 of 20

POWER SUPPLY RECOMMENDATION

POWER-UP SEQUENCE

Adhere to the absolute maximum ratings at all times during

power-up (see Table 6). The power-up sequence for the

ADV7482 is as follows:

1. Assert RESET (pull the pin low).

2. Power up the 3.3 V supplies (DVDDIO and TVDD). These

supplies must be powered up simultaneously.

3. Power up the 1.8 V supplies (DVDD, CVDD, PVDD, MVDD, and

AVDD). These supplies must be powered up simultaneously.

4. RESET can be deasserted (pulled high) 5 ms after all

supplies are fully powered up.

5. After all power supplies and the RESET pin are powered up

and stable, wait an additional 5 ms before initiating I2C

communication with the ADV7482.

POWER-DOWN SEQUENCE

The ADV7482 power supplies can be deasserted simultaneously

as long as a higher rated supply (for example, DVDDIO) does not

fall to a voltage level less than a lower rated supply (for example,

DVDD), and the absolute maximum ratings specifications are

followed.

Figure 10. Supply Power-Up Sequence

3.3V SUPPLIE

RESET

3.3V

1.8V SUPPLIE

1.8V

3.3V

RESET > 5ms

12047-017

Data Sheet ADV7482

THOERY OF OPERATION

HDMI RECEIVER

The HDMI receiver supports video formats ranging from 480i

to 1080p, and display resolutions from VGA (640 × 480 at

60 Hz) to UXGA (1600 × 1200 at 60 Hz).

The HDMI receiver allows programmable equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. The receiver is capable

of equalizing for cable lengths up to 30 meters to achieve robust

receiver performance.

The HDMI interface of the ADV7482 allows for authentication

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission, as

specified by the HDCP 1.4 protocol.

Dual extended display identification data (EDID) support is

provided via an on-chip 512-byte EDID RAM. The EDID RAM

must be programmed at power-up. It can be configured as two

256-byte EDIDs, or as a single 512-byte EDID.

The ADV7482 has a synchronization regeneration block used to

regenerate the data enable (DE) signal based on the measurement

of the video format being displayed and to filter the horizontal

and vertical synchronization signals to prevent glitches.

The HDMI receiver also supports TMDS error reduction

coding, 4-bit (TERC4) error detection, used for the detection of

corrupted HDMI packets.

The main HDMI receiver features include

• 162.0 MHz (UXGA at 24 BPP) maximum TMDS clock

frequency.

• Integrated fully adaptive equalizer for cable lengths up to

30 meters.

• HDCP 1.4 support.

• Internal HDCP keys.

• HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

• PCM audio packet support.

• Support for 8-channel TDM output data up to 48 kHz.

• Repeater support.

• Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

• Hot Plug assert output pin (HPD).

• CEC controller.

COMPONENT PROCESSOR

The ADV7482 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

CP features include

• Support for all video modes supported by the HDMI

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

• Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

• Free run output mode that provides stable timing when no

video input is present.

• Timing adjustments controls for HS/VS/DE timing.

ANALOG FRONT END

The ADV7482 AFE comprises a single high speed, 10-bit ADC

that digitizes the analog video signal before applying it to the

SDP. The AFE uses differential channels to the ADC to ensure

high performance in mixed-signal applications and to enable

differential CVBS to be connected directly to the ADV7482.

Up to eight analog inputs can be connected to the AFE. The

front end also includes an 8-channel input mux that enables

different configurations of single-ended CVBS (up to eight),

pseudo differential or fully differential CVBS (up to four), Y/C

(up to four), and YPbPr (up to two) analog inputs.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is within the range of the

ADC. Figure 11 shows a typical voltage divider network for

single-ended inputs, Figure 12 shows a typical voltage divider

network for pseudo differential inputs, and Figure 13 shows a

typical voltage divider network for fully differential inputs. The

choice of the resistor divider shown in Figure 13 provides a

common-mode range of up to 4 V in fully differential CVBS

input mode. Fine clamping of the video signal is performed

downstream by digital fine clamping within the ADV7482.

Figure 11. Typical Single-Ended Input Voltage Divider Network

Figure 12. Typical Pseudo Differential Input Resistor Divider Network

AIN

ANALOG

INPUT

51Ω

24Ω

100nF

12047-013

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

75Ω

430Ω

100nF

12047-014

Rev. 0 | Page 17 of 20

ADV7482 Data Sheet

Figure 13. Typical Fully Differential Input Resistor Divider Network

The ADC features three clocking rates that allow 4×

oversampling per channel for CVBS mode, Y/C mode, and

YPbPr mode.

The fully differential AFE of the ADV7482 provides inherent

small and large signal noise rejection, improved electromagnetic

interference (EMI) protection, and the ability to absorb ground

bounce. Support is provided for both true differential and

pseudo differential signals.

The main AFE features include

• A single 172 MHz, 10-bit ADC that enables true 8-bit

video decoding.

• 8-channel analog input mux that enables multiple source

connections without the requirement of an external mux.

• A current clamp control loop that ensures that any dc

offsets are removed from the video signal entering the SDP.

• Diagnostic capability on all differential inputs.

• Support for 4 V common-mode input range.

• Support for analog input signals up to 1 V p-p.

• Support for single-ended, pseudo differential, and fully

differential inputs.

SHORT TO BATTERY DIAGNOSTICS

In differential mode, the ADV7482 is protected against STB

events by ac coupling capacitors (see Figure 12 and Figure 13).

The input network resistors are sized to reduce the current flow

during an STB event, thus preventing damage to the resistors.

Note that the input network resistors and the ac coupling

capacitors must be chosen with ratings guaranteeing they are

able to withstand the high voltage of STB events.

The four diagnostic inputs of the ADV7482 provide diagnostic

capability for all differential inputs. The ADV7482 can detect an

STB event on either the positive or the negative composite input

and trigger an interrupt. The 75 Ω (pseudo differential) or 150 Ω

(fully differential) parallel termination resistor enables one

DIAGx pin to sense an STB event on either input, because there

is a minimal voltage drop across the resistor.

Figure 14. Diagnostic Connection for Differential Inputs

Resistors R4 and R5 divide down the voltage at the input

connector to protect the DIAGx pin from an STB event. The

DIAGx pin circuitry compares this voltage to a programmable

reference voltage, known as the diagnostic slice level. When the

diagnostic slice level is exceeded, an STB event has occurred.

R4 and R5 are sized to allow the use of low cost, small footprint

resistors that are tolerant of STB events.

Use the following equation to find the STB voltage for a selected

diagnostic slice level.

EL_SLICE_LEVDIAGNOSTIC

R4R5

VRSTB_TRIGGE ×

where:

VSTB_TRIGGER is the minimum voltage required at the input

connector to trigger the STB interrupt on the ADV7482.

DIAGNOSTIC_SLICE_LEVEL is the programmable reference

voltage.

For example, with a diagnostic slice level programmed to

1.125 V, an R4 value of 9.1 kΩ, and an R5 value of 1 kΩ, the

minimum voltage required at the input connector to trigger the

STB interrupt is approximately 11.4 V.

When the DIAGx pin voltage exceeds the diagnostic slice level

voltage, a hardware interrupt is triggered and indicated by one

of the interrupt pins. A readback register specifies the input on

which the STB event occurred.

STANDARD DEFINITION PROCESSOR

The ADV7482 is capable of decoding a large selection of

baseband video signals in composite (both single-ended and

differential), S-Video, and component formats. The video

standards supported by the video processor include

• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,

PAL Nc, and PAL 60

• NTSC J, NTSC M, and NTSC 4.43

• SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L

The ADV7482 can automatically detect the video standard and

process it accordingly.

The ADV7482 has a five-line adaptive 2D comb filter that

provides superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to the

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

150Ω

430Ω

100nF

12047-015

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

75Ω

150Ω

430Ω

DIAGx

100nF

12047-016

Rev. 0 | Page 18 of 20

Data Sheet ADV7482

video standard and signal quality without requiring user

intervention. Video user controls such as brightness, contrast,

saturation, and hue are also available with the ADV7482.

The ADV7482 implements the patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7482 to track and decode poor quality video sources such

as VCRs and noisy sources from tuner outputs, VCD players,

and camcorders. The ADV7482 contains a chroma transient

improvement (CTI) processor that sharpens the edge rate of

chroma transitions, resulting in sharper vertical transitions.

The ACE of the ADV7482 offers improved visual detail using

an algorithm that automatically varies contrast levels to enhance

picture detail. ACE allows the contrast of an image to increase

depending on the content of the picture. Typically, this allows

bright areas to be made brighter and dark areas to be made

darker. However, the ADV7482 ACE feature also allows the

contrast within dark areas to increase without significantly

affecting the bright areas of the picture. This feature is

particularly useful in automotive applications, where it is

important to discern objects in shaded areas.

Down dithering converts the output of the ADV7482 from an

8-bit to a 6-bit output, enabling ease of design for standard LCD

panels.

The SDP can process a variety of VBI data services, such as

closed captioning (CCAP), wide screen signaling (WSS), and

copy generation management system (CGMS).

The ADV7482 is fully Rovi®(Macrovision®) compliant; detection

circuitry enables Type I, Type II, and Type III protection levels

to be identified and reported to the user. The decoder is also

fully robust to all Macrovision signal inputs.

8-BIT DIGITAL INPUT/OUTPUT PORT

The ADV7482 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

• 8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

• 8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from either the SD core or the

CP core.

AUDIO PROCESSING

The ADV7482 features an audio processor that handles the

audio extracted from the HDMI stream by the HDMI receiver.

It contains an audio mute controller that can detect a variety of

conditions that may result in audible extraneous noise in the

audio output. On detection of these conditions, a 2-channel

linear PCM audio signal can be ramped down to a mute state to

prevent audio clicks or pops.

The audio is output on a single flexible serial digital audio

output port supporting I2S-compatible, left justified, and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

MIPI CSI-2 TRANSMITTERS

The ADV7482 features two MIPI CSI-2 transmitters: a four-

lane transmitter (Transmitter A) and a single lane transmitter

(Transmitter B).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P),

and a differential clock lane (CLKAN and CLKAP). It supports

four data lanes, two data lanes, and one data lane muxing

options, and can be used to transmit video received on either

the HDMI receiver (processed through the CP), the 8-bit digital

input port, or the AFE (processed through the SDP).

The main features of the four-lane MIPI transmitter

(Transmitter A) include

• Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

• Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

• Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

• Data lanes and clock lane remapping to ease PCB layout.

The single lane transmitter consists of a single differential data

lane (DB0N and DB0P) and a differential clock lane (CLKBN

and CLKBP). It transmits video received on the AFE (processed

through the SDP).

The main features of the single lane MIPI transmitter

(Transmitter B) include

• Support for 8-bit YCbCr 4:2:2 video mode.

• Support for 480i and 576i video formats.

INTERRUPTS

The ADV7482 features two interrupt request pins. INTRQ1 and

INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI receiver (video

and audio related), the SDP, and the CP.

Rev. 0 | Page 19 of 20

ADV7482 Data Sheet

OUTLINE DIMENSIONS

Figure 15. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-100-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2, 3 Temperature Range Package Description Package Option

ADV7482WBBCZ

−40°C to +85°C

100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

BC-100-4

ADV7482WBBCZ-RL −40°C to +85°C 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-100-4

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

3 This device is programmed with internal HDCP keys. Customer must have HDCP adopter status (consult Digital Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys

AUTOMOTIVE PRODUCTS

The ADV7482W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

9.10

9.00 SQ

8.90

7.20

BSC SQ

0.50

0.45

0.40

03-14-2013-A

*COMPLIANT TO JE DE C S TANDARDS MO-275- DDAB- 1

WITH THE EXCEPTION TO PACKAGE HEIGHT

COPLANARITY

0.12

0.26

REF

76321

BALL DIAM E TER

0.80

BSC

0.90

REF

DETAIL A

A1 BALL

CORNER

A1 BALL

CORNER

DETAIL A

BOTTOM VIEW

TOP VIEW

SEATING

PLANE

*1.400

1.253

1.173

0.975

0.910

0.845

0.383

0.343

0.303

8910

registered trademarks are the property of their respective owners.

D12047-0-6/14(0)

Rev. 0 | Page 20 of 20