INTEGRATED CIRCUITS DATA SHEET TDA8046 Multi-mode QAM demodulator Product specification Supersededs data of 1996 Jul 23 File under Integrated Circuits, IC02 1996 Nov 19 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 CONTENTS 1 FEATURES 2 APPLICATION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 Functional description of the individual blocks Quadrature demodulator and half Nyquist filter Equalizer Lock detector Carrier recovery Clock recovery AGC Offset control Loop amplifiers Output formatter Boundary scan I2C-bus interface I2C-bus write parameters I2C-bus read parameters 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS 11 LOCK DETECTOR CHARACTERISTICS 12 CARRIER RECOVERY CHARACTERISTICS 13 CLOCK RECOVERY CHARACTERISTICS 14 AGC CHARACTERISTICS 15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS 16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS 17 PACKAGE OUTLINE 18 SOLDERING 18.1 18.2 18.3 18.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 21 PURCHASE OF PHILIPS I2C COMPONENTS 1996 Nov 19 2 Philips Semiconductors Product specification Multi-mode QAM demodulator 1 TDA8046 * Input format: Straight binary or 2's complement (up to 9 bits, TTL compatible) FEATURES * Different modulation schemes: 4, 16, 32, 64 and 256-QAM * Output format: 8-bit wide bus (CMOS compatible) * I2C-bus interface to initialize and monitor the demodulator. When no I2C-bus usage; 64-QAM, 20% roll-off factor in default mode * Digital demodulator and square root raised cosine Nyquist filter with roll-off of 15% or 20% * High performance adaptive equalizer (no training sequence needed) * 5 V peripheral and analog supply voltage * 3.3 V core supply voltage * Digital detectors for generation of required control voltages for carrier recovery, clock recovery and AGC * Boundary scan test. * Digital-to-analog converters and operational amplifiers allowing high flexibility for selection of the (PLL) loop time constants 2 Demodulation for digital cable TV and cable modem. * High maximum symbol rate (rs) of 7 Msymbols/s 3 APPLICATION QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD(core) core supply voltage 3.00 3.30 3.60 V VDDD digital peripheral supply voltage 4.75 5.00 5.25 V VDDA analog supply voltage 4.75 5.00 5.25 V IDDD(core) core supply current VDDD(core) = 3.3 V; note 1 - 100 - mA IDDD digital peripheral supply current VDDD = 5 V; note 1 - 14 - mA VDDA = 5 V; note 1 - 16 - mA - - 7 Msym/s - 0.7 - dB IDDA analog supply current rs symbol rate IL implementation loss Nyquist roll-off (programmable) - 15 or 20 - % SNRlock signal-to-noise ratio for locking a 64-QAM constellation 21 - - dB signal-to-noise ratio for locking a 256-QAM constellation 27 - - dB note 2 Notes 1. The supply currents are specified for the maximum symbol frequency. 2. The implementation loss (IL) of the demodulator is defined as the distance between the measured and theoretical BER curve as function of signal-to-noise ratio at a BER = 10-6 for a back-to-back measurement at the IF frequency. This performance depends on the chosen loop parameters (see Application notes). 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8046H QFP64 1996 Nov 19 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm 3 VERSION SOT319-2 1996 Nov 19 4 CLKT PRESET DIN0 to DIN8 CLKADC CLK A0 SCL SDA 19 49 1 to 5, 8 to 11 15 62 37 35 36 54 VAGCTC VAGC 53 DAC rs 2rs Vref Iref1 VDDA 60 TDA8046 39 VSSA 59 Vref Iref2 48 OFFSET OFFSET CONTROL 47 44 Vref IBIAS 52 BIAS GENERATOR ANALOG SECTION NCO CONTROL VCLKREC 58 42 BOUNDARY SCAN TEST DIGITAL PHASE ROTATOR 43 TCK TRST TDI TDO TMS Iref3 Iref2 Iref1 56 Vref Iref3 VCARTC VCARREC 55 DAC OUTPUT FORMATTER 7, 12, 14, 17, 24, 26, 31, 34, 46, 50, 61, 64 VSSD1 to 12 CARRIER RECOVERY FINE AGC EQUALIZER FINE AGC CONTROL 6, 13, 16, 25, 33, 38, 45, 51, 63 VDDD1 to 9 MGG198 18 32 20 to 23 27 to 30 CLKSDV CLKOUT DO7 to DO0 Multi-mode QAM demodulator Fig.1 Block diagram. VCLKTC 57 DAC CLOCK RECOVERY SQUARE ROOT RAISED COSINE SQUARE ROOT RAISED COSINE to DACs internal clock for digital processing DEMODULATOR COARSE AGC INPUT REPRESENTATION 4rs CLOCK GENERATOR I2C-BUS CONTROL 40 41 TEST3 dbook, full pagewidth TEST2 5 TEST1 Philips Semiconductors Product specification TDA8046 BLOCK DIAGRAM Philips Semiconductors Product specification Multi-mode QAM demodulator 6 TDA8046 PINNING SYMBOL PIN I/O DESCRIPTION DIN0 1 I digital input bit 0 (LSB) DIN1 2 I digital input bit 1 DIN2 3 I digital input bit 2 DIN3 4 I digital input bit 3 DIN4 5 I digital input bit 4 VDDD1 6 supply digital peripheral supply voltage 1 (+5 V) VSSD1 7 supply digital ground 1; for input peripheral and core DIN5 8 I digital input bit 5 DIN6 9 I digital input bit 6 DIN7 10 I digital input bit 7 DIN8 11 I VSSD2 12 supply digital ground 2; for core and clock buffers VDDD2 13 supply digital supply voltage 2; for core and clock buffers (+3.3 V) VSSD3 14 supply digital peripheral ground 3 CLKADC 15 O clock output to ADC (4 x rs) VDDD3 16 supply digital peripheral supply voltage 3 (+5 V) VSSD4 17 supply digital ground 4; for core CLKSDV 18 O clock symbol data valid output CLKT 19 I for test purpose only DO7 20 O parallel data output (bit 7) DO6 21 O parallel data output (bit 6) DO5 22 O parallel data output (bit 5) DO4 23 O parallel data output (bit 4) VSSD5 24 supply digital peripheral ground 5 VDDD4 25 supply digital peripheral supply voltage 4 (+5 V) VSSD6 26 supply digital ground 6; for core DO3 27 O parallel data output (bit 3) DO2 28 O parallel data output (bit 2) DO1 29 O parallel data output (bit 1) DO0 30 O parallel data output (bit 0) VSSD7 31 supply digital peripheral ground 7 CLKOUT 32 I VDDD5 33 supply digital peripheral supply voltage 5 (+5 V) VSSD8 34 supply digital peripheral ground 8 SCL 35 I serial clock input (I2C-bus) SDA 36 I/O serial data input/output (I2C-bus) A0 37 I hardware address input (I2C-bus) VDDD6 38 supply TEST3 39 I test input 3 (normally connected to ground) TEST2 40 I test input 2 (normally connected to ground) 1996 Nov 19 digital input bit 8 (MSB) output formatter clock output digital peripheral supply voltage 6 (+5 V) 5 Philips Semiconductors Product specification Multi-mode QAM demodulator SYMBOL TDA8046 PIN I/O DESCRIPTION TEST1 41 I test input 1 input (normally connected to ground) TRST 42 I optional asynchronous reset input TCK 43 I dedicated test clock input TMS 44 I input control signal VDDD7 45 supply digital supply voltage 7; for core (+3.3 V) VSSD9 46 supply digital ground 9; for core TDO 47 O serial test data output TDI 48 I serial test data input PRESET 49 I VSSD10 50 supply digital ground 10; for the digital section of the analog block VDDD8 51 supply digital supply voltage 8; for the digital section of the analog block (+5 V) IBIAS 52 I input bias current for DACs VAGCTC 53 O inverted operational amplifier input voltage for loop filtering VAGC 54 O analog output voltage for AGC VCARTC 55 O inverted operational amplifier input voltage for carrier recovery loop filtering VCARREC 56 O analog output voltage for carrier recovery VCLKTC 57 O inverted operational amplifier input voltage for clock recovery loop filtering VCLKREC 58 O VSSA 59 supply analog ground VDDA 60 supply analog supply voltage (+5 V) VSSD11 61 supply digital ground 11; for clock CLK 62 I VDDD9 63 supply digital supply voltage 9; for clock VSSD12 64 supply digital peripheral ground 12 1996 Nov 19 set device into default mode input analog output voltage for clock recovery clock input (4 x rs) 6 Philips Semiconductors Product specification 52 IBIAS 53 VAGCTC 54 VAGC 55 VCARTC 56 VCARREC 57 VCLKTC 58 VCLKREC 59 VSSA TDA8046 60 VDDA 61 VSSD11 62 CLK handbook, full pagewidth 63 VDDD9 64 VSSD12 Multi-mode QAM demodulator DIN0 1 51 VDDD8 DIN1 2 50 VSSD10 DIN2 3 49 PRESET DIN3 4 48 TDI DIN4 5 47 TDO VDDD1 6 46 VSSD9 VSSD1 7 45 VDDD7 DIN5 8 44 TMS DIN6 9 43 TCK TDA8046 DIN7 10 42 TRST DIN8 11 41 TEST1 VSSD2 12 40 TEST2 VDDD2 13 39 TEST3 VSSD3 14 38 VDDD6 CLKADC 15 37 A0 VDDD3 16 36 SDA VSSD4 17 35 SCL Fig.2 Pin configuration. 1996 Nov 19 7 CLKOUT 32 VSSD7 31 DO0 30 DO1 29 DO2 28 DO3 27 VSSD6 26 VDDD4 25 VSSD5 24 DO4 23 33 VDDD5 DO5 22 CLKT 19 DO6 21 34 VSSD8 DO7 20 CLKSDV 18 MGG197 Philips Semiconductors Product specification Multi-mode QAM demodulator 7 TDA8046 currents which are then integrated by a loop filter. To perform this loop filtering, an operational amplifier is integrated after each DAC. FUNCTIONAL DESCRIPTION Figure 3 shows the application of the TDA8046 multi-mode QAM demodulator. The frequency of the IF signal (IFQAM) is down converted to a frequency that equals the symbol rate (rs) by a mixer which is driven from a local oscillator with a frequency of fCAR = fIF + rs. After low pass filtering this baseband signal is applied to an external 8 or 9-bit ADC. The carrier recovery consists of a two-loop system. The outer loop is shown in Fig.3, and controls both phase and frequency at a low speed. The inner loop controls the carrier phase at a high speed (wide loop bandwidth). The AGC also consists of two loops; the outer loop is the coarse AGC and one inner loop is the fine AGC. For 256-QAM, a 9-bit ADC is preferred, for the other modes an 8-bit ADC is sufficient. The recovered symbols are converted into bits according to a demapping scheme and represented at the output in an 8-bit parallel output format. The QAM demodulator can be initialized and monitored by the I2C-bus interface. The multi-mode QAM demodulator has digital detectors for AGC, carrier recovery and clock recovery. The on-chip DACs translate the detector values to analog control handbook, full pagewidth RF signal TUNER SAW IFQAM 8 or 9 bits LPF ADC fCAR = fIF + rs fclk clock recovery carrier recovery AGC TDA8046 I2C-BUS Fig.3 Application with multi-mode QAM demodulator. 1996 Nov 19 8 DO7 to DO0 CLKOUT CLKSDV MGG167 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1 TDA8046 The TDA8046 can handle five different digital modulation schemes; 4, 16, 32, 64 and 256-QAM. These schemes are selectable via the I2C-bus interface. Functional description of the individual blocks The functional block diagram of the multi-mode QAM demodulator is illustrated in Fig.1. This section describes the individual blocks in the demodulator. After adaptation for the used input format (2's complement or binary), the input signal is demodulated in the I and Q baseband signals which are applied to the inputs of the half-Nyquist filter (equals square root raised cosine). To avoid overloading of the ADC, an AGC detector is placed after the adaptation for the input format. The control value for the clock recovery is generated after half Nyquist filtering. The echoes created in the cable network are reduced significantly in the equalizer. QUADRATURE DEMODULATOR AND HALF NYQUIST 7.1.1 FILTER Quadrature demodulation is accomplished after selection of the appropriate input format via the I2C-bus. The in-phase and quadrature components are both applied to a half Nyquist filter. In default mode, this filter gives a 20% roll-off half Nyquist shaping. The basic schematic of the quadrature demodulator followed by the half Nyquist filter is shown in Fig.4. The signs of the multiplication factors in the Q-branch can be inverted (I2C-bus bit INVD). The equalizer produces a `clean' constellation diagram from which the information for the carrier recovery is derived. This constellation is also applied to the output formatter which demaps the transmitted symbols in corresponding bits. The carrier recovery and lock detection functions are based on the equalizer output. The output of the equalizer is applied to an output formatter, which translates the symbol bits to a FEC input format. The digital outputs of the clock recovery, AGC, and carrier recovery section are converted into currents which are integrated by the loop filters. To make these loop filters active, operational amplifiers are integrated on the chip. When using an 8-bit ADC the LSB of the 9-bit input word should be connected to the positive supply (VDDD). This ensures a symmetrical 2's complement representation which can be multiplied by -1 in a correct (2's complement) way. The overall transfer function of the square root raised cosine filters is shown in Figs 5 and 6. For characteristics see Chapter 10. I2C-BUS handbook, full pagewidth 9 DIN8 9 to DIN0 BINARY OR TWO's COMPLEMENT +1, 0, -1, 0 I HALF NYQUIST FILTER 0, -1, 0, +1 9 Q HALF NYQUIST FILTER I2C-BUS I2C-BUS I2C-BUS MGG168 Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter. 1996 Nov 19 9 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 MBG987 5 handbook, full pagewidth 0 -5 relative gain (dB) -15 -25 -35 -45 -55 0 0.25 0.5 0.75 1 1.25 1.5 1.75 relative frequency 2 ( f rs ) Fig.5 Half Nyquist receiver filter transfer function (20% roll-off). MGG169 handbook, full pagewidth 0 relative gain (dB) -10 -20 -30 -40 -50 0 0.25 0.5 0.75 1 1.25 1.5 1.75 relative frequency Fig.6 Half Nyquist receiver filter transfer function (15% roll-off). 1996 Nov 19 10 2 ( f rs ) Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.2 TDA8046 The equalizer has been proven to work correctly under bad channel conditions as indicated in Table 1. It is guaranteed that all loops (including equalizer) converge at a SNR of 21 dB for a 64-QAM modulation format and 27 dB for a 256-QAM modulation format. EQUALIZER This function is realized with a T spaced 12 or 14 taps (selected via the I2C-bus) adaptive filter with a feedback part. The equaliser is based on a Decision Feedback Equalizer (DFE) structure with Least Mean Square (LMS) coefficient updating algorithm. No training sequence is required. The block schematic of the total equalizer is shown in Fig.8. The main tap of the equalizer is adjustable for fine AGC function (6 dB AGC range). The settings of the equalizer taps can be read via the I2C-bus. If the equalizer diverges, an alarm bit is set (I2C-bus bit ALEQ) and an automatic reset of the taps can be performed (I2C-bus bit EAR). Table 1 Channel echo profile DELAY AMPLITUDE PHASE 8 x Tsym 1 1 8 x Tsym 0.08 130 0.20 60 3 To improve acquisition time, the convergence steps of the FFE/DFE parts of the equalizer are programmable via the I2C-bus. When the system locks, the steps are automatically modified for optimum performances. 2 x Tsym 0.05 310 458 x Tsym 0.10 200 678 0.03 200 x Tsym Figure 7 represents the QAM spectrum seen by the equalizer. It corresponds (in the frequency domain) to the multiplication of a full nyquist spectrum by the impulse response of the channel specified in Table 1. Besides reading the equalizer tap values, the main tap of the equalizer can also be programmed. After setting the main tap, the other coefficients can be set to zero. The equalizer settings can also be frozen via the I2C-bus. MGD636 1 handbook, full pagewidth relative gain (dB) -1 -3 -5 -7 -9 -11 -0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 relative frequency Fig.7 QAM spectrum with echo profile as seen by the equalizer. 1996 Nov 19 11 0.5 ( f rs ) Philips Semiconductors Product specification Multi-mode QAM demodulator handbook, full pagewidth input TDA8046 FEED FORWARD EQUALIZER DECISION FEEDBACK EQUALIZER TAPS CALCULATION TAPS CALCULATION decision - + MGG170 output Fig.8 DFE equalizer structure. 7.1.3 1. The outer loop; this loop controls the phase and frequency of the incoming QAM signal at the IF frequency in such a way that the constellation is optimally positioned for detection. LOCK DETECTOR The lock detector indicates whether all algorithms in the demodulator are converged or not. For a symbol error rate (at the input of the demodulator) smaller than 2 x 10-2, the detector will give the indication `LOCK' (I2C-bus bit LK = 1). For larger symbol error rates, the detector will generate the `UNLOCK' signal (I2C-bus bit LK = 0). It should ne noted that this `UNLOCK' signal is generated before any other part of the demodulator loses lock. The lock detector is part of the carrier recovery loop, see Fig.9. The Lock Detector Threshold (LDT) can be changed with the help of the I2C-bus. The estimation algorithm used in the lock detector also provides information about the SER ratio which can be read out via the I2C-bus interface. 2. The inner loop; the bandwidth of this loop can be large and can therefore reduce the influence of large bandwidth phase noise. A fully digital carrier recovery function is also possible and can be selected via the I2C-bus. Should this configuration be used, then the external components of the loop filter will not have to be implemented. Four different maximum DAC output currents can be selected via the I2C-bus. The output currents of the DAC are defined in such a way that a VCO with a behaviour as shown in Fig.9 can be connected directly to the output of the integrated operational amplifier. Should the VCO slope be negative then the sign of the current can be inverted by the I2C-bus. Figure 10 defines the DAC output currents. For characteristics see Chapter 11. 7.1.4 CARRIER RECOVERY The carrier recovery detector consists of a Phase-Frequency Detector (PFD) and Phase Detector (PD). Depending on the mode of operation, the carrier recovery is switched either between the phase frequency (no lock) or the phase detector (lock). The carrier recovery consists of the following two loops: 1996 Nov 19 For characteristics see Chapter 12. 12 Philips Semiconductors Product specification Multi-mode QAM demodulator handbook, full pagewidth TDA8046 VCO external 0 DAC IFQAM ICAR rs Vref LPF Iref1 lock I2C-BUS I2C-BUS I2C-BUS LOCK ADC DEMODULATION AND FILTERING EQUALIZER PHASE FREQUENCY DETECTOR PHASE DETECTOR DIGITAL INNER LOOP I2C-BUS lock Fig.9 Schematic diagram of the carrier recovery. 1996 Nov 19 13 I2C-BUS MGG171 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth DAC output current fVCO ICAR CARI = 1 CARI = 0 1/ I 2 CAR digital input VCARREC MGG180 -1/2 ICAR -ICAR Ipos = positive output current. Ineg = negative output current. ( I pos - I neg ) I O = -----------------------------2 ( I pos + I neg ) I O = --------------------------------- x 100 ( I pos - I neg ) Fig.10 Definition of the DAC currents and the expected frequency behaviour of the VCO. 1996 Nov 19 14 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.5 TDA8046 The clock generator generates the required internal clocks from the VCXO clock signal at 4 x rs. The input stage amplifier of this generator enables the designer to supply a low amplitude oscillator signal to the TDA8046. The DAC output current range (ICLK) can be varied via the I2C-bus. The sign of the output current can also be inverted to adjust for the correct sign of the VCXO slope. CLOCK RECOVERY The clock recovery function uses the unequalized I and Q signals, i.e. the half Nyquist filter outputs (see Fig.4). The clock recovery section generates a control value each symbol period. As this algorithm is based on the energy maximization, both main and mid symbols are required at the input. Consequently, the input data rate is twice the symbol rate. The schematic diagram of this detector is illustrated in Fig.11. For characteristics see Chapter 13. handbook, full pagewidth external I DAC CLOCK RECOVERY DETECTOR Q to VCXO ICLK rs Iref3 Vref from VCXO 4rs 2rs 2 rs 4 MGG172 Fig.11 Schematic diagram of the clock recovery. 1996 Nov 19 15 Philips Semiconductors Product specification Multi-mode QAM demodulator handbook, full pagewidth TDA8046 DAC output current fVCXO ICLK CLKI = 1 CLKI = 0 1/ I 2 CLK digital input VCLKREC MGG181 -1/2 ICLK -ICLK Ipos = positive output current; ICLK. Ineg = negative output current; -ICLK. ( I pos - I neg ) I oCLK = -----------------------------2 ( I pos + I neg ) I oCLK = --------------------------------- x 100 ( I pos - I neg ) Fig.12 The definition of the DAC currents and the expected frequency behaviour of the VCXO for clock recovery. 1996 Nov 19 16 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.6 TDA8046 The I2C-bus data on address 08 is a factor 16 smaller than the used AGC threshold ATH. AGC The AGC estimates the mean power based on the digital input signal and relates this to a peak value for a given constellation. To avoid overloading of the ADC, this estimation of the peak signals is used to control the AGC loop. The implemented AGC covers a range of 20 dB in gain variance. A schematic diagram of the AGC is illustrated in Fig.13. The DAC output current range can be varied via the I2C-bus interface (bits AGCA and AGCB) and the sign of the current can be inverted (bit AGCI). The definition of the DAC currents and the expected frequency behaviour of the AGC is illustrated in Fig.14. For characteristics see Chapter 14. If the SAW filter does not have sufficient adjacent channel attenuation, the AGC threshold can be varied to avoid clipping of the ADC. To do this, the threshold is made programmable via the I2C-bus (byte ATH). Table 2 shows that for each mode, a new ATH value (on address 08) must be set with the help of the I2C-bus. Table 2 AGC threshold values ATH (AGC THRESHOLD) I2C-BUS DATA FOR ADDRESS 08 256, 64, 16 and 4-QAM 2040 7F 32-QAM 1442 5A MODE handbook, full pagewidth external DIN8 to DIN0 AGC DETECTOR DAC to AGC amplifier IAGC I2C-BUS Vref rs Iref2 ADC I2C-BUS IBIAS BIAS GENERATOR Iref2 I2C-BUS MGG173 Fig.13 AGC schematic diagram. 1996 Nov 19 17 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth DAC output current gain IAGC AGCI = 1 AGCI = 0 1/ I 14 AGC digital input VAGC MGG182 -1/14 IACG -IAGC Ipos = positive output current; ICLK. Ineg = negative output current; -ICLK. ( I pos - I neg ) I oAGC = -----------------------------2 ( I pos + I neg ) I oAGC = --------------------------------- x 100 ( I pos - I neg ) Fig.14 Definition of the DAC currents and the expected frequency behaviour of the AGC. 1996 Nov 19 18 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.7 TDA8046 OFFSET CONTROL 7.1.9 To compensate offsets in the I and Q branch, due to spurious signals at the symbol frequency at the ADC input, an offset compensation loop is included. This loop forces the constellation to be symmetrically distributed over its four quadrants. This function can be switched off by I2C-bus bit OFFS. 7.1.8 OUTPUT FORMATTER The output formatter transforms the detected symbols into bits in accordance with the selected mapping. The TDA8046 has four possible mapping formats which can be selected via the I2C-bus interface. The demapping procedure and the corresponding bits are defined in Fig.16. After demapping the bits are allocated to the output. This output allocation corresponds to one of the selected demapping schemes. LOOP AMPLIFIERS By using the I2C-bus, it is possible to obtain the following output formats: Analog switches are integrated to discharge the loop filter capacitors or for test purposes on application boards (a reference voltage equal to the half of the positive supply voltage VDDA is available at the output of the amplifier when the switches are closed). The I2C-bus bit ANAS controls the three switches simultaneously. A schematic diagram of the loop amplifier and analog switch is illustrated in Fig.15. * 8 bits parallel * semi-serial * I and Q 8 bits multiplexed. The implemented demapping formats and output bit allocation are illustrated in Figs 17 to 30. For characteristics see Chapter 15. 7.1.10 BOUNDARY SCAN The TDA8046H offers the possibility of boundary scan test. The IEEE Standard Test Access Port and Boundary Scan Architecture allows board manufacturers to test board interconnections by using the boundary scan functions. handbook, halfpage external Complete information on boundary scan test is available in "Application note AN96048". I2C-BUS DAC Vref MGG174 Fig.15 Loop amplifier and analog switch. 1996 Nov 19 19 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth DO7 to DO0 I Q CLKSCV 8 DEMAPPING SCHEMES 1 to 4 8 PARALLEL AND SEMI-SERIAL DO1 to DO0 CLKSCV CLKOUT MUX DO7 to DO0 CLKSCV I2C-BUS CLKOUT MGG175 Fig.16 Schematic diagram of the output formatter. 7.1.10.1 Demapping scheme 1; differential decoding handbook, full pagewidth Q A quadrant b5 b4 b3 b2 b1 b0 000100 001100 011100 010100 110100 111100 101100 100100 000101 001101 011101 010101 110101 111101 101101 100101 000111 001111 011111 010111 110111 111111 101111 100111 000110 001110 011110 010110 110110 111110 101110 100110 000010 001010 011010 010010 110010 111010 101010 100010 000011 001011 011011 010011 110011 111011 101011 100011 000001 001001 011001 010001 110001 111001 101001 100001 000000 001000 011000 010000 110000 111000 101000 100000 MGG193 Bit allocation for 256-QAM: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Fig.17 Demapping scheme 1; bit allocation: 256-QAM. 1996 Nov 19 20 I Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 Q B quadrant handbook, full pagewidth A quadrant b5 b4 b3 b2 1010 1011 1001 1000 0010 0110 1110 1010 1110 1111 1101 1100 0011 0111 1111 1011 0110 0111 0101 0100 0001 0101 1101 1001 0010 0011 0001 0000 0000 0100 1100 1000 1000 1100 0100 0000 0000 0001 0011 0010 1001 1101 0101 0001 0100 0101 0111 0110 1011 1111 0111 0011 1100 1101 1111 1110 1010 1110 0110 0010 1000 1001 1011 1010 I C quadrant D quadrant MGG183 Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 64-QAM: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see Table 3). Fig.18 Demapping scheme 1; bit allocation: 4-QAM and 64-QAM. handbook, full pagewidth B quadrant Q A quadrant 11 10 01 11 01 00 00 10 10 00 00 01 11 01 10 11 b5 b4 I C quadrant D quadrant MGG184 Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 32-QAM: not implemented. Fig.19 Demapping scheme 1; bit allocation: 16-QAM and 32-QAM. 1996 Nov 19 21 Philips Semiconductors Product specification Multi-mode QAM demodulator Demapping scheme 2; direct translation Q b3 b2 b1 b0 1111 1110 1101 1100 1011 1010 b7 b6 b5 b4 1001 0111 0110 0101 0100 0011 0010 0001 0000 handbook, full pagewidth 1000 7.1.10.2 TDA8046 1111 1110 1101 1100 1011 1010 1001 1000 I 0111 0110 0101 0100 0011 0010 0001 0000 MGG195 Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0. Fig.20 Demapping scheme 2; bit allocation: 256-QAM. 1996 Nov 19 22 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth b7 b6 b5 Q 000 001 010 011 100 101 110 b3 b2 b1 111 111 110 101 100 I 011 010 001 000 MGG185 Bit allocation for 64-QAM: b7, b6, b5, b3, b2, b1; b4 = b0 = 0. Bit allocation for 32-QAM: not implemented. Fig.21 Demapping scheme 2; bit allocation: 64-QAM and 32-QAM. b7 b6 handbook, full pagewidth Q Q 00 b7 01 10 11 b3 0 b3 b2 11 1 1 10 I I 0 01 00 MGG186 a. Bit allocation for 4-QAM: b7 and b3; b6 = b5 = b4 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b3 and b2; b5 = b4 = b1 = b0 = 0. Fig.22 Demapping scheme 2; bit allocation: 4-QAM and 16-QAM. 1996 Nov 19 23 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.10.3 TDA8046 Demapping scheme 3; differential decoding: Draft prETS 429: 1994 handbook, full pagewidth Q A quadrant b5 b4 b3 b2 b1 b0 100000 100001 100101 100100 110100 110101 110001 110000 100010 100011 100111 100110 110110 110111 110011 110010 101010 101011 101111 101110 111110 111111 111011 111010 101000 101001 101101 101100 111100 111101 111001 111000 001000 001001 001101 001100 011100 011101 011001 011000 001010 001011 001111 001110 011110 011111 011011 011010 000010 000011 000111 000110 010110 010111 010011 010010 000000 000001 000101 000100 010100 010101 010001 010000 MGG194 Bit allocation for 256-QAM: b5, b4, b3, b2, b1, b0; b7 and b6 differentially decoded (see Table 3). Fig.23 Demapping scheme 3; bit allocation: 256-QAM. 1996 Nov 19 24 I Philips Semiconductors Product specification Multi-mode QAM demodulator handbook, full pagewidth TDA8046 Q B quadrant b5 b4 b3 b2 A quadrant 1100 1110 0110 0100 1000 1001 1101 1100 1101 1111 0111 0101 1010 1011 1111 1110 1001 1011 0011 0001 0010 0011 0111 0110 1000 1010 0010 0000 0000 0001 0101 0100 0100 0101 0001 0000 0000 0010 1010 1000 0110 0111 0011 0010 0001 0011 1011 1001 1110 1111 1011 1010 0101 0111 1111 1101 1100 1101 1001 1000 0100 0110 1110 1100 I C quadrant D quadrant MGG187 Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Bit allocation for 64-QAM: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Fig.24 Demapping scheme 3; bit allocation: 4-QAM and 64-QAM. handbook, full pagewidth B quadrant Q A quadrant 11 01 10 11 10 00 00 01 01 00 00 10 11 10 01 11 b5 b4 I C quadrant D quadrant MGG188 Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Fig.25 Demapping scheme 3; bit allocation: 16-QAM. 1996 Nov 19 25 Philips Semiconductors Product specification Multi-mode QAM demodulator handbook, full pagewidth TDA8046 Q B quadrant A quadrant 111 011 110 010 010 101 001 100 101 111 110 100 000 000 001 011 011 001 000 000 100 110 111 101 100 001 101 010 010 110 011 111 b5 b4 b3 I C quadrant D quadrant MGG189 Bit allocation for 32-QAM: b5, b4 and b3; b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3). Fig.26 Demapping scheme 3; bit allocation: 32-QAM. Demapping scheme 4; direct translation: HP8782B/K03 Q b4 b5 b6 b7 0000 0001 0010 0011 0100 0101 b3 b2 b1 b0 0110 1000 1001 1010 1011 1100 1101 1110 1111 handbook, full pagewidth 0111 7.1.10.4 0000 0001 0010 0011 0100 0101 0110 0111 I 1000 1001 1010 1011 1100 1101 1110 1111 MGG196 Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0. Fig.27 Demapping scheme 4; bit allocation: 256-QAM. 1996 Nov 19 26 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth b2 b3 b4 Q 111 110 101 100 011 010 001 b5 b6 b7 000 000 001 010 011 I 100 101 110 111 MGG190 Bit allocation for 64-QAM: b7, b6, b5, b4, b3 and b2; b1 = b0 = 0. Fig.28 Demapping scheme 4; bit allocation: 64-QAM. handbook, full pagewidth B quadrant Q A quadrant 01111 01011 00010 00110 b7 b6 b5 b4 b3 01110 01101 01001 00100 00101 00111 01010 01100 01000 00000 00001 00011 I 11011 11001 11000 10000 10100 10010 11111 11101 11100 10001 10101 10110 11110 11010 10011 10111 C quadrant D quadrant MGG191 Bit allocation for 32-QAM: b7, b6, b5, b4 and b3; b2 = b1 = b0 = 0. Fig.29 Demapping scheme 4; bit allocation: 32-QAM. 1996 Nov 19 27 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth b4 b5 Q Q 11 b6 10 01 00 b7 1 b6 b7 00 0 0 01 I I 1 10 11 MGG192 a. Bit allocation for 4-QAM: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0. Fig.30 Demapping scheme 4; bit allocation: 4-QAM and 16-QAM. Table 3 Definition of two MSB's in modulation schemes 1 and 3 QUADRANT OF CURRENTLY RECEIVED SYMBOL QUADRANT OF PREVIOUSLY RECEIVED SYMBOL PHASE CHANGE (DEGREES) A A 0 CURRENT OUTPUT BITS SCHEME 1 SCHEME 3 b7 b6 b7 b6 0 0 0 0 A B 270 1 0 0 1 A C 180 1 1 1 1 A D 90 0 1 1 0 B A 90 0 1 1 0 B B 0 0 0 0 0 B C 270 1 0 0 1 B D 180 1 1 1 1 C A 180 1 1 1 1 C B 90 0 1 1 0 C C 0 0 0 0 0 C D 270 1 0 0 1 D A 270 1 0 0 1 D B 180 1 1 1 1 D C 90 0 1 1 0 D D 0 0 0 0 0 Tables 4 and 5 give the output format of the data for semi-serial mode operations. 1996 Nov 19 28 Philips Semiconductors Product specification Multi-mode QAM demodulator Table 4 TDA8046 Semi-serial format 256, 64 and 32-QAM; see note 1 256-QAM 64-QAM 32-QAM SLOT DO1 DO0 CLKSDV DO1 DO0 CLKSDV DO1 DO0 CLKSDV 0 Sn-1(7) Sn-1(6) 1 Sn-1(5) Sn-1(4) 1 Sn-1(4) Sn-1(3) 1 1 Sn-1(5) Sn-1(4) 1 Sn-1(3) Sn-1(2) 1 Sn-1(2) Sn-1(1) 1 2 Sn-1(3) Sn-1(2) 1 Sn-1(1) Sn-1(0) 1 X X 0 3 Sn-1(1) Sn-1(0) 1 X X 0 X X 0 4 Sn(7) Sn(6) 1 Sn(5) Sn(4) 1 Sn-1(0) Sn(4) 1 5 Sn(5) Sn(4) 1 Sn(3) Sn(2) 1 Sn(3) Sn(2) 1 6 Sn(3) Sn(2) 1 Sn(1) Sn(0) 1 Sn(1) Sn(0) 1 7 Sn(1) Sn(0) 1 X X 0 X X 0 Note 1. The semi-serial format is only valid for demapping schemes 1, 3 and 4. Table 5 Semi-serial format 16-QAM and 4-QAM; see note 1 16-QAM 4-QAM SLOT DO1 DO0 CLKSDV DO1 DO0 CLKSDV 0 Sn-1(3) Sn-1(2) 1 Sn-1(1) Sn-1(0) 1 1 Sn-1(1) Sn-1(0) 1 X X 0 2 X X 0 X X 0 3 X X 0 X X 0 4 Sn(3) Sn(2) 1 Sn(1) Sn(0) 1 5 Sn(1) Sn(0) 1 X X 0 6 X X 0 X X 0 7 X X 0 X X 0 Note 1. The semi-serial format is only valid for demapping schemes 1, 3 and 4. 1996 Nov 19 29 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 I2C-BUS INTERFACE 7.1.11 The TDA8046 is controlled by an I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for selecting READ or WRITE mode. It should be noted that the TDA8046 starts up in accordance with to the settings defined in Tables 7, 8 and 9. Table 6 Slave address A6 A5 A4 A3 A2 A1 A0 R/W 0 0 0 1 1 1 A0 X Table 7 WRITE (R/W = 0) FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0 DAC current inversion/general 00 AGCI CLKI CARI OUTE DEM NYQ DPHR RST Demodulator 01 INP RLF OUTB OUTA INVD CONC CONB CONA DAC/OFFS/switch 02 ANAS OFFS AGCB AGCA CLKB CLKA CARB CARA Digital test/output formatter 03 - - - - OUTF TSEL2 TSEL1 TSEL0 Digital loop filter B.W. 04 DCA7 DCA6 DCA5 DCA4 DCA3 DCA2 DCA1 DCA0 Digital loop filter B.W. 05 FSOL - - - - DCB2 DCB1 DCB0 Lock detector threshold 06 LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0 Lock detector window size 07 - - - - - - WS1 WS0 AGC detector threshold 08 ATH7 ATH6 ATH5 ATH4 ATH3 ATH2 ATH1 ATH0 Equalizer mode 09 - - EAR FFEL EDFE EFFE EFC PRESET Equalizer tap FFEI 0A FFEI07 FFEI06 FFEI05 FFEI04 FFEI03 FFEI02 FFEI01 FFEI00 Equalizer steps 0B - FSTP2 FSTP1 FSTP0 - DSTP2 DSTP1 DSTP0 1996 Nov 19 30 Philips Semiconductors Product specification Multi-mode QAM demodulator Table 8 TDA8046 Default settings after reset FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0 DAC current inversion/ general 00 0 1 0 1 1 1 0 0 Demodulator 01 1 1 0 0 0 0 1 1 DAC/OFFS/switch 02 0 1 0 1 0 1 0 1 Digital test/output formatter 03 - - - - 0 0 0 0 Digital loop filter B.W. 04 0 1 0 0 0 0 0 0 Digital loop filter B.W. 05 1 - - - - 1 0 0 Lock detector threshold 06 0 0 0 1 1 0 0 0 Lock detector window size 07 - - - - - - 0 0 AGC detector threshold 08 0 1 1 1 1 1 1 1 Equalizer mode 09 - - 0 1 0 0 0 0 Equalizer tap FFEI 0A 0 1 0 0 0 0 0 0 Equalizer steps 0B - 0 0 0 - 0 0 0 ADD D7 D6 D5 D4 D3 D2 D1 D0 VCARREC (4 bits) 00 - - - - CR03 CR02 CR01 CR00 VCLKREC (4 bits) 01 - - - - CL03 CL02 CL01 CL00 VAGC (4 bits) 02 - - - - AG03 AG02 AG01 AG00 Alarm equalizer/ lock detector 03 - - - ALEQ - - - LK SER estimation 04 LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0 FFEI3 05 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 Table 9 READ (R/W = 1) FUNCTION FFEI0 08 b7 b6 b5 b4 b3 b2 b1 b0 DFEI1 09 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 DFEI7 0F b7 b6 b5 b4 b3 b2 b1 b0 DFEI8 10 b7 b6 b5 b4 b3 b2 b1 b0 FFEQ3 11 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 FFEQ0 14 b7 b6 b5 b4 b3 b2 b1 b0 DFEQ1 15 b7 b6 b5 b4 b3 b2 b1 b0 .... ... b7 b6 b5 b4 b3 b2 b1 b0 DFEQ8 1C b7 b6 b5 b4 b3 b2 b1 b0 FFEI5 1D b7 b6 b5 b4 b3 b2 b1 b0 FFEQ5 1E b7 b6 b5 b4 b3 b2 b1 b0 1996 Nov 19 31 Philips Semiconductors Product specification Multi-mode QAM demodulator FUNCTION FFEI4 TDA8046 ADD D7 D6 D5 D4 D3 D2 D1 D0 1F b7 b6 b5 b4 b3 b2 b1 b0 FFEQ4 20 b7 b6 b5 b4 b3 b2 b1 b0 IF_frequency_shift 21 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 IF_frequency_shift 22 - - - - FS11 FS10 FS9 FS8 7.1.12 I2C-BUS WRITE PARAMETERS Table 10 I2C-bus write parameters; 1-bit values PARAMETER Input format Inversion demodulator Demodulator BIT INP INVD DEM Half Nyquist filter NYQ Roll-off factor RLF Digital phase rotator DPHR General reset RST Offset OFFS Outer loop activation (carrier recovery) OUTE Analog switches ANAS 1st and 2nd-order loop (inner loop) FSOL DAC current inversion CARI CLKI AGCI 1996 Nov 19 VALUE DESCRIPTION 0 2's complement 1 straight binary 0 Q-branch = 0 - 1, 0, +1 1 Q-branch = 0 + 1, 0, -1 0 by-pass mode 1 normal mode 0 filter in by-pass mode 1 half Nyquist filter on 0 15% roll-off 1 20% roll-off 0 off: pass through mode 1 on 0 normal operation 1 reset (with automatic return to normal operation) 0 off 1 on 0 outer loop inactive 1 outer loop active 0 open 1 closed 0 1st-order loop 1 2nd-order loop 0 no inversion 1 inversion 0 no inversion 1 inversion 0 no inversion 1 inversion 32 Philips Semiconductors Product specification Multi-mode QAM demodulator PARAMETER Equalizer BIT TDA8046 VALUE DESCRIPTION PRESET 0 1 coefficient to zero (main tap to 1) EDFE 0 normal operation 1 freeze coefficients of DFE part 0 normal operation 1 freeze coefficients of FFE part EFC [fine AGC (equalizer freeze centre tap)] 0 normal operation 1 freeze centre tap, no fine AGC EAR 0 automatic reset switched OFF 1 automatic reset switched ON 0 5 taps in FFE part 1 3 taps in FFE part EFFE FFEL normal operation Table 11 I2C write parameters; 2-bit values PARAMETER Window size (lock detector) Output format DAC carrier recovery (maximum current) DAC clock recovery (maximum current) DAC AGC (maximum current) 1996 Nov 19 BITS DESCRIPTION WS1 WS0 0 0 256 symbols 0 1 512 symbols 1 0 1024 symbols 1 1 2048 symbols OUTB OUTA 0 0 scheme 1 0 1 scheme 2 1 0 scheme 3 1 1 scheme 4 CARB CARA 0 0 50 A 0 1 100 A 1 0 150 A 1 1 200 A CLKB CLKA 0 0 50 A 0 1 100 A 1 0 150 A 200 A 1 1 AGCB AGCA 0 0 50 A 0 1 100 A 1 0 150 A 1 1 200 A 33 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 Table 12 I2C-bus write parameters; 3-bit values BITS PARAMETER DESCRIPTION CONC CONB CONA 0 0 0 4-QAM 0 0 1 16-QAM 0 1 0 32-QAM 0 1 1 64-QAM 1 0 0 256-QAM Constellation Table 13 Convergence step for the equalizer (DFE and FFE parts) DSTP2 FSTP2 DSTP1 FSTP1 DSTP0 FSTP0 CONVERGENCE STEP (LOCK = 0) CONVERGENCE STEP (LOCK = 1) 0 0 0 2-13 2-15 0 0 1 2-13 2-14 0 1 0 2-13 2-13 2-15 0 1 1 2-12 1 0 0 2-12 2-14 1 0 1 2-12 2-13 2-12 2-15 1 1 0 2-12 1 1 1 2-11 Table 14 I2C-bus write parameters; 4-bit values BITS PARAMETER Output format Special test modes 1996 Nov 19 DESCRIPTION OUTF TSEL2 TSEL1 TSEL0 0 0 0 0 8 bits in parallel 0 1 1 1 I/Q 8 bits multiplexed (equalizer output) 1 x x x semi-serial 0 x 0 1 DO7 to DO4 = carrier recovery DAC input; DO3 to DO0 = AGC DAC input 0 x 1 0 DO7 to DO6 = fine AGC; DO5 to DO0 = clock recovery DAC input 0 0 1 1 DO7 to DO0 = I and Q equal input (I/Q 8 bits multiplexed format) 0 1 1 1 DO7 to DO0 = I and Q equal output (I/Q 8 bits multiplexed format) 34 Philips Semiconductors Product specification Multi-mode QAM demodulator 7.1.13 TDA8046 I2C-BUS READ PARAMETERS Table 15 I2C-bus read parameter; 1-bit values PARAMETER Lock detect Alarm equalizer BIT VALUE LK 0 no lock 1 lock 0 normal operation (alarm off) 1 divergence detected (alarm on) ALEQ DESCRIPTION Table 16 I2C-bus read parameter; ADC carrier recovery; 4-bit value PARAMETER BITS ADC carrier recovery DESCRIPTION CR03 CR02 CR01 CR00 b3 b2 b1 b0 carrier recovery: VCARREC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V Table 17 I2C-bus read parameter; ADC clock recovery; 4-bit value PARAMETER BITS ADC clock recovery DESCRIPTION CL03 CL02 CL01 CL00 b3 b2 b1 b0 clock recovery: VCLKREC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V Table 18 I2C-bus read parameter; ADC AGC; 4-bit value PARAMETER BITS ADC AGC DESCRIPTION AG03 AG02 AG01 AG00 b3 b2 b1 b0 AGC: VAGC = 0.25 + 116VDDD (8b3 + 4b2 + 2b1 + b0) V Table 19 I2C-bus read parameter; 8-bit value PARAMETER SER (1) BITS DESCRIPTION LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0 b7 b6 b5 b4 b3 b2 b1 b0 SER = f (b7 to b0) Note 1. The bits LE7 to LE0 give the number of symbols falling inside the lock detector active areas. The count is made during an observation period (256 to 2048 symbols). To obtain more details about the SER estimation, refer to "Application Note AN96048". Table 20 I2C-bus read parameter; 12-bit value PARAMETER IF_FREQ_SHIFT(1) BITS DESCRIPTION FS11 to FS0 frequency shift = f (FS11 to FS0) Note 1. The bits FS11 to FS0 indicate the remaining frequency shift of the QAM spectrum (IF spectrum). This data is useful if the TDA8046H does not use the outer loop of carrier recovery (bit `OUTE' of the I2C-bus table set to 0). To obtain more details about the frequency shift calculation, refer to the "Application Note AN96048". 1996 Nov 19 35 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage -0.3 6.0 V Vmax maximum voltage on all pins 0 VDDD V Ptot total power dissipation - 1.4 W Tstg storage temperature -55 +150 C Tamb operating ambient temperature 0 70 C 9 Tamb = 70 C THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 50 K/W in free air 10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS SYMBOL PARAMETER CONDITIONS TYP. MAX. - 15 or 20 - pass-band ripple - 0.05 stop-band ripple see Figs 5 and 6 power inter-symbol interference (15% roll-off filter) note 1 - power inter-symbol interference (20% roll-off filter) note 1 - roll-off ISIpower MIN. UNIT % - dB -43 - dB -44 - dB Note 1. Definition of the power inter-symbol interference: ( N conv - 1 ) 2 2x C conv (4k) 2 k=1 ISI power ( dB ) = 10 log -------------------------------------------------------------------2 C conv (0) Where Nconv is the number of coefficients Cconv. Cconv(k) represent the coefficient resulting from the convolution of the transmission and reception filters (K indicates the Kth coefficient). The power ISI specified in Table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters and a truncated half-Nyquist filter with 57 T/4 taps for the 15% roll-off filter and 41 T/4 taps for the 20% roll-of filter (see "Application note AN96048" - Appendix B). 1996 Nov 19 36 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 11 LOCK DETECTOR CHARACTERISTICS SYMBOL SNRlock PARAMETER signal-to-noise ratio to lock the demodulator CONDITIONS MIN. TYP. MAX. UNIT 4-QAM 8 - - dB 16-QAM 15 - - dB 32-QAM 18 - - dB 64-QAM 21 - - dB 256-QAM 27 - - dB 12 CARRIER RECOVERY CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Carrier recovery detector CARRIER RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 A Kd detector constant SNR = 21 dB for 64-QAM constellation - 3ICAR - A/rad SNR = 27 dB for 256-QAM constellation - 6.05ICAR - A/rad 0.017rs - - MHz 10 - - kHz fCAR frequency range fn(inner) loop bandwidth of inner loop fn(outer) loop bandwidth of outer loop - - 0.3fn(inner) kHz Izero zero current of DAC -100 - +100 nA ICAR maximum DAC output current (programmable) 50 - 200 A fDAC DAC sampling rate - rs - MHz - A rs = 5 Msym/s CARRIER RECOVERY DAC OUTPUT CURRENTS DURING LOCK IoCARlock mean output current - 1 IoCARlock matching of output currents -2.5 - +2.5 % - ICAR - A -2.5 - +2.5 % 2ICAR CARRIER RECOVERY DAC OUTPUT CURRENTS DURING UNLOCK IoCARunlock mean output current IoCARunlock matching of output currents 1996 Nov 19 37 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 13 CLOCK RECOVERY CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Clock recovery detector CLOCK RECOVERY: BIAS CURRENT FOR DACS SET TO 37.5 A - 0.24ICLK - A/rad frequency range 100 - - ppm fn natural frequency - 400 - Hz ICLK(max) maximum DAC output current (programmable) 50 - 200 A fDAC DAC sample rate - rs - MHz Kd detector constant fCLK SNR = 21 dB for 64-QAM constellation; SNR = 27 dB for 256-QAM constellation CLOCK RECOVERY DAC output currents IoCLKlock mean output current - ICLK - A IoCLKlock matching of output currents -2.5 - +2.5 % 14 AGC CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT AGC detector AGC DETECTOR: BIAS CURRENT FOR DACS SET TO 37.5 A RAGC AGC range of detector 20 - - dB Izero zero current -100 - +100 nA IAGC(max) maximum DAC output current (programmable) 50 - 200 A fDAC DAC sample rate - rs - MHz in lock - 1 - A unlock - IAGC - A +5 % AGC DAC output currents IoAGC IoAGC 1996 Nov 19 mean output current -5 matching of output current 38 14IAGC Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Integrated loop amplifiers LOOP AMPLIFIERS GOL open loop gain - 60 - dB GB gain bandwidth product - 1 - MHz Vref reference voltage - 2.5 - V Vo output voltage 0.1VDDA - 0.9VDDA V RL(VSSD) load to ground 5 - - k RL(VDDD) load to supply 6.5 - - k closed - 5 - k open 10 - - M ANALOG SWITCHES ZSW switch impedance 16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS VDDD = VDDA = 5 V; VDDD(core) = 3.3 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Clock outputs: CLKADC and CLKSDV VOL LOW level output voltage 0 - 0.1VDDD V VOH HIGH level output voltage 0.9VDDD - VDDD V TCLK cycle time 35 - - ns tw pulse width 40 : 60 duty cycle 14 - - ns tr rise time CL = 30 pF - - 6 ns tf fall time CL = 30 pF - - 6 ns RL load resistance 1 - - k 100 - - mV 35 - - ns 14 - - ns - - 50 Clock input: CLK Vi(rms) input voltage level (RMS value) TCLK cycle time tw pulse width Rsource source resistance sine wave 40 : 60 duty cycle Digital inputs: DIN8 to DIN0 VIL LOW level input voltage - - 0.8 V VIH High level input voltage 2.0 - - V tSU set-up time 15 - - ns tHD hold time 0 - - ns CL load capacitance - - 10 pF 1996 Nov 19 39 Philips Semiconductors Product specification Multi-mode QAM demodulator SYMBOL PARAMETER TDA8046 CONDITIONS MIN. TYP. MAX. UNIT Digital outputs: DO1 to DO0 with respect to CLKOUT for semi-serial mode VOL LOW level output voltage 0 - 0.1VDDD V VOH HIGH level output voltage 0.9VDDD - VDDD V tod output delay time - - 7 ns toHD output hold time - - 10 ns CL load capacitance 2 - 30 pF additional Digital outputs: DO7 to DO0 with respect to CLKSDV for 8-bit parallel mode VOL LOW level output voltage 0 - 0.1VDDD V VOH HIGH level output voltage 0.9VDDD - VDDD V tod output delay time - - 22 ns toHD output hold time - - 22 ns CL load capacitance 2 - 30 pF - 0.1VDDD V additional Digital outputs: DO7 to DO0 with respect to CLKOUT for I/Q multiplexed mode VOL LOW level output voltage 0 VOH HIGH level output voltage 0.9VDDD - VDDD V tod output delay time - - 22 ns toHD output hold time - - 22 ns Vo output voltage level 0.1VDDA - 0.9VDDA Gv DC voltage gain (open loop) - 60 - dB GB gain bandwidth product 1 - - MHz RL load resistance 5 - - K Loop amplifier 1996 Nov 19 40 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 handbook, full pagewidth MBG989 no convergence BER measured 10-4 implementation loss theory SNR (dB) Fig.31 Definition of the Implementation Loss. tr handbook, full pagewidth tf 90% CLKADC VOH 90% 10% 10% VOL tw tCLK VIH DIN 0 to DIN 8 VIL tSU; DAT tHD; DAT MGG176 Fig.32 CMOS input data timing diagram. 1996 Nov 19 41 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 Tsym handbook, full pagewidth VOH CLKOUT VOL VOH DO1 to DO0 slot 0 slot 1 slot 2 slot 3 VOL toHD tod VOH CLKSDV MGG179 Fig.33 CMOS semi-serial mode timing diagram. Tsym handbook, full pagewidth VOH CLKSDV VOL VOH DATA OUTPUT VOL toHD tod MGG177 Fig.34 CMOS 8-bit symbol in parallel mode timing diagram 1996 Nov 19 42 VOL Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 Tsym handbook, full pagewidth VOH CLKOUT VOL VOH CLKSDV VOL toHD tod VOH DO7 to DO0 I Q VOL MGG178 Fig.35 CMOS I and Q multiplexed timing diagram. 1996 Nov 19 43 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 17 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-2 1996 Nov 19 EUROPEAN PROJECTION 44 o 7 0o Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 18 SOLDERING 18.3 18.1 Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 18.2 * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Reflow soldering Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. 18.4 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 1996 Nov 19 Wave soldering 45 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 19 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Nov 19 46 Philips Semiconductors Product specification Multi-mode QAM demodulator TDA8046 NOTES 1996 Nov 19 47 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp48 Date of release: 1996 Nov 19 Document order number: 9397 750 01499