DATA SH EET
Product specification
Supersededs data of 1996 Jul 23
File under Integrated Circuits, IC02
1996 Nov 19
INTEGRATED CIRCUITS
TDA8046
Multi-mode QAM demodulator
1996 Nov 19 2
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
CONTENTS
1 FEATURES
2 APPLICATION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Functional description of the individual blocks
7.1.1 Quadrature demodulator and half Nyquist filter
7.1.2 Equalizer
7.1.3 Lock detector
7.1.4 Carrier recovery
7.1.5 Clock recovery
7.1.6 AGC
7.1.7 Offset control
7.1.8 Loop amplifiers
7.1.9 Output formatter
7.1.10 Boundary scan
7.1.11 I2C-bus interface
7.1.12 I2C-bus write parameters
7.1.13 I2C-bus read parameters
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 DEMODULATOR AND HALF NYQUIST
FILTER CHARACTERISTICS
11 LOCK DETECTOR CHARACTERISTICS
12 CARRIER RECOVERY CHARACTERISTICS
13 CLOCK RECOVERY CHARACTERISTICS
14 AGC CHARACTERISTICS
15 INTEGRATED LOOP AMPLIFIERS
CHARACTERISTICS
16 CHARACTERISTICS OF DIGITAL INPUTS
AND OUTPUTS
17 PACKAGE OUTLINE
18 SOLDERING
18.1 Introduction
18.2 Reflow soldering
18.3 Wave soldering
18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
21 PURCHASE OF PHILIPS I2C COMPONENTS
1996 Nov 19 3
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
1 FEATURES
•Different modulation schemes: 4, 16, 32,
64 and 256-QAM
•Digital demodulator and square root raised cosine
Nyquist filter with roll-off of 15% or 20%
•High performance adaptive equalizer (no training
sequence needed)
•Digital detectors for generation of required control
voltages for carrier recovery, clock recovery and AGC
•Digital-to-analog converters and operational amplifiers
allowing high flexibility for selection of the (PLL) loop
time constants
•High maximum symbol rate (rs) of 7 Msymbols/s
•Input format: Straight binary or 2’s complement
(up to 9 bits, TTL compatible)
•Output format: 8-bit wide bus (CMOS compatible)
•I2C-bus interface to initialize and monitor the
demodulator. When no I2C-bus usage; 64-QAM,
20% roll-off factor in default mode
•5 V peripheral and analog supply voltage
•3.3 V core supply voltage
•Boundary scan test.
2 APPLICATION
Demodulation for digital cable TV and cable modem.
3 QUICK REFERENCE DATA
Notes
1. The supply currents are specified for the maximum symbol frequency.
2. The implementation loss (IL) of the demodulator is defined as the distance between the measured and theoretical
BER curve as function of signal-to-noise ratio at a BER = 10−6 for a back-to-back measurement at the IF frequency.
This performance depends on the chosen loop parameters (see
Application notes
).
4 ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDDD(core) core supply voltage 3.00 3.30 3.60 V
VDDD digital peripheral supply voltage 4.75 5.00 5.25 V
VDDA analog supply voltage 4.75 5.00 5.25 V
IDDD(core) core supply current VDDD(core) = 3.3 V; note 1 −100 −mA
IDDD digital peripheral supply current VDDD = 5 V; note 1 −14 −mA
IDDA analog supply current VDDA = 5 V; note 1 −16 −mA
rssymbol rate −−7 Msym/s
IL implementation loss note 2 −0.7 −dB
αNyquist roll-off (programmable) −15 or 20 −%
SNRlock signal-to-noise ratio for locking a
64-QAM constellation 21 −−dB
signal-to-noise ratio for locking a
256-QAM constellation 27 −−dB
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8046H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 ×20 ×2.8 mm SOT319-2
1996 Nov 19 4
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
5 BLOCK DIAGRAM
d
book, full pagewidth
1 to 5,
8 to 11
DIN0
to
DIN8
SQUARE ROOT
RAISED COSINE
DEMODULATOR
INPUT
REPRESEN-
TATION SQUARE ROOT
RAISED COSINE
COARSE
AGC
DAC Iref1
Vref
5453
CLOCK
RECOVERY
DAC Iref2
Vref
5857
NCO
CONTROL
DIGITAL
PHASE
ROTATOR OFFSET
OFFSET
CONTROL
BOUNDARY
SCAN TEST
FINE AGC
EQUALIZER
FINE AGC
CONTROL
OUTPUT
FORMATTER
20 to 23
27 to 30
18
DO7 to
DO0
CLKSDV
VCARREC
VCARTC
VCLKREC
VCLKTC
VAGC
60
VDDA
59
VSSA
VAGCTC IBIAS
CARRIER
RECOVERY
DAC Iref3
Vref
565552
BIAS
GENERATOR
Vref
Iref1
Iref2
Iref3
ANALOG SECTION
CLOCK GENERATOR
15
62
4rs2rs
rsto DACs
internal clock for
digital processing
CLKADC
CLK
A0 37
SCL 35
TMS
44
PRESET 49
CLKT 19
TDO
47
TDI
48
TRST
42
TCK
43
SDA 36
I2C-BUS
CONTROL
32 CLKOUT
6, 13, 16,
25, 33, 38,
45, 51, 63
TDA8046
MGG198
VDDD1 to 9
7, 12, 14, 17,
24, 26, 31, 34,
46, 50, 61, 64
VSSD1 to 12
41
TEST1
40
TEST2
39
TEST3
Fig.1 Block diagram.
1996 Nov 19 5
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
6 PINNING
SYMBOL PIN I/O DESCRIPTION
DIN0 1 I digital input bit 0 (LSB)
DIN1 2 I digital input bit 1
DIN2 3 I digital input bit 2
DIN3 4 I digital input bit 3
DIN4 5 I digital input bit 4
VDDD1 6 supply digital peripheral supply voltage 1 (+5 V)
VSSD1 7 supply digital ground 1; for input peripheral and core
DIN5 8 I digital input bit 5
DIN6 9 I digital input bit 6
DIN7 10 I digital input bit 7
DIN8 11 I digital input bit 8 (MSB)
VSSD2 12 supply digital ground 2; for core and clock buffers
VDDD2 13 supply digital supply voltage 2; for core and clock buffers (+3.3 V)
VSSD3 14 supply digital peripheral ground 3
CLKADC 15 O clock output to ADC (4 ×rs)
VDDD3 16 supply digital peripheral supply voltage 3 (+5 V)
VSSD4 17 supply digital ground 4; for core
CLKSDV 18 O clock symbol data valid output
CLKT 19 I for test purpose only
DO7 20 O parallel data output (bit 7)
DO6 21 O parallel data output (bit 6)
DO5 22 O parallel data output (bit 5)
DO4 23 O parallel data output (bit 4)
VSSD5 24 supply digital peripheral ground 5
VDDD4 25 supply digital peripheral supply voltage 4 (+5 V)
VSSD6 26 supply digital ground 6; for core
DO3 27 O parallel data output (bit 3)
DO2 28 O parallel data output (bit 2)
DO1 29 O parallel data output (bit 1)
DO0 30 O parallel data output (bit 0)
VSSD7 31 supply digital peripheral ground 7
CLKOUT 32 I output formatter clock output
VDDD5 33 supply digital peripheral supply voltage 5 (+5 V)
VSSD8 34 supply digital peripheral ground 8
SCL 35 I serial clock input (I2C-bus)
SDA 36 I/O serial data input/output (I2C-bus)
A0 37 I hardware address input (I2C-bus)
VDDD6 38 supply digital peripheral supply voltage 6 (+5 V)
TEST3 39 I test input 3 (normally connected to ground)
TEST2 40 I test input 2 (normally connected to ground)
1996 Nov 19 6
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
TEST1 41 I test input 1 input (normally connected to ground)
TRST 42 I optional asynchronous reset input
TCK 43 I dedicated test clock input
TMS 44 I input control signal
VDDD7 45 supply digital supply voltage 7; for core (+3.3 V)
VSSD9 46 supply digital ground 9; for core
TDO 47 O serial test data output
TDI 48 I serial test data input
PRESET 49 I set device into default mode input
VSSD10 50 supply digital ground 10; for the digital section of the analog block
VDDD8 51 supply digital supply voltage 8; for the digital section of the analog block (+5 V)
IBIAS 52 I input bias current for DACs
VAGCTC 53 O inverted operational amplifier input voltage for loop filtering
VAGC 54 O analog output voltage for AGC
VCARTC 55 O inverted operational amplifier input voltage for carrier recovery loop
filtering
VCARREC 56 O analog output voltage for carrier recovery
VCLKTC 57 O inverted operational amplifier input voltage for clock recovery loop
filtering
VCLKREC 58 O analog output voltage for clock recovery
VSSA 59 supply analog ground
VDDA 60 supply analog supply voltage (+5 V)
VSSD11 61 supply digital ground 11; for clock
CLK 62 I clock input (4 ×rs)
VDDD9 63 supply digital supply voltage 9; for clock
VSSD12 64 supply digital peripheral ground 12
SYMBOL PIN I/O DESCRIPTION
1996 Nov 19 7
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
handbook, full pagewidth
TDA8046
MGG197
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
TDI
TDO
VSSD9
VDDD7
TMS
TCK
TRST
TEST1
TEST2
TEST3
VDDD6
A0
SDA
SCL
VSSD8
VDDD5
DIN0
DIN1
DIN2
DIN3
DIN4
VDDD1
VSSD1
DIN5
DIN6
DIN7
DIN8
VSSD2
VDDD2
VSSD3
CLKADC
VDDD3
VSSD12
VDDD9
CLK
VSSD11
VDDA
VSSA
VCLKREC
VCLKTC
VCARREC
VCARTC
VAGC
VAGCTC
IBIAS
VDDD8
VSSD10
PRESET
VSSD4
CLKSDV
CLKT
DO7
DO6
DO5
DO4
VSSD5
VDDD4
VSSD6
DO3
DO2
DO1
DO0
VSSD7
CLKOUT
Fig.2 Pin configuration.
1996 Nov 19 8
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7 FUNCTIONAL DESCRIPTION
Figure 3 shows the application of the TDA8046
multi-mode QAM demodulator. The frequency of the IF
signal (IFQAM) is down converted to a frequency that
equals the symbol rate (rs) by a mixer which is driven from
a local oscillator with a frequency of fCAR =f
IF +r
s
.
After low pass filtering this baseband signal is applied to an
external 8 or 9-bit ADC.
For 256-QAM, a 9-bit ADC is preferred, for the other
modes an 8-bit ADC is sufficient.
The multi-mode QAM demodulator has digital detectors for
AGC, carrier recovery and clock recovery. The on-chip
DACs translate the detector values to analog control
currents which are then integrated by a loop filter.
To perform this loop filtering, an operational amplifier is
integrated after each DAC.
The carrier recovery consists of a two-loop system.
The outer loop is shown in Fig.3, and controls both phase
and frequency at a low speed. The inner loop controls the
carrier phase at a high speed (wide loop bandwidth).
The AGC also consists of two loops; the outer loop is the
coarse AGC and one inner loop is the fine AGC.
The recovered symbols are converted into bits according
to a demapping scheme and represented at the output in
an 8-bit parallel output format. The QAM demodulator can
be initialized and monitored by the I2C-bus interface.
Fig.3 Application with multi-mode QAM demodulator.
handbook, full pagewidth
MGG167
LPF ADC
fCAR = fIF + rs
clock recovery
carrier recovery
AGC DO7 to DO0
CLKOUT
CLKSDV
8 or 9 bits
IFQAM
SAWTUNER
RF
signal
fclk
TDA8046
I2C-BUS
1996 Nov 19 9
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1 Functional description of the individual blocks
The functional block diagram of the multi-mode QAM
demodulator is illustrated in Fig.1. This section describes
the individual blocks in the demodulator. After adaptation
for the used input format (2’s complement or binary), the
input signal is demodulated in the I and Q baseband
signals which are applied to the inputs of the half-Nyquist
filter (equals square root raised cosine). To avoid
overloading of the ADC, an AGC detector is placed after
the adaptation for the input format. The control value for
the clock recovery is generated after half Nyquist filtering.
The echoes created in the cable network are reduced
significantly in the equalizer.
The equalizer produces a ‘clean’ constellation diagram
from which the information for the carrier recovery is
derived. This constellation is also applied to the output
formatter which demaps the transmitted symbols in
corresponding bits. The carrier recovery and lock
detection functions are based on the equalizer output.
The output of the equalizer is applied to an output
formatter, which translates the symbol bits to a FEC input
format. The digital outputs of the clock recovery, AGC, and
carrier recovery section are converted into currents which
are integrated by the loop filters.
To make these loop filters active, operational amplifiers
are integrated on the chip.
The TDA8046 can handle five different digital modulation
schemes; 4, 16, 32, 64 and 256-QAM. These schemes
are selectable via the I2C-bus interface.
7.1.1 QUADRATURE DEMODULATOR AND HALF NYQUIST
FILTER
Quadrature demodulation is accomplished after selection
of the appropriate input format via the I2C-bus.
The in-phase and quadrature components are both
applied to a half Nyquist filter. In default mode, this filter
gives a 20% roll-off half Nyquist shaping. The basic
schematic of the quadrature demodulator followed by the
half Nyquist filter is shown in Fig.4. The signs of the
multiplication factors in the Q-branch can be inverted
(I2C-bus bit INVD).
When using an 8-bit ADC the LSB of the 9-bit input word
should be connected to the positive supply (VDDD).
This ensures a symmetrical 2’s complement
representation which can be multiplied by −1 in a correct
(2’s complement) way. The overall transfer function of the
square root raised cosine filters is shown in Figs 5 and 6.
For characteristics see Chapter 10.
Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter.
handbook, full pagewidth
HALF NYQUIST
FILTER
HALF NYQUIST
FILTER
+1, 0, −1, 0
0, −1, 0, +1
9
9
DIN8
to
DIN0
BINARY OR
TWO's
COMPLEMENT
I
I2C-BUS
I2C-BUS
Q
MGG168
9
I2C-BUS
I2C-BUS
1996 Nov 19 10
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.5 Half Nyquist receiver filter transfer function (20% roll-off).
handbook, full pagewidth
2
5
0
relative
gain
(dB)
010.25 0.5 0.75 1.751.51.25
MBG987
−5
−15
−25
−35
−45
−55
relative frequency ( f )
rs
Fig.6 Half Nyquist receiver filter transfer function (15% roll-off).
handbook, full pagewidth
2
0
0 0.5 1 1.50.25 0.75 1.25 1.75
relative
gain
(dB)
−10
−20
−30
−40
−50
MGG169
relative frequency ( f )
rs
1996 Nov 19 11
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.2 EQUALIZER
This function is realized with a T spaced 12 or 14 taps
(selected via the I2C-bus) adaptive filter with a feedback
part. The equaliser is based on a Decision Feedback
Equalizer (DFE) structure with Least Mean Square (LMS)
coefficient updating algorithm. No training sequence is
required. The block schematic of the total equalizer is
shown in Fig.8. The main tap of the equalizer is adjustable
for fine AGC function (6 dB AGC range). The settings of
the equalizer taps can be read via the I2C-bus. If the
equalizer diverges, an alarm bit is set (I2C-bus bit ALEQ)
and an automatic reset of the taps can be performed
(I2C-bus bit EAR).
To improve acquisition time, the convergence steps of the
FFE/DFE parts of the equalizer are programmable via the
I2C-bus. When the system locks, the steps are
automatically modified for optimum performances.
Besides reading the equalizer tap values, the main tap of
the equalizer can also be programmed. After setting the
main tap, the other coefficients can be set to zero.
The equalizer settings can also be frozen via the I2C-bus.
The equalizer has been proven to work correctly under bad
channel conditions as indicated in Table 1. It is guaranteed
that all loops (including equalizer) converge at a SNR of
21 dB for a 64-QAM modulation format and 27 dB for a
256-QAM modulation format.
Table 1 Channel echo profile
Figure 7 represents the QAM spectrum seen by the
equalizer. It corresponds (in the frequency domain) to the
multiplication of a full nyquist spectrum by the impulse
response of the channel specified in Table 1.
DELAY AMPLITUDE PHASE
3⁄8×Tsym 0.08 130°
11⁄8×Tsym 0.20 60°
2×Tsym 0.05 310°
45⁄8×Tsym 0.10 200°
67⁄8×Tsym 0.03 200°
Fig.7 QAM spectrum with echo profile as seen by the equalizer.
handbook, full pagewidth
1
−11
−0.5 0.5
relative frequency
relative
gain
(dB)
−0.375 0.375−0.125 0.125−0.25 0.250
−3
−5
−9
−1
−7
MGD636
( f )
rs
1996 Nov 19 12
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.8 DFE equalizer structure.
handbook, full pagewidth
MGG170
FEED
FORWARD
EQUALIZER
TAPS CALCULATION
DECISION
FEEDBACK
EQUALIZER
TAPS CALCULATION
input
output
decision
+
−
7.1.3 LOCK DETECTOR
The lock detector indicates whether all algorithms in the
demodulator are converged or not. For a symbol error rate
(at the input of the demodulator) smaller than 2 ×10−2, the
detector will give the indication ‘LOCK’ (I2C-bus bit
LK = 1). For larger symbol error rates, the detector will
generate the ‘UNLOCK’ signal (I2C-bus bit LK = 0).
It should ne noted that this ‘UNLOCK’ signal is generated
before any other part of the demodulator loses lock.
The lock detector is part of the carrier recovery loop, see
Fig.9. The Lock Detector Threshold (LDT) can be changed
with the help of the I2C-bus. The estimation algorithm used
in the lock detector also provides information about the
SER ratio which can be read out via the I2C-bus interface.
For characteristics see Chapter 11.
7.1.4 CARRIER RECOVERY
The carrier recovery detector consists of a
Phase-Frequency Detector (PFD) and Phase Detector
(PD). Depending on the mode of operation, the carrier
recovery is switched either between the phase frequency
(no lock) or the phase detector (lock). The carrier recovery
consists of the following two loops:
1. The outer loop; this loop controls the phase and
frequency of the incoming QAM signal at the IF
frequency in such a way that the constellation is
optimally positioned for detection.
2. The inner loop; the bandwidth of this loop can be large
and can therefore reduce the influence of large
bandwidth phase noise.
A fully digital carrier recovery function is also possible and
can be selected via the I2C-bus. Should this configuration
be used, then the external components of the loop filter will
not have to be implemented.
Four different maximum DAC output currents can be
selected via the I2C-bus. The output currents of the DAC
are defined in such a way that a VCO with a behaviour as
shown in Fig.9 can be connected directly to the output of
the integrated operational amplifier. Should the VCO slope
be negative then the sign of the current can be inverted by
the I2C-bus. Figure 10 defines the DAC output currents.
For characteristics see Chapter 12.
1996 Nov 19 13
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.9 Schematic diagram of the carrier recovery.
handbook, full pagewidth
MGG171
DEMODULATION
AND
FILTERING EQUALIZER PHASE
FREQUENCY
DETECTOR
PHASE
DETECTOR
LOCK
0
DAC
rsIref1
ICAR
Vref lock
external
DIGITAL
INNER LOOP
ADC
LPF
VCO
IFQAM
I2C-BUS
I2C-BUS
I2C-BUS
I2C-BUS
lock I2C-BUS
1996 Nov 19 14
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.10 Definition of the DAC currents and the expected frequency behaviour of the VCO.
Ipos = positive output current.
Ineg = negative output current.
IOIpos Ineg
–()
2
-------------------------------
=
∆IOIpos Ineg
+()
I
pos Ineg
–()
--------------------------------- 100×=
handbook, full pagewidth
DAC output
current
ICAR
digital input
−ICAR
1/2 ICAR
−1/2 ICAR
CARI = 1 CARI = 0
fVCO
VCARREC
MGG180
1996 Nov 19 15
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.5 CLOCK RECOVERY
The clock recovery function uses the unequalized I and Q
signals, i.e. the half Nyquist filter outputs (see Fig.4).
The clock recovery section generates a control value each
symbol period. As this algorithm is based on the energy
maximization, both main and mid symbols are required at
the input. Consequently, the input data rate is twice the
symbol rate. The schematic diagram of this detector is
illustrated in Fig.11.
The clock generator generates the required internal clocks
from the VCXO clock signal at 4 ×rs. The input stage
amplifier of this generator enables the designer to supply
a low amplitude oscillator signal to the TDA8046. The DAC
output current range (ICLK) can be varied via the I2C-bus.
The sign of the output current can also be inverted to
adjust for the correct sign of the VCXO slope.
For characteristics see Chapter 13.
Fig.11 Schematic diagram of the clock recovery.
handbook, full pagewidth
DAC
rsIref3
ICLK
Vref
external
CLOCK
RECOVERY
DETECTOR
I
Q
to
VCXO
from
VCXO
4rs
2rs
rs
MGG172
2
4
1996 Nov 19 16
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.12 The definition of the DAC currents and the expected frequency behaviour of the VCXO for clock recovery.
Ipos = positive output current; ICLK.
Ineg = negative output current; −ICLK.
IoCLK Ipos Ineg
–()
2
-------------------------------
=
∆IoCLK Ipos Ineg
+()
I
pos Ineg
–()
--------------------------------- 100×=
handbook, full pagewidth
DAC output
current
ICLK
digital input
−ICLK
CLKI = 1 CLKI = 0
fVCXO
VCLKREC
MGG181
1/2 ICLK
−1/2 ICLK
1996 Nov 19 17
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.6 AGC
The AGC estimates the mean power based on the digital
input signal and relates this to a peak value for a given
constellation. To avoid overloading of the ADC, this
estimation of the peak signals is used to control the AGC
loop. The implemented AGC covers a range of ±20 dB in
gain variance. A schematic diagram of the AGC is
illustrated in Fig.13.
If the SAW filter does not have sufficient adjacent channel
attenuation, the AGC threshold can be varied to avoid
clipping of the ADC. To do this, the threshold is made
programmable via the I2C-bus (byte ATH). Table 2 shows
that for each mode, a new ATH value (on address 08)
must be set with the help of the I2C-bus.
The I2C-bus data on address 08 is a factor 16 smaller than
the used AGC threshold ATH.
The DAC output current range can be varied via the
I2C-bus interface (bits AGCA and AGCB) and the sign of
the current can be inverted (bit AGCI). The definition of the
DAC currents and the expected frequency behaviour of
the AGC is illustrated in Fig.14.
For characteristics see Chapter 14.
Table 2 AGC threshold values
MODE ATH (AGC THRESHOLD) I2C-BUS DATA FOR ADDRESS 08
256, 64, 16 and 4-QAM 2040 7F
32-QAM 1442 5A
Fig.13 AGC schematic diagram.
handbook, full pagewidth
DAC
rs
IBIAS
Iref2
Iref2
IAGC
Vref
external
AGC
DETECTOR
BIAS
GENERATOR
to AGC
amplifier
MGG173
ADC
I2C-BUS
I2C-BUS
I2C-BUS
DIN8
to
DIN0
1996 Nov 19 18
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.14 Definition of the DAC currents and the expected frequency behaviour of the AGC.
Ipos = positive output current; ICLK.
Ineg = negative output current; −ICLK.
IoAGC Ipos Ineg
–()
2
-------------------------------
=
∆IoAGC Ipos Ineg
+()
I
pos Ineg
–()
--------------------------------- 100×=
handbook, full pagewidth
DAC output
current
IAGC
digital input
−IAGC
AGCI = 1 AGCI = 0
gain
VAGC
MGG182
1/14 IAGC
−1/14 IACG
1996 Nov 19 19
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.7 OFFSET CONTROL
To compensate offsets in the I and Q branch, due to
spurious signals at the symbol frequency at the ADC input,
an offset compensation loop is included. This loop forces
the constellation to be symmetrically distributed over its
four quadrants. This function can be switched off by
I2C-bus bit OFFS.
7.1.8 LOOP AMPLIFIERS
Analog switches are integrated to discharge the loop filter
capacitors or for test purposes on application boards (a
reference voltage equal to the half of the positive supply
voltage VDDA is available at the output of the amplifier
when the switches are closed). The I2C-bus bit ANAS
controls the three switches simultaneously. A schematic
diagram of the loop amplifier and analog switch is
illustrated in Fig.15.
For characteristics see Chapter 15.
Fig.15 Loop amplifier and analog switch.
h
andbook, halfpage
DAC
Vref
external
MGG174
I
2
C-BUS
7.1.9 OUTPUT FORMATTER
The output formatter transforms the detected symbols into
bits in accordance with the selected mapping. The
TDA8046 has four possible mapping formats which can be
selected via the I2C-bus interface. The demapping
procedure and the corresponding bits are defined in
Fig.16. After demapping the bits are allocated to the
output. This output allocation corresponds to one of the
selected demapping schemes.
By using the I2C-bus, it is possible to obtain the following
output formats:
•8 bits parallel
•semi-serial
•I and Q 8 bits multiplexed.
The implemented demapping formats and output bit
allocation are illustrated in Figs 17 to 30.
7.1.10 BOUNDARY SCAN
The TDA8046H offers the possibility of boundary scan
test. The IEEE Standard Test Access Port and Boundary
Scan Architecture allows board manufacturers to test
board interconnections by using the boundary scan
functions.
Complete information on boundary scan test is available in
“Application note AN96048”
.
1996 Nov 19 20
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.16 Schematic diagram of the output formatter.
handbook, full pagewidth
MGG175
8
DO1 to DO0
CLKSCV
CLKOUT
DO7 to DO0
CLKSCV
DO7 to DO0
CLKSCV
CLKOUT
I
8
Q
DEMAPPING
SCHEMES
1 to 4
MUX
PARALLEL
AND
SEMI-SERIAL
I2C-BUS
7.1.10.1 Demapping scheme 1; differential decoding
Fig.17 Demapping scheme 1; bit allocation: 256-QAM.
Bit allocation for 256-QAM: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
handbook, full pagewidth
MGG193
010110011110001110000110
010111011111001111000111
010101011101001101000101
010100011100001100000100
100110101110111110110110
100111101111111111110111
100101101101111101110101
100100101100111100110100
I
QA quadrant b5 b4 b3 b2 b1 b0
010000011000001000000000
010001011001001001000001
010011011011001011000011
010010011010001010000010
100000101000111000110000
100001101001111001110001
100011101011111011110011
100010101010111010110010
1996 Nov 19 21
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 64-QAM: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see Table 3).
Fig.18 Demapping scheme 1; bit allocation: 4-QAM and 64-QAM.
handbook, full pagewidth
MGG183
0 0 0 00 0 0 10 0 1 10 0 1 0
0 1 0 00 1 0 10 1 1 10 1 1 0
1 1 0 01 1 0 11 1 1 11 1 1 0
1 0 0 01 0 0 11 0 1 11 0 1 0
1 0 0 01 1 0 00 1 0 00 0 0 0
1 0 0 11 1 0 10 1 0 10 0 0 1
1 0 1 11 1 1 10 1 1 10 0 1 1
1 0 1 01 1 1 00 1 1 00 0 1 0
I
QA quadrant b5 b4 b3 b2
B quadrant
D quadrantC quadrant
0 0 1 00 1 1 01 1 1 01 0 1 0
0 0 1 10 1 1 11 1 1 11 0 1 1
0 0 0 10 1 0 11 1 0 11 0 0 1
0 0 0 00 1 0 01 1 0 01 0 0 0
1 0 1 01 0 1 11 0 0 11 0 0 0
1 1 1 01 1 1 11 1 0 11 1 0 0
0 1 1 00 1 1 10 1 0 10 1 0 0
0 0 1 00 0 1 10 0 0 10 0 0 0
Fig.19 Demapping scheme 1; bit allocation: 16-QAM and 32-QAM.
Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 32-QAM: not implemented.
handbook, full pagewidth
MGG184
0 00 1
1 01 1
1 00 0
1 10 1
I
QA quadrant b5 b4
B quadrant
D quadrantC quadrant
0 11 1
0 01 0
1 11 0
0 10 0
1996 Nov 19 22
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.10.2 Demapping scheme 2; direct translation
Fig.20 Demapping scheme 2; bit allocation: 256-QAM.
Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.
handbook, full pagewidth
MGG195
I
Qb6b7 b5 b4 b3
b2
b1
b0
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1996 Nov 19 23
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.21 Demapping scheme 2; bit allocation: 64-QAM and 32-QAM.
Bit allocation for 64-QAM: b7, b6, b5, b3, b2, b1; b4 = b0 = 0.
Bit allocation for 32-QAM: not implemented.
handbook, full pagewidth
MGG185
0 1 10 1 00 0 10 0 0 1 1 11 1 01 0 11 0 0
I
Qb7 b6 b5 b3
b2
b1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
Fig.22 Demapping scheme 2; bit allocation: 4-QAM and 16-QAM.
a. Bit allocation for 4-QAM: b7 and b3; b6 = b5 = b4 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b3 and b2; b5 = b4 = b1 = b0 = 0.
handbook, full pagewidth
MGG186
0 10 0 1 11 0
I
Qb7 b6
b3
b2
1 0
1 1
0 0
0 1
0 1 1
0
I
Qb7 b3
1996 Nov 19 24
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.10.3 Demapping scheme 3; differential decoding: Draft prETS 429: 1994
Fig.23 Demapping scheme 3; bit allocation: 256-QAM.
Bit allocation for 256-QAM: b5, b4, b3, b2, b1, b0; b7 and b6 differentially decoded (see Table 3).
h
andbook, full pagewidth
MGG194
101100101101101001101000
101110101111101011101010
100110100111100011100010
100100100101100001100000
111000111001111101111100
111010111011111111111110
110010110011110111110110
110000110001110101110100
I
QA quadrant b5 b4 b3 b2 b1 b0
000100000101000001000000
000110000111000011000010
001110001111001011001010
001100001101001001001000
010000010001010101010100
010010010011010111010110
011010011011011111011110
011000011001011101011100
1996 Nov 19 25
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.24 Demapping scheme 3; bit allocation: 4-QAM and 64-QAM.
Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
Bit allocation for 64-QAM: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
handbook, full pagewidth
MGG187
0 0 0 00 0 1 01 0 1 01 0 0 0
0 0 0 10 0 1 11 0 1 11 0 0 1
0 1 0 10 1 1 11 1 1 11 1 0 1
0 1 0 00 1 1 01 1 1 01 1 0 0
0 1 0 00 1 0 10 0 0 10 0 0 0
0 1 1 00 1 1 10 0 1 10 0 1 0
1 1 1 01 1 1 11 0 1 11 0 1 0
1 1 0 01 1 0 11 0 0 11 0 0 0
I
QA quadrant b5 b4 b3 b2
B quadrant
D quadrantC quadrant
1 0 0 01 0 0 11 1 0 11 1 0 0
1 0 1 01 0 1 11 1 1 11 1 1 0
0 0 1 00 0 1 10 1 1 10 1 1 0
0 0 0 00 0 0 10 1 0 10 1 0 0
1 1 0 01 1 1 00 1 1 00 1 0 0
1 1 0 11 1 1 10 1 1 10 1 0 1
1 0 0 11 0 1 10 0 1 10 0 0 1
1 0 0 01 0 1 00 0 1 00 0 0 0
Fig.25 Demapping scheme 3; bit allocation: 16-QAM.
Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
handbook, full pagewidth
MGG188
0 01 0
0 11 1
0 10 0
1 11 0
I
QA quadrant b5 b4
B quadrant
D quadrantC quadrant
1 01 1
0 00 1
1 10 1
1 00 0
1996 Nov 19 26
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.26 Demapping scheme 3; bit allocation: 32-QAM.
Bit allocation for 32-QAM: b5, b4 and b3; b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).
handbook, full pagewidth
MGG189
0 0 01 0 01 1 0
0 0 1 1 0 10 1 0
0 1 11 1 1
0 1 10 0 10 0 0
1 1 11 0 11 0 0
0 1 01 1 0
I
QA quadrant
b5 b4 b3
B quadrant
D quadrantC quadrant
1 1 00 1 0
1 0 01 0 11 1 1
0 0 00 0 10 1 1
1 1 10 1 1
0 1 01 0 10 0 1
1 1 01 0 00 0 0
7.1.10.4 Demapping scheme 4; direct translation: HP8782B/K03
Fig.27 Demapping scheme 4; bit allocation: 256-QAM.
Bit allocation for 256-QAM: b7, b6, b5, b4, b3, b2, b1, b0.
handbook, full pagewidth
MGG196
I
Qb2b3 b1 b0 b4
b5
b6
b7
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1996 Nov 19 27
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.28 Demapping scheme 4; bit allocation: 64-QAM.
Bit allocation for 64-QAM: b7, b6, b5, b4, b3 and b2; b1 = b0 = 0.
handbook, full pagewidth
MGG190
1 0 01 0 11 1 01 1 1 0 0 00 0 10 1 00 1 1
I
Qb2 b3 b4 b5
b6
b7
0 1 1
0 1 0
0 0 1
0 0 0
1 1 1
1 1 0
1 0 1
1 0 0
Fig.29 Demapping scheme 4; bit allocation: 32-QAM.
Bit allocation for 32-QAM: b7, b6, b5, b4 and b3; b2 = b1 = b0 = 0.
handbook, full pagewidth
MGG191
0 1 0 0 00 1 1 0 00 1 0 1 0
0 1 0 0 10 1 1 0 10 1 1 1 0
0 1 0 1 10 1 1 1 1
0 0 0 1 10 0 0 0 10 0 0 0 0
0 0 1 1 10 0 1 0 10 0 1 0 0
0 0 1 1 00 0 0 1 0
I
QA quadrant b7 b6 b5 b4 b3
B quadrant
D quadrantC quadrant
1 1 0 1 01 1 1 1 0
1 1 1 0 01 1 1 0 11 1 1 1 1
1 1 0 0 01 1 0 0 11 1 0 1 1
1 0 1 1 11 0 0 1 1
1 0 1 1 01 0 1 0 11 0 0 0 1
1 0 0 1 01 0 1 0 01 0 0 0 0
1996 Nov 19 28
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Table 3 Definition of two MSB’s in modulation schemes 1 and 3
Tables 4 and 5 give the output format of the data for semi-serial mode operations.
QUADRANT OF
CURRENTLY
RECEIVED SYMBOL
QUADRANT OF
PREVIOUSLY
RECEIVED SYMBOL
PHASE
CHANGE
(DEGREES)
CURRENT OUTPUT BITS
SCHEME 1 SCHEME 3
b7 b6 b7 b6
A A 0 0000
A B 270 1001
A C 180 1111
A D 90 0110
B A 90 0110
B B 0 0000
B C 270 1001
B D 180 1111
C A 180 1111
C B 90 0110
C C 0 0000
C D 270 1001
D A 270 1001
D B 180 1111
D C 90 0110
D D 0 0000
Fig.30 Demapping scheme 4; bit allocation: 4-QAM and 16-QAM.
a. Bit allocation for 4-QAM: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0. b. Bit allocation for 16-QAM: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0.
handbook, full pagewidth
MGG192
1 01 1 0 00 1
I
Qb4 b5
b6
b7
0 1
0 0
1 1
1 0
1 0 0
1
I
Qb6 b7
1996 Nov 19 29
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Table 4 Semi-serial format 256, 64 and 32-QAM; see note 1
Note
1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.
Table 5 Semi-serial format 16-QAM and 4-QAM; see note 1
Note
1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.
SLOT 256-QAM 64-QAM 32-QAM
DO1 DO0 CLKSDV DO1 DO0 CLKSDV DO1 DO0 CLKSDV
0S
n-1(7) Sn-1(6) 1 Sn-1(5) Sn-1(4) 1 Sn-1(4) Sn-1(3) 1
1S
n-1(5) Sn-1(4) 1 Sn-1(3) Sn-1(2) 1 Sn-1(2) Sn-1(1) 1
2S
n-1(3) Sn-1(2) 1 Sn-1(1) Sn-1(0) 1 X X 0
3S
n-1(1) Sn-1(0) 1 X X 0 X X 0
4S
n
(7) Sn(6) 1 Sn(5) Sn(4) 1 Sn-1(0) Sn(4) 1
5S
n
(5) Sn(4) 1 Sn(3) Sn(2)1S
n
(3) Sn(2) 1
6S
n
(3) Sn(2) 1 Sn(1) Sn(0)1S
n
(1) Sn(0) 1
7S
n
(1) Sn(0) 1 X X 0 X X 0
SLOT 16-QAM 4-QAM
DO1 DO0 CLKSDV DO1 DO0 CLKSDV
0S
n-1(3) Sn-1(2) 1 Sn-1(1) Sn-1(0) 1
1S
n-1(1) Sn-1(0) 1 X X 0
2XX 0 XX 0
3XX 0 XX 0
4S
n
(3) Sn(2) 1 Sn(1) Sn(0) 1
5S
n
(1) Sn(0) 1 X X 0
6XX 0 XX 0
7XX 0 XX 0
1996 Nov 19 30
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.11 I2C-BUS INTERFACE
The TDA8046 is controlled by an I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for
selecting READ or WRITE mode. It should be noted that the TDA8046 starts up in accordance with to the settings defined
in Tables 7, 8 and 9.
Table 6 Slave address
Table 7 WRITE (R/W=0)
A6 A5 A4 A3 A2 A1 A0 R/W
000111A0X
FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0
DAC current
inversion/general 00 AGCI CLKI CARI OUTE DEM NYQ DPHR RST
Demodulator 01 INP RLF OUTB OUTA INVD CONC CONB CONA
DAC/OFFS/switch 02 ANAS OFFS AGCB AGCA CLKB CLKA CARB CARA
Digital test/output
formatter 03 −−− −OUTF TSEL2 TSEL1 TSEL0
Digital loop filter
B.W. 04 DCA7 DCA6 DCA5 DCA4 DCA3 DCA2 DCA1 DCA0
Digital loop filter
B.W. 05 FSOL −−−−DCB2 DCB1 DCB0
Lock detector
threshold 06 LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0
Lock detector
window size 07 −−− −− −WS1 WS0
AGC detector
threshold 08 ATH7 ATH6 ATH5 ATH4 ATH3 ATH2 ATH1 ATH0
Equalizer mode 09 −−EAR FFEL EDFE EFFE EFC PRESET
Equalizer tap FFEI 0A FFEI07 FFEI06 FFEI05 FFEI04 FFEI03 FFEI02 FFEI01 FFEI00
Equalizer steps 0B −FSTP2 FSTP1 FSTP0 −DSTP2 DSTP1 DSTP0
1996 Nov 19 31
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Table 8 Default settings after reset
Table 9 READ (R/W=1)
FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0
DAC current inversion/
general 0001011100
Demodulator 01 1 1 0 0 0 0 1 1
DAC/OFFS/switch 02 0 1 0 1 0 1 0 1
Digital test/output
formatter 03 −−−−0000
Digital loop filter B.W. 04 0 1 0 0 0 0 0 0
Digital loop filter B.W. 05 1 −−−−100
Lock detector
threshold 0600011000
Lock detector window
size 07 −−−−−−00
AGC detector
threshold 0801111111
Equalizer mode 09 −−010000
Equalizer tap FFEI 0A 0 1 0 0 0 0 0 0
Equalizer steps 0B −000−000
FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0
VCARREC (4 bits) 00 −−−−CR03 CR02 CR01 CR00
VCLKREC (4 bits) 01 −−−−CL03 CL02 CL01 CL00
VAGC (4 bits) 02 −−−−AG03 AG02 AG01 AG00
Alarm equalizer/
lock detector 03 −−−ALEQ −−−LK
SER estimation 04 LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0
FFEI3 05 b7 b6 b5 b4 b3 b2 b1 b0
.... ... b7 b6 b5 b4 b3 b2 b1 b0
FFEI0 08 b7 b6 b5 b4 b3 b2 b1 b0
DFEI1 09 b7 b6 b5 b4 b3 b2 b1 b0
.... ... b7 b6 b5 b4 b3 b2 b1 b0
DFEI7 0F b7 b6 b5 b4 b3 b2 b1 b0
DFEI8 10 b7 b6 b5 b4 b3 b2 b1 b0
FFEQ3 11 b7 b6 b5 b4 b3 b2 b1 b0
.... ... b7 b6 b5 b4 b3 b2 b1 b0
FFEQ0 14 b7 b6 b5 b4 b3 b2 b1 b0
DFEQ1 15 b7 b6 b5 b4 b3 b2 b1 b0
.... ... b7 b6 b5 b4 b3 b2 b1 b0
DFEQ8 1C b7 b6 b5 b4 b3 b2 b1 b0
FFEI5 1D b7 b6 b5 b4 b3 b2 b1 b0
FFEQ5 1E b7 b6 b5 b4 b3 b2 b1 b0
1996 Nov 19 32
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.12 I2C-BUS WRITE PARAMETERS
Table 10 I2C-bus write parameters; 1-bit values
FFEI4 1F b7 b6 b5 b4 b3 b2 b1 b0
FFEQ4 20 b7 b6 b5 b4 b3 b2 b1 b0
IF_frequency_shift 21 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
IF_frequency_shift 22 −−−−FS11 FS10 FS9 FS8
PARAMETER BIT VALUE DESCRIPTION
Input format INP 0 2’s complement
1 straight binary
Inversion demodulator INVD 0 Q-branch = 0 −1, 0, +1
1 Q-branch = 0 + 1, 0, −1
Demodulator DEM 0 by-pass mode
1 normal mode
Half Nyquist filter NYQ 0 filter in by-pass mode
1 half Nyquist filter on
Roll-off factor RLF 0 15% roll-off
1 20% roll-off
Digital phase rotator DPHR 0 off: pass through mode
1on
General reset RST 0 normal operation
1 reset (with automatic return to normal operation)
Offset OFFS 0 off
1on
Outer loop activation
(carrier recovery) OUTE 0 outer loop inactive
1 outer loop active
Analog switches ANAS 0 open
1 closed
1st and 2nd-order loop
(inner loop) FSOL 0 1st-order loop
1 2nd-order loop
DAC current inversion CARI 0 no inversion
1 inversion
CLKI 0 no inversion
1 inversion
AGCI 0 no inversion
1 inversion
FUNCTION ADD D7 D6 D5 D4 D3 D2 D1 D0
1996 Nov 19 33
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Table 11 I2C write parameters; 2-bit values
Equalizer PRESET 0 normal operation
1 coefficient to zero (main tap to 1)
EDFE 0 normal operation
1 freeze coefficients of DFE part
EFFE 0 normal operation
1 freeze coefficients of FFE part
EFC
[fine AGC (equalizer
freeze centre tap)]
0 normal operation
1 freeze centre tap, no fine AGC
EAR 0 automatic reset switched OFF
1 automatic reset switched ON
FFEL 0 5 taps in FFE part
1 3 taps in FFE part
PARAMETER BITS DESCRIPTION
Window size (lock detector) WS1 WS0
0 0 256 symbols
0 1 512 symbols
1 0 1024 symbols
1 1 2048 symbols
Output format OUTB OUTA
0 0 scheme 1
0 1 scheme 2
1 0 scheme 3
1 1 scheme 4
DAC carrier recovery
(maximum current) CARB CARA
0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA
DAC clock recovery
(maximum current) CLKB CLKA
0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA
DAC AGC
(maximum current) AGCB AGCA
0050µA
0 1 100 µA
1 0 150 µA
1 1 200 µA
PARAMETER BIT VALUE DESCRIPTION
1996 Nov 19 34
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Table 12 I2C-bus write parameters; 3-bit values
Table 13 Convergence step for the equalizer (DFE and FFE parts)
Table 14 I2C-bus write parameters; 4-bit values
PARAMETER BITS DESCRIPTION
CONC CONB CONA
Constellation 0 0 0 4-QAM
0 0 1 16-QAM
0 1 0 32-QAM
0 1 1 64-QAM
1 0 0 256-QAM
DSTP2 FSTP2 DSTP1 FSTP1 DSTP0 FSTP0 CONVERGENCE STEP
(LOCK = 0) CONVERGENCE STEP
(LOCK = 1)
000 2
-13 2-15
001 2
-13 2-14
010 2
-13 2-13
011 2
-12 2-15
100 2
-12 2-14
101 2
-12 2-13
110 2
-12 2-12
111 2
-11 2-15
PARAMETER BITS DESCRIPTION
OUTF TSEL2 TSEL1 TSEL0
Output format 0 0 0 0 8 bits in parallel
0 1 1 1 I/Q 8 bits multiplexed (equalizer output)
1 x x x semi-serial
Special test
modes 0 x 0 1 DO7 to DO4 = carrier recovery DAC input;
DO3 to DO0 = AGC DAC input
0 x 1 0 DO7 to DO6 = fine AGC;
DO5 to DO0 = clock recovery DAC input
0 0 1 1 DO7 to DO0 = I and Q equal input
(I/Q 8 bits multiplexed format)
0 1 1 1 DO7 to DO0 = I and Q equal output
(I/Q 8 bits multiplexed format)
1996 Nov 19 35
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
7.1.13 I2C-BUS READ PARAMETERS
Table 15 I2C-bus read parameter; 1-bit values
Table 16 I2C-bus read parameter; ADC carrier recovery; 4-bit value
Table 17 I2C-bus read parameter; ADC clock recovery; 4-bit value
Table 18 I2C-bus read parameter; ADC AGC; 4-bit value
Table 19 I2C-bus read parameter; 8-bit value
Note
1. The bits LE7 to LE0 give the number of symbols falling inside the lock detector active areas. The count is made during
an observation period (256 to 2048 symbols).
To obtain more details about the SER estimation, refer to
“Application Note AN96048”
.
Table 20 I2C-bus read parameter; 12-bit value
Note
1. The bits FS11 to FS0 indicate the remaining frequency shift of the QAM spectrum (IF spectrum). This data is useful
if the TDA8046H does not use the outer loop of carrier recovery (bit ‘OUTE’ of the I2C-bus table set to 0).
To obtain more details about the frequency shift calculation, refer to the
“Application Note AN96048”
.
PARAMETER BIT VALUE DESCRIPTION
Lock detect LK 0 no lock
1 lock
Alarm equalizer ALEQ 0 normal operation (alarm off)
1 divergence detected (alarm on)
PARAMETER BITS DESCRIPTION
ADC carrier
recovery CR03 CR02 CR01 CR00
b3 b2 b1 b0 carrier recovery: VCARREC = 0.25 + 1⁄16VDDD
(8b3 + 4b2 + 2b1 + b0) V
PARAMETER BITS DESCRIPTION
ADC clock
recovery CL03 CL02 CL01 CL00
b3 b2 b1 b0 clock recovery: VCLKREC = 0.25 + 1⁄16VDDD
(8b3 + 4b2 + 2b1 + b0) V
PARAMETER BITS DESCRIPTION
ADC AGC AG03 AG02 AG01 AG00
b3 b2 b1 b0 AGC: VAGC = 0.25 + 1⁄16VDDD (8b3 + 4b2 + 2b1 + b0) V
PARAMETER BITS DESCRIPTION
SER (1) LE7 LE6 LE5 LE4 LE3 LE2 LE1 LE0
b7 b6 b5 b4 b3 b2 b1 b0 SER = f (b7 to b0)
PARAMETER BITS DESCRIPTION
IF_FREQ_SHIFT(1) FS11 to FS0 frequency shift = f (FS11 to FS0)
1996 Nov 19 36
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
9 THERMAL CHARACTERISTICS
10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS
Note
1. Definition of the power inter-symbol interference:
Where Nconv is the number of coefficients Cconv. Cconv(k) represent the coefficient resulting from the convolution of
the transmission and reception filters (K indicates the Kth coefficient).
The power ISI specified in Table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters
and a truncated half-Nyquist filter with 57 T/4 taps for the 15% roll-off filter and 41 T/4 taps for the 20% roll-of filter
(see “
Application note AN96048”
- Appendix B).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage −0.3 6.0 V
Vmax maximum voltage on all pins 0 VDDD V
Ptot total power dissipation Tamb =70°C−1.4 W
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature 0 70 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient in free air 50 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
αroll-off −15 or 20 −%
pass-band ripple −0.05 −dB
stop-band ripple see Figs 5 and 6
ISIpower power inter-symbol interference (15% roll-off filter) note 1 −−43 −dB
power inter-symbol interference (20% roll-off filter) note 1 −−44 −dB
ISIpower dB()10 log 2C
conv(4k) 2
k1=
N
conv 1–()2⁄
∑
×
C
conv(0) 2
---------------------------------------------------------------------
=
1996 Nov 19 37
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
11 LOCK DETECTOR CHARACTERISTICS
12 CARRIER RECOVERY CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
SNRlock signal-to-noise ratio to lock the
demodulator 4-QAM 8 −−dB
16-QAM 15 −−dB
32-QAM 18 −−dB
64-QAM 21 −−dB
256-QAM 27 −−dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Carrier recovery detector
CARRIER RECOVERY:BIAS CURRENT FOR DACS SET TO 37.5 µA
Kddetector constant SNR = 21 dB for
64-QAM constellation −3ICAR −µA/rad
SNR = 27 dB for
256-QAM constellation −6.05ICAR −µA/rad
∆fCAR frequency range ±0.017rs−−MHz
fn(inner) loop bandwidth of inner loop rs= 5 Msym/s 10 −−kHz
fn(outer) loop bandwidth of outer loop −− 0.3fn(inner) kHz
Izero zero current of DAC −100 −+100 nA
ICAR maximum DAC output current
(programmable) 50 −200 µA
fDAC DAC sampling rate −rs−MHz
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING LOCK
IoCARlock mean output current −1⁄2ICAR −µA
∆I
oCARlock matching of output currents −2.5 −+2.5 %
CARRIER RECOVERY DAC OUTPUT CURRENTS DURING UNLOCK
IoCARunlock mean output current −ICAR −µA
∆I
oCARunlock matching of output currents −2.5 −+2.5 %
1996 Nov 19 38
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
13 CLOCK RECOVERY CHARACTERISTICS
14 AGC CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Clock recovery detector
CLOCK RECOVERY:BIAS CURRENT FOR DACS SET TO 37.5 µA
Kddetector constant SNR = 21 dB for
64-QAM constellation;
SNR = 27 dB for
256-QAM constellation
−0.24ICLK −µA/rad
∆fCLK frequency range 100 −−ppm
fnnatural frequency −400 −Hz
ICLK(max) maximum DAC output current
(programmable) 50 −200 µA
fDAC DAC sample rate −rs−MHz
CLOCK RECOVERY DAC output currents
IoCLKlock mean output current −ICLK −µA
∆I
oCLKlock matching of output currents −2.5 −+2.5 %
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
AGC detector
AGC DETECTOR:BIAS CURRENT FOR DACS SET TO 37.5 µA
∆RAGC AGC range of detector ±20 −−dB
Izero zero current −100 −+100 nA
IAGC(max) maximum DAC output current
(programmable) 50 −200 µA
fDAC DAC sample rate −rs−MHz
AGC DAC output currents
IoAGC mean output current in lock −1⁄14IAGC −µA
unlock −IAGC −µA
∆I
oAGC matching of output current −5+5%
1996 Nov 19 39
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS
16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS
VDDD =V
DDA =5V; V
DDD(core) = 3.3 V; Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Integrated loop amplifiers
LOOP AMPLIFIERS
GOL open loop gain −60 −dB
GBgain bandwidth product −1−MHz
Vref reference voltage −2.5 −V
Vooutput voltage 0.1VDDA −0.9VDDA V
RL(VSSD) load to ground 5 −−kΩ
R
L(VDDD) load to supply 6.5 −−kΩ
ANALOG SWITCHES
ZSW switch impedance closed −5−kΩ
open 10 −−MΩ
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Clock outputs: CLKADC and CLKSDV
VOL LOW level output voltage 0 −0.1VDDD V
VOH HIGH level output voltage 0.9VDDD −VDDD V
TCLK cycle time 35 −−ns
twpulse width 40 : 60 duty cycle 14 −−ns
trrise time CL=30pF −−6ns
t
ffall time CL=30pF −−6ns
R
Lload resistance 1 −−kΩ
Clock input: CLK
Vi(rms) input voltage level (RMS value) sine wave 100 −−mV
TCLK cycle time 35 −−ns
twpulse width 40 : 60 duty cycle 14 −−ns
Rsource source resistance −−50 Ω
Digital inputs: DIN8 to DIN0
VIL LOW level input voltage −−0.8 V
VIH High level input voltage 2.0 −−V
t
SU set-up time 15 −−ns
tHD hold time 0 −−ns
CLload capacitance −−10 pF
1996 Nov 19 40
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Digital outputs: DO1 to DO0 with respect to CLKOUT for semi-serial mode
VOL LOW level output voltage 0 −0.1VDDD V
VOH HIGH level output voltage 0.9VDDD −VDDD V
tod output delay time −−7ns
t
oHD output hold time −−10 ns
CLload capacitance additional 2 −30 pF
Digital outputs: DO7 to DO0 with respect to CLKSDV for 8-bit parallel mode
VOL LOW level output voltage 0 −0.1VDDD V
VOH HIGH level output voltage 0.9VDDD −VDDD V
tod output delay time −−22 ns
toHD output hold time −−22 ns
CLload capacitance additional 2 −30 pF
Digital outputs: DO7 to DO0 with respect to CLKOUT for I/Q multiplexed mode
VOL LOW level output voltage 0 −0.1VDDD V
VOH HIGH level output voltage 0.9VDDD −VDDD V
tod output delay time −−22 ns
toHD output hold time −−22 ns
Loop amplifier
Vooutput voltage level 0.1VDDA −0.9VDDA
GvDC voltage gain (open loop) −60 −dB
GBgain bandwidth product 1 −−MHz
RLload resistance 5 −−KΩ
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 19 41
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.31 Definition of the Implementation Loss.
handbook, full pagewidth
MBG989
10−4
no convergence
theory
measured
SNR (dB)
implementation
loss
BER
Fig.32 CMOS input data timing diagram.
handbook, full pagewidth
MGG176
CLKADC
DIN 0 to
DIN 8
90% 90%
10% 10%
tw
tSU; DAT tHD; DAT
tCLK
VOH
VOL
VIH
VIL
tf
tr
1996 Nov 19 42
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.33 CMOS semi-serial mode timing diagram.
handbook, full pagewidth
VOH
VOL
CLKOUT
CLKSDV
DO1 to DO0
toHD tod
VOH
VOL
VOH
VOL
Tsym
slot 3slot 2slot 1slot 0
MGG179
Fig.34 CMOS 8-bit symbol in parallel mode timing diagram
handbook, full pagewidth
MGG177
VOH
VOL
VOH
VOL
CLKSDV
DATA
OUTPUT
toHD tod
Tsym
1996 Nov 19 43
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
Fig.35 CMOS I and Q multiplexed timing diagram.
handbook, full pagewidth
VOH
VOL
CLKOUT
CLKSDV
DO7 to DO0
toHD tod
VOH
VOL
VOH
VOL
Tsym
IQ
MGG178
1996 Nov 19 44
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
17 PACKAGE OUTLINE
UNIT A1A2A3bpcE
(1) eH
E
LL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.25
0.05 2.90
2.65 0.25 0.50
0.35 0.25
0.14 14.1
13.9 118.2
17.6 1.4
1.2 1.2
0.8 7
0
o
o
0.2 0.10.21.95
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.6
SOT319-2 92-11-17
95-02-04
D(1) (1)(1)
20.1
19.9
HD
24.2
23.6
E
Z
1.2
0.8
D
e
θ
EA1
A
Lp
Q
detail X
L
(A )
3
B
19
y
c
E
HA2
D
ZD
A
ZE
e
vMA
1
64
52 51 33 32
20
X
pin 1 index
bp
D
H
bp
vMB
wM
wM
0 5 10 mm
scale
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2
A
max.
3.20
1996 Nov 19 45
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
18 SOLDERING
18.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
18.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
“Quality
Reference Handbook”
(order code 9397 750 00192).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
18.3 Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
•The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
18.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1996 Nov 19 46
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 19 47
Philips Semiconductors Product specification
Multi-mode QAM demodulator TDA8046
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Printed in The Netherlands 537021/1200/02/pp48 Date of release: 1996 Nov 19 Document order number: 9397 750 01499
