LP621024D-I Series
128K X 8 BIT CMOS SRAM
(July, 2006, Version 1.2) AMIC Technology, Corp.
Document Title
128K X 8 BIT CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue August 9, 2002 Preliminary
1.0 Final version release July 17, 2003 Final
1.1 Add Pb-Free package type August 19, 2004
1.2 Remove non-Pb-free package type July 3, 2006
LP621024D-I Series
128K X 8 BIT CMOS SRAM
(July, 2006, Version 1.2) 1 AMIC Technology, Corp.
Features General Description
Single +5V power supply
Access times: 55/70 ns (max.)
Current:
Very low power version: Operating: 70mA (max.)
Standby: 50μA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 2V (min.)
Available in 32-pin DIP, SOP TSOP and TSSOP
(8 X 13.4mm) packages
Pb-Free package only
All Pb-free (Lead-free) products are RoHS compliant
The LP621024D-I is a low operating current 1,048,576-bit
static random access memory organized as 131,072 words
by 8 bits and operates on a single 5V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2V.
Product Family
Pow er Dissipation
Product Family Operating
Temperature VCC
Range Speed Data Retention
(ICCDR, Typ.) Standby
(ISB1, Typ.) Operating
(ICC2, Typ.)
Package
Type
LP621024D -40°C ~ +85°C4.5V~5.5V 55ns / 70ns 0.5μA 2μA 10mA 32L DIP/
SOP/TSOP/
TSSOP
1. Typical values are measured at VCC = 5.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
DIP SOP TSOP/(TSSOP)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
LP621024D-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
LP621024DM-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
LP621024DV-I
(LP621024DX-I)
1
16
17 32
Pin No.
Pin
Name
Pin No.
Pin
Name
12
A9
3 4 5 6 7 8 9 1011121314
302928272625242219 2120 231817
A8 A13 CE2 A15 VCC NC
I/O
8
A16 A14 A12 A7 A6
A3 A2 A1 A0 I/O
1
I/O
2
GND I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11 WE
CE1
15 16
31 32
A5 A4
A10 OE
CE1
WE
CE1
WE
LP621024D-I Series
(July, 2006, Version 1.2) 2 AMIC Technology, Corp.
Block Diagram
ROW
DECODER
512 X 2048
MEMORY ARRAY
INPUT DATA
CIRCUIT COLUMN I/O
CONTROL
CIRCUIT
CE2
CE1
WE
I/O
8
I/O
1
A16
A15
A14
A0 VCC
GND
OE
Pin Descriptions - DIP/SOP
Pin No. Symbol Description
1 NC No Connection
2 - 12, 23,
25 - 28, 31 A0 - A16 Address Inputs
13 - 15,
17 - 21 I/O1 - I/O8 Data Input/Outputs
16 GND Ground
22 CE1 Chip Enable
24 OE Output Enable
29 WE Write Enable
30 CE2 Chip Enable
32 VCC Power Supply (+5V)
Pin Description - TSOP/TSSOP
Pin No. Symbol Description
1 - 4, 7,
10 - 20, 31 A0 - A16 Address Inputs
5 WE Write Enable
6 CE2 Chip Enable
8 VCC Power Supply
9 NC No Connection
21 - 23,
25 - 29 I/O1 - I/O8 Data Input/Outputs
24 GND Ground
30 CE1 Chip Enable
32 OE Output Enable
LP621024D-I Series
(July, 2006, Version 1.2) 3 AMIC Technology, Corp.
Recommended DC Operating Conditions
(TA = -40°C to + 85°C)
Symbol Parameter Min. Typ. Max. Unit
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.2 3.5 VCC + 0.3 V
VIL Input Low Voltage -0.3 0 +0.8 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
Absolute Maximum Ratings*
VCC to GND..............................................-0.5V to + 7.0V
IN, IN/OUT Volt to GND....................-0.5V to VCC + 0.5V
Operating Temperature, Topr.................. -40°C to + 85°C
Storage Temperature, Tstg.................... -55°C to + 125°C
Temperature Under Bias, Tbias............... -40°C to + 85°C
Power Dissipation, PT .............................................0.7W
Soldering Temp. & Time.............................260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 5V ± 10%, GND = 0V)
Symbol Parameter LP621024D-55LLI LP621024D-70LLI
Unit Conditions
Min. Max. Min. Max.
⎜ILI⎥ Input Leakage
Current - 1 - 1
μA VIN = GND to VCC
⎜ILO⎥ Output Leakage
Current - 1 - 1
μA CE1 = VIH or CE2 = VIL
or OE = VIH or WE = VIL
VI/O = GND to VCC
ICC Active Power
Supply Current - 15 - 15 mA
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC1 Dynamic
Operating - 70 - 70 mA
Min. Cycle, Duty = 100%
CE1 = VIL, CE2 = VIH
II/O = 0mA
ICC2
Current
- 15 - 15 mA
CE1 = VIL, CE2 = VIH
VIH = VCC, VIL = 0V
f = 1MHZ, II/O = 0mA
LP621024D-I Series
(July, 2006, Version 1.2) 4 AMIC Technology, Corp.
DC Electrical Characteristics (continued)
Symbol Parameter LP621024D-55LLI LP621024D-70LLI
Unit Conditions
Min. Max. Min. Max.
ISB - 2 - 2 mA
CE1 = VIH or CE2 =VIL
ISB1 Standby Power
Supply Current - 50 - 50
μA CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
ISB2 - 50 - 50 μA CE2 ≤ 0.2V
VIN ≥ 0V
VOL Output Low
Voltage - 0.4 - 0.4 V IOL = 2.1mA
VOH Output High
Voltage 2.4 - 2.4 - V IOH = -1.0mA
Truth Table
Mode CE1 CE2 OE WE I/O Operation Supply Current
Standby H X X X High Z ISB, ISB1
X L X X High Z ISB, ISB2
Output Disable L H H H High Z ICC, ICC1, ICC2
Read L H L H DOUT ICC, ICC1, ICC2
Write L H X L DIN ICC, ICC1, ICC2
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% test ed.
LP621024D-I Series
(July, 2006, Version 1.2) 5 AMIC Technology, Corp.
AC Characteristics (TA = -40°C to + 85°C, VCC = 5V ± 10%)
Symbol Parameter LP621024D-55LLI LP621024D-70LLI Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 - 70 - ns
tAA Address Access T ime - 55 - 70 ns
tACE1 Chip Enable Access Time CE1 - 55 - 70 ns
tACE2 CE2 - 55 - 70 ns
tOE Output Enable to Output Valid - 30 - 35 ns
tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns
tCLZ2 CE2 10 - 10 - ns
tOLZ Output Enable to Output in Low Z 5 - 5 - ns
tCHZ1 Chip Disable to Output in High Z CE1 0 20 0 25 ns
tCHZ2 CE2 0 20 0 25 ns
tOHZ Output Disable to Output in High Z 0 20 0 25 ns
tOH Output Hold from Address Change 5 - 5 - ns
Write Cycle
tWC Write Cycle Time 55 - 70 - ns
tCW Chip Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z 0 25 0 30 ns
tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write T ime 0 - 0 - ns
tOW Output Active from End of Writ e 5 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
LP621024D-I Series
(July, 2006, Version 1.2) 6 AMIC Technology, Corp.
Timing Waveforms
Read Cycle 1(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
Read Cycle 2 (1, 3, 4, 6)
t
CLZ15
t
ACE1
t
CHZ15
CE1
D
OUT
Read Cycle 3 (1, 4, 7, 8)
t
CLZ25
t
ACE2
t
CHZ25
CE2
D
OUT
LP621024D-I Series
(July, 2006, Version 1.2) 7 AMIC Technology, Corp.
Timing Waveforms (continued)
Read Cycle 4 (1)
t
RC
Address
CE2
D
OUT
t
AA
t
OE
t
OLZ5
t
ACE1
t
CLZ15
t
ACE2
t
CLZ25
t
CHZ25
t
OHZ5
t
CHZ15
t
OH
OE
CE1
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4.
OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7.
CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
CE1
CE2
DIN
tOW
tDHtDW
tWHZ
tWP2
tAS1
(4) tCW5
tAW tWR3
WE
DOUT
(4)
LP621024D-I Series
(July, 2006, Version 1.2) 8 AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
CE1
CE2
D
IN
t
DH
t
DW
(4)
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
WP2
t
CW5
t
AS1
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE.
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Writ e cycle.
4. If the
CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the
WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6.
OE is continuously low. (OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
LP621024D-I Series
(July, 2006, Version 1.2) 9 AMIC Technology, Corp.
AC Test Conditions
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
+5V
I/O
990
Ω
1800
Ω
30pF*
* Including scope and jig.
+5V
I/O
990
Ω
1800
Ω
5pF*
* Including scope and jig.
Figure 1. Output Load Figure 2. Output Load for tCLZ1,
t
CLZ2, tOHZ, tOLZ, tCHZ1,
t
CHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR1 2.0 5.5 V CE1 ≥ VCC - 0.2V
VDR2 VCC for Data Retention 2.0 5.5 V CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
ICCDR1
Data Retention Current
LL-Version
-
20**
μA
VCC = 2.0V,
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ 0V
ICCDR2
LL-Version
-
20**
μA VCC = 2.0V
CE2 ≤ 0.2V
VIN ≥ 0V
tCDR Chip Disable to Data Retention Time 0 - ns See Retention Waveform
tR Operation Recovery Time 5 - ms
** LP621024D-55LLI/70LLI ICCDR: Max. 2μA at TA = 0°C to + 40 °C
LP621024D-I Series
(July, 2006, Version 1.2) 10 AMIC Technology, Corp.
Low VCC Data Retention Waveform (1) (CE1 Controlled)
VCC
CE1
t
CDR
V
IH
4.5V
t
R
V
IH
4.5V
DATA RETENTION MODE
V
DR
≥
2V
CE1
≥
V
DR
- 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
VCC
CE2
t
CDR
V
IL
4.5V
t
R
V
IL
4.5V
DATA RETENTION MODE
V
DR
≥
2V
CE2
<
0.2V
LP621024D-I Series
(July, 2006, Version 1.2) 11 AMIC Technology, Corp.
Ordering Information
Part No. Access Time
(ns) Operating Current
Max. (mA) Standby Current
Max. (μA) Package
LP621024D-55LLIF 70 50 32L Pb-Free DIP
LP621024DM-55LLIF 70 50 32L Pb-Free SOP
LP621024DV-55LLIF 70 50 32L Pb-Free TSOP
LP621024DX-55LLIF
55
70 50 32L Pb-Free TSSOP
LP621024D-70LLIF 70 50 32L Pb-Free DIP
LP621024DM-70LLIF 70 50 32L Pb-Free SOP
LP621024DV-70LLIF 70 50 32L Pb-Free TSOP
LP621024DX-70LLIF
70
70 50 32L Pb-Free TSSOP
LP621024D-I Series
(July, 2006, Version 1.2) 12 AMIC Technology, Corp.
Package Information
P-DIP 32L Outline Dimensions unit: inches/mm
1
32
E
1
S
A
2
AL
E
e
A
D
C
α
B
1
B
A
1
Base Plane
Seating Plane
16
17
e
1
Symbol Dimensions in inches Dimensions in mm
A 0.210 Max. 5.33 Max.
A1 0.010 Min. 0.25 Min.
A2 0.155±0.010 3.94±0.25
B 0.018 +0.004 0.46 +0.10
-0.002 -0.05
B1 0.050 +0.004 1.27 +0.10
-0.002 -0.05
C 0.010 +0.004 0.25 +0.11
-0.002 -0.05
D 1.650 Typ. (1.670 Max.) 41.91 Typ. (42.42 Max.)
E 0.600±0.010 15.24±0.25
E1 0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.)
e1 0.100±0.010 2.54±0.25
L 0.130±0.010 3.30±0.25
α 0° ~ 15° 0° ~ 15°
eA 0.655±0.035 16.64±0.89
S 0.090 Max. 2.29 Max.
Notes:
1. T he maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
LP621024D-I Series
(July, 2006, Version 1.2) 13 AMIC Technology, Corp.
Package Information
SOP (W.B.) 32L Outline Dimensions unit: inches/mm
1
E
H
E
L
L
E
c
16
See Detail F
Detail F
1732 e
1
e
1
A
1
A
2
A
s
D
Seating Plane
D
y
e
b
~
~
Symbol Dimensions in inches Dimensions in mm
A 0.118 Max. 3.00 Max.
A1 0.004 Min. 0.10 Min.
A2 0.106±0.005 2.69±0.13
b 0.016 +0.004 0.41 +0.10
-0.002 -0.05
c 0.008 +0.004 0.20 +0.10
-0.002 -0.05
D 0.805 Typ. (0.820 Max.) 20.45 Typ. (20.83 Max.)
E 0.445±0.010 11.30±0.25
e 0.050 ±0.006 1.27±0.15
e1 0.525 NOM. 13.34 NOM.
HE 0.556±0.010 14.12±0.25
L 0.031±0.008 0.79±0.20
LE 0.055±0.008 1.40±0.20
S 0.044 Max. 1.12 Max.
y 0.004 Max. 0.10 Max.
θ 0° ~ 10° 0° ~ 10°
Notes:
1. T he maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
LP621024D-I Series
(July, 2006, Version 1.2) 14 AMIC Technology, Corp.
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm
e
L
E
L
GAUGE PLANE
A
A2
c
0.25
BSC
Detail "A"
D
y
Detail "A"
S
A1
b
H
D
D
E
0.10(0.004) M
°12.0
θ
Symbol Dimensions in inches Dimensions in mm
A 0.047 Max. 1.20 Max.
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.001 0.15±0.02
D 0.724±0.004 18.40±0.10
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
HD 0.787±0.007 20.00±0.20
L 0.020±0.004 0.50±0.10
LE 0.031 TYP. 0.80 TYP.
S 0.0167 TYP. 0.425 TYP.
Y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. T he maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
LP621024D-I Series
(July, 2006, Version 1.2) 15 AMIC Technology, Corp.
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm
e
Detail "A"
D
0.10MM
Detail "A"
Sb
D
1
E
D
L
E
L
GAUGE PLANE
A
A2
c
0.25
BSC
Detail "A"
A1
SEATING PLANE
°12.0
θ
Symbol Dimensions in inches Dimensions in mm
A 0.049 Max. 1.25 Max.
A1 0.002 Min. 0.05 Min.
A2 0.039±0.002 1.00±0.05
b 0.008±0.001 0.20±0.03
c 0.006±0.0003 0.15±0.008
E 0.315±0.004 8.00±0.10
e 0.020 TYP. 0.50 TYP.
D 0.528±0.008 13.40±0.20
D1 0.465±0.004 11.80±0.10
L 0.02±0.008 0.50±0.20
LE 0.0266 Min. 0.675 Min.
S 0.0109 TYP. 0.278 TYP.
y 0.004 Max. 0.10 Max.
θ 0° ~ 6° 0° ~ 6°
Notes:
1. T he maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
