National Semiconductor Programmable Array Logic (PAL) 20-Pin Medium PAL Family General Description The 20-pin Medium PAL family contains four of the most popular PAL architectures used in industry. National Semi- conductors advanced Schottky TTL process with titanium tungsten fusible links is used in manufacturing the standard, Series-A, Series-A2, Series-B and Series-B2 devices. Se- ries-D devices are manufactured using National Semicon- ductors isoplanar FAST-Z" TTL process with highly reli- able vertical-fuse programmable cells. Vertical fuses are implemented using avalanche-induced migration (AIM) technology offering very high programming yields and is an extension of Nationals FAST logic family. The 20-pin Medi- um PAL Family provides high-speed user-programmable re- placements for conventional SSI/MSi logic with significant chip-count reduction. Programmable logic devices provide convenient solutions for a wide variety of application-specific functions, including random logic, custom decoders, state machines, etc. By programming the programmable cells to configure AND/OR gate connections, the system designer can implement cus- tom logic as convenient sum-of-products Boolean functions. System prototyping and design iterations can be performed quickly using these off-the-shelf products. A large variety of programming units and software makes design develop- ment and functional testing of PAL devices quick and easy. The PAL logic array has a total of 16 complementary input pairs and 8 outputs generated by a single programmable AND-gate array with fixed OR-gate connections. Device qut- puts are either taken directly from the AND-OR functions (combinatorial) or passed through D-type flip-flops (regis- tered). Registers allow the PAL device to implement se- quential logic circuits. TRI-STATE outputs facilitate busing and provide bidirectional I/O capability. The medium PAL family offers a variety of combinatorial and registered output mixtures, as shown in the Device Types table below. On power-up, Series-D devices reset all registers to simplify sequential circuit design and testing. For these devices, di- rect register preload is also provided to facilitate device test- ing. Security fuses can be programmed to prevent direct copying of proprietery logic patterns in alt the family devices. Features @ As fast as 7 ns maximum propagation delay (combinatorial) a User-programmabie replacement for TTL logic @ High programming yield and reliability of vertical-fuse technology for Series-D/-7 products. (Programming equipment with certified vertical-fuse algorithm required.) m@ Extension of FAST product line m Large variety of JEDEC-compatible programming equip- ment and design development software available @ Fully supported by National PLAN development software w Power-up reset for registered outputs @ Register preioad facilitates device testing @ Security fuse prevents direct copying of logic patterns Device Types Device |Dedicated Pe etpats.. Combinatorial ype | IMPU's | (with Feedback)! 17o5 Outputs PALI6L8 10 6 2 PAL16R4 8 4 4 PAL16R6 8 6 2 PAL16R8 8 8 = _ Speed/Power Versions Series | Exampie Commercial Military tpp lec tpp Icc Standard| PAL16L8 35ns |180mA] 45ns |180mA A |PALi6L8A | 25ns |180mA| 30ns |180mA A2 |PALI6L8A2| 35ns | 90mA| 50ns | 90mA B |PALI6L8B | 15ns {180mA! 20ns |180 mA B2 |PALI6L8B2] 25ns {90mA*| 30ns | 90 mA* D |PALI6L8D | 10ns |180mA -7 |PAL16L8-7| 7ns |180mA For the registered devices Igg = 100 mA. Block DiagramPAL16R8 C}he> Ha] GY Peis Gy Pore Ce) POT eel EH. PTE Cy POE pea CH PD tp Gy POT ea cH petien (ofa <P] TL/L/9391-* 2-23 Aywied Wd WNIPaW Uld-0220-Pin Medium PAL Family Standard Series (aciecs, PAL16R4, PAL16R6, PAL16R8) Absolute Maximum Ratings (note 1) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Output Current (lol) Storage Temperature Ambient Temperature 100 mA 65C to + 150C Supply Voltage (Vcc) (Note 2) 0.5V to +7.0V with Power Applied 65C to + 125C Input Voltage (Notes 2 and 3) 1.5V to +5.5V Junction Temperature ~65C to + 150C Off-State Output Voltage (Note 2) 1.5V to + 5.5V ESD 1500V Input Current (Note 2) 30.0 mA to + 5.0 mA Recommended Operating Conditions Symbol! Parameter Military Commercial Units Min Nom Max Min Nom Max Veco Supply Voltage 4.5 5 5.5 4.75 5 5.25 Vv Ta Operating Free-Air Temperature 55 0 75 i Te Operating Case Temperature 125 a2) tw Clock Pulse Width Low 25 25 ns High 25 25 ns SY | crrecdbackto Clock 4 35 ns tH Hold Time of Input after Clock 0 ~15 0 15 ns foik Clock Frequency With Feedback 12.2 16.6 MHz (Note 4) Without Feedback . 20 20 MHz Eiectrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units Vit Low Level Input Voltage (Note 6) 0.8 Vv Vin High Level Input Voltage (Note 6) 2 Vv Vic Input Clamp Voltage Voc = Min, | = 18mA 0.8 -15 Vv Iie Low Level Input Current (Note 7) Voc = Max, V; = 0.4V 0.02 | 0.25 mA NH High Level Input Current (Note 7) | Voc = Max, V; = 2.4V 25 pA h Maximum Input Current Voc = Max, V; = 5.5V 100 pA Voi Low Level Output Voltage Veco = Min lol = 12 mA MIL 03 05 Vv lo. = 24mA COM Vou High Level Output Voitage Voc = Min low = ~2mA MIL 24 29 v lon = 3.2mA | COM loz Low Level Off-State Output Voc = Max | Vo = 0.4V ~400 pA Current (Note 7) lozH High Level Off-State Output Voc = Max | Vo = 2.4V 100 yA Current (Note 7) los Output Short-Circuit Current Voc = 5V, Vo = OV _90 _70 130 mA (Note 8) loc Supply Current Voc = Max, Outputs Open 120 180 mA 2-24Standard Series (Pav:6.s, PAL16R4, PAL16R6, PAL16RB) (Continued) Note 1: Absoiute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the specitied recommended operating conditions. Note 2; Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 7 and 11 are connected directly to the security fuses, and the security fuses may be damaged, preventing subsequent programming and verification operations. Note 4: fo. with feedback is derived as (toLk + tgy)-1. icLk without feedback Is darived as (2ty)~1. Note 6: All typical values are for Voc = 5.0V and Ta = 25C. Note 6: These are absolute voltages with respect to the ground pin on the device and include alt overshoots due to systam and/or tester noise. Do not attempt to test these values without suitable equipment. Note 7: Leakage current for bidirectional |/O pins is the worst case between |), and Ioz_ or between I and [ozn. Note 6: To avoid invalid readings in other parameter tests it is preferable to conduct the Ipg test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each. Pralonged shorting of a High output may raise the chip temperatura above normal and permanent damage may result. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military Commercial | Units Min | Typ | Max | Min | Typ | Max tpp Input or Feedback to C_ = 50 pF, $1 Closed Combinatorial Output 2 | 48 25 | 35 | 1s toLK Clock to Registered C_ = 50 pF, $1 Closed Output or Feedback 18 25 18 25 ns tezxG G Pin to Registered C. = 50 pF, Active High: S1 Open, Output Enabled Active Low: S1 Closed 15 | 28 18 | 25 ) ns tpxzG G Pin to Registered CL = SpF, From Voy: $1 Open, Output Disabled From Vo,: $1 Closed 15 | 2 1S | 25) Ns tpzxI Input to Combinatorial Output | C, = 50 pF, Active High: $1 Open, 25 45 25 95 ns Enabled via Product Term Active Low: S1 Closed tex) Input to Combinatorial Output | CL = 5 pF, From Voy: $1 Open, 25 45 25 35 ns Disabled via Product Term From Vo,: S1 Closed Test Load Schematic of Inputs and Outputs 0 ee er EQUIVALENT INPUT TYPICAL OUTPUT st / Yee o 0 Yoo 3" , OUTPUT ] MIL COM'L 3 Ska NOM. 3 400. NOM. me See R1 = 380 RI = 200 Lt j A2= 750 R2 = 390 = = PUT O=4 TL/L/8391-2 PO OUTPUT az = = TL/L/9391 -7 2-25 Awe 1Wd Wn|paW Uld-0Z20-Pin Medium PAL Family Series-A (PALI6L8A, PAL16R4A, PAL16R6A, PAL16R8A) Absolute Maximum Ratings (note 1) if Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Output Currant {loL) Storage Temperature Ambient Temperature 100 mA 65C to + 150C Supply Voltage (Vcc) (Note 2) 0.5V to +7.0V with Power Applied 65C to + 125C Input Voltage (Notes 2 and 3) 1.5V to + 5.5V Junction Temperature 65C to + 150C Off-State Output Voltage (Note 2) 1.5V to + 5.5V ESD 4500V Input Current (Note 2) 30.0 mA to +5.0 mA Recommended Operating Conditions Symbol Parameter Military Commercial - Units Min Nom Max Min Nom Max Veco Supply Voltage 4.5 5 5.5 4.76 5 .25 Vv Ta Operating Free-Air Temperature ~55 0 75 G Tc Operating Case Temperature 125 C tw Clock Pulse Width Low 20 10 15 10 ns High 20 10 15 10 ns SY | crracdbeck to Glos | 2 | 1 ne tH Hold Time of Input after Clock 0 10 0 -10 ns foik Clock Frequency With Feedback 20 25 MHz (Note 4) Without Feedback 25 33.3 | MHz Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units VIL Low Level Input Voltage (Note 6) 0.8 v Vind High Level Input Voltage (Note 6) 2 Vv Vic Input Clamp Voltage Voc = Min, | = 18mA 0.8 14.5 V hit Low Level Input Current (Note 7) Voc = Max, V; = 0.4V 0.02 0.25 mA lin High Leve! Input Current (Note 7) | Yoo = Max, Vv = 2.4V 25 pa I Maximum Input Current Voc = Max, Vv; = 5.5V 100 pA VoL Low Level Output Voltage Voc = Min lo. = 12 mA MIL 03 05 Vv lo. = 24mA COM Vou High Level Output Voltage Voc = Min lon = 2mA MIL 24 29 Vv low = 3.2mA | COM lozL Low Level Off-State Output Voc = Max | Vo = 0.4V 100 yA Current (Note 7) lozH High Level Off-State Output Voc = Max | Vo = 2.4V 100 pA Current (Note 7) los Output Short-Circuit Gurrent Veco = 5V, Vo = OV ~30 70 ~130 mA (Note 8) lec Supply Current Vcc = Max, Outputs Open 120 180 mA 2-26Series-A (PALI6L8A, PAL16R4A, PAL16R6A, PAL16R8A) (Continued) Note 1: Absolute maximum ratings are those values beyond which the davice may be permanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Soma device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 11 are connected directly to the security fuses, and the security fuses may be damaged, preventing subsequent programming and verification operations. Note 4: fo. with feedback is derived as (tcLK + tgy)1. fo_k without feedback is derived as (2tyw)-1. Note 5: All typical values are for Voc = 5.0V and Ta = 26C. Note 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots dus to system and/or tester noise. Do not attempt to test these values without suitable equipmant. Note 7: Leakage current for bidirectional [/O pins is the worst casa between |, and inz, or between |)y and lozy. Note 8: To avoid invalid readings in other parameter tests it is preterable to conduct the Igg test last. Fo minimize internal heating, only one output should be shorted at a time with a maximum duration of t.0 sec. each. Prolonged shorting of a High output may raise the chip temperature above normal and permanent damage may resutt. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military Commercial Units Min | Typ | Max | Min | Typ | Max tpp Input or Feedback to Cy = 50 pF, $1 Closed Combinatorial Output 18 30 8 26 ns toLk Clock to Registered CL = 50 pF, S71 Closed Output or Feedback 10 20 10 15 ns tpzxG G Pin to Registered C, = 50 pF, Active High: S1 Open, Output Enabled Active Low: S1 Closed 10 25 10 20 ns texzG G Pinto Registered CL = 5pF, From Vou: $1 Open, 41.1 25 11. | 20 ns Output Disabled From Voy: $1 Closed tpzyxI Input to Combinatorial Output | CL = 50 pF, Active High: $1 Open, 10 30 10 25 ns Enabled via Product Term Active Low: S1 Closed tpxz} Input to Combinatorial Output | CL = 5 pF, From Voy: $1 Open, 19 90 13 25 ns Disabled via Product Term From Voc: $1 Closed Test Load Schematic of Inputs and Outputs EQUIVALENT PUT TYPICAL OUTPUT sv 7 Yee Yoo mt $ ska. Now. $ 400 wow. MIL COM'L 4 4 ouTPUT Ri = 390 Al = 200 yy A2= 750 A2 = 390 4 a2 INPUT ort = = TL/L/9394 +2 T b= OUTPUT x | T ~ TuL/eae1-7 2-27 Awe TW WNIPay Uld-0220-Pin Medium PAL Family Series-A2 (PAti6csa2, PAL1GR4A2, PAL1GR6A2, PAL16R8A2) Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, Output Current (lo.} 100 mA please contact the National Semiconductor Sales Storage Temperature 65C to + 150C Office/Distributors for availability and specifications. Ambient Temperature Supply Voltage (Vcc) (Nate 2) 0.5V to + 7.0V with Power Applied 65C to + 125C Input Voltage (Notes 2 and 3) 1.5V to + 5.5V Junction Temperature 65C to + 150C Off-State Output Voltage (Note 2) 1.5 to + 5.5V ESD 1500V Input Current (Note 2) 30.0 mA to + 5.0 mA Recommended Operating Conditions Symbol Parameter Military Commercial Units Min Nom Max Min Nom Max Voc Supply Voitage 45 5 5.5 4.75 5 .25 Vv Ta Operating Frae-Air Temperature 55 125 0 75 C tw Clock Pulse Width Low 25 10 25 10 ns High 25 10 25 10 ns tsu Setup Time from Input or Feedback to Clock 50 25 38 25 ns ty Hold Time of Inout after Clock 0 -15 0 15 ns fcLk Clock Frequency With Feedback 13.3 16.7 MHz (Note 4) Without Feedback 20 20 MHz Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units Vit Low Level Input Voitage (Note 6) 0.8 Vv Vind High Level Input Voltage (Note 6) 2 Vic Input Clamp Voltage Voc = Min, = 18mA 0.8 15 Vv HL Low Level Input Current (Note 7) Veco = Max, V; = 0.4V 0.02 | 0.25 mA lit High Level Input Current (Note 7) | Voc = Max, V| = 2.4V 25 pA h Maximum Input Current Voc = Max, V| = 5.5V 160 pA VoL Low Level Output Voltage Voc = Min lo. = 12mA MIL 03 05 Vv lo, = 24mA COM Vou High Level Output Voltage Vec = Min lon = -2mA MIL 24 29 Vv lon = 3.2mA | COM loz. Low Level Off-State Output Voc = Max | Vo = 0.4V ~100 pA Current (Note 7) lozH High Level Cff-State Output Voc = Max | Vo = 2.4V 100 pA Current (Note 7) los Output Short-Circuit Current Veco = 5V, Vo = OV 30 -~70 130 mA (Note 8) loc Supply Currant Voc = Max, Outputs Open 70 90 mA 2-28Series-A2 (PAL16L8A2, PAL16R4A2, PAL1GR6A2, PAL16R8A2) (Continued) Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Praper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Same device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this praduct. Pins 1 and 11 are connected directly to the security fuses, and the security fuses may be damaged, preventing subsequent programming and verification operations. Note 4: fco_k with feedback is derived as (tcLq + tsy)!. fock without feedback is derived as (2tw)1. Note 5: All typical values are for Voc = 5.0V and Ta = 26C. Note 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Da nat attempt to test these values without suitable equipment. Nate 7: Leakage current for bidirectional I/O pins is the worst case between I, and ioz, or between |iyq and IozH. Note 8: To avoid invalid readings in other parameter tests it is preferable to conduct the log test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each. Prolonged shorting of a High output may raise the chip temperature above normal and permanent damage may result. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military Commercial Units Min | Typ | Max | Min | Typ | Max tpp Input or Feedback to C._ = 50 pF, S1 Closed 25 50 25 35 ns Combinatorial Output toLK Clock to Registered C_ = 50 pF, $1 Closed Output or Feedback 15 28 1 25 ns tpzxG G Pin to Registered CL = 50 pF, Active High: Si Open, Output Enabled Active Low: S1 Closed 18 25 ' 26 ns tpxzG G Pin to Registered CL = S5pF, From Vox: $1 Open, Output Disabled Fram Voi: $1 Closed 18 2s 1 2s ns tpzxi Input to Combinatorial Output | CL = 50 pF, Active High: $1 Open, 25 45 95 35 ns Enabled via Product Term Active Low: $1 Closed tpxz| Input to Combinatorial Output | CL = S5pF, From Voy: $1 Open, 25 45 25 35 ns Disabled via Product Term Fram Voi: $1 Glosed Test Load Schematic of Inputs and Outputs O wn EQUIVALENT INPUT TYPICAL OUTPUT ad 51 Vea 0 Yeo a & 5k0. Now. 3 400 Now. MIL COM'L 4 1 ouTPUT Ri = 380 Rt = 200 Cy a2 R2= 750 A2 = 390 weur TL/L/9391-2 p> OUTPUT a A TL/L/9391-7 2-29 Awe Wd WNIPaW Uld-0220-Pin Medium PAL Family Series-B (PAcieies, PAL16R4B, PAL16R6B, PAL1GR8B) Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, Output Current (Io,) 100 mA please contact the National Semiconducter Sales Storage Temperature 65C to + 150C Office/Distributors for availability and specifications. Ambient Temperature Supply Voltage (Vcc) (Note 2) 0.5V to +7.0V with Power Applied B85C to + 125C Input Voltage (Notes 2 and 3) 1.5 to +5.5V Junction Temperature B5C to + 150C Off-State Output Voltage (Note 2) 1.5V to + 5.5V ESD 4000V Input Current (Note 2) 30.0 mA to + 5.0 mA Recommended Operating Conditions Symbol Parameter Military Commercial Units Min Nom Max Min Nom Max Voc Supply Voltage 4.5 5 5.5 4.75 5 5.25 Vv Ta Operating Free-Air Temperature ~55 0 75 C Te Operating Case Temperature 125 C tw Clock Pulse Width Low 12 5 10 5 ns High 12 5 10 5 ns SY | orreedbackw Glock 2 | 8 | 10 ns tH Hold Time of Input after Clock 0 5 0 ns. fcLK Clock Frequency With Feedback 28.6 40 MHz (Note 4) Without Feedback 417 50 MHz Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units Vit Low Level Input Voltage (Note 6) 0.8 Vv Vie High Level Input Voltage (Note 6) 2 v Vic Input Clamp Voltage Voc = Min,| = 18mA 0.8 1.5 Vv lit Low Level Input Current (Note 7) Voc = Max, V; = 0.4V 0.02 | -0.25 mA lie High Level Input Current (Note 7) | Voc = Max, V) = 2.4V 25 pA \ Maximum Input Current Voc = Max, V| = 5.5V 100 pA VoL Low Level Output Voltage Voc = Min Jo. = 72 mA MIL 03 05 Vv lo. = 24mA COM Vou High Level Output Voltage Voc = Min Jon = 2mA MIL 24 3.4 Vv ioH = 3.2mA | COM loze Low Level Off-State Output Veco = Max | Vo = 0.4V ~100 yA Current (Note 7) lozH High Level Off-State Output Voc = Max | Vo = 2.4V 400 pA Current (Note 7) los Output Short-Circuit Current Voc = 5V, Vo = OV 30 _70 _190 mA (Note 8) lec Supply Current Voc = Max, Outputs Open 120 180 mA 2-30Series-B (PALt6L8B, PAL16R4B, PALt6R6B, PAL16R8B) (Continued) Note 1: Absolute maximum ratings are those values beyond which the devica may be permanently damaged. Proper operation is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preload aperations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 11 are connected directly to the security fuses, and the security fuses may be damaged, preventing subsequent programming and verification operations. Note 4: fo, with feedback is derived as {tek + tgu)1. feLk without feedback is derived as (twrow + twHiGH)7*- Nate 5; All typical values are for Voc = 5.0V and Ta = 25C. Note 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 7: Leakage current for bidiractional I/O pins is the worst case between |), and loz, or between Ij and lozy. Note 8: To avoid invalid readings in other parameter tests it is preferable to conduct the log test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each. Prolonged shorting of a High output may raise the chip temperature above normal and permanent damage may result. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military Commercial Units Min | Typ | Max | Min | Typ | Max tpp Input or Feedback to GC. = 50 pF, $1 Closed Combinatorial Output " 20 u 1s ns tcLk Clock to Registered CG, = 50 pF, $1 Closed Output or Feedback 8 18 8 2 ns tpzxG G Pin to Registered C_ = 50 pF, Active High: S1 Open, Output Enabled Active Low: $1 Closed 10 20 10 18 ns tpxza G Pin to Registered CL = SpF, From Voy: $1 Open, . 1 1 15 Output Disabled From Voi: $1 Closed 20 ns tp2xI Input to Combinatorial Output | C_ = 50 pF, Active High: $1 Open, 1 20 11 15 ns Enabled via Product Term Active Low: S1 Closed tpxzi Input to Combinatorial Output | C, = 5 pF, From Voy: S1 Open, 1 20 1 15 ns Disabled via Product Term From Voi: $1 Closed Test Load Schematic of inputs and Outputs O wo EQUIVALENT #NPUT TYPICAL, OUTPUT St Yoo oO 2 Yeo m S 5&0 Nom. & 400 now, MIL COM'L 5 1 OUTPUT R1= 390 Ri = 200 on Ro R2= 750 R2 = 390 eur o TL/L/9391-2 p OUTPUT TL/L/9391 -7 2-31 Anwe 4 Wd WwN|peW Uld-0Z20-Pin Medium PAL Family Series-B2 (Pacisias2, PAL16R4B2, PAL16R6B2, PAL1GR8B2) Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Oftice/Distributors for availability and specifications. Storage Temperature Ambient Temperature with Power Applied 65C to + 150C 65Cto + 125C Supply Voltage (Voc) {Note 2) 0.5V to + 7.0V Junction Temperature 65C to + 150C Input Voltage (Note 2) 1.5V to +5.5V ESD Tolerance (Note 3) 2000V Off-State Output Voltage (Note 2) 1.5V to + 5.5V Czap = 100 pF Input Current (Note 2) 30.0 mA to +5.0 mA Rizap = 15000 Cup Curent oy room Festa Hu Soy et Recommended Operating Conditions Symbol Parameter Military Commercial Units Min Nom Max Min Nom Max Voc Supply Voltage 45 5 55 4.75 5 5.25 V Ta Operating Free-Air Temperature 55 125 0 75 C tw Clock Pulse Width Low 16 8 10 8 ns High 20 10 15 10 ns so | Spe aeereree = | 1 0 | on : tH Hold Time of Input after Clock 0 10 0 10 ns foik Clock Frequency With Feedback 22.2 28.6 MHz (Note 4) Without Feedback 28.6 40 MHz Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units VIL Low Level Input Voltage (Note 6) 0.8 Vv Vin High Levai Input Voltage (Note 6) 2 Vv Vic Input Clamp Voltage Voc = Min,! = -18mA -0.8 -1.6 Vv Ne Low Level Input Current (Note 7) | Voc = Max, V; = 0.4V -0.02 | 0.25 mA he High Level Input Current (Note 7) | Voc = Max, V; = 2.4V 25 BA I Maximum [nput Current Voc = Max, V, = 5.5V 100 pA Vo. Low Level Output Voltage Voc = Min lo. = 12mA MIL 04 05 V lo. = 24mA COM Vou High Level Output Voltage Voc = Min lox = 2mA MIL 24 3.4 V loH = 3.2mA | COM loze Low Level Off-State Output Voc = Max Vo = 0.4V 400 pA Current (Note 7) lozH High Level Off-State Output Voc = Max Vo = 2.4V 100 uA Current (Note 7) los Output Short-Cireuit Current Vec = 5V, Vo = OV 30 ~70 430 mA (Note 8) lec Supply Current ae = Max, 16L8B2 60 90 mA utputs Open | +6R482, 16R6B2, 16R8B2 70 100 2-32Series-B2 (Pacie6iese2, PAL16R482, PALIGREB2, PAL16R8B2) (Continued) Note 1: Absolute maximum ratings are those values beyond which the devica may be permanently damaged. Proper operation is not guaranteed outside the specified racommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preioad operations according to the applicable specification. Note 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and tasting this product. Pins 1 and 11 are connected directly to the security fuses, and, although the input circuitry can withstand the specified ESD conditions, the security fuses may be damaged, praventing subsequent programming and verification operations. Note 4: fc_K with feedback is derived as (toLh + tsy)1. tok without feedback is derived as (twrow + Wwuien)~1- Note 5: All typical values are for Voc = 5.0V and Ta = 25C. Note 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 7: Leakage current for bidirectional |/O pins is the worst case between {)_ and Ioz_ or between Iq and IozH. Note &: To avoid invalid readings in cther parameter tests it is preferable to conduct the Iog test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each. Prolonged shorting of a High output may raise the chip temperature above normal and permanent damage may result. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Military Commercial Units Min | Typ | Max | Min | Typ | Max tpp Input or Feedback to C_ = 50 pF, $1 Closed Combinatorial Output 15 30 ' 28 ns toLK Clock to Registered C, = 50 pF, $1 Closed Output or Feedback 10 20 10 15 ns tpzxG G Pin to Registered CL = 50 pF, Active High: $1 Open, 1 Output Enabled Active Low: $1 Closed 5 | 2 15) 20 | 1s tpxzG G Pin to Registered CL = SpF, From Voy: $1 Open, Output Disabled From Voi: $1 Closed 4 25 4 20 ns tpzx] Input to Combinatorial Output | CL = 50 pF, Active High: $1 Open, 10 30 40 25 ns Enabled via Product Term Active Low: S1 Closed tpxz1 Input to Combinatorial Output | C_ = 5pF, From Voy: $1 Open, 13 30 13 25 ns Disabled via Product Term From Voc: $1 Closed Test Load Schematic of Inputs and Outputs O en EQUIVALENT INPUT TYPICAL OUTPUT v $1 ec o O Yor a & ka Now. S 400 Now MIL COM'L 4 ouTPUT R1= 390 A = 200 oh a R2= 750 R2 = 390 eur o1 TL/L/9391-2 p) OUTPUT _ il TLAL/9391 -7 2-33 Ayes Wd WN|paW Uld-0220-Pin Medium PAL Family Series-D (Paci6isp, PAL16R4D, PAL1GRED, PAL16R8D) Absolute Maximum Ratings (note 1) It Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature Ambient Temperature with Power Applied 65C to + 150C 65C to + 125C Supply Voltage (Vcc) (Note 2) 0.5V to +7.0V Junction Temperature 65C to + 150C Input Voltage (Note 2) 1.5V to +7.0V ESD Tolerance 2000V Off-State Output Voltage Czap = 100 pF (Vo) (Notes 2 & 3) 1.5 to +5.5V Rzap = 15000 Input Current (Note 2) 30.0 mA to +5.0mA Test Method: Human Body Model Output Current (lo) +4100 mA Test Specification: NSC SOP-5-028 Recommended Operating Conditions Symbol Parameter Commercial Units Min Nom Max Vec Supply Voltage 4.75 5 5.25 v Ta Operating Free-Air Temperature . 0 25 75 c tw Clock Pulse Width Low 7 3.5 ns High 7 2 ns st or aedback to Clock 0 55 ne ty Hold Time of Input after Clock 0 3.7 ns foLk Clock Frequency With Feedback 55.5 MHz (Note 4) Without Feedback 71 MHz Vz Register Preload Control Voltage 9.5 9.75 10.0 Vv Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units VIL Low Level Input Voltage (Note 6) 0.8 Vv VK High Levet Input Voltage (Note 6) 2 V Vic Input Clamp Voltage Voc = Min, | = 18mA -0.8 1.2 V Iie Low Level Input Current (Note 7) Voc = Max, V) = 0.4V 60 ~~ 250 pA le High Level Input Current (Note 7) Voc = Max, Vv; = 2.4V 0 25 pA I Maximum Input Current Voc = Max, V; = 5.5V 20 100 pA VoL Low Level Output Voltage Voc = Min, 03 05 V lol = 24 mA Vou High Level Output Voltage Voc = Min, 27 44 V loH = 3.2 mA lozL Low Level Off-State Output Voc = Max, Vo = 0.4V 0 50 nA Current (Note 7) lozH High Level Off-State Output Voc = Max, Vo = 2.4V 0 50 yA Current (Note 7) los Output Short-Circuit Current Voc = 5V,Vo = OV 50 77 ~ 130 mA (Note 8) icc Supply Current Voc = Max, Outputs Open 125 180 mA, C Input Capacitance Voc = 5.0V,V, = 2.0V pF Co Output Capacitance Voc = 5.0V, Vo = 2.0V pF Ciro 1/0 Capacitance Voc = 5.0V, Vizo = 2.0V pF 2-34Series-D (PALi16L8D, PAL16R4D, PAL16R6D, PAL16R8D) (Continued) Note 1: Absolute maximum ratings are those values beyand which the device may be permanently damaged. Propar operation is not guaranteed outside the specified recommended aperating conditions. Note 2: Some device pins may be raised abova these limits during programming and preload operations according to the applicable specification. Note 3: Vp must not exceed Voc + 1V Note 4: fc. with feedback is derived as (tcLk + tgu)7. foik without feedback is derived as (2tw)- 1. Note 5: All typical values are for Voc = 5.0V and Ta = 25C. Note 6: Thase are absolute voltages with respect to the ground pin on the device and include ail ovarshaots due to systam and/or tester noise. Do not attempt to test these values without suitable equipment Note 7: Leakage current for bidirectional 1/O pins is the worst case between |), and Ioz, or between I and IozH. Note 8: To avoid invalid readings in other parameter tests it is preferable to conduct the Ing test last. To minimize internal haating, only one output should be shorted at a time with a maximum duration of 1.0 second each. Prolonged shorting of a High output may raise the chip temperature abova normal and permanent damage may resuit. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Commercial Units Min Typ Max tpp Input or Feedback to C_ = 50 pF, S1 Closed : . 7.1 10 ns Combinatorial Output tcoLK Clock to Registered C_ = 50 pF, S1 Closed 5.5 8 as Output or Feedback . tpzxg G Pin to Registered CL = 50 pF, Active High: $1 Open, 55 10 ns Output Enabled Active Low: 51 Closed . tpxzG G Pin to Registered Cy = SpF, From Vox: S1 Open, 4.0 10 ns Output Disabled From Vo.: $1 Closed , tp2x! Input to Combinatorial Output CL = 50 pF, Active High: $1 Open, 72 10 ns Enabted via Product Term Active Low: $1 Closed tpxz! input to Combinatorial Output CL = SpF, From Vox: St Open, 5.0 10 ns Disabled via Product Term From Voi: $1 Closed tRESET Power-Up to Registered Output High 1000 ns Test Load Schematic of Inputs and Outputs v9" EQUIVALENT INPUT TYPICAL OUTPUT St | Vee O O Yeo 2m { $ 12ka NOM S400 Now wr 7 > : > . < 4 P oi ; RZ I = INPUT O< TL/L9391-2 R1 = 200 R2 = 390 O OUTPUT TL/L/9391-24 2-35 Aywey Wd WNIpay- Uid-0220-Pin Medium PAL Family 7 ns Series (PAL16L8-7, PAL16R4-7, PAL16R6-7, PAL16R8-7) Absolute Maximum Ratings (note 1) It Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature 65C to + 150C Ambient Temperature with Power Applied 65C to + 125C Supply Voltage (Vic) (Note 2) O.5V to +7.0V Junction Temperature 65C to + 150C Input Voltage (Note 2} 1.5V to + 7.0V ESD Tolerance TBD Off-State Output Voitage Czap = 100 pF (Vo) (Notes 2 & 3) 1.5V to +5.5V Rzap = 150002 Input Current (Note 2) 30.0 mA to +5.0 mA Test Method: Human Body Model Output Current (Io.) +100 mA Test Specification: NSC SOP-5-028 Recommended Operating Conditions Commercial Symbol Parameter Units Min Nom Max Voc Supply Voltage 4.75 5 5.25 Vv Ta Operating Free-Air Temperature 0 25 75 C tw Clock Pulse Width Low 5.0 ns High 5.0 ns tsu Setup Time from Input 6.5 ns or Feedback to Clock . tH Hold Time of input after Clock 0 ns fotk Glock Frequency With Feedback 77 MHz (Note 4) Without Feedback 100 MHz Vz Register Preload Control Voltage 9.5 9.75 10.0 Vv Electrical Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Min Typ Max Units VIL Low Level Input Voltage (Note 5) 0.8 Vv Vir High Level Input Voltage (Note 5) 2 Vv Vic Input Clamp Voltage Voc = Min, | = 18mA 1.2 v lit Low Level Input Current (Note 6) Voc = Max, V; = 0.4V 250 BA lin High Level Input Current (Note 6) Voc = Max, Vj = 2.4V 25 pA II Maximum Input Current Voc = Max, V) = 5.5V 100 BA VoL Low Level Output Voltage Voc = Min, 0.5 v lo. = 24mA Vou High Level Output Voltage Voc = Min, 2.7 Vv lon = 3.2mA loz Low Level Off-State Output Voc = Max, Vo = 0.4V _50 A Current (Note 6) be lozH High Level Off-State Output Voc = Max, Vo = 2.4V 50 A Current (Note 6) Me los Output Short-Circuit Current Voce = 5V, Vo = OV _50 130 mA (Note 7) loc Supply Current Voc = Max, Outputs Open 125 180 mA C Input Capacitance Voc = 5.0V, V, = 2.0V 8 pF Co Output Capacitance Voc = 5.0V, Vo = 2.0V 8 pF Clio 1/0 Capacitance Voc = 5.0V, Vizq = 2.0V 8 pF 2-367 ns Series (PAL16L8-7, PAL16R4-7, PAL16R6-7, PAL16R8-7) Nate 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operatian is not guaranteed outside the specified recommended operating conditions. Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: Vo must not exceed Voc + 1V Note 4: fo. with feedback is derived as (tcLK + tsy)71. fcoLk without feedback is derived as (2tw)1. Note 5: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 6: Leakage current for bidiractional I/O pins is the worst case between Ij, and Ioz_ or between Iq and lozy. Note 7: To avoid invalid readings in other parameter tests it is preferable to conduct the Iog test last. To minimize internal heating, only one output should be shorted at a tima with a maximum duration of 1.0 second each. Prolonged shorting of a High output may raise the chip temperature above normal and permanent damage may result, Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions Commercial Units Min Typ Max tpp Input or Feedback to CL = 50 pF, $1 Closed 7.0 ns Combinatorial Output , ICLK Clock to Registered C, = 50 pF, S1 Closed Output or Feedback 3.0 88 ns tp2xG G Pin to Registered G,_ = 50 pF, Active High: $1 Open, 3.0 70 ns Output Enabled Active Low: $1 Closed , tpxzG G Pin to Registered CL = 5pF, From Voy: $1 Open, 40 70 ns Output Disabled From Vo_: $1 Closed . , tpzx| Input to Combinatorial Output C_ = 50 pF, Active High: S1 Open, 30 70 ns Enabied via Product Term Active Low: S1 Closed , texz) Input to Combinatorial Output Cy. = SpF, Fram Voy: $1 Open, 3.0 70 ns Disabled via Product Term Fram Vo : $1 Closed , , tsxeEw Skew between Registered 1.0 ns Outputs tRESET Power-Up to Registered Output High 1000 ns Test Load Schematic of Inputs and Outputs voo EQUIVALENT INPUT TYPICAL OUTPLT 5} | Voc oO Yee $ s a1 \ b 2 12kQ NOM. 2 400 NOM. OUTPUT yt ' a 302 Tr INPUT orf f+$ TL/L/9391-28 Ri = 200 y Re = 390 pO OUTPUT +4 TL/L/9391-29 2-37 Ayjwey WWd Wnipay Uld-0z20-Pin Medium PAL Family Test Waveforms Set-Up and Hold CLOCK Ht av tset-uP} tyoLo DATA VV wv INPUT TUT Kes TL/L/9391-3 Propagation Delay INPUT iN=PHASE OUTPUT (S1 CLOSED) OUT OF PHASE OUTPUT (S1 CLOSED) TL/L/9391 -5 Notes: Vr = 1.5V C, includes probe and jig capacitance. in the examples above, the phase relationships between inputs and outputs have Deen chosen arbitrarily. Switching Waveforms wwPuTS XOOK VAL PUT) AAA XVALIO INPUT XOX VaLib INPUTX XXX XIX Pulse Width HIGH=LEVEL PULSE INPUT LOW=LEVEL PULSE INPUT TL/L/9391-4 Enable and Disable ENABLING INPUT Xi ENABLE V7 DISABLE >| pe tzu truz-| + NORMALLY HIGH Voy, QUTPUT fv 7_ T NORMALLY LOW (S1 OPEN) | + fez tpuz i OUTPUT Oy (s1 cLosep) Yo ut ov 0.5V 0.5V +t f TLYL/9391-6 VY KKK tgy 14 ty ty CLOCK j & tox texze] j tezxe REGISTERED x OUTPUTS ANY INPUT PROGRAMMED VALID DISABLE VALID ENABLE x FOR TRESTATE CONTROL ; n PO texzi PZXI COMBINATORIAL OUTPUTS XXXXA y Power-Up Reset Waveform Sv TLAL/9391 -8 90% Voc / ov treser Yon REGISTERED OUTPUTS (G Low) Vou Yiu INTERNAL REGISTERS RESET TO LOGIC 0 -_ CLOCK * Vit *The clock input should not be switched from low to high until after time tReser- TL/L/9391-9 2-38Functional Description All of the 20-pin Medium PAL logic arrays consist of 16 com- plementary input lines and 64 product-term lines with a pro- grammable cell at each intersection (2048 cells). The prod- uct terms are organized into eight groups of eight each. Seven or aight of the product terms in each group connect into an OR-gate to produce the sum-of-products logic func- tion, depending on whether the output is combinatorial or registered. For the fuse-link PAL devices (all PAL devices excluding 0 and -7} an unprogrammed (intact) fuse establishes a con- nection between an input line (true or complement phase of an array input signal) and a product term; programming the fuse removes the connection. In the National Series-D/-7 vertical fuse PAL devices, a programmed vertical fuse cell astablishes a connection between an input line and a prod- uct term. A product term is satisfied (logically true) while all of the input lines connected to it (via unprogrammed fuses for the fuse-link devices, or by programming the corre- sponding cells for the vertical fuse devices) are in the high logic state. Therefore, if both the true and complement of at least one array input is connected to a product line, that product term is always held in the low logic state (which is the state of all product terms in an unprogrammed fuse-link device). Conversely, if all input lines are disconnected from @ product line, the product term and the resulting logic func- tion would be held in the high state (which is the state of all product terms in an unprogrammed National Series-D/-7 PAL device). The medium PAL family consists of four device types with differing mixtures of combinatorial and registered outputs. The 16L8, 16R4, 16R6 and 16R6 architectures have 0, 4, 6 and 8 registered outputs, respectively, with the balance of the 8 outputs combinatorial. All outputs are active-low and have TRI-STATE capability. Each combinatorial cutput has a seven product-term logic function, with the eighth product term being used for TRI-STATE control. A combinatorial output is enabled while the TRI-STATE product term is satisfied (true). Combinatori- al outputs also have feedback paths from the device pins into the logic array (except for two outputs on the 16L8). This allows a pin to perform bidirectional 1/0 or, if the asso- ciated TRI-STATE control product term were programmed to remain unsatisfied (always false), the output driver would remain disabled and the pin could be used as an additional dedicated input. Registered outputs each have an eight product-term logic function feeding into a D-type flip-flop. All registers are trig- gered by the high-going edge of the clock input pin. Ali reg- istered outputs are controlled by a common output enable (G) pin (enabled while low). The output of each register is also fed back into the logic array via an internal path. This provides for sequential logic circuits {state machines, coun- ters, etc.) which can be sequenced even while the outputs are disabled. Series-D/-7 Medium PAL devices reset all registers to a low state upon power-up (active-low outputs assume high logic levels if enabled). This may simplify sequential circuit design and test. To ensure successful power-up reset, Voc must rise monotonically until the specified operating voltage is attained. During power-up, the clock input should assume a valid, stable logic state as early as possible to avoid interfer- ing with the reset operation. The clock input should also remain stable until after the power-up reset operation is completed to allow the registers to capture the proper next state on the first high-going clock transition. For the National Series-D/-7 PAL device, during power-up, all outputs are held in the high-impedance state until DC power supply conditions are met (Vcc approximately 3.0V), after which they may be enabled by the TRI-STATE control product terms (combinatorial outputs) or the G pin (regis- tered outputs). Whenever Vcc goes below 3V (at 25C), the outputs are disabled as shown in Figure 7 below. Vor 3.0V 3.0 4 ty | _.| ty r ouTruTs < 5 TL/L/939125 Note: tz is less than 100 ns. FIGURE 1. Series-D Power-Up TRI-STATE Waveform In an unprogrammed National Series-D/-7 PAL device, no array inputs are connected to any product-term lines. There- fore, atl combinatorial outputs would be enabled and driving low logic levels (after power-up is completed). All ragisters would still initialize to the low state, but would become per- manenily set (low-level outputs, if enabled) following the first clock transition. As with any TTL logic circuits, unused inputs to a PAL de- vice should be connected to ground, Vo;, Vou, or resistive- ly to Voc. However, switching any input not connected to a product term or logic function has no effect on its output logic state. 2-39 Awe TW WNIpay Uid-0z20-Pin Medium PAL Family 20-Pin Medium PAL Family Block DiagramsDIP Connections PALI6Le PALIGR4 a a} [1] E2] a] [ve] [2] a] [+] Es] a) [=] [3] a) Lu] 73 7} [vo] 7a jf] [7] i] a] [=] 3] = [x} a] [1] [8] [=] a [u] 0] [+] a [} fy] = [1s] LIL A [x] Zo a [2] oe (1s) [Be 3 fu) oe [1] Du] @ L_,. Pv | L =, PIN NUM pI TL/L/9391 -10 TL/L/9391-11 20 [20] vor PALIGRS PALIGRS al [2] a0 iE] 3} [] (2) B] a] [1] iD] oO = [v] id CIE, petal ['] [5] a [] [8] J [u] 0] a [4] J [] 0] a [s] DIG = [1] DIL [x] o {19} [2 fo] o [18] [2 Af] | , PIN np Le PIN | TL/L/9391~12 TL/L/9391 -13 za] [20] [1] [-] [o]s we] [is] @ 3] [is] 2 2-4020-Lead PLCC Connection Conversion Diagram og _ 5 5 S - - e 8 o 20PIN DIP PIN> | 3 2 1 20 19 NUMBERS 3 2 1 20 19 ij4 4 18 18 | 1/0 or Q 1] 5 5 17 17] 1/0 or Q ile 6 20=LEAD PLCC 16 16} oor (TOP VIEW) i|7 7 15 15] 1/0 or Q tifa 8 14 14] 1/0 or Q 9 10 11 12 13 9 10 "1 12 13 ~ o - ao ao & 3 5 s $ & o TLAL/ 9301-14 Typical Registered Logic Function Without Feedback TL/L/93991~15 2-41 AjWe4 Wd WN|PEW Uld-0Z20-Pin Medium PAL Family Typical Registered Logic Function With Feedback Functional Description (continued) CLOCK FREQUENCY SPECIFICATION The clock frequency (fo_x) parameter specifies the maxi- mum speed at which a registered PAL device is guaranteed to operate. Clock frequency is defined differently for the two cases in which register feedback is used versus when it is not. In a data-path type appiication, where the logic func- tions fed into the registers are not dependent on register feedback from the previous cycle (i.e.-based only on exter- nal inputs), the minimum required cycle period (fo_K- 1 with- out feedback) is defined as the greater of the minimum clock period (tw high + tw low) and the minimum data window period (tsu + ty). This assumes optimal alignment between data inputs and the clock input. In sequential logic applications such as state machines, the minimum required cycle period {fo_K1 with feedback) is defined as toy. + tsu. This provides sufficient time for outputs from the regis- ters ta feed back through the logic array and set-up on the inputs to the registers before the end of each cycle. Output Register Preload in the 20-pin Medium PAL family, register preload is avail- able on the Series-D/-7 PAL devices only. TL/L/9391-16 The output register preload feature simplifies device testing since any state may be loaded into the registers at any time during the functional test sequence. This allows complete verification of sequential logic circuits, including states that are normally impossible or difficult to reach. Register pre- load is not an operational mode and is not intended for board level testing because elevated voltage levels are re- quired. The programming system normally provides the pre- load capability as part of its functional test facility. The preload function allows the register to be loaded direct- ly and asynchronously with any desired pattern. These verti- cal-fuse devices provide two register preload operations: 1. All registers can be reset to the low state (high-level out- puts) by applying the elevated control voltage (Vz) to in- put Pin 2* for time tp (Figure 2a). 2. Selected registers can be set to the high state (low-level outputs) as follows (Figure 2b): a. All registered outputs are disabled by raising the G in- put Pin 1* to Vip. b. After time tp, the selected registered output pins are raised to the elevated control voltage (Vz) for time tp to set the corresponding registers. *Applies to both DIP and PCG packages for 20-pin PAL devices. Vz Vin PIN 2 Vip by ALL REGISTERED ou OUTPUTS / ZL, / Vo. TL/L/9391-26 a) To Reset All Registers Vin typ e] \; SELECTED REGISTERED OUTPUT PIN OL TL/L/9391 -27 b) To Set Selected Registers Note: Vz = 9.5V to 10.0V, ip min. = 500 ns, FIGURE 2. Series-D Register Preload Waveforms 2-42Security Fuse Security fuses are provided on all National PAL devices which, when programmed, inhibit any further programming or verifying operations. This feature prevents direct copying of proprietary iogic patterns. The security fuses should be programmed only after programming and verifying all other device fuses. Register preload is not affected by the securi- ty fuses. Design Development Support A variety of software tools and programming hardware is available to support the development of designs using PAL products. Typical software packages accept Boolean logic equations to define desired functions. Most are available to run on personal computers and generate JEDEC-compati- ble fuse maps. The industry-standard JEDEC format en- sures that the resulting fuse-map files can be down-loaded into a variety of programming equipment. Many software packages and programming units support a wide variety of programmable logic products as well, The PLANTM software package from National Semiconductor supports alt pro- grammable logic products available from National and is ful- ly JEDEC-compatible. PLAN software also provides auto- matic device selection based on the designer's Boolean logic equations. In National Series-D/-7 PAL devices, logical and physical connections between array input lines and product-term lines are established when vertical fuse cells are pro- grammed. This is opposite to other PAL products based on fusible links in which connections are established when Ordering Information Output Type: fuses are left unprogrammed (intact). This difference is compensated by the vertical-fuse PAL programming algo- rithm so that the user's design development process looks the same. {The only functional difference due to vertical- fuse technology is the behavior of unprogrammed" devic- es.) The JEDEC programming maps produced by PAL de- velopment software for all Medium PAL devices denote a connection with a 0, and a non-connection with a 4. The programming algorithms for most fuse-link PLDs program fuses where ones are located in the map to re- move corresponding connections, whereas the algorithm for National Series-D PAL products automatically compensates by programming vertical-fuse cells where zeroes are locat- ed in the map to establish connections. Therefore, the sarne JEDEC map representing the user's desired logic equations produces the same functional results when using either PAL technology. The user need only provide the appropriate de- vice code and/or adapter for the programming equipment to invoke the proper programming algorithm. Only program- mers with the certified National Series-D/-7 vertical-fuse PAL programming algorithm can be used to program these vertical-fuse devices. Detailed logic diagrams showing ali JEDEC fuse-map ad- dresses for the 20-pin Medium PAL family are provided for direct map editing and diagnostic purposes. For a list of current software and programming support tools available for these devices, please contact your local National Semi- conductor sales representative or distributor. If detailed specifications of the PAL programming algorithm are need- ed, please contact the National Semiconductor Programma- ble Device Support Department. Programmable Array Logic Family Number of Array Inputs Ajwey Td wnipayZ Uld-0Z H = Active High L = Active Low C = Complementary R = Registered X = Exclusive-OR Ragistered P = Programmable Polarity Number of Registered Outputs (or total outputs if non-registered) Speed/Power Version: No Symbol = 35 ns A = 25ns A2 = 35ns, Half Power Lateral Fuse B = i5ns B2 = 25ns, Half Power D = 10ns Vertical Fuse 7 =7ns8 Package Type: N = 20-Pin Plastic DIP J = 20-Pin Ceramic DIP V = 20-Lead Plastic Chip Carrier Temperature Range: C = Commercial (0C to + 75C) M = Military ( 55C to + 125C} at wo ot o z 2 PAL 2-4320-Pin Medium PAL Family Logic DiagramPAL16L8 a NUMBERS INPUT LINE PRODUCT LINE FIRST CELL NUMBERS NUMBERS 02 4 6 819 1214 1618 2022 2426 2830 1{S 75] 7 YO yit 13415 [179 [21 1 1 1024, 1088 | 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, 1856, 1920 1984! 9 4l6l sliolzhal 2 10] '135-7-9 4 1315 1719 2123 2527 29 31 JEOQEG Logic Array Cell Number = Product Line First Cell Number + Input Lina Number PIN NUMBERS Voc } A. 20 18 17 16 15 14 13 12 TL/L/9391-19 2-44Logic DiagramPAL16R4 y PN NUMBERS INPUT LINE PIN mee PRODUCT LINE FIRST CELL NUMBERS NUMBERS Yoo 02 4 6 8 10 ey s\oyn oo 24 26 Fo ee HPS ypS/7 9] 9 ]2 1 1 20 19 2 18 5 17 4 16 5 15 6 14 7 13 8 12 g os O15 5 7g 11 15.15 1719 2123 2597 29 31 " TL/L/9391 -20 JEDEC Lagic Array Call Number = Product Line First Celi Number + Input Line Number 2-45 Ajywmey Fwd WNIpaW Uld-0220-Pin Medium PAL Family Logic DiagramPAL16R6 pr" NUMBERS INPUT LINE PIN NUMBERS PRODUCT LINE FIRST CELL NUMBERS NUMBERS Veo A209 02 4 6 810 1214 1618 2022 2426 28 30 1] 3 [S77 [9 pit [13/15 p17 p19 421 1 { 19 18 17 16 13 12 g O}2 416] s|iol r2ital 1 2 OJ], 435 7-9 11 1315 1719 2123 2527 2931 " TLYL/9391-21 JEDEG Logic Array Cell Number = Product Line First Cell Number + input Line Number 2-46Logic DiagramPAL16R8 Ps NUMBERS INPUT LINE PIN NUMBERS PRODUCT LINE FIRST CELL NUMBERS NUMBERS eee * 0 2 4 6 8 10 1214 1618 2022 2426 2830 173 (577 [9911 [13p15 (17/19 421 31 1 17 14 13 12 9 O12 4 101 12/141 161181 2olzal 2 10. 1357 911 1315 1719 2123 2527 29 31 " TL/L19391-22 JEDEC Logic Array Cel Number = Product Line First Gell Number + Input Line Number 2-47 Awe TW WNIpaW Uld-0Z