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Am29BL162C
Data Sheet
T
his Data Sheet states A MD’s cur rent specific ations regard ing the Products descr ibed herei n. This Data Sheet ma y
b
e revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22142 Rev: FAmendment/+5
Issue Date: November 22, 2002
Refer to AMD’s Website (www.a md.com) for the latest information.
Am29BL162C
16 Megabit (1 M x 16-Bit)
CMOS 3.0 Vol t-only Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
■32 words sequential with wrap around (linear
32), bottom boot
■One 8 Kword, two 4 Kword, one 112 Kword, and
seven 128 Kword sectors
■Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■Read access tim es
Burst access times as fast as 17 ns at industrial
temperature range (18 ns at extended
temperature range)
Initial/random access times as fast as 65 ns
■Alterable burst length via BAA# pin
■Power dissipation (typical)
— Burst Mode Read: 15 mA @ 25 MHz,
20 mA @ 33 MHz, 25 mA @ 40 MHz
— Program/Erase: 20 mA
— Standby mode, CMOS: 3 µA
■5 V-tolerant data, address, and control signals
■Sector Protection
— Implemented using in-system or via
programmi ng equi pm ent
— T emporary Sector Unprotect feature allows code
changes in previously locked sectors
■Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■Minimum 1 million erase cycle guarantee
per sector
■20-year data retention
■CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigur e for different Flas h devic es
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— Backward-compatible with AMD Am29LVxxx
and Am29Fxxx flash memories: powers up in
asynchronous mode for system boot, but can
immediately be placed into burst mode
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operati on compl etion
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■Package Option
— 56-pin SSOP
2 Am29BL162C November 22, 2002
GENERAL DESCRIPTION
The Am29BL162C is a 16 Mbit, 3.0 Volt-only burst
mode Flash memory devices organized as 1,048,576
words. The device is offered in a 56-pin SSOP
package. These devices are designed to be pro-
grammed in-system with the standard system 3.0-volt
VCC supp ly. A 12.0 -v ol t VPP or 5.0 VCC is not required
for program or erase operations. The device can also
be programmed in standard EPROM programmers.
The dev ice offers acces s times of 65 , 70, 9 0, and 120
ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Burst Mode Features
The Am29BL162C offers a Linear Burst mode—a
32 word sequential burst with wrap around—in a
bottom boot configuration only. This devices require
additional control pins for burst operations: Load
Burst Address (LBA#), Burst Address Advance
(BAA#), and Clock ( CLK). This implementatio n allows
easy inte rface with minimal g lue logic to a wide range
of microprocessors/microcontrollers for high perfor-
mance read operations.
AMD Flash Memory Features
Each device requires only a single 3.0 volt power
supply for both read and write functions. Internally
generate d and reg ulated voltages are prov ided for the
program and erase operations. The I/O and control
signals are 5V toler ant.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
tro l s the erase and pro gr am mi n g ci rcu it ry. W r i t e cyc le s
also internally latch addresses and data needed for the
programmi ng and erase opera tions. Reading d ata out
of the device is similar to reading from other Flash or
EPROM devices.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device a utomati call y times th e eras e puls e widths an d
verifies proper cell margin.
The host system can detect whether a program or
erase o peration i s compl ete by ob serving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggl e) status bits. After a program or erase cycle
has been c om ple ted, the devic e is rea dy to r ead arr ay
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC
detector that au tomatica ll y in hi bi ts wr i te op er a tio ns d ur-
ing po wer tran sitio ns. Th e hardware sector protection
feature disab les both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put eras e o n hold for any period of tim e t o
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operatio n
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system res et circuitry. A system res et would thus also
reset the device, e nabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
address es have been s table for a specified am ount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality , reliability and cost effectiveness.
The device electri cally erases all bits within a sector
s imu ltan eousl y v ia Fo wler -Nor dheim tunneling. The
data is programmed using hot electron injection.
November 22, 2002 Am29BL162C 3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations .......................................................9
Requirements for Reading Array Data Array in Asynchronous
(Non-Burst) Mode................................................................... 10
Requirements for Reading Array Data in Synchronous
(Burst) Mode ...........................................................................10
Burst Suspend/Burst Resume Operations.............................. 11
IND# End of Burst Indicator ....................................................11
Writing Commands/Command Sequences ............................11
Program and Erase Operation Status ....................................11
Standby Mode ........................................................................11
Automatic Sleep Mode ...........................................................11
RESET#: Hardware Reset Pin ...............................................11
Output Disable Mode ..............................................................12
Table 2. Sector Address Table ........................................................12
Autoselect Mode..................................................................... 13
Table 3. Am29BL162C Autoselect Codes (High Voltage Method) ..13
Sector Protection/Unprotection ...............................................13
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 14
Temporary Sector Unprotect ..................................................15
Figure 2. Temporary Sector Unprotect Operation........................... 15
Hardware Data Protection. . . . . . . . . . . . . . . . . . 15
Low VCC Write Inhibit ..............................................................15
Write Pulse “Glitch” Protection ...............................................15
Logical Inhibit ..........................................................................15
Power-Up Write Inhibit ............................................................15
Common Flash Memory Interface (CFI) . . . . . . .16
Table 4. CFI Query Identification String ..........................................16
Table 5. System Interface String .....................................................16
Table 6. Device Geometry Definition ..............................................17
Table 7. Primary Vendor-Specific Extended Query ........................17
Command Definitions . . . . . . . . . . . . . . . . . . . . . 18
Reading Array Data in Non-burst Mode .................................18
Reading Array Data in Burst Mode .........................................18
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns
tIACC,18nst
BACC Parameters.................. ............. ........................ 19
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns
tIACC,24nst
BACC Parameters.................. ............. ........................ 19
Reset Command .....................................................................19
Autoselect Command Sequence ............................................19
Program Command Sequence ...............................................20
Unlock Bypass Command Sequence .....................................20
Figure 5. Program Operation.......................................................... 21
Chip Erase Command Sequence ...........................................21
Sector Erase Command Sequence ........................................21
Figure 6. Erase Operation............................................................... 22
Erase Suspend/Erase Resume Commands ...........................22
Asynchronous Mode ...............................................................22
Burst Mode .............................................................................22
General ...................................................................................22
Command Definitions............................................................. 24
Table 8. Am29BL162C Command Definitions ............................... 24
Write Operation Status . . . . . . . . . . . . . . . . . . . . 25
DQ7: Data# Polling .................................................................25
Figure 7. Data# Polling Algorithm.................................................. 25
RY/BY#: Ready/Busy# ............................................................26
DQ6: Toggle Bit I ....................................................................26
DQ2: Toggle Bit II ...................................................................26
Reading Toggle Bits DQ6/DQ2 ...............................................26
DQ5: Exceeded Timing Limits ................................................27
DQ3: Sector Erase Timer .......................................................27
Figure 8. Toggle Bit Algorithm........................................................ 27
Table 9. Write Operation Status ..................................................... 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 29
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents).............................................................................. 31
Figure 12. Typical ICC1 vs. Frequency........................................... 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. Test Setup..................................................................... 32
Table 10. Test Specifications ...................... ............. ...................... 32
Key to Switching Waveforms ..................................................32
Figure 14. Input Waveforms and Measurement Levels................. 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. Conventional Read Operations Timings....................... 35
Figure 16. Burst Mode Read.......................................................... 35
Hardware Reset (RESET#) ....................................................36
Figure 17. RESET# Timings.......................................................... 36
Erase/Program Operations .....................................................37
Figure 18. Program Operation Timings.......................................... 38
Figure 19. Chip/Sector Erase Operation Timings.......................... 39
Figure 20. Data# Polling Timings (During Embedded Algorithms). 40
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 40
Figure 22. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations............................................................ 41
Figure 23. Temporary Sector Unprotect Timing Diagram.............. 41
Figure 24. Sector Protect/Unprotect Timing Diagram.................... 42
Alternate CE# Controlled Erase/Program Operations ............43
Figure 25. Alternate CE# Controlled Write Operation Timings...... 44
Erase and Programming Performance . . . . . . . 45
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 45
SSOP Pin Capacitance. . . . . . . . . . . . . . . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
SSO056—56-Pin Shrink Small Outline Package ....................46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision A (September 1998) .................................................47
Revision B (December 1998) ..................................................47
Revision C (December 1998) .................................................47
Revision D (May 17, 1999) .....................................................47
Revision D+1 (July 2, 1999) ...................................................47
Revision E (November 2, 1999) ..............................................47
Revision F (June 20, 2000) .....................................................48
Revision F+1 (November 21, 2000) ........................................48
Revision F+2 (July 22, 2002) ..................................................48
Revision F+3 (August 19, 2002) .............................................48
November 22, 2002 Am29BL162C 5
PRODUCT SELEC TOR GUIDE
Note:
1. See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Par t Number Am29BL162C
Speed
Option Regulated Voltage Range: VCC =3.0–3.6 V 65R 70R 90R 120R
Te mperature Range: Industrial (I), Extended (E) I E I, E I, E I, E
Max access time, ns (tACC)657090120
Max CE# access time, ns (t CE)657090120
Max burst ac cess time, ns (tBACC) 1718242626
Burst
State
Counter
Burst
Address
Counter
LBA#
BAA#
CLK
VCC
VSS
State
Control
Command
Register PGM Voltage
Generator
VCC Detector Timer
Erase Voltage
Generator
Input/Output
Buffers IND#
Buffer
Sector
Switches
Chip Enable
Output Enable
Logic
Y-Gating
Cell Matrix
Address Latch
Y-Decoder
X-Decoder
Data Latch
RESET#
RY/BY# IND#
STB
STB
A0–A19
A0–A2
A0–A2
A3, A4
A3, A4
CE#
OE#
WE#
DQ0–DQ15
A0–A4
6 Am29BL162C November 22, 2002
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
WE#
R
ESET#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
NC
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
LBA
#
VCC
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
NC
VSS
DQ1
5
DQ7
DQ1
4
DQ6
DQ1
3
DQ5
23
24
25
26
27
28
DQ10
DQ3
DQ11
VSS
CLK
BAA#
34
33
32
31
30
29
DQ1
2
DQ4
VCC
VCC
IND
#
NC
56-Pin SSOP
November 22, 2002 Am29BL162C 7
PIN CONFIGURATION
A0–A1 9 = 20 addresse s
DQ0–DQ1 5 = 16 data inputs/ou tpu ts
CE# = Chip Enable Input. This signal shall be
asynchronous relative to CLK for the
burst mode.
OE# = Output Enable Input. This signal shall
be asynchronous relative to CLK for
the burst mode.
WE# = Write enable. This signal shall be
asynchronous relative to CLK for the
burst mode.
VSS = Device ground
NC = No connect. Pin not connected
internally
RY/BY# = Ready Busy output
CLK = Clock Input that can be tied to the
system or microprocessor clock and
provides the fundamental timing and
internal operating frequency. CLK
latches input addresses in conjunction
with LBA# input and increments the
burst address with the BAA# input.
LBA# = Load Burst Address input. Indicates
that the valid address is present on the
address inputs.
LBA# Low at the rising edge of the
clock latches the address on the
address inputs into the burst mode
Flash device. Data becomes available
tPACC ns of initial access time after the
rising edge of the same clock that
latches the address.
LBA# High indicates that the address
is not valid
BAA# = Burst Address Advance input.
Increments the address during the
burst mode operation
BAA# Low enables the burst mode
Flash device to read from the next
word when gated with the rising edge
of the clock. Data become s av ail able
tBACC ns of burst access time after the
rising edge of the clock
BAA # High prevents the rising edge of
the clock from advancing the data to
the next word output. The output data
remains unchanged.
IND# = Highest burst counter address
reached. IND# is low at the end of a
32-word burst sequence (when word
Da + 31 is output). The output will
wrap around to Da on the next CLK
cycle (with B AA# low).
RESET# = Hardware reset input
Note: The a ddress, data , and contro l si gnals (R Y/BY#, LBA,
BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant.
LOGIC SYMBOL
20 16
DQ0–DQ15
A0–A19
CE#
OE#
WE#
RESET#
CLK
RY/BY#
IND#
LBA#
BAA#
8 Am29BL162C November 22, 2002
ORDERING INFORMATION
Standard Products
AMD st andard pr oduct s are a vail able in severa l pa ckages a nd op erating r anges . The ord er num ber (Valid Comb i-
nation) is formed by a combination of th e elements below.
For information on full voltage range options (2.7–3.6 V),
please contact AMD.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Con sult the local AMD sale s
of fice to conf irm availabili ty of speci fic valid c ombinations an d
to check on newly released combinations.
Am29BL162C B 65R Z I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E= Extend ed ( –55°C to +125° C )
PACKAGE TYPE
Z= 56- Pin Shr ink Sma ll Outline Packa ge ( SSOP 056)
SPEED OPTION
See Produ ct Sel ec to r Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
B= Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29BL162C
16 Megabit (1 M x 16-Bit)
CMOS 3. 0 Volt-only High Performanc e Bur st M ode Flash Mem or y
Valid Combinations
Am29BL162CB-65R ZI, ZE
Am29BL162CB-70R ZI, ZE
Am29BL162CB-90R ZI, ZE
Am29BL162CB-120R ZI, ZE
November 22, 2002 Am29BL162C 9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command . The conte nts of th e
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device . Tabl e 1 lists the d evice b us operation s, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend:
L = Logic Lo w = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Notes:
1. Addresse s are A19:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Operation CE# OE# WE# RESET# CLK LBA# BAA# Addresses
(N ote 1) Data
(DQ0–DQ15)
Read L L H H X X X AIN DOUT
Write L H L H X X X AIN DIN
Standby VCC ±
0.3 V XXVCC ±
0.3 V X X X X HIGH Z
Output Disable L H H H X X X HIGH Z HIGH Z
Reset X X X L X X X X HIGH Z
Sector Protect (Note 2) L H L VID XXX
Sector Address,
A6 = L , A1 = H,
A0 = L DIN
Sector Un pr ot ect (Note 2) L H L VID XXX
Sector Address,
A6 = H, A1 = H,
A0 = L DIN
Temporary Sector Unprot ect X X X VID XXX AIN HIGH Z
Burst Read Operations
Load Start ing Bur st Add re ss L X H H L H AIN X
Advance Bu rs t to Next Address (no
data pre sen t ed on the data bus) L H H H H L X HIGH Z
Advance Burst to Next address
(appropriate data presented on the
data bus) LLH H HL X Data Out
DQ0-DQ15
Terminate Curre nt Burst Read Cycle H X H H X X X HIGH Z
Terminate Curre nt Burst Read Cycle;
Start New Burst Read Cycle LXH H LH AIN X
Burst Suspend (all data is retain ed
internall y i n th e device) L H H H X H H X HIGH Z
Burst Resume (same data as Burst
Suspend) LLH H HH X Data Out
DQ0–DQ15
Burst Resume (incremented data from
Burst Suspend) LLH H HL X Data Out
DQ0–DQ15
10 Am29BL162C November 22, 2002
Requirements for Reading Array Data
Array in Asynchronous (Non-Burst) Mode
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
contro l and se lects t he device . OE# is the output contro l
and ga te s a rr ay data to th e o utp ut pi ns. WE# sh ould r e-
main at VIH.
Addres s access time (t ACC) is equal to the dela y from
stable addr es ses to val id out put dat a. The ch ip enable
access time (tCE) is the delay from the stable
addresses and stable CE# to valid data at the output
pins. The output enable access tim e is th e delay from
the fa lling edge o f OE # to valid data a t t he ou tput pi ns
(assuming the addresses have been stable for at least
tACC–tOE time).
The internal state machine is set for reading array
data in the upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the com-
mand register con tents ar e al tered.
See “Reading Array Data in Non-burst Mode” for more
information. Refer to the AC Read Operations table for
timing specifications and to Figure 15 for the timing di-
agram. ICC1 in the DC Characteristics table represents
the active current specification for reading array data.
Requirements for Reading Array Data in
Synchronous (Burst) Mode
The device offers fast 32-word sequential burst reads
and is used to support microprocessors that implement
an instruction prefetch queue, as well as large data
transfers during system configuration.
Three additional pins—Load Burst Address (LBA#),
Burst Address Advance (BAA#), and Clock (CLK)—
allow inter facing to micropr ocess ors and mic rocont rol-
lers wi th mini mal gl ue lo gi c. Bu rst mode rea d i s a sy n-
chronous operation tied to the rising edge of CLK. CE#,
OE#, and WE# are asynchronous (relative to CLK).
When the device is in asynchronous mode (after
power-u p or RESET# pu lse), any signal s on the CLK,
LBA#, a nd B AA # inp uts a re i gn or ed. The de vi c e oper -
ates as a conventional flash device, as described in the
previous section.
To enable burst mode operation, the system must issue
the Burst Mode Enable command sequence (see Table
8). After the device has entered the burst mode, the
system must assert Load Burst Address (LBA#) low for
one clock period, which loads the starting address into
the device. The first burst data is available after the
initial access time (tIACC) from the rising edge of the
CLK that loads the burst address. After the initial
access , subseq uen t burst data is av ailable tBACC after
each rising edge of CLK.
The device increments the address at each rising edge
of the cloc k cycl es while B AA# is asser ted low. Th e 5-
bit burst address counter is set to 00000b at the starting
address. When the burst address counter is reaches
11111b, the device outputs the last word in the burst
sequence, and outputs a low on IND#. If the system
continue s to as sert BAA# , on the ne xt C LK the d evic e
will outpu t the data for th e startin g address—th e burst
address counter will have “wrapped around” to 00000b.
For example, if the initial address is xxxx0h, the data
order will be 0-1-2-3.....28-29-30-31-0-1...; if the initial
address is xxxx2h, the data order will be 2-3-4-5.....28-
29-30- 31-0-1-2- 3...; if the init ial add ress is xxxx8 h, the
data order will be 8-9-10-11.....30-31-0-1-2-3-4-5-6-7-
8-9....; and so on. Data will be repeated if more than 32
clocks are supplied, and BAA# remains asserted low.
A burst mode read operation is terminated using one of
three methods:
— In the first method, CE# is asserted high. The
device in this case remains in burst mode;
asserting LBA# low terminates the previous
burst read cycle and starts a new burst read
cycle with the address that is currently valid.
— In the second method, the Burst Disable
command sequence is written to the device. The
device halts the burst operation and returns to
the asynchronous mode.
— In the third method, RESET# is asserted low . All
opertations are immediately terminated, and the
device will revert to the asynchronous mode.
Note that writ ing the r eset co mmand will not termi nate
the burst mode.
November 22, 2002 Am29BL162C 11
Burst Suspend/Burst Resu me Operations
The device offers Burst Suspend and Burst Resume
operations. When both OE# and BAA# are taken high,
the device removes (“suspends”) the data from the
outputs (because OE# is high), but “holds” the data
internally. The device resumes burst operation when
either OE# and/or BAA# is asserted low. Asserting the
OE# only causes the device to present the same dat a
that was hel d during the Bur st Suspend oper ation. As
long as BAA# is high, the device will continue to output
that word of data. Asserting both OE# and BAA# low
resumes the burst operation, and on the next rising
edge of CLK, increments the counter and outputs the
next word of data.
IND# End of Burst Indicator
The IND# output signal goes low when the device is
ouputting the last word of a 32-word burst sequence
(word Da +31). When the starting ad dress was lo aded
with LBA#, the 5-bit burst address counter was set to
00000b. The counter increments to 11 11 1b on the 32nd
word in the burs t s eque nce. If the syste m conti nue s t o
assert BAA# low, on the next CLK the device will output
the starting address data (Da). The burst address
counter will be again set to 00000b, and will have
“wrapped around.”
W riting Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing sec-
tors of memory), the system must drive WE# and CE# to
VIL, an d OE # to VIH.
The d evice featur es an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un-
lock By pass m od e, on ly t wo w rit e c ycle s are re qu ire d to
program a word, instead of four. The “Program Com-
mand Sequence” section has details on programming
data to the device using both standard and Unlock By-
pass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. The “Command Definitions” section has details
on erasing a sector or the entire chip, or suspending/re-
suming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. R ef e r t o t h e “Aut o select Mode ” an d “Re set C o m-
mand” sections f or more informat ion.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check t he status of the op eration by reading t he status
bit s on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation Sta-
tus” for more information, and to “ AC Characteristics” for
tim ing di ag ram s .
Standby Mode
When th e sy st em i s not r e ad ing o r wri ti ng to th e d evi ce,
it can place the device in the standby mode. In this
mode, cu rrent co nsumptio n is greatly red uced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the st andb y curr ent wi ll be gr eat er. Th e devi ce req uir es
standard a ccess time (tCE) fo r read access when the de-
vice is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
In the DC Characteristics table, ICC3 and ICC4 represents
the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this m ode wh en addres ses re main st able for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output d ata is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin to VIL for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted
shoul d be rei niti at ed once the devi ce is ready to ac cep t
anoth er comm an d sequ en ce , t o ensu r e dat a in te gri t y.
12 Am29BL162C November 22, 2002
Current is reduced for the duration of the RESET#
pulse . When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL b ut no t with in VSS±0.3 V, the standby current will
be gr ea te r.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
war e fr om t he F las h me mo ry.
If RES ET# i s a s se rte d durin g a p rogram o r era s e op er -
ation, the R Y/BY# pin remains a “0” (busy) until the inter-
nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset op-
erati on is co m p le te. If RE SE T# is a ss e rt ed wh en a p r o-
gram or erase oper ation is not execut ing (RY/BY# pin is
“1”), the reset operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET# pin returns to VIH.
Refer t o the AC Cha racterist ics tables for RESET # pa-
rame te rs an d t o Fig ur e 17 fo r th e ti ming diagra m.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disab le d. The ou tput pins a re placed in th e h ig h i m pe d-
ance stat e.
Table 2. Sector Address Table
Sector Sector Size A19 A18 A17 A16 A15 A14 A13 A12 Address Range
SA08 Kwords0000000X00000h–01FFFh
SA14 Kwords0000001002000h–02FFFh
SA24 Kwords0000001103000h–03FFFh
SA3 112 Kwords 0 0 0 00100–11111 04000h–1FFFFh
SA4128 Kwords001XXXXX20000h–3FFFFh
SA5128 Kwords010XXXXX40000h–5FFFFh
SA6128 Kwords011XXXXX60000h–7FFFFh
SA7128 Kwords100XXXXX80000h–9FFFFh
SA8128 Kwords101XXXXXA0000h–BFFFFh
SA9128 Kwords110XXXXXC0000h–DFFFFh
SA10128 Kwords111XXXXXE0000h–FFFFFh
November 22, 2002 Am29BL162C 13
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the au toselect code s can al so be acces sed in-sys tem
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 1. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 1 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 8. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Table 3. Am29BL162C Autoselect Codes (High Voltage Method)
L = Logic Lo w = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 8.
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and e rase op eration s in an y sect or. The ha rd-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protectin g
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection/unprotection can be implemented via
two methods.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 24 shows the timing diagram. This
method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect
write cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-onl y AMD flas h devices . De-
tails on this method are provided in a supplement, pub-
lication number 22240. Contact an AMD representative
to request a copy.
Description CE# OE# WE#
A19
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0 DQ15 to
DQ0
Manufacturer ID: AMD L L H X X VID X L X L L 0001h
Device ID:
Am29BL162CB
(Bottom Boot Block) LLHXXV
ID X L X L H 2203h
Sector Protection
Verification LLHSA
XV
ID X L X H L 0001h (protected)
XV
ID X L X H L 0000h (unprotected)
Burst Mode Statu s L L H X X VID XLXHH
0000h
(non-burst mo de)
0001h
(burst mo de)
14 Am29BL162C November 22, 2002
Figure 1. In-System Sector Protect/Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Secto
r
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
S
ector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
November 22, 2002 Am29BL162C 15
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Secto r Unpro tect mo de is ac tiva ted by setti ng the R E-
SET# p in to VID. Durin g this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 23 shows the timing diagrams, for this feature.
HARDWARE DATA PROTECTION
The comm and seq uenc e requirement of unlock cycl es
for programming or erasing provides data protection
against inadvertent writes (refer to Table 8 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or progra mming, which m ight otherwis e be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a wr ite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept c ommands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
F
igure 2. Temporary Sector Unprote ct Operatio
n
16 Am29BL162C November 22, 2002
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-indepen-
dent, JEDE C I D-independen t, and forward- and b ack-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array
data. The system can read CFI information at the
addresses given in Tables 4–7. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 4–7. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
To terminate reading CFI data, the system must write
the reset command.
Table 4. CFI Query Identification String
Addresses Data Description
10h
11h
12h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
15h
16h 0040h
0000h Addr ess for Prima ry Extended Table
17h
18h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
Table 5. System Interface String
Addresses Data Description
1Bh 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single word write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0005h Max. timeout for word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max. timeout per indiv idu al blo ck erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
November 22, 2002 Am29BL162C 17
Table 6. Device Geometry Definition
Addresses Data Description
27h 0015h Device Size = 2N byte
28h
29h 0001h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 0000h
0000h Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch 0004h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0000h
0000h
0040h
0000h
Erase Block Regi on 1 Inform ati on
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
0001h
0000h
0020h
0000h
Erase Block Regi on 2 Inform ati on
35h
36h
37h
38h
0000h
0000h
0080h
0003h
Erase Block Regi on 3 Inform ati on
39h
3Ah
3Bh
3Ch
0006h
0000h
0000h
0004h
Erase Block Regi on 4 Inform ati on
Table 7. Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 0031h Major version number, ASCII
44h 0030h Minor version number, ASCII
45h 0000h Address Sensitive Unlock
0 = Requir ed, 1 = Not Required
46h 0002h Erase Susp end
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0004h Sector Protect/Unprotect scheme
4Ah 0000h Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh 0003h Burst Mode Type
00 = Not Supported, 01 = 4 word Linear Burst, 02 = 8 Word linear Burst,
03 = 32 Word Linear Burst, 04 = 4 Word Interleave Burst
4Ch 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
18 Am29BL162C November 22, 2002
COM MAND DE F I N I T I O N S
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 8 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them i n the im proper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of
WE# or CE#, whichever happens later. All data is
latched o n the rising edge o f WE# or CE#, whichever
happens first. Refer to the appropriate timing diagrams
in the AC Characteristics section.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same excepti on.
See “Erase Suspend/Erase Resum e Commands” for
more information on thi s mod e.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand ” section, n ext.
See also “Requirem ents for Re adin g Arr ay Data Ar ray in
Asynchronous (Non-Burst) Mode” in the “Key to Switch-
ing Waveforms” section for mo re information. The Read
Operations table provides the read parameters, and Fig-
ure 1 5 show s t he ti ming diag ram.
Reading Array Data in Burst Mode
The devic e powers up i n the non-bur st mode. To read
array data in burst mode, the system must write the
four-cycle Burst Mode Enable command sequence
(see Table 8). The device then enters burst mode. In
addition to asser ting CE#, O E#, and W E# control sig-
nals, burst mode operation requires that the system
provide appropriate LBA#, BAA#, and CLK signals. For
successful burst mode reads, the following events
must occur (refer to Figures 3 and 4 for this discus-
sion):
1. The system asserts LBA# l ow, indicati ng to the de-
vice that a va lid ini tial bu rst addre ss is available on
the address bus. LBA# must be kept low until at
least the next rising edge of the CLK signal, upon
which the device loads the initial burst address.
2. The system returns LBA# to a logic high. The de-
vice requires that the next rising edge of CLK occur
with LBA# high for proper burst mode operation.
Typica lly, the initial n umber of CLK cy cl es d epe nds
on the clock frequency and the rated speed of the
device.
3. After the ini tial data has been read, the system as-
serts BAA# low to indicate it is ready to read the re-
maining burst read cycles. Each successive rising
edge of the CLK signal then causes the flash device
to incremen t the bur st addre ss and outp ut sequ en-
tial burst data.
4. When the device outputs the last word of data in the
32-word burst mode read sequence, the device out-
puts a logic low on the IND# pin. This indicates to
the system that the burst mode read sequence is
complete.
5. To exit the burst mode, the system must write the
four-cycle Burst Mode Disable command se-
quence. The device will also exit the burst mode if
powered down or if RESET# is asserted. The de-
vice will not exit the burst mode if the reset com-
mand is written.
November 22, 2002 Am29BL162C 19
Figure 3. Burst Mode Read with 40 MHz CLK, 65 ns tIACC, 18nst
BACC Parameters
Figure 4. Burst Mode Read with 25 MHz CLK, 70 ns tIACC, 24nst
BACC Parameters
Reset Command
Writing the reset command to the device resets the de-
vice to rea ding array da ta. Addres s bits are don ’t care
for this command.
The reset command may be written between the se-
quence cy cl es in an er as e co mm and s equ ence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
howeve r, the devic e igno res res et com mands un til the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to r eturn to reading array data (also appli es
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the res et command returns th e device to read-
ing array data (also applies during Erase Suspend).
See “AC Characteri stics” for param eters, and to Figure
17 for the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 8 shows the address and data requirements.
CLK
LBA#
BAA#
Data
OE#
Step 1 Step 2 Step 3
25 ns 25 ns 25 ns 25 ns
65 ns
25 ns
18 ns
Da Da +1 Da +2
18 ns
CLK
LBA#
BAA#
Data
Step 1 Step 2 Step 3
40 ns 40 ns 40 ns 40 ns
70 ns
40 ns
24 ns
Da Da +1
24 ns
Da +2 Da +3
24 ns
OE#
20 Am29BL162C November 22, 2002
This m eth od is an al ternative to that sh own in Table 1,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unl ock cy c les, fol lo wed by the auto se lec t co m-
mand. The device then enters the autoselect mode,
and the sys tem may read at any add ress any number
of times, without initiating another command sequence.
A read cycle at address 00h retrieves the manufacturer
code. A read cycle at address 01h returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode returns 0001h if that
sect or is prote cted, or 0000h if it i s unprote cted. Re fer
to Table 2 for valid sector addresses. A read cycle at
address 03h returns 0000h if the device is in asynchro-
nous mode, or 0001h if in synchronous (burst) mode.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically gener-
ates the p rogram pulses and verifi es the progr ammed
cell margin. Table 8 shows the address and data re-
quirements for the progr am co mmand s equen ce.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresse s are no longer latche d. The system can deter -
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminat es the program-
ming operat ion .
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However , a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock bypass
command s equence is initiate d by first writing two un-
lock cy cle s. This is followe d by a thi rd write c ycl e con-
taining t he unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock by pass progr am comman d sequenc e is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in f aster total program-
ming time. Table 8 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid . To exit the un lock bypas s mode, th e system
must issue the two-cycle unlock bypass reset com-
mand se quence. The first cyc le must contain the dat a
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 5 illus tr ates the al gor it hm for the pr og ra m oper-
ation. See the Era se/Pr ogram O pera tions t able in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
November 22, 2002 Am29BL162C 21
Note: See Table 8 for program command sequence.
Figure 5. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycle s, followed by a se t-up comm and . Two additio nal
unlock write cycles are then followed by the chip erase
command, which in tur n inv okes th e E mb edde d E r as e
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The s ystem is not required to provide any co n-
trols or timings during these operations. Table 8 shows
the address and data requirements for the chip erase
comma nd se quen ce .
Any com mands written to the chip during the E mbed-
ded Erase algorithm are ignored. Note that a hardware
reset dur ing th e chip erase ope ratio n im mediat ely ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The syste m can determ ine the sta tus of the e rase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“W rite O perat ion St atus” for information on these status
bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses
are no longer latched.
Figure 6 illustrates the algorithm for the erase opera-
tion. See the Er ase/Progr am Operati ons tables in “AC
Characteristics” for parameters, and to Figure 19 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock write cycles are then followed by the ad-
dress of the secto r to be erased, and the se ctor erase
command. Table 8 shows the address and data re-
quirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-ena bled after the last Se ctor Erase comma nd is
written. If the time between additional sector erase
command s ca n be ass um ed to be les s than 50 µs , the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector eras e ope ra tio n i mm edi ate ly te rmin ates t he op-
eration. Th e Se ct or E rase c omm and s equ enc e sh oul d
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
22 Am29BL162C November 22, 2002
be reini tiated once the device has re turned to readin g
array data, to ensure data integrity.
When the Embe dded Erase alg orith m is com pl ete, the
device returns to reading array data and addresses are
no longer latched. Th e system ca n determine the s ta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “W ri te O pera tion St atus” for informa-
tion on these status bits.)
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 19 for timing diagrams.
Notes:
1. See Table 8 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 6. Erase Oper at ion
Erase S uspend/Erase R esume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. The Erase Suspend command has a different
effect depending on whether the Flash device is in
Asynchronous Mode or Burst Mode.
Asynchronous Mode
The Erase Suspend command is only valid when the
Flash device is in Asynchronous Mode. During Erase
Susp end opera tion Async hrono us read/p rogram o per-
ations behave normally in non-erasing sectors. How-
ever, Erase Suspend operation prevents the Flash
device from entering Burst Mode. To enter Burst Mode
either the Erase operation must be allowed to complete
normally , or it can be prematurely terminated by issuing
a Hardware Reset.
Burst Mode
While in Burst Mode the Erase Suspend command is
ignored and the device continues to operate normally
in Burst Mode. If Erase Suspend operation is required,
then Burst Mode must be terminated and Asynchro-
nous Mod e initiate d.
General
This command is valid only during the sector erase op-
eration, including the 50 µs time-out period during the
sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase op-
eration or Embedded Program algorithm. Writing the
Erase Suspend command during the Sector Erase
time-out immediately terminates the time-out period
and suspends the erase operation. Addresses are
“don’t-cares” when writing the Erase Suspend com-
mand.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However , when
the Era se Su spen d comm and is writte n dur ing th e sec-
tor erase time-out, the device immediately terminates
the time-out period and suspends the erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any se ctor n ot sel ected f or er asure. (The device “ erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Note that burst read is not available when the device is
erase-suspended. Only asynchronous reads are al-
lowed. Reading at any address within erase-sus-
pended sectors produces status data on DQ7–DQ0.
The system can use DQ7, or DQ6 and DQ2 together,
to dete rmine if a sector is active ly erasin g or is erase-
suspended. See “Write Operation Status” for informa-
tion on these status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedde
d
Erase
algorithm
in progres
s
November 22, 2002 Am29BL162C 23
the Erase Suspend mode, and is ready for another
valid op erati on. See “Re set Comm and” fo r more i nfor-
mation.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be wr itten after the de-
vice has resumed erasing.
24 Am29BL162C November 22, 2002
Command Definitions
Table 8. Am29BL162C Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read opera tion.
PA = Address of the m emory loca tion to b e pr ogrammed.
Address es l at ch on the falling edge of the WE# or C E# pulse,
whichever happens later.
PD = Data to be programmed at location P A. Data latches on the
rising ed ge of W E # or C E# pulse, which ever happens fir st.
SA = Address of the sector to be verified (in autoselect mode) or
era sed. Addr ess bits A19 –A12 uniq uely select any sector .
Notes:
1. See Ta ble 1 f or description of bu s operations .
2. All values ar e in hex adecimal.
3. Except for the read cycle and th e f our t h cycle of the
autoselect command sequence, all bus cycles are write
cycles.
4. Data bits D Q 1 5–D Q8 are don ’t ca re s f or unlock and
command cycles.
5. Address bits A1 9–A11 ar e don’t cares for unl ock and
comm and cycles, unles s SA or PA requi r ed.
6. No unlock or command cycles r equ i red when readi ng array
data.
7. The Reset command is required to return to reading a rray
dat a when devi ce i s i n t he autose l ect mode, or if DQ5 goes
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unpro te ct ed sector and 01h for a
protected sector. See “Reset Command” for more
information.
10. Th e dat a i s 00h if the device is in as ynchronou s m ode and
01h if in syn chronous (b ur st ) m ode.
1 1. Command is valid when device is ready to read array data or
when de vi ce is in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock
Bypass Pr ogr am command.
13. The Unlock Bypass Res et command is required to return to
readin g ar ra y data when the device is in the unlock bypass
mode.
14. The system may read and program in non-erasing sectors, or
enter the au t oselect mode , wh en i n t he Er as e Suspend
mode. T he Er as e Suspend com m and is valid only during a
sec t or erase operati on.
15. The Erase Resume command is valid only during the Erase
Suspend m ode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect
(Not e 8)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 2203
Sector Protect Verify (Note 9) 4 555 AA 2AA 55 555 90 (SA)
X02 0000
0001
Burst Mode Status (Note 10) 4 555 AA 2AA 55 555 90 X03 0000
0001
CFI Quer y ( N ote 11) 1 55 98
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Byp as s 3 555 AA 2 AA 55 555 20
Unlock Byp ass Program (N ote 12) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Er ase Suspe nd (Note 14) 1 XXX B0
Erase Resume (Note 15) 1 XXX 30
Burst Mode
Burst Mode Enable 4 5 55 AA 2AA 55 555 C 0 XXX 0 1
Burst Mode Dis able 4 555 AA 2AA 55 555 C0 X XX 00
November 22, 2002 Am29BL162C 25
WRITE OPERATION STATUS
The devi ce provide s several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 9 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Dat a# Polli ng bit, DQ7, indic ates to the host system
whether an Embedded Alg orithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embed ded Program algorithm i s compl ete, the devi ce
outputs the datum programmed to DQ7. The system
must pro vide the program add ress to re ad v alid sta t us
information on DQ7. If a program address falls within a
protected sector , Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sect ors are protect ed, the Embedded E rase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that a re protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low . Figure 20, Data#
Polling Timings (D uring Embedded A lgorithms), in th e
“AC Characteristics” section illustrates this.
Table 9 shows the outputs for Data# Polling on DQ7.
Figure 7 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within an
y
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
26 Am29BL162C November 22, 2002
RY/BY #: Ready/Bus y#
The RY/BY# is a dedi ca ted, op en- drai n ou tput pi n tha t
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since R Y/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. (The RY/BY# pin is not avail-
able on the 44-pin SO package.)
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 9 shows the outputs for RY/BY#. Figures 15, 17,
18 and 19 shows RY/BY# for read, reset, program, and
erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether th e de vi ce has entered the E r ase S us pen d
mode. Toggle Bit I m ay be r ead at any add re ss, and is
valid afte r the r isin g edg e of th e fin a l WE# pul se in th e
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During a n Embedde d Program or Erase al gorithm o p-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to contro l the read cycles.) Wh en the operati on is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If n ot all sel ected s ectors are pr otect ed, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 s tops to gglin g. Howeve r, the sy stem m ust
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggl es for approxima tely 1 µs after the program
command s equenc e is wri tten, then returns to readin g
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 9 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 8 sh ows the togg le bit algor ithm in flowc hart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex-
plains the a lg orith m. Fi gur e 2 1 i n the “AC C har ac teri s-
tics” section shows the toggle bit timing diagrams.
Figure 22 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” o n DQ 2, whe n u sed wi th DQ 6, ind i-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (T he sys tem m ay use either OE# o r CE# to c on-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is active ly erasin g or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device i s actively erasing, or is in Erase Susp end, but
cannot distinguish which sectors are select ed for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 9 to compare outputs
for DQ2 and DQ6.
Figure 8 shows the toggle bit algorithm in flowchart
form, and th e sect ion “R eading Toggle Bits DQ6 /DQ2”
explain s the algo rithm. See al so the DQ6: Toggle Bit I
subsectio n. Figure 2 1 shows th e toggle bi t timing dia-
gram. Figure 22 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. When-
ever the system initi ally begins read ing toggl e bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can r ead array data on DQ7–DQ0 on the fol-
lowing read cy cle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still t oggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have st opped toggli ng just as
DQ5 went high. If the toggle bit is no longer toggling,
the devic e has s uccess full y comple ted th e progra m or
erase operat ion. If it is still togg ling, the device di d not
complete the operation successfully, and the system
November 22, 2002 Am29BL162C 27
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially
determin es that the tog gle bit is toggl ing and DQ 5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 8).
DQ5: Exceeded Timing Limits
DQ5 indic ates wh ether the program or e rase time has
exceede d a specified internal pulse co unt limit. Under
these co nditions DQ5 pr oduces a “1.” T his is a failu re
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0 ” ba ck t o a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Eras e Timer
After writing a sector erase command sequence, the
system may read DQ3 to d etermine wh ether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the tim e-out i s comple te, DQ3 switch es from “0”
to “1.” The system may i gnore DQ3 if the syst em can
guarantee that the time between additional sector
erase comm ands will al ways be less than 50 µs. See
also the “Sector Erase Command Sequence” section.
After the sector erase command sequence is written,
the syste m sh oul d re ad t he s tatu s on DQ7 (Dat a# Poll -
ing) or DQ6 (Toggle Bit I ) to ens ur e the dev ice has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 9 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
DQ6 = Toggle? No
Read Byte
(DQ0-DQ7)
Address = VA
DQ6 = Toggle?
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
Read Byte
(DQ0-DQ7)
Address = VA
FAIL PASS
N
otes:
1
. Read toggle bit twice to determine whether or not it is
toggling. See text.
2
. Recheck toggle bit becau se it may stop togg ling as DQ
5
changes to “1”. See text.
Figure 8. Toggle Bit Algorithm
(Not e 1)
(Notes
1, 2)
28 Am29BL162C November 22, 2002
Table 9. Write Operation St atus
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and D Q2 require a v alid address w hen reading s tatus informatio n. Refer to the appropriate s ubsection for furth er details.
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Readi ng withi n Erase
Suspend ed Sec tor 1 No toggle 0 N/A Toggle 1
Readi ng withi n Non-Eras e
Suspend ed Sec tor Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
November 22, 2002 Am29BL162C 29
ABSOLUTE MAXIMUM RATINGS
Storage Temperatur e
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2). .–0.5 V to +13.0 V
All other pins (Note 1). . . . . . –0.5 V to +VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input and I/O pins is –0.5 V.
During voltage transitions, input and I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 9. Maximum DC voltage on input and I/O pins is
VCC + 0.5 V. During voltage transitions input or I/O pins
may overshoot to VCC + 2.0 V for periods up to 20 ns. See
Figure 10.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. Se e Figure 9. Maxim um DC input voltage on pi n
A9 and OE# is +13.0 V which may overshoot to 14.0 V for
periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stre ss rat ing on ly; fu nction al ope ration of the d e-
vice at these or any other conditions above those indi-
cated in the operational section s of this data s heet is not
implied. Exposure of the devic e to absolute maxim um rat-
ing conditions for extended perio ds may affect devic e reli-
ability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . .3.0 V to 3.6 V
Operati ng ranges defin e those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 9. Maximum Negative Overshoot
Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 10. Maximum Positive Overshoot
Waveform
30 Am29BL162C November 22, 2002
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when ad dresses remain stable for tACC + 30 ns. Typical sleep mode
current is 3 µA.
5. 32-word average.
6. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to 5.5 V,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to 5.5 V,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH, 5 MHz 9 16 mA
ICC2 VCC Active Write Current
(Notes 2, 3, 6) CE# = VIL, OE# = VIH 20 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 3 10 µA
ICC4 VCC Standby Current During
Reset (Note 2) RESET# = VSS ± 0.3 V 3 10 µA
ICC5 Automatic Sleep Mode
(Notes 2, 4) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V OE# = VIH 310µA
OE# = VIL 820µA
ICC6 VCC Burst Mode Read Current
(Notes 2, 5) CE# = VIL,
OE# = VIH
25 MHz 15 30 mA
33 MHz 20 35 mA
40 MHz 25 40 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC 5.5 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage (Note
4) 2.3 2.5 V
November 22, 2002 Am29BL162C 31
DC CHARACTERISTICS (Continued)
Zero Power Flash
N
ote: Addresses are switching at 1 MHz
Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
1 2345
Frequency in MHz
Supply Current in mA
N
ote: T = 25 °CFigure 12. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
32 Am29BL162C November 22, 2002
TEST CONDITIONS Table 10. Test Specifications
Key to Switching Waveforms
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Figure 13. Test Setup
N
ote: Diodes are IN3064 or equivalent
Test Condition 65R,
70R 90R,
120R Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
Figure 14. Input Waveforms and Measurement Levels
November 22, 2002 Am29BL162C 33
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 13 and Table 10 for test specifications
Parameter
Description Test Setup
Speed Options and
Temperature Ranges
UnitJEDEC Std.
65R 70R 90R 120R
I E I, E I, E I, E
tAVAV tRC Read Cycle Time (Note 1) Min 65 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 65 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 65 70 90 120 ns
tGLQV tOE Out put Enab le to Out put Dela y Max 17 18 24 26 26 ns
tEHQZ tDF Chip Enable to Output High Z
(Not e 1) Max1718242626ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 25 30 30 ns
tOEH Output Enable
Hold Time (Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1) Min 0 ns
34 Am29BL162C November 22, 2002
AC CHARACTERISTICS
Burst Mode Read
Note: Initial valid data will be output after second clock rising edge of LBA# assertion.
Parameter
Description
Speed Options and Temperature Ranges
UnitJEDEC Std.
65R 70R 90R 120R
I E I, E I, E I, E
tIACC
Initial Access Time
LBA# Valid Clock to Output Delay
(See Note) Max 65 70 90 120 ns
tBACC Burst Access Time
BAA# Valid Clock to Output Delay Max1718242626ns
tLBAS LBA# Setup Time Min 6 ns
tLBAH LBA# Hold Time Min 2 ns
tBAAS BAA# Setup Time Min 6 ns
tBAAH BAA# Hold Time Min 2 ns
tBDH Data Hold Time from Next Clock Cycle Max 4 ns
tACS Address Setup Time to CLK
(See Note) Min 6 ns
tACH Address Hold Time from CLK
(See Note) Min 2 ns
tOE Out put Enable to Output Va lid Max 17 18 24 26 26 ns
tOEZ Output Enab le to Output High Z Max 20 25 30 30 n s
tCEZ Chip Enable to Output High Z Min 20 25 30 30 ns
tCES CE# Setup Time to Clock Min 6 ns
November 22, 2002 Am29BL162C 35
AC CHARACTERISTICS
Figure 15. Conventional Read Operations Timings
Figure 16. Burst Mode Read
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Da Da + 2 Da + 3 Da + 31
OE#*
DQ0: DQ15
A0: A18 Aa
IND#
BAA#
LBA#
CLK
CE# tCES
tBAAS
tBAAH
tACS
tLBAS
tLBAH
tACH
tOE
tBACC
tBDH
tOEZ
tCEZ
tIACC Da + 1
36 Am29BL162C November 22, 2002
AC CHARACTERISTICS
Hardware Reset (RESET# )
Note: Not 100% tested.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin L ow (NOT Durin g Embedd ed
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See
Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 17. RESET# Timings
November 22, 2002 Am29BL162C 37
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description 65R 70R 90R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min45454550ns
tDVWH tDS Data Setup Time Min35354550ns
tWHDX tDH Dat a Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 35 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Oper ati on (Note 2) T y p 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns
38 Am29BL162C November 22, 2002
AC CHARACTERISTICS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 18. Program Operation Timings
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
November 22, 2002 Am29BL162C 39
AC CHARACTERISTICS
Note: SA = sector a ddress (for Sector Era se), VA = V alid Add ress for re ading st atus data (s ee “W rite Oper ation Status” ).
Figure 19. Chip/Sector Erase Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
t
RB
t
BUSY
40 Am29BL162C November 22, 2002
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement True
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
t
ACC
t
RC
N
ote: V A = V alid address. Illustration shows first status cycle after command sequence, last status read cycle, a nd arra
y
d
ata read cy cle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6/DQ2
RY/BY#
tBUSY
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
N
ote: VA = Valid addre ss; no t r equi red for D Q6. Illustration shows firs t tw o stat us cy cle afte r c omm and sequ enc e, la s
t
s
tatus read cycle, and array data read cycle.
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
November 22, 2002 Am29BL162C 41
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
N
ote: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
e
rase-suspended sector.
Figure 22. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
Parameter
All Speed OptionsJEDEC Std. Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup T ime for Temporary Sector
Unprotect Min 4 µs
RESET#
tVIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
Figure 23. Temporary Sector Unprotect Timing Diagram
42 Am29BL162C November 22, 2002
AC CHARACTERISTICS
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
R
ESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Protect/Unprotect Verify
VID
VIH
N
ote: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24. Sector Protect/Unprotect Timing Diagram
November 22, 2002 Am29BL162C 43
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program
Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description 65R 70R 90R 120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 65 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min45454550ns
tDVEH tDS Data Setup Time Min35354550ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWsH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
44 Am29BL162C November 22, 2002
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
N
otes:
1
. PA = progr am address, PD = program data, DQ7 # = complement of t he data written to the device, DOUT = data written to th
e
device.
2
. Figure indicates the last two bus cycles of the command sequence.
Figure 25. Alternate CE# Controlled Write Operation Timings
November 22, 2002 Am29BL162C 45
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles .
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 8 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: V CC = 3.0 V, one pin at a time.
SSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test co ndi tio n s TA = 25°C, f = 1.0 MHz.
DATA RETENTION
* For reference only. BSC is an ANSI standard for Basic Space Centering
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 1 15 s Excludes 00h progra mming
prior to erasure (Note 4)
Chip Erase Time 15 s
Word Programming Time 9 360 µs Exclud es system level
overhead (Note 5)
Chip Programming Time (Note 3) 18 54 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Outp ut Capacitance VOUT = 0 8.5 1 2 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Test Conditions M in Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
46 Am29BL162C November 22, 2002
PHYSICAL DIMENSIONS*
SSO056—56-Pin Shrink Small Outline Package
Dwg rev AB; 10/99
November 22, 2002 Am29BL162C 47
REVISION SUMMARY
Revision A (September 1998)
Initial release.
Revision B (December 1998)
Global
Expanded data sheet into full version.
Revision C (December 1998)
Global
Added a separate set of read access specifications for
devices at industrial temperature range. Changed read
access specifications for 90 and 120 ns devices at
extended temperature range to 28 ns.
Ordering Information
Deleted commercial temperature rating.
Revisi on D (May 17, 1999)
Global
Changed dat a shee t status to pr elimina ry. Del eted th e
70R speed option. Deleted the 70 speed option at
extended temperature range. Added the 90R and 120R
speed options at extended temperature range. Deleted
the 90 and 120 speed options at extended temperature
range.
Distinctive Characteristics
Changed device endurance from program/erase
cycles to erase cycles.
Block Diagram
Deleted redundant path between state control and
erase voltage generator. Added sector switch block.
Deleted RY/BY# buffer. VCC and VSS are now shown
properly.
Pin Configuration
Clarified the explanation of IND#.
Device Bus Operations
Reorganized and rewrote the following subsections:
Requirements for Reading Array Data, Read Mode,
Burst Mode Read, IND# End of Burst Indicator, and
Burst Mode Status. “Reading Array Data in Non-burst
Mode”. The Burst Mode Status section is now inte-
grated into the autoselect mode section.
Device Bus Operations table: In the notes, deleted ref-
erence to BYTE# pin.
Sector Address table: Added sector address bit set-
tings for A19–A12.
Common Flash Memory Interface (CFI)
Corrected data for the following hex CFI addresses: 28,
38, 39, 3C.
Command Definitions
Reorganized and rewrote the “Reading Array Data”
section into t wo sectio ns entitl ed “R eading Arr ay Data
in Non- burst Mode” and “Reading Array Data in Burst
Mode”. Added burst mode read figures comparing
system frequency and device speed. Added burst
mode status to autoselect command sequence in
command definitions table.
Absolute Maximum Ratings
Corrected the maximum VCC rating to +4.0 V, an d the
maximum all other pins rating to +5.5 V.
DC Characteristics table
Corrected the maximum rating for VIH to 5.5 V.
AC Characteristics
In the read operations and burst mode operations
tables, reflected the global changes in speed options
(see the “g lobal” revision entry).
Burst Mode Read figure
Corrected figure. Deleted note; OE# and BAA# should
not be tied together. LBA# should be returned high
after it coincides with a rising edge of CLK. BAA#
should not be asserted before the first word of data
appears on the bus. The data is held on the outputs for
only tBDH after the next clock.
Revision D+1 (July 2, 1999)
Command Definitions
Reading Array Data in Burst Mode: Added reference to
figure 3 to the first paragraph.
Revis ion E (November 2, 1999)
Global
All speed options are now offered only at the regulated
voltage range of 3.0 to 3.6 V. The 90 and 120 ns speed
options n ow have a tOE of 26 ns at the industr ial tem-
perature range. The 70R speed option is now available
at the extended temperature range.
AC Characteristics
In figures 17 and 18, deleted tGHWL. Modified OE#
waveform.
Physical Dimensions
Updated drawing of SSOP to new version.
48 Am29BL162C November 22, 2002
Revision F (June 20, 2000)
Global
The “prel iminary” de signatio n has been rem oved from
the document. Parameters are now stable, and only
speed, p acka ge, an d tem per atu r e range c om bin ati ons
are expected to change in future data sheet revisions.
Distinctive Characteristics
Changed burst access time specification for the 65R
speed option in the industrial temperature range from
19 to 18 ns.
Product Sel ector Guide
Replaced tOE with tBACC to more clearly distinguish
burst mode access from asynchronous access times.
Note however, that in burst mode, tOE and tBACC spec-
ifications are identical. Changed tBACC for the 65R
speed option in the industrial temperature range from
19 to 18 ns.
Ordering Information
Burn-in processing is no longer available.
Requirements for Reading Array Data Array in
Asynchronous (Non-Burst) Mode
Clarified the description of how to terminate a burst
mode read operation.
Burst Mode Read with 40 MHz CLK figure
Changed tBACC for th e 65R sp eed opti on in the i ndus-
trial temperature range from 19 to 18 ns.
Read Operations table
Changed tOE and tDF for the 65R speed option in the
industrial temperature range from 19 to 18 ns.
Burst Mode Read table
Changed tOE and tBACC for the 65R speed option in the
industrial temperature range from 19 to 18 ns.
Burst Mode Read figure
Corrected BAA# waveform to return high before the
final clock cycle shown.
Erase and Programming Pe rformance table, Erase
and Program Operations table, Alternate CE#
Controlled Erase and Program Ope rations table
Resolved differences in typical sector erase times. The
typical sector erase time for all sectors is 3 sec.
Revision F+1 (November 21, 2000)
Added table of contents. Added Figure 1, In-System
Sector Protect/Unprotect Algorithms figure to docu-
ment (was missing from previous revisions).
Revision F+2 (July 22, 2002)
Pin Description, IND# End of Burst Indicator
Clarified description of IND# function.
Table 1, Device Bus Operations
In burst read operations section, changed BAA# to “H”
for “Load starting Burst Address” and Terminate
Current Burst Read Cycle; Start New Burst Read
Cycle.”
Requirements for Reading Array Data in
Synchronous (Burst) Mode
Modified section to clarify the description of the IND#
and burst read functions.
Burst Sequence Table
Deleted table.
Absolute Maxiumum Ratings
Modif ied maxi mum DC voltag e and m axim um pos itive
overshoot in Note 1 to refer to input and I/O pins.
Revision F+3 (August 19, 2002)
Product Selector Guide
Added Note #2.
Revision F+4 (September 12, 2002)
Product Selector Guide
Removed Note #2.
Revis ion F+5 (November 22, 2002)
Distinctive Characteristics
Changed endurance to 1 million cycles.
Erase Suspend/Erase Resume Command
Sequence
Noted that only asynchronous reads are allowed during
the erase suspend mode.
Erase/Program Operations table, Alternate CE#
Controlled Erase/Program Ope rations table
Changed typical sector erase time from 3 s to 1 s.
Erase and Programming Performance
Changed typical/maximum sector erase time from 3
s/60 s to 1 s/15 s, respectively. Changed typical chip
erase time from 40 s to 15 s. Changed endurance to 1
million cycles. Added Asynchronous mode and Burst
mode sections.
November 22, 2002 Am29BL162C 49
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advan ced Micro Devices , Inc.
Product names used in this publication are for identificat ion purposes only and may be trademarks of their respective companies.
