SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC100EP220/D
1REV 1
Motorola, Inc. 2001
09/01
The MC100EP220 is a dual low skew 1–to–10 differential driver,
designed with clock distribution in mind. The VBB output provides a DC
threshold bias for single ended sources. The VBB can be connected to the
true input or the complementary input, the latter will produce an inverted
output. If used, the VBB output should be bypassed to ground.
•225ps Max. Part–to–Part Skew
•60ps Output–to–Output Skew
•Differential Design
•VBB Output
•Voltage and Temperature Compensated Outputs
•Low Voltage VEE Range of –2.375 to –3.8V
•65kΩ Input Pulldown Resistors
The EP220 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate–
to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that
both pairs of the differential outputs are terminated into 50Ω, even if only
one side is being used. In applications which do not use all of the outputs,
it is best to leave unused pairs open to minimize power consumption in
the device.
The MC100EP220, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP220 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP220’s performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For more information on using PECL, designers
should refer to Motorola Application Note AN1406/D.
LOW–VOLTAGE
DUAL 1:10 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
TB SUFFIX
52–LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
DATA SHEET
MC100EP220
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
1
Low-Voltage Dual 1:10 Differential
ECL/PECL Clock Driver
MC100EP220
MOTOROLA TIMING SOLUTIONS2
LOGIC SYMBOL
Pinout: 52–Lead LQFP
(Top View)
MC100EP220
W
W
W
W
W
W
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
2
MC100EP220
TIMING SOLUTIONS 3 MOTOROLA
Table 1: PIN CONFIGURATION
Pin I/O Type Function
CLKA, CLKA Input ECL/LVPECL Differential reference clock signal input for fanout buffer A
CLKB, CLKB Input ECL/LVPECL Differential reference clock signal input for fanout buffer B
Q[0-19], Q[0-19] Output LVPECL Differential clock outputs
VEEaSupply Negative power supply
VCC, VCCO Supply Positive power supply. All VCC and VCCO pins must be connected to
the positive power supply for correct DC and AC operation
VBB Output DC bias output for single ended input operation
a. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V).
In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V.
In both modes, the input and output levels are referrenced to the most positive supply (VCC).
Table 2: ABSOLUTE MAXIMUM RATINGSa
Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage -0.3 4.6 V
VIN DC Input Voltage -0.3 VCC+0.3 V
VOUT DC Output Voltage -0.3 VCC+0.3 V
IIN DC Input Current ±20 mA
IOUT DC Output Current ±50 mA
TSStorage temperature -65 125 °C
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 3: GENERAL SPECIFICATIONS
Symbol Characteristics Min Typ Max Unit Condition
VTT Output termination voltage VCC - 2aV
MM ESD Protection (Machine model) 75 V
HBM ESD Protection (Human body model) 1500 V
CDM ESD Protection (Charged device model) 500 V
LU Latch-up immunity 200 mA
CIN 4.0 pF Inputs
θJA Thermal resistance junction to ambient See application informationb
θJC Thermal resistance junction to case See application information
a. Output termination voltage VTT = 0V for VCC=2.5V operation is supported but the power consumption of the device will increase.
b. Proper thermal management is critical for reliable system operation. This especially true for high-fanout and high drive capability
products. Thermal package information and exposed pad land pattern design recommendations are available in the applications section
of this datasheet. In addition, the means of calculating die power consumption, the corresponding die temperature and the relationship to
long-term reliability is addressed in the Motorola application note AN1545. Thermal modeling is recommended for the MC100EP220.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
3
MC100EP220
MOTOROLA TIMING SOLUTIONS4
Table 4: PECL DC Characteristics (VCCO = VCC = 2.375V to 3.8V, VEE = GND)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condition
y
Min Max Min Max Min Max
Clock input pair CLKA, CLKA, CLKB, CLKB (LVPECL differential signals)
VPP Differential input
voltagea V
CC=3.3V
VCC=2.5V
0.10
0.15
0.10
0.15
0.10
0.15
V
V
VCMR Differential cross point
voltagebCLKA, CLKB 1.0 VCC-0.4 1.0 VCC-0.4 1.0 VCC-0.4 V
All inputs (LVPECL single ended signals)
VIH Input high voltage VCC-1.14 VCC-1.14 VCC-1.14 V
VIL Input low voltage VCC-1.46 VCC-1.46 VCC-1.46 V
IIH Input Current 150 150 150 µA VIN = VCC to VEE
LVPECL clock outputs (Q0-19, Q0-19)
VOH Output High Voltage VCC-1.20 VCC-0.82 VCC-1.15 VCC-0.82 VCC-1.15 VCC-0.82 V IOH= -30mAc
VOL Output Low Voltage VCC-1.90 VCC-1.40 VCC-1.90 VCC-1.40 VCC-1.9 VCC-1.40 V IOL= -5mAc
Supply current and VBB
IEE Max. Supply Current 190 190 190 mA VEE pin
ICC Max. Supply Currentd750 750 750 mA VCC pins
VBB Output reference voltageeVCC-1.36 VCC-1.24 VCC-1.36 VCC-1.24 VCC-1.36 VCC-1.24 V
a. VPP is the minimum differential input voltage swing required to maintain device functionality.
b. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
c. Equivalent to an output termination of 50Ω to VTT
.
d. ICC includes current through the output resistors (all outputs terminated 50W to VTT).
e. VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3
mA DC current.
Table 5: ECL DC Characteristics (VCC = VCCO = GND, VEE = -3.8V to -2.375V)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condition
y
Min Max Min Max Min Max
Clock input pair CLKA, CLKA, CLKB, CLKB for ECL differential signals
VPP Differential input voltagea
VEE=-3.3V
VEE=-2.5V
0.10
0.15
0.10
0.15
0.10
0.15
V
V
VCMR Differential cross point voltagebVEE+1.0 -0.4 VEE+1.0 -0.4 VEE+1.0 -0.4 V
All inputs ECL single ended signals
VIH Input high voltage -1.14 -1.14 -1.14 V
VIL Input low voltage -1.46 -1.46 -1.46 V
IIH Input Current 150 150 150 µA VIN = VEE to VCC
LVPECL clock outputs (Q0-19, Q0-19)
VOH Output High Voltage -1.20 -0.82 -1.15 -0.82 -1.15 -0.82 V IOH= -30 mAc
VOL Output Low Voltage -1.90 -1.40 -1.90 -1.40 -1.90 -1.40 V IOL= -5 mAc
Supply current and VBB
IEE Max. Supply Current 190 190 190 mA VEE pin
ICC Max. Supply Currentd750 750 750 mA VCC Pins
VBB Output reference voltagee-1.36 -1.24 -1.36 -1.24 -1.36 -1.24 V
a. VPP is the minimum differential input voltage swing required to maintain device functionality.
b. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
c. Equivalent to an output termination of 50Ω to VTT
.
d. ICC includes current through the output resistors (all outputs terminated 50W to VTT).
e. VBB output can be used to bias the complementary input when the device is used with single ended clock signals. VBB can sink max. 0.3
mA DC current.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
4
MC100EP220
TIMING SOLUTIONS 5 MOTOROLA
Table 6: PECL/ECL AC Characteristicsa (VCC = VCCO = 2.375V to 3.8V, VEE = GND) or (VEE = -3.8V to -2.375V, VCC =
VCCO = GND)
Symbol Characteristics TA = -40°C TA = 25°C TA = 85°CUnit Condi-
ti
y
Min Typ Max Min Typ Max Min Typ Max tion
Clock input pair CLKA, CLKA, CLKB, CLKB for PECL differential signals
VPP Differential input voltageb
(peak-to-peak)
0.4 1.0 0.4 1.0 0.4 1.0 V
VCMR Differential cross point
voltagec1.0 VCC-0.4 1.0 VCC-0.4 1.0 VCC-0.4 V
fCLK Input Frequency (PECL) 0 1.0 0 1.0 0 1.0 GHz
Clock input pair CLKA, CLKA, CLKB, CLKB for ECL differential signals
VPP Differential input voltage
(peak-to-peak)
0.4 1.0 0.4 1.0 0.4 1.0 V
VCMR Differential cross point
voltage VEE+1.0 -0.4 VEE+1.0 -0.4 VEE+1.0 -0.4 V
fCLK Input Frequency (ECL) 0 1.0 0 1.0 0 1.0 GHz
PECL/ECL clock outputs (Q0-19, Q0-19)
tPD Propagation Delay
CLKA or CLKB to Qx 300 400 500 350 450 550 425 535 650 ps
VO(P-P) Differential output voltage
(peak-to-peak) 450 700 500 700 500 700 mV
tsk(O) Output-to-output skew
(within device) 35 60 35 60 35 60 ps Diff.
tsk(PP) Output-to-output skew
(part-to-part) 200 200 225 ps Diff.
tJIT(CC) Output cycle-to-cycle
jitter (RMS) TBD TBD TBD ps
DCOPositive output pulse
width
tp – 50 tptp + 50 tp – 50 tptp + 50 tp – 50 tptp + 50 ps tp input
positive
pulse
width
tr, tfOutput Rise/Fall Time 100 500 100 500 100 500 ps 20% to
80%
a. AC characteristics apply for parallel output termination of 50Ω to VTT
.
b. VPP (AC) is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
c. VCMR (AC) is the crosspoint of the differential input signal. AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay and part-to-part skew.
Figure 1. MC100EP220 AC test reference
W
Ω
Ω
Ω
Ω
Figure 2. MC100EP220 AC reference measurement waveform
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
5
MC100EP220
MOTOROLA TIMING SOLUTIONS6
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
MC100EP220
The MC100EP220 uses a thermally enhanced exposed
pad (EP) 52 lead LQFP package. The package is molded so
that the leadframe is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the MC100EP220 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the
enhanced thermal capabilities of the MC100EP220. Direct
soldering of the exposed pad to the thermal land will provide
an efficient thermal path. In multilayer board designs, thermal
vias thermally connect the exposed pad to internal copper
planes. Number of vias, spacing, via diameters and land
pattern design depend on the application and the amount of
heat to be removed from the package. A nine thermal via
array, arranged in a 3 x 3 array and using a 1.2 mm pitch in
the center of the thermal land is the absolute minimum
requirement for MC100EP220 applications on multi-layer
boards. The recommended thermal land design comprises a
5 x 5 thermal via array as shown in Figure 1.
“Recommended thermal land pattern”, providing an efficient
heat removal path.
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Figure 1. Recommended thermal land pattern
The via diameter is should be approx. 0.3 mm with 1 oz.
copper via barrel plating. Solder wicking inside the via
resulting in voids during the solder process must be avoided.
If the copper plating does not plug the vias, stencil print
solder paste onto the printed circuit pad. This will supply
enough solder paste to fill those vias and not starve the
solder joints. The attachment process for exposed pad
package is equivalent to standard surface mount packages.
Figure 2. “Recommended solder mask openings” shows a
recommend solder mask opening with respect to the
recommended 5 x 5 thermal via array. Because a large solder
mask opening may result in a poor release, the opening
should be subdivided as shown in Figure 2. For the nominal
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils
should be considered.
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
ÏÏ
ÏÏ
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Ï
Figure 2. Recommended solder mask openings
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided. For thermal system analysis and junction
temperature calculation the thermal resistance parameters of
the package is provided:
Table 7: Thermal Resistancea
Convection-
LFPM
RTHJAb
°C/W
RTHJAc
°C/W
RTHJCd
°C/W
RTHJBe
°C/W
Natural 57.1 24.9
100 50.0 21.3
200 46.9 20.0 15.8 9.7
400 43.4 18.7
800 38.6 16.9
a. Thermal data pattern with a 3 x 3 thermal via array on
2S2P boards (based on empirical results)
b. Junction to ambient, single layer test board, per
JESD51-6
c. Junction to ambient, four conductor layer test board
(2S2P), per JES51-6
d. Junction to case, per MIL-SPEC 883E, method 1012.1
e. Junction to board, four conductor layer test board (2S2P)
per JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100EP220 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals. The thermal land should be connected to GND
through connection of internal board layers.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
6
MC100EP220
TIMING SOLUTIONS 7 MOTOROLA
OUTLINE DIMENSIONS
TB SUFFIX
PLASTIC LQFP PACKAGE
CASE 1336–01
ISSUE O
b1
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
ÇÇÇ
VIEW AA
AB
AB
VIEW Y
SECTION AB–AB
ROTATED 90 CLOCKWISE
DIM
D
MIN MAX
MILLIMETERS
D1
e
E
A
A1
A2
b
b1
c
E1
c1
L1
L
R1
R2
S
F
G
Z
X=A, B OR D
1
13
14 26
27
39
4052
4X 13 TIPS
4X
SEATING
PLANE
A
A2
A1
S
L
L1
PLATING
BASE METAL
b
cc1
E1 E
E1/2
D1
D
E/2
D1/2
D/2
e
VIEW Y
VIEW AA
R1
Z1
Z2
Z3
B
D
A
C
52X b
VIEW J–J
EXPOSED PAD
G
F
H52X
4X Z2
4X Z3
Z1
Z
R2
X
48X
8
8
8
8
J J
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
IDT™ Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100EP220
7
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
PART NUMBERS
INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM
MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer NETCOM
MC100EP220
Low-Voltage Dual 1:10 Differential ECL/PECL Clock Driver NETCOM
