8-Channel, 24-Bit, Simultaneous Sampling ADC AD7770 Data Sheet FEATURES 8-channel, 24-bit simultaneous sampling analog-to-digital converter (ADC) Single-ended or true differential inputs Programmable gain amplifier (PGA) per channel (gains of 1, 2, 4, and 8) Low dc input current 4 nA (differential) and 8 nA (single-ended) Up to 32 kSPS output data rate (ODR) per channel Programmable ODRs and bandwidth Sample rate converter (SRC) for coherent sampling Sampling rate resolution up to 15.2 x 10-6 SPS Low latency sinc3 filter path Adjustable phase synchronization Internal 2.5 V reference Two power modes optimizing power dissipation and performance: high resolution mode and low power mode Low resolution successive approximation register (SAR) ADC for system and chip diagnostics Power supply Bipolar (1.65 V) or unipolar (3.3 V) supplies Digital input/output (I/O) supply: 1.8 V to 3.6 V Performance temperature range: -40C to +105C Functional temperature range: -40C to +125C Performance Combined ac and dc performance 103 dB dynamic range at 32 kSPS in high resolution mode -109 dB total harmonic distortion (THD) 9 ppm of FSR integral nonlinearity (INL) 15 V offset error 0.1% FS gain error 10 ppm/C typical temperature coefficient APPLICATIONS Protection relays General-purpose data acquisition Industrial process control GENERAL DESCRIPTION The AD7770 is an 8-channel, simultaneous sampling ADC. Eight full sigma-delta (-) ADCs are on chip. The AD7770 provides a low input current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor outputs into the full-scale ADC input range, maximizing the dynamic range of the signal chain. The AD7770 accepts a VREF voltage from 1 V up to 3.6 V. Rev. E The analog inputs accept unipolar (0 V to VREF) or true bipolar (VREF/2) analog input signals with 3.3 V or 1.65 V analog supply voltages, respectively for PGAGAIN = 1. The analog inputs can be configured to accept true differential, pseudo differential, or single-ended signals to match different sensor output configurations. Each channel contains a PGA, an ADC modulator and a sinc3, low latency digital filter. An SRC is provided to allow fine resolution control over the AD7770 ODR. This control can be used in applications where the ODR resolution is required to maintain coherency with 0.01 Hz changes in the line frequency. The SRC is programmable through the serial port interface (SPI). The AD7770 implements two different interfaces: a data output interface and SPI control interface. The ADC data output interface is dedicated to transmitting the ADC conversion results from the AD7770 to the processor. The SPI writes to and reads from the AD7770 configuration registers and for the control and reading of data from the SAR ADC. The SPI can also be configured to output the - conversion data. The AD7770 includes a 12-bit SAR ADC. This ADC can be used for AD7770 diagnostics without having to decommission one of the - ADC channels dedicated to system measurement functions. With the use of an external multiplexer, which can be controlled through the three general-purpose input/output pins (GPIOs), and signal conditioning, the SAR ADC can validate the - ADC measurements in applications where functional safety is required. In addition, the AD7770 SAR ADC includes an internal multiplexer to sense internal nodes. The AD7770 contains a 2.5 V reference and reference buffer. The reference has a typical temperature coefficient of 10 ppm/C. The AD7770 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher dynamic range while consuming 10.75 mW per channel; low power mode consumes just 3.37 mW per channel at a reduced dynamic range specification. The specified operating temperature range is -40C to +105C, although the device is operational up to +125C. Note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK0/SDO, are referred to either by the entire pin name or by a single function of the pin, for example, DCLK0, when only that function is relevant. In the case of ranges of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7770 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 - Output Data............................................................................. 51 Applications ....................................................................................... 1 ADC Conversion Output--Header and Data ........................ 51 General Description ......................................................................... 1 Sample Rate Converter (SRC) (SPI Control Mode) .............. 52 Revision History ............................................................................... 4 Data Output Interface ................................................................ 53 Functional Block Diagram .............................................................. 5 Calculating the CRC Checksum .............................................. 58 Specifications..................................................................................... 6 Register Summary .......................................................................... 60 DOUTx Timing Characterististics ........................................... 10 Register Details ............................................................................... 64 SPI Timing Characterististics ................................................... 11 Channel 0 Configuration Register ........................................... 64 Synchronization Pins and Reset Timing Characteristics ...... 12 Channel 1 Configuration Register ........................................... 64 SAR ADC Timing Characterististics ....................................... 13 Channel 2 Configuration Register ........................................... 65 GPIO SRC Update Timing Characterististics......................... 13 Channel 3 Configuration Register ........................................... 65 Absolute Maximum Ratings.......................................................... 14 Channel 4 Configuration Register ........................................... 66 Thermal Resistance .................................................................... 14 Channel 5 Configuration Register ........................................... 66 ESD Caution ................................................................................ 14 Channel 6 Configuration Register ........................................... 67 Pin Configuration and Function Descriptions ........................... 15 Channel 7 Configuration Register ........................................... 67 Typical Performance Characteristics ........................................... 18 Disable Clocks to ADC Channel Register .............................. 68 Terminology .................................................................................... 31 Channel 0 Sync Offset Register ................................................ 68 Theory of Operation ...................................................................... 33 Channel 1 Sync Offset Register ................................................ 68 Analog Inputs .............................................................................. 33 Channel 2 Sync Offset Register ................................................ 68 Transfer Function ....................................................................... 34 Channel 3 Sync Offset Register ................................................ 69 Core Signal Chain....................................................................... 35 Channel 4 Sync Offset Register ................................................ 69 Capacitive PGA........................................................................... 35 Channel 5 Sync Offset Register ................................................ 69 Internal Reference and Reference Buffers ............................... 35 Channel 6 Sync Offset Register ................................................ 69 Integrated LDOs ......................................................................... 36 Channel 7 Sync Offset Register ................................................ 69 Clocking and Sampling.............................................................. 36 General User Configuration 1 Register ................................... 70 Digital Reset and Synchronization Pins .................................. 36 General User Configuration 2 Register ................................... 70 Digital Filtering........................................................................... 37 General User Configuration 3 Register ................................... 71 Shutdown Mode.......................................................................... 37 Data Output Format Register ................................................... 72 Controlling the AD7770 ............................................................ 38 Main ADC Meter and Reference Mux Control Register ...... 73 Pin Control Mode ....................................................................... 38 Global Diagnostics Mux Register............................................. 74 SPI Control .................................................................................. 40 GPIO Configuration Register ................................................... 74 Digital SPI .................................................................................... 43 GPIO Data Register.................................................................... 75 RMS Noise and Resolution............................................................ 46 Buffer Configuration 1 Register ............................................... 75 High Resolution Mode............................................................... 46 Buffer Configuration 2 Register ............................................... 75 Low Power Mode ........................................................................ 46 Channel 0 Offset Upper Byte Register..................................... 76 Diagnostics and Monitoring ......................................................... 47 Channel 0 Offset Middle Byte Register ................................... 76 Self Diagnostics Error ................................................................ 47 Channel 0 Offset Lower Byte Register ..................................... 76 Monitoring Using the AD7770 SAR ADC (SPI Control Mode) ........................................................................................... 48 Channel 0 Gain Upper Byte Register ....................................... 76 - ADC Diagnostics (SPI Control Mode) ............................ 50 Channel 0 Gain Middle Byte Register ..................................... 76 Channel 0 Gain Lower Byte Register ....................................... 77 Rev. E | Page 2 of 97 Data Sheet AD7770 Channel 1 Offset Upper Byte Register .....................................77 Channel 6 Gain Lower Byte Register ....................................... 84 Channel 1 Offset Middle Byte Register ....................................77 Channel 7 Offset Upper Byte Register ..................................... 84 Channel 1 Offset Lower Byte Register .....................................77 Channel 7 Offset Middle Byte Register .................................... 84 Channel 1 Gain Upper Byte Register........................................78 Channel 7 Offset Lower Byte Register ..................................... 85 Channel 1 Gain Middle Byte Register ......................................78 Channel 7 Gain Upper Byte Register ....................................... 85 Channel 1 Gain Lower Byte Register........................................78 Channel 7 Gain Middle Byte Register ...................................... 85 Channel 2 Offset Upper Byte Register .....................................78 Channel 7 Gain Lower Byte Register ....................................... 85 Channel 2 Offset Middle Byte Register ....................................78 Channel 0 Status Register .......................................................... 86 Channel 2 Offset Lower Byte Register .....................................79 Channel 1 Status Register .......................................................... 86 Channel 2 Gain Upper Byte Register........................................79 Channel 2 Status Register .......................................................... 87 Channel 2 Gain Middle Byte Register ......................................79 Channel 3 Status Register .......................................................... 87 Channel 2 Gain Lower Byte Register........................................79 Channel 4 Status Register .......................................................... 88 Channel 3 Offset Upper Byte Register .....................................79 Channel 5 Status Register .......................................................... 88 Channel 3 Offset Middle Byte Register ....................................80 Channel 6 Status Register .......................................................... 89 Channel 3 Offset Lower Byte Register .....................................80 Channel 7 Status Register .......................................................... 89 Channel 3 Gain Upper Byte Register........................................80 Channel 0/Channel 1 DSP Errors Register.............................. 90 Channel 3 Gain Middle Byte Register ......................................80 Channel 2/Channel 3 DSP Errors Register.............................. 90 Channel 3 Gain Lower Byte Register........................................80 Channel 4/Channel 5 DSP Errors Register.............................. 91 Channel 4 Offset Upper Byte Register .....................................81 Channel 6/Channel 7 DSP Errors Register.............................. 91 Channel 4 Offset Middle Byte Register ....................................81 Channel 0 to Channel 7 Error Register Enable Register........ 92 Channel 4 Offset Lower Byte Register .....................................81 General Errors Register 1 ........................................................... 92 Channel 4 Gain Upper Byte Register........................................81 General Errors Register 1 Enable .............................................. 93 Channel 4 Gain Middle Byte Register ......................................81 General Errors Register 2 ........................................................... 93 Channel 4 Gain Lower Byte Register........................................82 General Errors Register 2 Enable .............................................. 94 Channel 5 Offset Upper Byte Register .....................................82 Error Status Register 1 ................................................................ 94 Channel 5 Offset Middle Byte Register ....................................82 Error Status Register 2 ................................................................ 95 Channel 5 Offset Lower Byte Register .....................................82 Error Status Register 3 ................................................................ 95 Channel 5 Gain Upper Byte Register........................................82 Decimation Rate (N) MSB Register ......................................... 95 Channel 5 Gain Middle Byte Register ......................................83 Decimation Rate (N) LSB Register ........................................... 96 Channel 5 Gain Lower Byte Register........................................83 Decimation Rate (IF) MSB Register ......................................... 96 Channel 6 Offset Upper Byte Register .....................................83 Decimation Rate (IF) LSB Register .......................................... 96 Channel 6 Offset Middle Byte Register ....................................83 SRC Load Source and Load Update Register .......................... 96 Channel 6 Offset Lower Byte Register .....................................83 Outline Dimensions ........................................................................ 97 Channel 6 Gain Upper Byte Register........................................84 Ordering Guide ........................................................................... 97 Channel 6 Gain Middle Byte Register ......................................84 Rev. E | Page 3 of 97 AD7770 Data Sheet REVISION HISTORY 5/2020--Rev. D to Rev. E Changes to Table 1 ............................................................................ 6 Changes to Table 6 and Figure 6 ................................................... 13 Changes to Terminology Section.................................................. 31 Changes to Figure 99 ...................................................................... 40 Changes to Sample Rate Converter (SRC) (SPI Control Mode) Section and Figure 110................................................................... 52 Changes to Figure 119.................................................................... 56 5/2018--Rev. C to Rev. D Change to t22B Parameter, Table 3 ................................................. 11 Changes to AUXAIN Parameter, Table 7 .................................. 14 Changes to Table 13 ........................................................................ 38 Changes to - Data, ADC Mode Section ................................. 45 Added Figure 105; Renumbered Sequentially ............................ 45 Changes to SRC Group Delay and Latency Section................... 53 Changed SPI Section to SPI Interface Section ............................ 57 Updated Outline Dimensions ....................................................... 97 Changes to Ordering Guide .......................................................... 97 8/2017--Rev. B to Rev. C Changes to Features Section and General Description Section....... 1 Change to START Pin Description, Table 9 ................................ 15 Changes to Figure 48 ...................................................................... 24 Change to Digital Reset and Synchronization Pins Section and Internal Reference and Reference Buffers Section ..................... 36 Change to Figure 95 ....................................................................... 37 Changes to Phase Adjustment Section and Table 16 ................. 41 Added Table 17; Renumbered Sequentially ................................ 41 Change to Digital SPI Section....................................................... 43 Change to Table 25 ......................................................................... 46 10/2016--Rev. A to Rev. B Changes to Figure 45...................................................................... 24 Changes to Figure 56, Figure 59, and Figure 61 ......................... 26 Changes to Figure 72 and Figure 73 ............................................ 28 Changes to Figure 76...................................................................... 29 Added Figure 82; Renumbered Sequentially .............................. 30 Changes to Figure 86 to Figure 89 ............................................... 34 Changes to SPI Transmission Errors (SPI Control Mode) Section.............................................................................................. 48 Changes to Table 33 and Table 34 ................................................ 51 Changes to SRC Group Delay and Latency Section and Settling Time Section ................................................................................... 53 Changes to Table 39 and Table 40 ................................................ 57 Changes to Calculating the CRC Checksum Section and Table 42 ............................................................................................ 58 Changes to Ordering Guide .......................................................... 97 5/2016--Rev. 0 to Rev. A Change to Features ............................................................................1 Changes to Table 1.............................................................................6 Changes to Figure 33 and Figure 36 ............................................ 21 Change to Figure 78 ....................................................................... 28 4/2016--Revision 0: Initial Version Rev. E | Page 4 of 97 Data Sheet AD7770 FUNCTIONAL BLOCK DIAGRAM AVDD1x VCM REF_OUT REFx+ REFx- AVDD2 COMMONMODE VOLTAGE AREGxCAP ANALOG LDO IOVDD DREGCAP DIGITAL LDO 2.5V REF AIN0+ AIN0- CLOCK MANAGER XTAL1 XTAL2/MCLK SYNC_IN SYNC_OUT START 280mV p-p EXT_REF PGA - ADC SINC3/ SRC FILTER - ADC SINC3/ SRC FILTER GAIN OFFSET GAIN OFFSET GAIN OFFSET DCLK DRDY INT_REF AIN1+ AIN1- PGA DATA OUTPUT INTERFACE DOUT3 DOUT2 DOUT1 REFERENCES DOUT0 AIN2+ AIN2- PGA - ADC SINC3/ SRC FILTER PGA - ADC SINC3/ SRC FILTER GAIN OFFSET GAIN OFFSET GAIN OFFSET REGISTER MAP AND LOGIC CONTROL RESET REFERENCES AIN3+ AIN3- REFERENCES AIN4+ AIN4- PGA - ADC SINC3/ SRC FILTER PGA - ADC SINC3/ SRC FILTER REFERENCES AIN5+ AIN5- REFERENCES AIN6+ AIN6- FORMAT0 HARDWARE MODE CONFIGURATION PGA - ADC SINC3/ SRC FILTER PGA - ADC SINC3/ SRC FILTER REFERENCES GAIN OFFSET GAIN OFFSET AUXAIN+ AUXAIN- MODE3/ALERT MODE2/GPIO2 MODE1/GPIO1 MODE0/GPIO0 ALERT/CS SPI INTERFACE REFERENCES AIN7+ AIN7- FORMAT1 DCLK2/SCLK DCLK1/SDI DCLK0/SDO AD7770 SAR ADC AVSSx AVDD4 CONVST_SAR Figure 1. Rev. E | Page 5 of 97 12538-001 DIAGNOSTIC INPUTS AD7770 Data Sheet SPECIFICATIONS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = analog ground (AGND) (single-supply operation), AVDD2x - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V (internal/external), master clock (MCLK) = 8192 kHz for high resolution mode and 4096 kHz for low power mode, ODR = 32 kSPS for high resolution mode and 8 kSPS for low power mode; all specifications at TMIN to TMAX, unless otherwise noted. Table 1. Parameter - ADC CHANNELS Speed and Performance Resolution ODR No Missing Codes Gain Settings, PGAGAIN Bandwidth AC Accuracy Dynamic Range 32 kSPS 8 kSPS 2 kSPS THD Signal-to-Noise-and-Distortion Ratio (SINAD) SFDR Intermodulation Distortion (IMD) DC Power Supply Rejection DC Common-Mode Rejection Ratio Crosstalk DC ACCURACY INL High Resolution Mode Low Power Mode Test Conditions/Comments Min Typ Max Unit 32 8 Bits kSPS kSPS Bits 2 512 5 1.5 MHz kHz kHz kHz 24 High resolution mode Low power mode Up to 24 kSPS 24 1, 2, 4, or 8 Small signal, high resolution mode Small signal, low power mode Large signal, high resolution mode Large signal, low power mode Shorted inputs, PGAGAIN = 1 High resolution mode High resolution mode Low power mode Low power mode -0.5 dBFS, high resolution mode -0.5 dBFS, low power mode fIN = 60 Hz High resolution mode, 16 kSPS, PGAGAIN = 1 fA = 50 Hz, fB = 51 Hz, high resolution mode fA = 50 Hz, fB = 51 Hz, low power mode AVDD1x = 3.3 V 103 113 103 113 -109 -105 106 dB dB dB dB dB dB dB 132 dB -125 dB -105 dB -90 dB dB -120 dB 8 4 9 6 15 0.25 -2 ppm of FSR ppm of FSR ppm of FSR ppm of FSR V V/C V/ 1000 hours V % FS ppm/C % 80 Endpoint method, PGAGAIN = 1 Other PGA gains Endpoint method, PGAGAIN = 1 Other PGA gains Offset Error Offset Error Drift Over time Offset Matching Gain Error Gain Drift vs. Temperature Gain Matching 25 0.1 0.75 0.1 Rev. E | Page 6 of 97 90 Data Sheet Parameter ANALOG INPUTS Differential Input Voltage Range Single-Ended Input Voltage Range AINx Common-Mode Input Range Absolute AINx Voltage Limits DC Input Current Differential Single-Ended Input Current Drift AC Input Capacitance REFERENCE Internal Initial Accuracy Temperature Coefficient Reference Load Current, IL DC Power Supply Rejection Load Regulation, VOUT/IL Voltage Noise, eN p-p Voltage Noise Density, eN Turn On Settling Time External Input Voltage Buffer Headroom REFx- Input Voltage Average REFx Input Current TEMPERATURE RANGE Specified Performance Functional2 TEMPERATURE SENSOR Accuracy DIGITAL FILTER RESPONSE (SINC3) Group Delay Settling Time Pass Band Decimation Rate AD7770 Test Conditions/Comments Min Typ VREF = (REFx+ - REFx-) AVSSx + 0.10 (AVDD1x + AVSSx)/2 AVSSx + 0.10 High resolution, MCLK = 8192 kHz Low power mode, MCLK = 4096 kHz High resolution, MCLK = 8192 kHz Low power mode, MCLK = 4096 kHz REF_OUT, TA = 25C Unit VREF/PGAGAIN 0 to VREF/PGAGAIN AVDD1x - 0.10 V V V AVDD1x - 0.10 V 4 1 8 2 50 8 2.495 2.5 10 -10 Line regulation nA nA nA nA pA/C pF 2.505 38 +10 V ppm/C mA dB V/mA V rms nV/Hz ms AVDD1x AVDD1x - 0.1 AVDD1x - REFx+ V V V 95 100 6.8 273.5 1.5 0.1 Hz to 10 Hz 1 kHz, 2.5 V reference 100 nF VREF = (REFx+ - REFx-) 1 AVSSx + 0.1 2.5 AVSSx Current per channel Reference buffer disabled, high resolution mode Reference buffer precharge mode (pre-Q), high resolution mode Reference buffer disabled, low power mode Reference buffer pre-Q, low power mode Reference buffer enabled, high resolution mode Reference buffer enabled, low power mode TMIN to TMAX TMIN to TMAX Max 18 A/V 600 nA/V 4.5 A/V 100 nA/V 12 nA/V 5 nA/V -40 -40 +105 +125 2 -0.1 dB -3 dB 64 Rev. E | Page 7 of 97 See the SRC Group Delay section See the Settling Time section See the SRC Bandwidth section See the SRC Bandwidth section 4095.99 C C C AD7770 Parameter CLOCK SOURCE Frequency Duty Cycle SAR ADC Speed and Performance Resolution Analog Input Range Analog Input Common-Mode Range Analog Input Dynamic Current Throughput DC Accuracy INL DNL Offset Gain AC Performance SNR THD VCM PIN Output Load Current, IL Load Regulation, VOUT/IL Short-Circuit Current LOGIC INPUTS Input Voltage High, VIH Low, VIL Hysteresis Input Currents LOGIC OUTPUTS3 Output Voltage High, VOH Low, VOL Leakage Current Output Capacitance - ADC Data Output Coding SAR ADC Data Output Coding Data Sheet Test Conditions/Comments Min High resolution mode Low power mode 0.655 1.3 45:55 Typ Max Unit 50:50 8.192 4.096 55:45 MHz MHz % AVDD4 - 0.1 AVDD4 - 0.1 Bits V V 256 nA kSPS 12 AVSS4 + 0.1 AVSS4 + 0.1 256 kSPS, 0 dBFS (AVDD4 + AVSS4)/2 100 Differential mode 1.5 No missing codes (12-bit) 1 12 LSB LSB LSB LSB 66 -81 dB dB (AVDD1x + AVSSx)/2 1 12 5 V -0.99 1 kHz 1 kHz +1 mA mV/mA mA 0.7 x IOVDD 0.4 0.1 -10 IOVDD 3 V, ISOURCE = 1 mA 2.3 V IOVDD < 3 V, ISOURCE = 500 A IOVDD < 2.3 V, ISOURCE = 200 A IOVDD 3 V, ISINK = 2 mA 2.3 V IOVDD < 3 V, ISINK = 1 mA IOVDD < 2.3 V, ISINK = 100 A Floating state Floating state +10 V V V A 0.8 x IOVDD 0.8 x IOVDD V V 0.8 x IOVDD V V V V A pF 0.4 0.4 0.4 +10 -10 Rev. E | Page 8 of 97 10 Twos complement Binary Data Sheet Parameter POWER SUPPLIES AVDD1x - AVSSx IAVDD1x4, 5 AVDD2x - AVSSx IAVDD2x AD7770 Test Conditions/Comments All - channels enabled AVSSxv - DGND IOVDD - DGND IIOVDD Power Dissipation6 High Resolution Mode Low Power Mode Power-Down Typ Max Unit 3.6 V 18.5 5 23.7 6.4 mA mA 20.5 5.5 26.7 7.1 mA mA 14.3 3.9 18.8 5.1 3.6 9.45 3.7 AVDD1x mA mA V mA mA V 2 10 0 3.6 11.3 4.4 mA A V V mA mA 136 44 mW mW W 3.0 Reference buffer pre-Q, VCM enabled, internal reference enabled High resolution mode Low power mode Reference buffer enabled, VCM enabled, internal reference enabled High resolution mode Low power mode Reference buffer disabled, VCM disabled, internal reference disabled High resolution mode Low power mode 2.2 High resolution mode Low power mode 9 3.5 AVDD1x - 0.3 AVDD4 - AVSSx IAVDD4 Min SAR enabled SAR disabled 1.7 1 -1.8 1.8 High resolution mode Low power mode Internal buffers bypassed, internal reference disabled, internal oscillator disabled, SAR disabled 32 kSPS 8 kSPS All ADCs disabled 8 3 117 38 530 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. At temperatures higher than 105C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because these specifications are only guaranteed up to 105C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at high temperatures. 3 The SDO pin and the DOUTx pin are configured in the default mode of strength. 4 AVDD1x = 3.3 V, AVSSx = GND = ground, IOVDD = 1.8 V, CMOS clock. 5 Disabling either the VCM pin or the internal reference results in a 40 A typical current consumption reduction. 6 Power dissipation is calculated using the maximum supply voltage, 3.6 V. 1 2 Rev. E | Page 9 of 97 AD7770 Data Sheet DOUTx TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND (single-supply operation), AVDD2 - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V internal/external, MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 2 Test Conditions/Comments 50:50 MCLK/2 MCLK/2 Min 0.655 60 60 121 121 Typ Max 8.192 45 45 2 1 20 20 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. t1 t2 t3 MCLK DCLK t4 t6 t5 t8 t7 t9 DRDY DOUTx LSB MSB MSB - 1 t10 t11 Figure 2. Data Interface Timing Diagram Rev. E | Page 10 of 97 LSB + 1 LSB 12538-002 1 Description2 MCLK frequency MCLK low time MCLK high time DCLK high time DCLK low time MCLK falling edge to DCLK rising edge MCLK falling edge to DCLK falling edge DCLK rising edge to DRDY rising edge DCLK rising edge to DRDY falling edge DOUTx setup time DOUTx hold time Unit MHz ns ns ns ns ns ns ns ns ns ns Data Sheet AD7770 SPI TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 3. Parameter t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22A t22B t23 t24 t25 2 Test Conditions/Comments 50:50 Min 7 7 10 10 10 10 10 5 5 30 49 10 10 30 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. t19 CS t15 t16 t17 t13 t14 t18 SCLK t20 SDI MSB t22A SDO MSB - 1 t12 LSB + 1 LSB t21 MSB t22B MSB - 1 LSB + 1 t24 t23 Figure 3. SPI Control Interface Timing Diagram Rev. E | Page 11 of 97 LSB t25 12538-003 1 Description2 SCLK period SCLK low time SCLK high time SCLK rising edge to CS falling edge CS falling edge to SCLK rising edge SCLK rising edge to CS rising edge CS rising edge to SCLK rising edge Minimum CS high time SDI setup time SDI hold time CS falling edge to SDO enable (SPI = Mode 0) SCLK falling edge to SDO enable (SPI = Mode 3) SDO setup time SDO hold time CS rising edge to SDO disable Typ Max 30 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns AD7770 Data Sheet SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 4. Parameter t26 t27 t28 t29 t30 tINIT_SYNC_IN tINIT_RESET t31 tPOWER_UP 2 Test Conditions/Comments 16 kSPS, high resolution mode 16 kSPS, high resolution mode Min 10 MCLK MCLK 10 MCLK 145 225 2 x MCLK Typ tPOWER_UP is not shown in Figure 4 2 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. MCLK START t26 t27 SYNC_OUT t28 SYNC_IN t29 t30 DRDY tINIT_SYNC_IN RESET t31 tINIT_RESET Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram Rev. E | Page 12 of 97 12538-004 1 Description2 START setup time START hold time MCLK falling edge to SYNC_OUT falling edge SYNC_IN setup time SYNC_IN hold time SYNC_IN rising edge to first DRDY RESET rising edge to first DRDY RESET hold time Start time Max Unit ns ns ns ns ns s s ns ms Data Sheet AD7770 SAR ADC TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted. Table 5. Parameter t32 t33 t34 t35 1 2 3 Description2 Conversion time Acquisition time3 Delay time Throughput data rate Min 1 500 50 Typ Max 3.4 Unit s ns ns kSPS 256 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK as described in Table 30. CS t33 t32 t34 12538-005 CONVST_SAR t35 Figure 5. SAR ADC Timing Diagram GPIO SRC UPDATE TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = -1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 - AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx- = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter t36 t37 t37 t38 t39 t40 2 Min 10 Typ MCLK 2 x MCLK 20 MCLK 5 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. MCLK GPIO2 t36 t37 GPIO1 t38 GPIO0 t39 t40 Figure 6. GPIOs for SRC Update Timing Diagram Rev. E | Page 13 of 97 12538-006 1 Description2 GPIO2 setup time GPIO2 hold time High resolution mode Low power mode MCLK rising edge to GPIO1 rising edge time GPIO0 hold time GPIO0 setup time Max Unit ns ns ns ns ns AD7770 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Any Supply Pin to AVSSx AVSSx to DGND AREGxCAP to AVSSx DREGCAP to DGND IOVDD to DGND IOVDD to AVSSx AVDD4 to AVSSx Analog Input Voltage REFx Input Voltage AUXAIN Digital Input Voltage to DGND Digital Output Voltage to DGND XTAL1 to DGND AINx, AUXAIN, and Digital Input Current Operating Temperature Range Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering ESD Field Induced Charged Device Model (FICDM) Rating -0.3 V to +3.96 V -1.98 V to +0.3 V -0.3 V to +1.98 V -0.3 V to +1.98 V -0.3 V to +3.96 V -0.3 V to +5.94 V AVDD1x - 0.3 V to 3.96 V AVSSx - 0.3 V to AVDD1x + 0.3 V or 3.96 V (whichever is less) AVSSx - 0.3 V to AVDD1x + 0.3 V or 3.96 V (whichever is less) AVSSx - 0.3 V to AVDD4 + 0.3 V or 3.96 V (whichever is less) DGND - 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less) DGND - 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less) DGND - 0.3 V to DREGCAP + 0.3 V or 1.98 V (whichever is less) 10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 8. Thermal Resistance Package Type1 64-Lead LFCSP No Thermal Vias 49 Thermal Vias 1 JA JB JT JB Unit 30.43 22.62 N/A2 3.17 0.13 0.09 6.59 3.19 C/W C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. 2 N/A means not applicable. ESD CAUTION -40C to +125C 150C -65C to +150C 260C 2 kV 500 V Rev. E | Page 14 of 97 Data Sheet AD7770 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AUXAIN- AUXAIN+ AVDD4 AVSS4 AVSS2A AREG1CAP AVDD2A VCM CLK_SEL FORMAT0 FORMAT1 AVSS3 AVDD2B AREG2CAP AVSS2B REF_OUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD7770 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AIN4- AIN4+ AIN5- AIN5+ AVSS1B AVDD1B REF2- REF2+ AIN6- AIN6+ AIN7- AIN7+ RESET SYNC_IN SYNC_OUT START NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx. 12538-007 CONVST_SAR ALERT/CS DCLK2/SCLK DCLK1/SDI DCLK0/SDO DGND DREGCAP IOVDD DOUT3 DOUT2 DOUT1 DOUT0 DCLK DRDY XTAL1 XTAL2/MCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AIN0- AIN0+ AIN1- AIN1+ AVSS1A AVDD1A REF1- REF1+ AIN2- AIN2+ AIN3- AIN3+ MODE0/GPIO0 MODE1/GPIO1 MODE2/GPIO2 MODE3/ALERT Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic AIN0- AIN0+ AIN1- AIN1+ AVSS1A Type Analog input Analog input Analog input Analog input Supply Direction Input Input Input Input Supply 6 AVDD1A Supply Supply 7 REF1- Reference Input 8 9 10 11 12 13 REF1+ AIN2- AIN2+ AIN3- AIN3+ MODE0/GPIO0 Reference Analog input Analog input Analog input Analog input Digital I/O Input Input Input Input Input I/O 14 MODE1/GPIO1 Digital I/O I/O Description Analog Input Channel 0, Negative. Analog Input Channel 0, Positive. Analog Input Channel 1, Negative. Analog Input Channel 1, Positive. Negative Front-End Analog Supply for Channel 0 to Channel 3, Typical at -1.65 V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the same potential. Positive Front-End Analog Supply for Channel 0 to Channel 3, Typical at AVSSx + 3.3 V. Connect this pin to AVDD1B. Negative Reference Input 1 for Channel 0 to Channel 3, Typical at AVSSx. Connect all the REFx- pins to the same potential. Positive Reference Input 1 for Channel 0 to Channel 3, Typical at REF1- + 2.5 V. Analog Input Channel 2, Negative. Analog Input Channel 2, Positive. Analog Input Channel 3, Negative. Analog Input Channel 3, Positive. Mode 0 Input in Pin Control Mode (MODE0). See Table 14 for more details. Configurable General-Purpose Input/Output 0 in SPI Control Mode (GPIO0). If not in use, connect this pin to DGND or IOVDD. Mode 1 Input in Pin Control Mode (MODE1). See Table 14 for more details. Configurable General-Purpose Input/Output 1 in SPI Control Mode (GPIO1). If not in use, connect this pin to DGND or IOVDD. Rev. E | Page 15 of 97 AD7770 Data Sheet Pin No. 15 Mnemonic MODE2/GPIO2 Type Digital I/O Direction I/O 16 MODE3/ALERT Digital I/O I/O 17 CONVST_SAR Digital input Input 18 ALERT/CS Digital input Input 19 DCLK2/SCLK Digital input Input 20 DCLK1/SDI Digital input Input 21 DCLK0/SDO Digital output Output 22 23 DGND DREGCAP Supply Supply Supply Output 24 IOVDD Supply Supply 25 DOUT3 Digital output I/O 26 DOUT2 Digital output I/O 27 28 29 30 31 DOUT1 DOUT0 DCLK DRDY XTAL1 Digital output Digital output Digital output Digital output Clock Output Output Output Output Input 32 XTAL2/MCLK Clock Input 33 START Digital input Input 34 SYNC_OUT Digital output Input 35 SYNC_IN Digital input Input 36 RESET Digital input Input 37 38 39 40 41 AIN7+ AIN7- AIN6+ AIN6- REF2+ Analog input Analog input Analog input Analog input Reference Input Input Input Input Input Description Mode 2 Input in Pin Control Mode (MODE2). See Table 14 for more details. Configurable General-Purpose Input/Output 2 in SPI Control Mode (GPIO2). If not in use, connect this pin to DGND or IOVDD. Mode 3 Input in Pin Control Mode (MODE3). See Table 14 for more details. Alert Output in SPI Control Mode (ALERT). - Output Interface Selection Pin in Pin Control Mode. See Table 13 for more details. This pin also functions as the start for the SAR conversion in SPI control mode. Alert Output in Pin Control Mode (ALERT). Chip Select in SPI Control Mode (CS). DCLK Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15 for more details. SPI Clock in SPI Control Mode (SCLK). DCLK Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 15 for more details. SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the device is configured in pin control mode with the SPI as the data output interface. DCLK Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 15 for more details. SPI Data Output in SPI Control Mode (SDO). Digital Ground. Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a 1 F capacitor. Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V. IOVDD must not be lower than DREGCAP. Data Output Pin 3. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. Data Output Pin 2. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. Data Output Pin 1. Data Output Pin 0. Data Output Clock. Data Output Ready Pin. Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to DGND. See Table 12 for more details. Crystal 2 Input Connection (XTAL2). See Table 12 for more details. CMOS Clock (MCLK). See Table 12 for more details. Synchronization Pulse. This pin internally synchronizes an external START asynchronous pulse with MCLK. The synchronize signal is shifted out by the SYNC_OUT pin. If not in use, tie this pin to IOVDD. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. Synchronization Signal. This pin generates a synchronous pulse generated and driven by hardware (via the START pin) or by software (GENERAL_USER_ CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. Reset for the Internal Digital Block and Synchronize for Multiple Devices. See the Digital Reset and Synchronization Pins section for more details. Asynchronous Reset Pin. This pin resets all registers to their default value. It is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. Analog Input Channel 7, Positive. Analog Input Channel 7, Negative. Analog Input Channel 6, Positive. Analog Input Channel 6, Negative. Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2- + 2.5 V. Rev. E | Page 16 of 97 Data Sheet AD7770 Pin No. 42 Mnemonic REF2- Type Reference Direction Input 43 AVDD1B Supply Supply 44 AVSS1B Supply Supply 45 46 47 48 49 AIN5+ AIN5- AIN4+ AIN4- REF_OUT Analog input Analog input Analog input Analog input Reference Input Input Input Input Output 50 51 52 53 54 55 56 57 58 AVSS2B AREG2CAP AVDD2B AVSS3 FORMAT1 FORMAT0 CLK_SEL VCM AVDD2A Supply Supply Supply Supply Digital input Digital input Digital input Analog output Supply Supply Output Supply Supply Input Input Input Output Input 59 60 61 AREG1CAP AVSS2A AVSS4 Supply Supply Supply Output Input Supply 62 63 64 AVDD4 AUXAIN+ AUXAIN- EPAD Supply Analog input Analog input Supply Supply Input Input Input Description Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx. Connect all the REFx- pins to the same potential. Positive Front-End Analog Supply for Channel 4 to Channel 7. Connect this pin to AVDD1A. Negative Front-End Analog Supply for Channel 4 to Channel 7, typical at -1.65 V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the same potential. Analog Input Channel 5, Positive. Analog Input Channel 5, Negative. Analog Input Channel 4, Positive. Analog Input Channel 4, Negative. 2.5 V Reference Output. Connect a 100 nF capacitor on this pin if using the internal reference. Negative Analog Supply. Connect all the AVSSx pins to the same potential. Analog LDO Output 2. Decouple this pin to AVSS2B with a 1 F capacitor. Positive Analog Supply. Connect this pin to AVDD2A. Negative Analog Ground. Connect all the AVSSx pins to the same potential. Output Data Frame 1. See Table 13 for more details. Output Data Frame 0. See Table 13 for more details. Select Clock Source. See Table 12 for more details. Common-Mode Voltage Output, Typical at (AVDD1 + AVSSx)/2. Analog Supply from 2.2 V to 3.6 V. AVSS2x must not be lower than AREGxCAP. Connect this pin to AVDD2B. Analog LDO Output 1. Decouple this pin to AVSSx with a 1 F capacitor. Negative Analog supply. Connect all the AVSSx pins to the same potential. Negative SAR Analog Supply and Reference. Connect all AVSSx pins to the same potential. Positive SAR Analog Supply and Reference Source. Positive SAR Analog Input Channel. Negative SAR Analog Input Channel. Exposed Pad. Connect the exposed pad to AVSSx. Rev. E | Page 17 of 97 AD7770 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 5 INL (ppm) CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 INPUT VOLTAGE (V) Figure 8. INL vs. Input Voltage and Channel at 16 kSPS, High Resolution Mode 10 8 6 1.77 1.41 1.06 0.70 0 0.35 -0.35 -0.70 -15 -1.06 1.77 1.41 1.06 0.70 0 0.35 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -2.48 -10 -10 -2.48 -8 12538-208 -6 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -5 2.48 -4 2.48 -2 0 INPUT VOLTAGE (V) 12538-211 0 2.12 2 2.12 INL (ppm) 4 -1.41 6 TEMPERATURE = 25C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 -1.77 8 15 TEMPERATURE = 25C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 -2.12 10 Figure 11. INL vs. Input Voltage and Channel at 4 kSPS, Low Power Mode 10 TEMPERATURE = 25C VREF = 2.5V DIFFERENTIAL VIN x GAIN VCM = (AVDD1x + AVSSx) / 2 TEMPERATURE = 25C VREF = 2.5V DIFFERENTIAL VIN x GAIN VCM = (AVDD1x + AVSSx) / 2 5 2 INL (ppm) INL (ppm) 4 0 -2 0 -5 -4 Figure 9. INL vs. Input Voltage and PGA Gain at 16 kSPS, High Resolution Mode 10 8 6 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -2.48 -15 INPUT VOLTAGE (V) 12538-212 INPUT VOLTAGE (V) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -10 12538-209 2.48 1.41 1.06 0.70 0.35 0 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -2.48 -10 2.12 -8 1.77 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -6 Figure 12. INL vs. Input Voltage and PGA Gain at 4 kSPS, Low Power Mode 15 GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 10 GAIN = 1 DIFFERENTIAL INPUT SIGNAL VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 4 5 INL (ppm) 0 -2 -4 0 -5 -6 INPUT VOLTAGE (V) Figure 13. INL vs. Input Voltage and Temperature at 4 kSPS, Low Power Mode Figure 10. INL vs. Input Voltage and Temperature at 16 kSPS, High Resolution Mode Rev. E | Page 18 of 97 2.48 2.12 1.77 1.41 1.06 0.70 0.35 0 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -2.48 -15 12538-213 INPUT VOLTAGE (V) TA = -40C TA = +25C TA = +105C TA = +125C -10 12538-210 2.48 2.12 1.06 0.70 0.35 0 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -12 1.77 -10 1.41 TA = -40C TA = +25C TA = +105C TA = +125C -8 -2.48 INL (ppm) 2 Data Sheet 20 20 TEMPERATURE = 25C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VCM = (AVDD1x + AVSSx) / 2 15 10 10 5 5 0 -5 -15 -20 -4 -3 -2 -1 0 1 2 = 1V = 1.5V = 2V = 2.5V = 3V = 3.3V 3 -15 4 INPUT VOLTAGE (V) -20 -4 6 -2 -1 0 1 2 3 4 Figure 17. INL vs. Input Voltage and VREF at 4 kSPS, Low Power Mode 15 TEMPERATURE = 25C VREF = 2.5V DIFFERENTIAL INPUT SIGNAL GAIN = 1 8 -3 = 1V = 1.5V = 2V = 2.5V = 3V = 3.3V INPUT VOLTAGE (V) Figure 14. INL vs. Input Voltage and Reference Voltage (VREF) at 16 kSPS, High Resolution Mode 10 VREF VREF VREF VREF VREF VREF -10 12538-214 VREF VREF VREF VREF VREF VREF -10 TEMPERATURE = 25C VREF = 2.5V DIFFERENTIAL INPUT SIGNAL GAIN =1 10 4 5 2 INL (ppm) 0 -2 0 -5 -10 1000 2.48 12538-218 2.12 1.77 1.06 0.70 0.35 -0.35 -0.70 -1.06 0 Rev. E | Page 19 of 97 12538-219 ADC CODE Figure 19. Noise Histogram at 4 kSPS, Low Power Mode Figure 16. Noise Histogram at 16 kSPS, High Resolution Mode 8388644 8388604 8388564 8388524 8388484 8388444 8388404 8388364 12538-216 8388652 8388608 8388564 8388520 8388476 8388432 0 8388388 0 8388344 200 8388300 200 8388256 400 8388212 400 ADC CODE -1.41 600 8388324 600 800 8388284 800 8388244 1000 VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 TEMPERATURE = 25C GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1200 SAMPLE COUNT 1200 Figure 18. INL vs. Input Voltage and VCM at 4 kSPS, Low Power Mode 1400 VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 TEMPERATURE = 25C GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -1.77 INPUT VOLTAGE (V) Figure 15. INL vs. Input Voltage and VCM at 16 kSPS, High Resolution Mode 1400 -2.12 -2.48 2.48 INPUT VOLTAGE (V) VCM = 1.35V VCM = 1.65V VCM = 1.95V -15 12538-215 2.12 1.41 1.06 0.70 0 0.35 -0.35 -0.70 -1.06 -1.41 -1.77 -2.12 -2.48 -10 1.77 VCM = 1.35V VCM = 1.65V VCM = 1.95V -8 8388204 -6 1.41 -4 8388164 INL (ppm) 0 12538-217 -5 SAMPLE COUNT TEMPERATURE = 25C GAIN = 1 DIFFERENTIAL INPUT SIGNAL VCM = (AVDD1x + AVSSx) / 2 15 INL (ppm) INL (ppm) AD7770 AD7770 8 Data Sheet 8 VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 7 6 NOISE (V rms) 5 4 3 4 3 2 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 0 -40 25 105 TEMPERATURE (C) 125 0 -40 Figure 20. Noise vs. Temperature at 16 kSPS, High Resolution Mode 25 105 TEMPERATURE (C) 125 Figure 23. Noise vs. Temperature at 4 kSPS, Low Power Mode 7 7 6 6 VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 TEMPERATURE = 25C DECIMATION = 256 VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 TEMPERATURE = 25C DECIMATION = 256 5 NOISE (V rms) 5 4 3 4 3 2 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 CLOCK FREQUENCY (Hz) 0 CLOCK FREQUENCY (Hz) Figure 21. Noise vs. Clock Frequency, High Resolution Mode 140 120 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1 12538-221 335360 652800 970240 1287680 1605120 1922560 2240000 2557440 2874880 3192320 3509760 3827200 4144640 4462080 4779520 5096960 5414400 5731840 6049280 6366720 6684160 7001600 7319040 7636480 7953920 1 12538-224 2 0 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 1 12538-220 1 12538-223 2 5 294400 448000 601600 755200 908800 1062400 1216000 1369600 1523200 1676800 1830400 1984000 2137600 2291200 2444800 2598400 2752000 2905600 3059200 3212800 3366400 3520000 3673600 3827200 3980800 NOISE (V rms) 6 NOISE (V rms) VREF = 2.5V VCM = (AVDD1x + AVSSx) / 2 7 Figure 24. Noise vs. Clock Frequency, Low Power Mode 300 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 250 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 NOISE (nV/Hz) 80 60 200 150 100 40 0 2000 4000 8000 16000 32000 ODR (SPS) Figure 22. Noise vs. ODR, High Resolution Mode 0 500 1000 2000 4000 ODR (SPS) Figure 25. Noise vs. ODR, Low Power Mode Rev. E | Page 20 of 97 8000 12538-225 50 20 12538-222 NOISE (nV/Hz) 100 FREQUENCY (Hz) 3925.78125 12538-229 3664.06250 3402.34375 3140.62500 2878.90625 2617.18750 2355.46875 2093.75000 1832.03125 1570.31250 1308.59375 12538-230 3828.1250 3554.6875 3281.2500 3007.8125 2734.3750 2460.9375 2187.5000 1914.0625 1640.6250 1367.1875 1093.7500 -100 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -105 -110 THD (dB) -115 -120 -115 -120 -125 Figure 28. THD vs. Input Frequency at 16 kSPS, High Resolution Mode Rev. E | Page 21 of 97 INPUT FREQUENCY (Hz) Figure 31. THD vs. Input Frequency at 4 kSPS, Low Power Mode 12538-231 1870.0 1660.0 1440.0 1220.0 1010.0 811.9 604.0 VIN = -0.5dBFS VREF = 2.5V TEMPERATURE = 25C 406.0 7860 7160 6320 5620 4710 -130 12538-228 INPUT FREQUENCY (Hz) 3870 3170 2400 1700 1000 901 802 703 604 505 406 307 208 10 109 VIN = -0.5dBFS VREF = 2.5V TEMPERATURE = 25C 208.0 -125 10.0 THD (dB) 820.3125 Figure 30. FFT at 8 kSPS, Low Power Mode, Input Frequency (fIN) = 1 kHz -110 -130 546.8750 FREQUENCY (Hz) Figure 27. FFT at 32 kSPS, High Resolution Mode, Input Frequency (fIN) = 1 kHz -105 VREF = 2.5V TEMPERATURE = 25C DIFFERENTIAL INPUT = -0.5dBFS VCM = (AVDD1x + AVSSx) / 2 INPUT FREQUENCY = 1kHz 8192 SAMPLES 8kSPS GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 12538-227 0 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 273.4375 AMPLITUDE (dB) 14984.375000 13914.062500 12843.750000 FREQUENCY (Hz) -100 785.15625 Figure 29. FFT at 8 kSPS, Low Power Mode, Input Frequency (fIN) = 50 Hz GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 11773.437500 9632.812500 10703.125000 8562.500000 7648.437500 6533.203125 5462.890625 4388.671875 3304.687500 2234.375000 0 1103.515625 AMPLITUDE (dB) VREF = 2.5V TEMPERATURE = 25C DIFFERENTIAL INPUT = -0.5dBFS VCM = (AVDD1x + AVSSx) / 2 INPUT FREQUENCY = 1kHz 16384 SAMPLES 32kSPS GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 FREQUENCY (Hz) Figure 26. FFT at 32 kSPS, High Resolution Mode, Input Frequency (fIN) = 50 Hz 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 1046.87500 VREF = 2.5V TEMPERATURE = 25C DIFFERENTIAL INPUT = -0.5dBFS VCM = (AVDD1x + AVSSx) / 2 INPUT FREQUENCY = 50Hz 8192 SAMPLES 8kSPS 523.43750 0 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 261.71875 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 AMPLITUDE (dB) VREF = 2.5V TEMPERATURE = 25C DIFFERENTIAL INPUT = -0.5dBFS VCM = (AVDD1x + AVSSx) / 2 INPUT FREQUENCY = 50Hz 16384 SAMPLES 32kSPS 12538-226 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 AD7770 0 656.250000 1296.875000 1986.328125 2617.187500 3250.000000 3884.765625 4156.250000 4789.062500 5427.734375 6066.406250 6703.125000 7312.500000 7921.875000 8531.250000 9140.625000 9750.000000 10359.375000 10968.750000 11578.125000 12187.500000 12796.875000 13406.250000 14015.625000 14625.000000 15234.375000 15843.750000 AMPLITUDE (dB) Data Sheet AD7770 Data Sheet -105 -110 -115 -115 THD (dB) -110 -120 -125 -130 -130 INPUT FREQUENCY = 50Hz VREF = 2.5V TEMPERATURE = 25C INPUT VOLTAGE (V) 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 -140 INPUT VOLTAGE (V) Figure 32. THD vs. Input Voltage at 16 kSPS, High Resolution Mode -90 Figure 35. THD vs. Input Voltage at 4 kSPS, Low Power Mode -90 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -95 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -95 -100 -105 -105 THD (dB) -100 -110 -115 -110 -115 -120 INPUT FREQUENCY = 50Hz INPUT VOLTAGE = -0.5dBFS TEMPERATURE = 25C REFERENCE VOLTAGE (V) -125 12538-233 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 -105 Figure 36. THD vs. Reference Voltage at 4 kSPS, Low Power Mode -100 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 INPUT FREQUENCY = 50Hz VREF = 2.5V INPUT VOLTAGE = -0.5dBFS TEMPERATURE = 25C DECIMATION = 256 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 REFERENCE VOLTAGE (V) Figure 33. THD vs. Reference Voltage at 16 kSPS, High Resolution Mode -100 INPUT FREQUENCY = 50Hz INPUT VOLTAGE = -0.5dBFS TEMPERATURE = 25C 12538-236 -120 -125 INPUT FREQUENCY = 50Hz VREF = 2.5V TEMPERATURE = 25C -135 0.172 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 4.644 -140 THD (dB) -120 -125 -135 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -105 12538-232 THD (dB) -100 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 12538-235 -100 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 INPUT FREQUENCY = 50Hz VREF = 2.5V INPUT VOLTAGE = -0.5dBFS TEMPERATURE = 25C DECIMATION = 256 -105 THD (dB) -115 -115 -120 -120 Figure 34. THD vs. MCLK Frequency, High Resolution Mode Rev. E | Page 22 of 97 3976960 3659520 3342080 3024640 2707200 2389760 2072320 1754880 1437440 802560 1120000 485120 167680 MCLK FREQUENCY (Hz) Figure 37. THD vs. MCLK Frequency, Low Power Mode 12538-237 MCLK FREQUENCY (Hz) -130 12538-234 7953920 7319040 6684160 6049280 5414400 4779520 4144640 3509760 2874880 2240000 1605120 970240 -125 -125 335360 THD (dB) -110 -110 Data Sheet AD7770 GAIN = GAIN = GAIN = GAIN = 115 110 110 SNR (dB) 115 105 100 95 95 VIN = 0dBFS VREF = 2.5V TEMPERATURE = 25C 1 2 VIN = 0dBFS VREF = 2.5V TEMPERATURE = 25C 90 4 8 16 32 ODR (kHz) 85 0.5 120 TEMPERATURE = 25C ODR = 16kSPS DYNAMIC RANGE (dB) TEMPERATURE = 25C ODR = 4kSPS 110 105 110 105 100 1 2 4 95 12538-239 95 8 PGA GAIN 1 8 Figure 42. Dynamic Range vs. PGA Gain, Low Power Mode 5 TEMPERATURE = 25C VIN = 0V VREF = 2.5V AVDD1x = 3.3V -5 4 PGA GAIN Figure 39. Dynamic Range vs. PGA Gain, High Resolution Mode 0 2 12538-242 DYNAMIC RANGE (dB) 8 115 100 TEMPERATURE = 25C VIN = 0V VREF = 2.5V AVDD1x = 3.3V 0 -5 OFFSET ERROR (V) -10 -15 -20 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -25 -30 1 2 4 PGA GAIN -10 -15 -20 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -25 -30 8 12538-240 OFFSET ERROR (V) 4 Figure 41. SNR vs. ODR at 4 kSPS, Low Power Mode 115 -35 2 ODR (kHz) Figure 38. SNR vs. ODR at 16 kSPS, High Resolution Mode 120 1 Figure 40. Offset Error vs. PGA Gain, High Resolution Mode -35 1 2 4 PGA GAIN Figure 43. Offset Error vs. PGA Gain, Low Power Mode Rev. E | Page 23 of 97 8 12538-243 85 1 2 4 8 105 100 90 GAIN = GAIN = GAIN = GAIN = 120 12538-238 SNR (dB) 120 125 1 2 4 8 12538-241 125 AD7770 0 Data Sheet -2 4 TEMPERATURE = 25C VIN = 0V VREF = 2.5V GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 2 0 -2 OFFSET ERROR (V) -6 -8 -10 -12 -4 -6 -8 -14 -12 -16 -16 3.0 Figure 44. Offset Error vs. Power Supply Setting, High Resolution Mode 40 3.3 3.6 POWER SUPPLY SETTING 12538-247 3.6 12538-244 3.3 POWER SUPPLY SETTING Figure 47. Offset Error vs. Power Supply Setting, Low Power Mode 45 AVDD1x = 3.3V 40 30 35 GAIN ERROR DRIFT (ppm) 20 10 0 -10 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -50 -40 -20 0 20 40 60 80 100 30 25 20 15 10 5 0 -5 -10 -15 120 -20 TEMPERATURE (C) 0 0 0.017 TEMPERATURE = 25C GAIN = 1 VREF = 2.5V VIN = 0dBFS 0.008 0 -0.008 -0.017 -0.035 3.6 AVDD1x SUPPLY (V) 12538-246 -0.035 3.3 Figure 46. Gain Error vs. AVDD1x Supply, High Resolution Mode TEMPERATURE = 25C GAIN = 1 VREF = 2.5V VIN = 0dBFS -0.017 -0.026 3.0 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -0.008 -0.026 -0.043 1000 Figure 48. Gain Error Drift vs. Time GAIN ERROR (%) 0.008 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 500 TIME (Hours) Figure 45. Offset Drift vs. Temperature 0.017 168 12538-248 -40 12538-245 -20 -30 GAIN ERROR (%) TEMPERATURE = 25C VIN = 0V VREF = 2.5V -14 -18 3.0 OFFSET DRIFT (V) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -10 -0.043 3.0 3.3 AVDD1x SUPPLY (V) Figure 49. Gain Error vs. AVDD1x Supply, Low Power Mode Rev. E | Page 24 of 97 3.6 12538-249 OFFSET ERROR (V) -4 Data Sheet 0.005 0 -0.005 -0.011 -0.017 -0.011 -0.017 -0.023 -0.029 -0.029 -0.035 -0.035 25 105 125 TEMPERATURE (C) -0.400 -40 0.09 3 0.06 HIGH RESOLUTION LOW POWER 0.05 0.04 0.03 0.02 0.01 2 1 0 -1 -2 -3 -4 1 2 4 8 PGA GAIN -6 -40 25 105 125 TEMPERATURE (C) Figure 51. Channel Gain Mismatch, High Resolution Mode 12538-254 -5 12538-251 0 125 4 REFERENCE VOLTAGE DRIFT (mV) 0.07 105 Figure 53. Gain Error vs. Temperature, Low Power Mode TEMPERATURE = 25C AVDD1x = 3.3V VREF = 2.5V VIN = 0dBFS 0.08 25 TEMPERATURE (C) Figure 50. Gain Error vs. Temperature, High Resolution Mode GAIN ERROR (%) -0.005 -0.023 -0.400 -40 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 AVDD1x = 3.3V VREF = 2.5V VIN = 0dBFS 0.005 12538-250 GAIN ERROR (%) 0 0.011 12538-253 0.011 0.017 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 AVDD1x = 3.3V VREF = 2.5V VIN = 0dBFS GAIN ERROR (%) 0.017 AD7770 Figure 54. Internal Reference Voltage Drift 0.005 0.010 0 0.005 TEMPERATURE = 25C VIN = -0.5dBFS VREF = 2.5V AVDD1x = 3.3V GAIN = 1 -0.015 -0.020 TEMPERATURE = 25C VIN = -0.5dBFS VREF = 2.5V AVDD1x = 3.3V GAIN = 1 -0.025 -0.030 -40 25 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 105 TEMPERATURE (C) Figure 52. Total Unadjusted Error (TUE) vs. Temperature, High Resolution Mode 125 0 -0.005 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 -0.010 -0.015 -40 25 105 TEMPERATURE (C) 125 12538-255 TUE (% OF INPUT) -0.010 12538-252 TUE (% OF INPUT) -0.005 Figure 55. Total Unadjusted Error (TUE) vs. Temperature, Low Power Mode Rev. E | Page 25 of 97 AD7770 Data Sheet 1.0 4 AINx+; VCM = 1.95V AINx-; VCM = 1.95V AINx+; VCM = 1.35V AINx-; VCM = 1.35V 3 AINx+; VCM = 1.95V AINx-; VCM = 1.95V AINx+; VCM = 1.35V AINx-; VCM = 1.35V 0.8 0.6 INPUT CURRENT (nA) INPUT CURRENT (nA) 2 1 0 -1 0.4 0.2 0 -0.2 -0.4 -2 -0.6 -0.8 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 DIFFERENTIAL INPUT VOLTAGE ((AINx+) - (AINx-)) Figure 56. Input Current vs. Differential Input Voltage, High Resolution Mode ABSOLUTE INPUT CURRENT (nA) -4 -6 -8 -10 -12 -40 AIN0+ AIN0- AIN2+ AIN2- 105 125 TEMPERATURE (C) Figure 57. Absolute Input Current vs. Temperature, High Resolution Mode VREF = 2.5V AVDD1x = 3.3V 2 1 0 -1 -2 -3 -4 -5 -2.5 2.0 2.5 -3 -4 -6 -40 AIN0+ AIN0- AIN2+ AIN2- 25 105 125 TEMPERATURE (C) Figure 60. Absolute Input Current vs. Temperature, Low Power Mode 1.0 3 1.5 -2 1.2 AINx+ - AINx-; V CM = 1.95V AINx+ - AINx-; V CM = 1.35V 1.0 -1 DIFFERENTIAL INPUT CURRENT (nA) 4 0.5 0 VREF = 2.5V AVDD1x = 3.3V AINx+ - AINx-; V CM = 1.95V AINx+ - AINx-; V CM = 1.35V 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) - (AINx-)) 2.5 12538-258 DIFFERENTIAL INPUT CURRENT (nA) 5 0 1 -5 25 -0.5 2 12538-257 ABSOLUTE INPUT CURRENT (nA) -2 -1.0 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 3 0 -1.5 Figure 59. Input Current vs. Differential Input Voltage, Low Power Mode 4 2 -2.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) - (AINx-)) VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 4 VREF = 2.5V AVDD1x = 3.3V Figure 58. Differential Input Current vs. Differential Input Voltage, High Resolution Mode -1 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT VOLTAGE ((AINx+) - (AINx-)) 2.5 Figure 61. Differential Input Current vs. Differential Input Voltage, Low Power Mode Rev. E | Page 26 of 97 12538-261 6 -1.0 -2.5 12538-259 VREF = 2.5V AVDD1x = 3.3V 12538-256 -4 -2.5 12538-260 -3 Data Sheet AD7770 8 105 125 TEMPERATURE (C) Figure 62. Differential Input Current vs. Temperature, High Resolution Mode 0 -20 6 5 4 3 2 1 0 -40 125 0 -20 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 AVDD1x = 3.3V VCM = 1.65V + 100mV p-p Figure 64. AC Power Supply Rejection Ratio (PSRR) vs. Input Frequency at 16 kSPS, High Resolution Mode Rev. E | Page 27 of 97 188933.526 12538-266 175653.757 162215.895 148461.848 121586.125 107990.171 81114.447 135023.987 INPUT FREQUENCY (Hz) Figure 67. AC PSRR vs. Input Frequency at 4 kSPS, Low Power Mode 12538-267 9460001.00 8900002.00 8360002.00 7780003.00 7240004.00 6680005.00 6140006.00 5580007.00 5040007.00 4500008.00 3880009.00 12538-264 9460001.00 8900002.00 8360002.00 7780003.00 7240004.00 6680005.00 6140006.00 5580007.00 5040007.00 4500008.00 3880009.00 3320010.00 2780011.00 -150 -160 2220012.00 -150 -160 1680012.00 -130 -140 1140013.00 -120 -130 -140 20014.97 -120 3320010.00 -100 -110 2780011.00 -100 -110 -80 -90 2220012.00 -80 -90 1680012.00 AC PSRR (dB) -60 -70 1140013.00 198023.844000 -50 -60 -70 580014.13 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -30 -40 -50 INPUT FREQUENCY (Hz) 94552.309 0 AVDD1x = 3.3V + 100mV p-p -10 TEMPERATURE = 25C -20 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -30 -40 67360.401 Figure 66. CMRR vs. Input Frequency at 4 kSPS, Low Power Mode 20014.97 0 AVDD1x = 3.3V + 100mV p-p -10 TEMPERATURE = 25C -20 40642.77 INPUT FREQUENCY (Hz) Figure 63. Common-Mode Rejection Ratio (CMRR) vs. Input Frequency at 16 kSPS, High Resolution Mode 580014.13 INPUT FREQUENCY (Hz) 12538-263 184506.936000 171543.352000 158105.490000 145141.906000 132178.322000 118661.414000 92101.875000 105697.830000 79138.291000 -140 66174.707000 -140 52578.753000 -120 39615.169000 -120 26177.307000 -100 250.138735 -100 53922.539 -80 26888.723 -80 -60 13450.862 -60 171.09249 CMRR (dB) -40 13213.723000 CMRR (dB) 105 Figure 65. Differential Input Current vs. Temperature, Low Power Mode -40 AC PSRR (dB) 25 TEMPERATURE (C) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 AVDD1x = 3.3V VCM = 1.65V + 100mV p-p CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 12538-265 25 VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V 7 DIFFERENTIAL INPUT CURRENT (nA) CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 12538-262 DIFFERENTIAL INPUT CURRENT (nA) VREF = 2.5V VIN = 2.5V AVDD1x = 3.3V AD7770 Data Sheet 0 0 GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -10 -20 -20 -30 -70 Figure 68. Filter Profiles at 16 kSPS, High Resolution Mode 20 18 7681.0 7202.5 6724.0 6245.5 5767.0 5288.5 4810.0 4331.5 3853.0 Figure 71. Filter Profiles at 4 kSPS, Low Power Mode 6 AVDD1x AVDD2x AVDD4 IOVDD 5 ALL CHANNELS ENABLED SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 3374.5 FREQUENCY (Hz) 12538-271 FREQUENCY (Hz) 12538-268 30721.0 28802.5 26884.0 24965.5 23047.0 21128.5 19210.0 17291.5 15373.0 13454.5 9617.5 11536.0 7699.0 -120 5780.5 -110 -120 3862.0 -110 25.0 -100 1943.5 -90 -100 2896.0 -80 -90 2417.5 -80 -60 1939.0 -70 -50 982.0 -60 -40 1460.5 -50 25.0 -40 503.5 ATTENUATION (dB) -30 ATTENUATION (dB) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 -10 14 12 10 8 6 4 AVDD1x AVDD2x AVDD4 IOVDD ALL CHANNELS ENABLED 4 3 2 1 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 0 2.0 12538-269 0 2.0 2.6 2.8 3.0 3.2 3.4 3.6 Figure 72. Supply Current vs. Supply Voltage, Low Power Mode 25 7 AVDD1x AVDD2x AVDD4 IOVDD ALL CHANNELS ENABLED SUPPLY CURRENT (mA) 6 15 10 5 AVDD1x AVDD2x AVDD4 IOVDD ALL CHANNELS ENABLED 5 4 3 2 0 -40 25 105 125 TEMPERATURE (C) Figure 70. Supply Current vs. Temperature, High Resolution Mode 0 -40 25 105 125 TEMPERATURE (C) Figure 73. Supply Current vs. Temperature, Low Power Mode Rev. E | Page 28 of 97 12538-273 1 12538-270 SUPPLY CURRENT (mA) 2.4 SUPPLY VOLTAGE (V) Figure 69. Supply Current vs. Supply Voltage, High Resolution Mode 20 2.2 12538-272 2 Data Sheet 300 REF1- REF1+ REF2- REF2+ 200 REFERENCE INPUT CURRENT (nA) 200 0 -200 -400 100 0 -100 -200 -300 -400 -500 -800 -600 12538-274 TEMPERATURE (C) Figure 74. Reference Input Current vs. Temperature, High Resolution Mode TEMPERATURE (C) Figure 77. Reference Input Current vs. Temperature, Low Power Mode 60 80 SHUTDOWN SUPPLY CURRENT (A) 70 60 50 40 30 20 AVDD1x AVDD2x AVDD4 IOVDD 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 40 30 20 10 0 -40 POWER CONSUMPTION (mW) 12 25 20 15 10 60 80 100 120 ONLY ONE CHANNEL ENABLED AVDD1x AVDD2x AVDD4 IOVDD 10 8 6 4 2 5 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 12538-276 POWER CONSUMPTION (mW) 40 14 ONLY ONE CHANNEL ENABLED AVDD1x AVDD2x AVDD4 IOVDD 0 1.8 20 Figure 78. Shutdown Supply Current vs. Temperature 40 30 0 TEMPERATURE (C) Figure 75. Shutdown Supply Current vs. Supply Voltage 35 -20 Figure 76. Power Consumption per Channel vs. Supply Voltage, High Resolution Mode 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) Figure 79. Power Consumption per Channel vs. Supply Voltage, Low Power Mode Rev. E | Page 29 of 97 12538-279 10 AVDD1x AVDD2x AVDD4 IOVDD 50 12538-275 SHUTDOWN SUPPLY CURRENT (A) REF1- REF1+ REF2- REF2+ -35.263 -29.594 -22.185 -15.223 -7.366 -0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 -600 12538-277 400 12538-278 600 -35.263 -29.594 -22.185 -15.223 -7.366 -0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 REFERENCE INPUT CURRENT (nA) 800 AD7770 AD7770 Data Sheet 90 80 70 300 Figure 80. Power Dissipation vs. Temperature, High Resolution Mode 25 15 10 5 125.9 12538-281 114.5 104.1 77.9 48.1 27.9 6.6 -15.2 -20.2 -28.8 -35.9 -37.1 0 TEMPERATURE (C) 1475.0 12538-300 1372.2 1268.4 1165.5 950.6 1061.8 847.6 744.8 ELAPSED TIME (Hours) Figure 82. Internal Reference Long Term Drift from 0 Hours to 1500 Hours AVDD1x AVDD2x AVDD4 IOVDD 20 639.9 0 125.9 12538-280 114.5 104.1 77.9 48.1 27.9 6.6 -15.2 -100 -20.2 0 -28.8 -50 -35.9 0 10 535.6 50 20 TEMPERATURE (C) POWER DISSIPATION (mW) 100 432.3 30 150 327.6 40 200 224.1 50 120.3 60 44.5 VOLTAGE DRIFT (ppm) 250 -37.1 POWER DISSIPATION (mW) 350 AVDD1x AVDD2x AVDD4 IOVDD Figure 81. Power Dissipation vs. Temperature, Low Power Mode Rev. E | Page 30 of 97 Data Sheet AD7770 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output of a 100 mV p-p differential input (AINx+ - AINx-), at a fixed frequency, f = 1 kHz, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of AINx+ and AINx- at frequency, fS. CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. DNL error is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) Error Integral nonlinearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale input signal to the rms noise measured for an input. The value for dynamic range is expressed in decibels. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale frequency sweep sine wave signal to all seven unselected input channels and determining how much that signal is attenuated in the selected channel. The value is given for worst case scenarios across all eight channels of the AD7770. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfA and nfB, where m, n = 0,1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fA + fB) and (fA - fb) and the third-order terms include (2fA + fB), (2fA - fb), (fA + 2fB), and (fA - 2fB). The AD7770 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. Gain Error The first transition (from 100 ... 000 to 100 ... 001) occurs at a level 1/2 LSB above nominal negative full scale (-2.49999 V for the 2.5 V range). The last transition (from 011 ... 110 to 011 ... 111) occurs for an analog voltage 11/2 LSB below the nominal full scale (2.49999 V for the 2.5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Drift Gain error drift is the ratio of the gain error change due to a temperature change of 1C and the full-scale range (2N). It is expressed in parts per million. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is LSB (V) = 2VREF 2N The LSB referred to the input is LSB (VIN) = 2 VREF PGAGAIN 2N Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in the power supply voltage from the nominal value. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Rev. E | Page 31 of 97 AD7770 Data Sheet Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1C and the full-scale code range (2N). It is expressed in V/C. Rev. E | Page 32 of 97 Data Sheet AD7770 THEORY OF OPERATION The AD7770 is an 8-channel, simultaneously sampling, low noise, 24-bit - ADC with integrated digital filtering per channel and SRC. Due to the high oversampling rate, this technique spreads the quantization noise from 0 Hz to fCLKIN/2 (in the case of the AD7770, fCLKIN relates to the external clock); therefore, the noise energy contained in the band of interest is reduced (see Figure 83). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see Figure 84). The digital filter that follows the modulator removes the large out of band quantization noise (see Figure 85). For more information on basic and advanced concepts of - ADCs, see the MT-022 Tutorial and MT-023 Tutorial. Digital filtering has certain advantages over analog filtering. Because digital filtering occurs after the analog-to-digital conversion process, it can remove noise injected during the conversion. Analog filtering cannot remove noise injected during conversion. fCLKIN/2 Figure 83. - ADC Operation, Reduction of Noise Energy Contained in the Band of Interest (Linear Scale X-Axis) NOISE SHAPING BAND OF INTEREST fCLKIN/2 Figure 84. - ADC Operation, Majority of Noise Energy Shifted Out of the Band of Interest (Linear Scale X-Axis) DIGITAL FILTER CUTOFF FREQUENCY BAND OF INTEREST fCLKIN/2 Figure 85. - ADC Operation, Removal of Noise Energy from the Band of Interest (Linear Scale X-Axis) The - ADC starts the conversions of the input signal after the supplies generated by the internal LDOs become stable. An external signal is not required to generate the conversions. ANALOG INPUTS The AD7770 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single-ended input signals, as shown in Figure 86 through Figure 89. Table 10 summarizes the maximum differential input signal and dynamic range for the different input modes. Table 10. Input Signal Modes Input Signal Mode True differential Pseudo differential Single-ended PGA Gain All gains All gains All gains 12538-101 The AD7770 employs a - conversion technique to convert the analog input signal into an equivalent digital word. The overview of the - technique is that the modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, fCLKIN. BAND OF INTEREST 12538-102 The AD7770 offers two operation modes: high resolution mode, which offers up to 32 kSPS, and low power mode, which offers up to 8 kSPS. 12538-100 QUANTIZATION NOISE Maximum Differential Signal (VREF/PGAGAIN) (VREF/PGAGAIN) VREF/PGAGAIN Rev. E | Page 33 of 97 Maximum Peak-to-Peak Signal 2 x VREF/PGAGAIN 2 x VREF/PGAGAIN VREF/PGAGAIN AD7770 Data Sheet BIPOLAR OR UNIPOLAR TRUE DIFFERENTIAL AVDD1x - 0.1V AVSSx + 0.1V Figure 86. - ADC Input Signal Configuration, True Differential -0.4125 -0.8250 VREF = 2.5V AVDD1x = 1.65V AVSSx = -1.65V -1.6500 1 2 4 PGA GAIN -1.2375 8 The AD7770 provides a common-mode voltage pin (AVDD1x + AVSSx)/2), VCM, for the single-supply, pseudo differential, or true differential input configurations. AVDD1x - 0.1V VREF/PGAGAIN TRANSFER FUNCTION AINx+ AINx- The AD7770 can operate with up to a 3.6 V reference, typical at 2.5 V, and converts the differential voltage between the analog inputs (AINx+ and AINx-) into a digital output. The ADC converts the voltage difference between the analog input pins (AINx+ - AINx-) into a digital code on the output. The 24-bit conversion result is in MSB first, twos complement format, as shown in Table 11 and Figure 91. 12538-104 PSEUDO DIFFERENTIAL 0.4125 (AVDD1x + AVSSx)/2 Figure 90. Maximum Common-Mode Voltage Range for a Maximum Differential Input Signal BIPOLAR OR UNIPOLAR VCM TRUE DIFFERENTIAL PSEUDO DIFFERENTIAL 0.8250 12538-103 AINx+ VCM AINx- VREF /PGAGAIN 1.2375 12538-107 COMMON-MODE VOLTAGE (V) 1.6500 AVSSx + 0.1V Figure 87. - ADC Input Signal Configuration, Pseudo Differential BIPOLAR SINGLE-ENDED Table 11. Output Codes and Ideal Input Voltages for PGA = 1x VREF /PGAGAIN AINx+ AINx- 12538-105 AVSSx + 0.1V Figure 88. - ADC Input Signal Configuration, Single-Ended Bipolar Condition FS - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FS + 1 LSB -FS Analog Input ((AINx+) - (AINx-)), VREF = 2.5 V +2.499999702 V +298 nV 0V -298 nV -2.499999702 V -2.5 V Digital Output Code, Twos Complement (Hex) 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 + 0.1V Figure 89. - ADC Input Signal Configuration, Single-Ended Unipolar The common-mode input signal is not limited, but keep the absolute input signal voltage on any AINx pin between AVSSx + 100 mV and AVDD1x - 100 mV; otherwise, the input signal linearity degrades and, if the signal voltage exceeds the absolute maximum signal rating, damages the device. Figure 90 shows the maximum and minimum voltage commonmode range at different PGA gains for a maximum differential input voltage. Rev. E | Page 34 of 97 011 ... 111 011 ... 110 011 ... 101 100 ... 010 100 ... 001 100 ... 000 -FSR -FSR + 1LSB -FSR + 0.5LSB +FSR - 1LSB +FSR - 1.5LSB ANALOG INPUT Figure 91. Transfer Function 12538-108 AINx+ AINx- ADC CODE (TWOS COMPLEMENT) VREF /PGAGAIN 12538-106 SINGLE-ENDED UNIPOLAR Data Sheet AD7770 MCLK START SYNC_OUT SYNC_IN RESET PGA GAIN 1, 2, 4, 8 AINx+ - MODULATOR AINx- DIGITAL FILTER SINC3 SRC ESD PROTECTION GAIN SCALING AND OFFSET CORRECTION DRDY CONVERSION DATA INTERFACE DOUTx SCLK SIGNAL CHAIN FOR CHANNEL x CONTROL BLOCK FORMAT0 AND FORMAT1 CONTROL OPTION PIN OR SPI MODE0 TO MODE3 SPI CONTROL 12538-109 PIN CONTROL CS SCLK SDO SDI Figure 92. Top Level Core Signal Chain CORE SIGNAL CHAIN Each - ADC channel on the AD7770 has an identical signal path from the analog input pins to the digital output pins. Figure 92 shows a top level implementation of this signal chain. Prior to each - ADC, a PGA maps sensor outputs into the ADC inputs, providing low input current in dc (8 nA in high resolution mode) single-ended input current, and 4 nA differential input current in high resolution mode), an 8 pF input capacitance in ac, and configurable gains of 1, 2, 4, and 8. See the AN-1392 Application Note for more information. Each ADC channel has its own - modulator, which oversamples the analog input and passes the digital representation to the digital filter block. The data is filtered, scaled for gain and offset, and is then output on the data interface. To minimize power consumption, the channels can be individually disabled. for the maximum common-mode voltage at maximum differential input signals. INTERNAL REFERENCE AND REFERENCE BUFFERS The AD7770 integrates a 2.5 V, 10 ppm/C typical, voltage reference that is disabled at power-up. The buffered reference is available at Pin 49 and offers up to 10 mA of continuous current. A 100 nF capacitor is required if the reference is enabled. In applications where a low noise reference is required, it is recommended to add a low-pass filter (LPF) with a cutoff frequency (fCUTOFF) below 10 Hz to the REF_OUT pin. Connect the output of this filter to REFx+, and connect AVSSx to REFx-. In this scenario, configure the - reference to be external by configuring the reference buffers in enable or precharge mode. An example of performance with and without the output filter is shown in Figure 93. 115 CAPACITIVE PGA VREF = INTERNAL REFERENCE fCUTOFF < 10Hz 105 SNR (dB) The AD7770 uses chopping of the PGA to minimize offset and offset drift in the input amplifier, reducing the 1/f noise as well. For the AD7770, the chopping frequency is set to 128 kHz for high resolution mode, and 32 kHz for low power mode (see the AN-1392 Application Note for more information). The chopping tone is rejected by the sinc3 filter. To minimize intermodulation effects that may cause image in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency. The capacitive PGA common-mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within AVSSx + 100 mV to AVDD1x - 100 mV. See Figure 90 95 85 75 0.05 0.50 1.00 2.00 DIFFERENTIAL INPUT VOLTAGE (V) 2.50 12538-110 Each - ADC has a dedicated PGA, offering gain ranges of 1, 2, 4, and 8. This PGA reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the AD7770. The PGA maximize the signal chain dynamic range for small sensor output signals. Figure 93. SNR Adding External LPF with VREF = Internal Reference and fCUTOFF < 10 Hz The AD7770 can be used with an external reference connected between the REFx+ and REFx- pins. Recommended reference voltage sources for the AD7770 include the ADR441 and ADR4525 family of low noise, high accuracy voltage references. Rev. E | Page 35 of 97 AD7770 Data Sheet DCLK DIVIDER 1, 2, 4, 8, 16, 32, 64, 128 MCLK MCLK DIVIDER HIGH RESOLUTION MODE: MCLK/4 LOW POWER MODE: MCLK/8 MOD_MCLK DCLKx PGA ADC MODULATOR DATA INTERFACE CONTROL SINC FILTER AINx- DRDY DOUT3 TO DOUT0 DEC RATES = FROM x64 TO x4095.99 12538-111 AINx+ Figure 94. Clock Generation on the AD7770 The reference buffers can be operated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer pre-Q mode. In buffer enabled mode, the buffer is fully enabled, minimizing the current requirements from the external references. Note that the buffer output voltage headroom is 100 mV from the rails. In buffer bypassed mode, the external reference is directly connected to the ADC reference capacitors; the reference must provide enough current to correctly charge the internal ADC reference capacitors. In this mode of operation, a slight degradation in crosstalk is expected because the ADC channels are not isolated from each other. Buffer pre-charged (pre-Q) mode is the default operation mode. It is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to precharge the internal ADC reference capacitors. During the final phase of the acquisition, the reference is connected directly to the ADC capacitors. This mode has some benefits compared to the buffer enabled and buffer bypassed modes. In buffer pre-Q mode, the reference current requirements are minimized compared to buffer bypassed mode and the noise contribution from the internal reference buffers is removed (compared to buffer enabled mode). In buffer pre-Q mode, the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the ADC reference capacitors. INTEGRATED LDOs The AD7770 has three internal LDOs to regulate the internal supplies: two LDOs for the analog block and one LDO for the digital core. The internal LDOs requires an external 1 F decoupling capacitor on the DREGCAP, AREG1CAP, and the AREG2CAP pins. The LDO slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsing the RESET pin at power-up is required to guarantee that the digital block initializes correctly. CLOCKING AND SAMPLING The AD7770 includes eight - ADC cores. Each ADC receives the same master clock signal. The AD7770 requires a maximum external MCLK frequency of 8192 kHz for high resolution mode and 4096 kHz for low power mode. The MCLK is internally divided by 4 in high performance mode and by 8 in low power mode to produce the modulator MCLK (MOD_MCLK) signal used as the modulator sampling clock for the ADCs. The MCLK can be decreased to accommodate lower ODRs if the minimum ODR selected by the sinc3 filter is not low enough. If the external clock is lower than 256 kHz, set the CLK_QUAL_DIS bit (in SPI control mode only). The AD7770 integrates an internal oscillator clock that initializes the internal registers at power-up. The CLK_SEL pin defines the external clock used after initialization (see Table 12). Table 12. Clock Sources CLK_SEL State 0 Clock Source CMOS 1 Crystal Connection Input to XTAL2/MCLK, IOVDD logic level. XTAL1 must be tied to DGND. Connected between XTAL1 and XTAL2/MCLK. The MCLK signal generates the DCLK output signal, which in turn clocks the - conversion data from the AD7770, as shown in Figure 94. DIGITAL RESET AND SYNCHRONIZATION PINS An external pulse in the SYNC_IN pin generates the internal reset of the digital block; this pulse does not affect the data programmed in the internal registers. A pulse in this pin is required in two cases as follows: After updating one or more registers directly related to the sinc3 filter. These are power mode, offset, gain, and phase compensation. To synchronize multiple devices. The pulse in the SYNC_IN pin must be synchronous with MCLK. Rev. E | Page 36 of 97 Data Sheet AD7770 There are two different ways to achieve a synchronous pulse if the controller/processor cannot generate it, as follows: The SYNC_IN and SYNC_OUT pins must be externally connected if internal synchronization is used. The digital filter implements three main notches, one at the maximum ODR (32 kHz or 8 kHz, depending on the power mode) and another two at the ODR frequency selected to stop noise aliasing into the pass band. Figure 96 shows the typical filter transfer function for the high resolution and low power modes using a decimation rate of 128. 0 -20 -30 If the START pin is not used, tie it to IOVDD. ASYNCHRONOUS PULSE -40 -50 -60 -70 AD7770 START MCLK LOW POWER MODE DECIMATION = 128 HIGH RESOLUTION MODE DECIMATION = 128 -10 GAIN (dB) If multiple AD7770 devices must be synchronized, the SYNC_OUT pin of one device can be connected to multiple devices. This synchronization method requires the use of a common MCLK signal for all the AD7770 devices connected, as shown in Figure 95. The AD7770 offers a low latency sinc3 filter. Most precision - ADCs use sinc3 filters because the sinc3 filter offers a low latency path for applications requiring low bandwidth signals, for example, in control loops or where application specific postprocessing is required. The digital filter adds notches at multiples of the sampling frequency. -80 SYNCHRONIZATION SYNC_OUT LOGIC -90 -100 DIGITAL FILTER 0 10 20 30 40 50 60 FREQUENCY (kHz) SYNC_IN 12538-113 Applying an asynchronous pulse on the START pin, which is then internally synchronized with the external MCLK clock, and the resulting synchronous signal is output on the SYNC_OUT pin. Triggering the SYNC_OUT internally. When the AD7770 is configured in SPI control mode, toggling Bit 0 in the GENERAL_USER_CONFIG_2 register generates a synchronous pulse that is output on the SYNC_OUT pin. Figure 96. Sinc3 Frequency Response The sample rate converter featured allows fine tuning of the decimation rate, even for noninteger multiples of the decimation rate. See the Sample Rate Converter (SRC section for more information on filter profiles for noninteger decimation rates. IOVDD AD7770 MCLK MCLK START SYNCHRONIZATION SYNC_OUT LOGIC NC SHUTDOWN MODE DIGITAL FILTER The AD7770 can be placed in shutdown mode by pulling AVDD2 to ground and connecting 1 M resistance, pulled low, to XTAL2. In this mode, the average current consumption is reduced below 1 mA, as shown in Figure 97. SYNC_IN IOVDD AD7770 1.0 IAVDD1x IAVDD2x IAVDD4x IIOVDD START SYNCHRONIZATION SYNC_OUT LOGIC NC SYNC_IN NOTES 1. NC = NO CONNECT. Figure 95. Multiple AD7770 Devices Synchronization 12538-112 DIGITAL FILTER SUPPLY CURRENT (mA) MCLK AVDDx = 3.3V IOVDD = 3.3V 0.5 0 -0.5 -40 10 60 TEMPERATURE (C) Figure 97. Shutdown Current Rev. E | Page 37 of 97 125 12538-114 DIGITAL FILTERING AD7770 Data Sheet CONTROLLING THE AD7770 The AD7770 can be controlled using either pin control mode or SPI control mode. Pin control mode allows the AD7770 to be hardwired to predefined settings that offer a subset of the overall functionality of the AD7770. In this mode, the SRC and diagnostic features or extended errors source are not available. Controlling the AD7770 over the SPI allows the user access to the full monitoring, diagnostic, and - control functionality. SPI control offers additional functionality such as offset, gain, and phase correction per channel, in addition to access to the flexible SRC to achieve a coherent sampling. See Table 13 for more details about these different configurations. PIN CONTROL MODE In pin control mode, the AD7770 is configured at power-up based on the level of the mode pins, MODE0, MODE1, MODE2, and MODE3. These four pins set the following functions on the AD7770: the mode of operation, the decimation rate/ODR, the PGA gain, and the reference source, as shown in Table 14. Due to the limited number of mode pins and the number of options available, the PGA gain control is grouped into blocks of 4, and the ODR is selected for the maximum value defined by the decimation rate; ODR (kHz) = 2048/decimation for high resolution mode, and ODR (kHz) = 512/decimation for low power mode. Depending on the mode selected, the device is configured to use an external or an internal reference. The conversion data can be read back using the SPI or the data output interface, as shown in Table 13. If the data output interface is used to read back the data from the conversions, the number of DOUTx lines enabled and the number of clocks required for the - data transfer are determined by the logic level of the CONVST_SAR, FORMAT0, and FORMAT1 pins. In this case, the DCLK2, DCLK1, and DCLK0 pins select the - output interface and control the DCLKx divide function, which is a submultiple of MCLK, as shown in Table 15. The DCLKx divide function sets the frequency of the data output interface DCLKx signal. The DCLK minimum frequency depends on the decimation rate and operation mode. See the Data Output Interface section for more details about the minimum DCLKx frequency. All the pins that define the AD7770 configuration mode are reevaluated each time the SYNC_IN pin is pulsed. The typical connection diagram for pin control mode is shown in Figure 98. Table 13. Format of the Data Interface CONVST_SAR State 1 0 FORMAT1 0 0 1 1 0 FORMAT0 0 1 0 1 0 Control Mode Pin Pin Pin SPI Pin 0 1 Pin 1 1 0 1 Pin SPI Data Output Mode SPI output SPI output SPI output Defined in Register 0x013 and Register 0x014 DOUT0, Channel 0 and Channel 1 DOUT1, Channel 2 and Channel 3 DOUT2, Channel 4 and Channel 5 DOUT3, Channel 6 to Channel 7 DOUT0, Channel 0 to Channel 3 DOUT1, Channel 4 to Channel 7 DOUT0, Channel 0 to Channel 7 Defined in Register 0x013 and Register 0x014 Table 14. Pin Mode Options Pin State MODE3 0 0 0 0 0 0 0 0 1 MODE2 0 0 0 0 1 1 1 1 0 MODE1 0 0 1 1 0 0 1 1 0 MODE0 0 1 0 1 0 1 0 1 0 Decimation Rate 1024 512 256 128 64 512 256 128 64 Power Mode High resolution High resolution High resolution High resolution High resolution High resolution High resolution High resolution High resolution Rev. E | Page 38 of 97 PGA Gain Channel Channel 0 to Channel 4 to Channel 3 Channel 7 1 1 1 1 1 1 1 1 1 1 1 4 1 4 1 4 1 4 Reference Source External External External External External External External External External Data Sheet AD7770 Pin State MODE3 1 1 1 1 1 1 1 MODE2 0 0 0 1 1 1 1 MODE1 0 1 1 0 0 1 1 Decimation Rate 512 256 128 512 256 128 64 MODE0 1 0 1 0 1 0 1 Power Mode High resolution High resolution High resolution Low power Low power Low power Low power PGA Gain Channel Channel 0 to Channel 4 to Channel 3 Channel 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reference Source Internal Internal Internal External External External External Table 15. DCLKx Selection for Pin Control Mode State DCLK2/SCLK 0 0 0 0 1 1 1 1 DCLK1/SDI 0 0 1 1 0 0 1 1 DCLK0/SDO 0 1 0 1 0 1 0 1 MCLK Divider 1 2 4 8 16 32 64 128 EXTERNAL REFERENCE AVDD 3.3V AVDD 3.3V AVSSx AVDD1x VCM REFx+ VCM AVDD 3.3V AVSSx AVSSx AVSSx REFx- AVDD4 REF_OUT AVDD2x AREGxCAP BUFFER AVSSx IOVDD 1.8V TO 3.6V AVSSx IOVDD AD7770 BUFFER DREGCAP SYNC_IN SYNC_OUT START RESET DRDY AIN0+ PGA AIN7+ 24-BIT - ADC PGA AIN7- DCLK DOUT0 DOUT1 DOUT2 DOUT3 ADC DATA SERIAL INTERFACE AIN0- SINC3/SRC CS SCLK SDO SPI CONTROL INTERFACE SDI SPI/SPORT SLAVE INTERFACE FPGA OR DSP SPI MASTER INTERFACE CLK_SEL XTAL1 XTAL2 MODE3 TO MODE0 CONVST_SAR DCLK2 TO DCLK0 FORMAT1 AND FORMAT0 12538-115 AVSSx CLOCK SOURCE Figure 98. Pin Mode Connection Diagram with External Reference Rev. E | Page 39 of 97 AD7770 Data Sheet AVDD 3.3V AVDD3.3V AVSSx AVSSx AVDD1x VCM REFx+ VCM REFx- AVSSx REF_OUT BUFFER AVDD4 IOVDD 2V TO 3.6V AVSSx AVSSx AVDD2x AREGxCAP AD7770 BUFFER IOVDD DREGCAP SYNC_IN SYNC_OUT START RESET DRDY AIN0+ PGA ADC DATA SERIAL INTERFACE AIN0- 24-BIT - ADC PGA AIN7- SINC3/SRC SPI CONTROL INTERFACE DIAGNOSTIC INPUTS CS SCLK SDO SDI FULL BUFFER AUXAIN+ 12-BIT SAR ADC MUX AUXAIN- AVSSx GPIO2 TO GPIO0 CLK_SEL XTAL1 SPI/SPORT SLAVE INTERFACE FPGA OR DSP SPI MASTER INTERFACE CONVST_SAR XTAL2 FORMAT1 IOVDD FORMAT0 IOVDD CLOCK SOURCE 12538-116 AIN7+ DCLK DOUT0 DOUT1 DOUT2 DOUT3 Figure 99. SPI Control Mode Connection Diagram with Internal Reference SPI CONTROL The second option for control and monitoring the AD7770 is via the SPI. This option allows access to the full functionality on the AD7770, including access to the SAR converter, phase synchronization, offset and gain adjustment, diagnostics and the SRC. To use the SPI control, set the FORMAT0 and FORMAT1 pins to logic high. In this mode, the SPI can also read the - conversation data by setting the SPI_SLAVE_MODE_EN bit. The typical connection diagram for SPI control mode is shown in Figure 99. Functionality Available in SPI Mode SPI control of the AD7770 offers the super set of the functions and diagnostics. The SPI Control Functionality section describes the functionality and diagnostics offered when in SPI control mode. Offset and Gain Correction Offset and gain registers are available for system calibration. The gain register is preprogrammed during final production for a PGA gain of 1, but can be overwritten with a new value if required. The gain register is 24 bits long and is split across three registers, CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and CHx_GAIN_LOWER_BYTE, which set the gain on a per channel basis. The gain value is relative to 0x555555, which represents a gain of 1. The offset register is 24 bits long and is spread across three byte registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_ BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is 0x000000 at power-up. Program the offset as a twos complement, signed 24-bit number. If the channel gain is set to its nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by -4/3 LSBs. As an example of calibration, the offset measured is -200 LSB (with both AINx pins connected to the same potential). An offset adjustment of -150 LSB changes the digital output by -150 x (-4/3) = 200 LSBs (gain value = 0x555555), representing this number as two complement, 0xFFFFFF - 0x96 + 1 = 0xFFFF70. Program the offset register as follows: CHx_OFFSET_UPPER_BYTE = 0xFF CHx_OFFSET_MID_BYTE = 0xFF CHx_OFFSET_LOWER_BYTE = 0x70 Note that the offset compensation is performed before the gain compensation. The gain is programmed during final testing for PGAGAIN = 1. The gain register values can be overwritten; however, after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting. If the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is 0x555555 x 0.75 = 0x400000 Then, an LSB of the offset register adjustment changes the digital output by -4/3 x 0.75 = 1 LSB. Program the gain register as follows: Rev. E | Page 40 of 97 CHx_GAIN_UPPER_BYTE = 0x40 CHx_GAIN_MID_BYTE = 0x00 CHx_GAIN_LOWER_BYTE = 0x00 Data Sheet AD7770 SPI Control Functionality Global Control Functions Table 16. Phase Adjustment vs. Decimation Rate The following list details the global control functions of the AD7770: High resolution and low power modes of operation ODR: SRC VCM buffer power-down Internal/external reference selection Enable, precharged, or bypassed reference buffer modes Internal reference power-down SAR diagnostic mux SAR power-down GPIO write/read SPI SAR conversion readback SPI slave mode--read - results SDO and DOUTx drive strength DOUTx mode DCLK division Internal LDO bypassed CRC protection: enabled or disabled Per Channel Functions The following list details the per channel functions of the AD7770: Phase Adjustment Compensation (n) x1 x2 x4 x8 x16 Decimation Rate 255 511 1023 2047 4095 The maximum phase delay cannot be equal to or greater than the decimation rate. If this is the case, the value changes internally to the decimation rate value minus 1. When the CHx_SYNC_OFFSET register is written it automatically overwrites itself multiplied by the corresponding factor (n), as defined in Table 16. As CHx_SYNC_OFFSET is only 8 bits long, the resulting value is scaled down to fit 8 bits. To know whether the phase adjustment has clipped or not, see Table 17. Table 17. CHx_SYNC_OFFSET x n 255 511 1023 2047 4095 CHx_SYNC_OFFSET Overwrite CHx_SYNC_OFFSET x n CHx_SYNC_OFFSET x n/2 CHx_SYNC_OFFSET x n/4 CHx_SYNC_OFFSET x n/8 CHx_SYNC_OFFSET x n/16 As an example, the phase mismatch between Channel 0 and Channel 1 is 5, and the ODR is 5 kSPS in high resolution mode. In this case, the decimation rate is 2048 kHz/5 kHz = 409.6, which means that the offset register value is multiplied internally by 2. PGA gain - channel power-down Phase delay: synchronization phase offset per channel Calibration of offset Calibration of gain - input signal mux Channel error register PGA gain Assuming an input signal of 50 Hz, the number of MOD_ MCLK pulses required to sample a full period is 2048 kHz/ 50 Hz = 40960 > 360/40960 = 0.00878. Phase Adjustment The AD7770 phase delay can be adjusted to compensate for phase mismatches between channels due to sensors or signal channel phase errors connected to the AD7770. Achieve phase adjustment by programming the CHx_SYNC_OFFSET register. This programming delays the synchronization signal by a certain number of modulator clocks (MOD_CLK) to individually initiate the digital filter for each - ADC. In other words, program the channel with a higher phase with Phase 0, whereas for the channel with lower phase, delay to compensate the phase mismatch. The phase adjustment register is read after a pulse on the SYNC_IN pin; consequently, any further changes on the register have no effect unless a pulse is generated (see the Digital Reset and Synchronization Pins section for more information on how to generate a pulse in the pin). The phase offset register is multiplied internally by a factor (n) that depends on the decimation rate, as shown in Table 16. If a 5 delay is required, the number of MOD_MCLK delays must be 569 (5/0.00878) because the offset register is multiplied by 2; the final offset register value is 409.6/2 - 569/2, which gives a negative value. In this case, if the offset value programmed to the register is higher than 204 (for example, 210 x 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 x 0.00878 = 3.58. PGA Gain The PGA gain can be selected individually by appropriately selecting Bits[7:6] in the CHx_CONFIG register, as shown in Table 18. Table 18. PGA Gain Settings via CHx_CONFIG CHx_CONFIG, Bits[7:6] Setting 00 01 10 11 PGA Gain Setting 1 2 4 8 If the - reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference Rev. E | Page 41 of 97 AD7770 Data Sheet Decimation - Reference Configuration The decimation defines the sampling frequency as follows: The AD7770 can operate with internal or external references. In addition, for diagnostic purposes, the analog supply can be used as a reference, as shown in Table 19. REFx-/REFx+ allows the selection of a voltage reference where the REFx+ is lower voltage than REFx- pin. In high resolution mode, the sampling frequency = MCLK/(4 x decimation) In low power mode, the sampling frequency = MCLK/ (8 x decimation) Table 19. - References Refer to the Sample Rate Converter (SRC section for more information. GPIOx Pins If the AD7770 operates in SPI control mode, the mode pins operate as GPIOx pins, as shown in Figure 100. The GPIOx pins can be configured as inputs or outputs in any order. GPIO0 Setting for ADC_MUX_CONFIG, Bits[7:6] 00 01 10 11 Channel 0 to Channel 3 REF1+/REF1- Internal reference AVDD1A/AVSS1A REF1-/REF1+ Channel 4 to Channel 7 REF2+/REF2- Internal reference AVDD1B/AVSS1B REF2-/REF2+ Reference buffer operation is described in Table 20. The selected reference and buffer operation mode affect all channels. GPIO1 REGISTER MAP If the - reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference. 12538-117 GPIO2 Power Modes Figure 100. GPIOx Pin Functionality Configuration control and readback of the GPIOx pins are set via Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output) and the GPIO_DATA register. Among other uses, the GPIOs can control an external mux connected to the auxiliary inputs of the SAR ADC. Use this mux to verify the results on the - ADCs. In addition, the GPIOx pins can be used to externally trigger a new decimation rate. Refer to the Sample Rate Converter (SRC section for more information about this functionality. The AD7770 offers different power modes to improve the power efficiency, high resolution and low power mode, which can be controlled via GENERAL_USER_CONFIG_1, Bit 6. To further reduce the power, additional blocks can be disabled independently, as described in Table 21. If the power mode changes, a pulse on the SYNC_IN pin is required. Table 20. Reference Buffer Operation Modes Reference Buffer Operation Mode Enabled Precharged Disabled REFx+ BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0 BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1 BUFFER_CONFIG_1, Bit 4 = 0 REFx- BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0 BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1 BUFFER_CONFIG_1, Bit 3 = 0 Table 21. Additional Disable Power-Down Blocks Block VCM Reference Buffer Internal Reference Buffer - Channel SAR Internal Oscillator Register GENERAL_USER_CONFIG_1, Bit 5 BUFFER_CONFIG_1, Bits[4:3] GENERAL_USER_CONFIG_1, Bit 4 CH_DISABLE, Bits[7:0] GENERAL_USER_CONFIG_1, Bit 3 GENERAL_USER_CONFIG_1, Bit 2 Rev. E | Page 42 of 97 Notes Enable by default Precharged mode by default Disable by default All channels enable Disable by default Enable by default Data Sheet AD7770 LDO Bypassing The internal LDOs can be individually bypassed and an external supply can be applied directly to the AREG1CAP, AREG2CAP, or DREGCAP pin. Table 22 shows the absolute minimum and maximum supplies for these pins, as well as the associated register used to bypass the regulator. Table 22. LDO Bypassing LDO AREG1CAP AREG2CAP DREGCAP 1 BUFFER_CONFIG_2, Bits[2:0]1 1XX X1X XX1 Max (V) 1.9 1.9 1.98 Supply Min (V) 1.85 1.85 1.65 Table 24. SDO Strength GENERAL_USER_CONFIG_2, Bits[4:3] Setting 00 01 10 11 Mode Nominal Strong Weak Extra strong SCLK is the serial clock input for the device. All data transfers (on either SDO or SDI) occur with respect to this SCLK signal. X means don't care. DIGITAL SPI The SPI serial interface on the AD7770 consists of four signals: CS, SDI, SCLK, and SDO. A typical connection diagram of the SPI is shown in Figure 101. DSP/FPGA AD7770 In SPI control mode, there are four different levels of I/O strength on the SDO pin that can be selected in GENERAL_USER_ CONFIG_2, Bits[4:3], as described in Table 24. CS SCLK SDI The SPI can operate in multiples of eight bits. For example, in SPI control mode, if the SDO pin is used to read back the data from the internal register or the SAR ADC, the data frame is 16 bits wide (CRC disabled), as shown in Figure 102, or 24 bits wide (CRC enabled), as shown in Figure 103. In this case, the controller can generate one frame of 16 bits or 24 bits (with and without the CRC enabled), or 2 or 3 frames of 8 bits (with and without the CRC enabled). When the SDO pin reads back the data from the - channels, 64 bits must be read back from the controller (in this case, the controller can generate a frame of 64 bits--either 2 x 32 bits, 4 x 16 bits, or 8 x 8 bits). SPI CRC--Checksum Protection (SPI Control Mode) 12538-118 SDO Figure 101. SPI Control Interface--AD7770 is the SPI Slave, Digital Signal Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master The SPI operates in Mode 0 and Mode 3: CPOL = 0, CPHA = 0 (Mode 0) or CPOL = 1, CPHA = 1 (Mode 3). In pin control mode, the SDO can read back the - results, depending on the level of the CONVST_SAR pin, as described in Table 13. In SPI control mode, the SPI transfers data into the on-chip registers while the SDO pin reads back data from the on-chip registers or reads the SAR or the - conversions results, depending on the selected operation mode. The AD7770 has a checksum mode that improves SPI robustness in SPI control mode. Using the checksum ensures that only valid data is written to a register and allows data read from the device to be validated. The SPI CRC can be enabled by setting the SPI_CRC_TEST_EN bit. If an error occurs during a register write, the SPI_CRC_ERR is set in the error register. Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum being performed on all the R/W operations. When SPI_ CRC_TEST_EN is enabled, an 8-bit CRC word is appended to every SPI transaction for SAR and register map operations. For more information on - readback operations, see the CRC Header section. To ensure that the register write is successful, it is recommended to read back the register and verify the checksum. The SDO data source in SPI control mode is defined by the GENERAL_USER_CONFIG_2 and GENERAL_USER_ CONFIG_3 registers, as described in Table 23. For CRC checksum calculations, the following polynomial is always used: x8 + x2 + x + 1. See the SPI Control Mode Checksum section for more information. Table 23. SPI Operation Mode in SPI Control Mode SPI Read/Write Register Mode (SPI Control Mode) GENERAL_USER_ CONFIG_2, Bit 5 Setting 0 0 1 The AD7770 has on-board registers to configure and control the device. 1 X means don't care. GENERAL_USER_ CONFIG_3, Bit 4 Setting1 0 1 X Mode Internal register - data conversion SAR conversion The registers have 7-bit addresses--the 7-bit register address on the SDI line selects the register for the read/write function. The 7-bit register address follows the R/W bit in the SDI data. The 8 bits on the SDI line following the 7-bit register address are the data to be written to the selected register if the SPI is a write transfer. Data on the SDI line is clocked into the AD7770 on the rising edge of SCLK, as shown in Figure 3. Rev. E | Page 43 of 97 AD7770 Data Sheet register address, the 8-bit data, and an 8-bit CRC (if enabled). To avoid unwanted writes to the internal register while the SAR conversions are read back through the SDO line, it is recommended to send a readback command, for example, 0x8000, to the device, which is ignored because the SDO pin shifts out the content of the SAR ADC. The data on the SDO line during the SPI transfer contains the 8-bit 0010 0000 header: 8 bits of register data in the case of a read (R) operation, or 8 zeros in the case of a write (W) operation. With the CRC disabled, the basic data frame on the SDI line during the transfer is 16 bits long, as shown in Figure 102. When the CRC is enabled, a minimum frame length of 24 SCLK periods are required on SPI transfers. The 24 bits of data on the SDO line consist of an 8-bit header (0010 0000), 8 bits of data, and an 8-bit CRC (see Figure 103). If consecutive conversions are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted. SPI SAR Diagnostic Mode (SPI Control Mode) - Data, ADC Mode Setting Bit 5 in the GENERAL_USER_CONFIG_2 register configures the SDO line to shift out data from the SAR ADC conversions, as described in Table 23. In pin control mode, the SPI can be used to read back the - conversions as described in Table 13. In SPI control mode, the SPI reads back the - conversions by setting GENERAL_USER_ CONFIG_3, Bit 4, as described in Table 23; in this mode, the AD7770 internal register can be written to, but any readback command is ignored because the SDO data frame is dedicated to shifting out the conversion results from the - ADCs. To avoid unwanted writes to the internal register, it is recommended to send a readback command, for example, 0x8000, to the device, which is ignored because the SDO pin shifts out the content of the - ADC. In SAR mode, the AD7770 internal registers can be written to, but any readback command is ignored because the SDO data frame is dedicated to shift out the conversion results from the SAR ADC. To exit this mode of operation, reset Bit 5 in the GENERAL_ USER_CONFIG_2 register. The data on the SDO line during the SPI transfer contains a 4-bit 0010 header and the 12-bit SAR conversion result if the CRC is disabled. The SDO pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 x 32 bits, 4 x 16 bits, or 8 x 8 bits. See the 24-bit example in Figure 105. When the CRC is enabled, a minimum frame length of 24 SCLK periods are required on SPI transfers. The 24 bits of data on the SDO line consist of a 4-bit header (0010), the 12-bit data, and an 8-bit CRC, as shown in Figure 104. SPI Software Reset Keeping the SDI pin high during 64 consecutives clocks generates a software reset. Per the SPI read/write register mode (see the SPI Read/Write Register Mode section), the SDI line contains the R/W bit, a 7-bit CS SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 12538-119 SCLK Figure 102. 16-Bit SPI Transfer--CRC Disabled CS SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 SDO 0 0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 Figure 103. 24-Bit SPI Transfer--CRC Enabled Rev. E | Page 44 of 97 12538-120 SCLK Data Sheet AD7770 CS SCLK R/W A6 A5 A4 SDO 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR I CRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 11 10 9 8 7 6 5 4 3 2 1 0 12538-121 SDI Figure 104. SAR ADC/Diagnostic Mode--CRC Enabled DRDY CS SCLK SDO 0x800000 0x800000 HEADER CH0 D23 TO D8CH0 D7 TO D0CH0 HEADER CH1 Figure 105. SPI Used to Read Back the - ADC Data, in 24-Bit Frames Rev. E | Page 45 of 97 D23 TO D16CH1 12538-301 SDI AD7770 Data Sheet RMS NOISE AND RESOLUTION Table 25 through Table 27 show the dynamic range (DR), rms noise referred to input (RTI), effective number of bits (ENOB), and effective resolution (ER) of the AD7770 for various output data rates and gain settings. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise. Effective Resolution = log2(Input Range/RMS Noise) ENOB = (DR - 1.78)/6 HIGH RESOLUTION MODE Table 25. DR and RTI for High Resolution Mode Decimation Rate 64 128 256 512 1024 2048 Output Data Rate (SPS) 32,000 16,000 8000 4000 2000 1000 f-3 dB (Hz) 8369 4818.8 2511 1269 636.3 318.5 Gain = 1 DR (dB) RTI (V rms) 103.20 12.10 109.43 6.00 112.97 4.00 116.00 2.80 119.00 1.98 123.00 1.38 Gain = 2 DR (dB) RTI (V rms) 101.96 6.97 108.30 3.39 112.38 2.13 115.86 1.45 119.19 1.01 121.98 0.72 Gain = 4 DR (dB) RTI (V rms) 99.20 4.71 105.07 2.38 110.23 1.39 113.68 0.92 116.75 0.65 119.79 0.46 Gain = 8 DR (dB) RTI (V rms) 95.30 3.82 100.71 1.94 105.98 1.13 109.81 0.7 113.12 0.51 115.88 0.35 Gain = 2 ENOB (Bits) ER (Bits) 16.94 18.45 17.99 19.49 18.67 20.16 19.24 20.72 19.8 21.24 20.26 21.73 Gain = 4 ENOB (Bits) ER (Bits) 16.48 18.02 17.45 19.00 18.31 19.78 18.88 20.38 19.39 20.89 19.9 21.39 Gain = 8 ENOB (Bits) ER (Bits) 15.83 17.32 16.73 18.30 17.6 19.08 18.24 16.39 18.79 20.23 19.25 20.76 Gain = 2 DR (dB) RTI (V rms) 101.63 7.19 108.38 3.51 112.01 2.24 115 1.51 118.72 1.05 Gain = 4 DR (dB) RTI (V rms) 99.35 4.84 104.7 2.47 109.4 1.49 112.95 0.99 116.43 0.67 Gain = 8 DR (dB) RTI (V rms) 93.96 4.15 100.25 2.12 105.18 1.18 109.14 0.77 112.47 0.54 Gain = 2 ENOB (Bits) ER (Bits) 16.88 18.41 18.00 19.44 18.60 20.09 19.10 20.66 19.72 21.18 Gain = 4 ENOB (Bits) ER (Bits) 16.5 17.98 17.39 18.95 18.17 19.68 18.76 20.27 19.34 20.84 Gain = 8 ENOB (Bits) ER (Bits) 15.61 17.2 16.65 18.17 17.47 19.01 18.13 19.62 18.68 20.15 Table 26. ENOB and ER for High Resolution Mode Decimation Rate 64 128 256 512 1024 2048 Output Data Rate (SPS) 32,000 16,000 8000 4000 2000 1000 f-3 dB (Hz) 8369 4818.8 2511 1269 636.3 318.5 Gain = 1 ENOB (Bits) ER (Bits) 17.14 18.66 18.18 19.67 18.76 20.25 19.27 20.77 19.77 21.27 20.43 21.79 LOW POWER MODE Table 27. DR and RTI for Low Power Mode Decimation Rate 64 128 256 512 1024 Output Data Rate (SPS) 8000 4000 2000 1000 500 f-3 dB (Hz) 2092.2 1204.8 627.75 317.25 159.25 Gain = 1 DR (dB) RTI (V rms) 102.8 12.5 108.94 6.45 112.7 4.23 115.83 2.94 118.97 2.04 Table 28. ENOB and ER for Low Power Mode Decimation Rate 64 128 256 512 1024 Output Data Rate (SPS) 8000 4000 2000 1000 500 f-3 dB (Hz) 2092.2 1204.8 627.75 317.25 159.25 Gain = 1 ENOB (Bits) ER (Bits) 17.07 18.61 18.09 19.56 18.72 20.17 19.24 20.70 19.76 21.22 Rev. E | Page 46 of 97 Data Sheet AD7770 DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR The AD7770 includes self diagnostic features to guarantee the correct operation. If an error is detected, the ALERT pin is pulled high to generate an external interruption to the controller. In addition, the header of the - output data contains an alert bit that informs the controller of a chip error (see the ADC Conversion Output--Header and Data section). the EXT_MCLK_SWITCH_ERR bit is set in the general error register, GEN_ERR_REG_2. If EXT_MCLK_SWITCH_ERR is set, the device is operating off the internal oscillator, and is waiting for an appropriate external clock. To use a slow external clock (<265 kHz), set the CLK_QUAL_ DIS bit. Setting this bit also clears the error bit. Both the ALERT pin and bit (status header) are automatically cleared if the error is no longer present. The errors related to the SPI do not recover automatically; read back the appropriate register to clear the error. The ALERT pin and bit reset in the next SPI access after the bit is read back. If the external clock is between 132 kHz and 265 kHz, depending on the internal synchronization between the internal oscillator and the external clock, the error may not trigger. However, it is still recommended to set the CLK_QUAL_DIS bit. If an error detector is manually disabled, it does not generate an internal error and, consequently, the register map or the ALERT pin and bit are not triggered. Reset Detection There are different sources of errors, as described in Table 29. In pin control code, it is not possible to check the error source, and some sources of error are not enabled. In SPI control mode, check the source of an error by reading the appropriate register bit. The STATUS_REG_x register bits identify the register that generates an error, as summarized in Table 29. Table 29. Register Error Source Bit Name ERR_LOC_GEN2 ERR_LOC_GEN1 ERR_LOC_CH7 ERR_LOC_CH6 ERR_LOC_CH5 ERR_LOC_CH4 ERR_LOC_CH3 ERR_LOC_CH2 ERR_LOC_CH1 ERR_LOC_CH0 ERR_LOC_SAT_CH6_7 ERR_LOC_SAT_CH4_5 ERR_LOC_SAT_CH2_3 ERR_LOC_SAT_CH0_1 Register Source GEN_ERR_REG_2 GEN_ERR_REG_1 CH7_ERR_REG CH6_ERR_REG CH5_ERR_REG CH4_ERR_REG CH3_ERR_REG CH2_ERR_REG CH1_ERR_REG CH0_ERR_REG CH6_7_SAT_ERR CH4_5_SAT_ERR CH2_3_SAT_ERR CH0_1_SAT_ERR If a slow clock is not in use and the error triggers, a reset is required. The AD7770 general error register contains a RESET_DETECTED bit. This bit is asserted if a reset pulse is applied to the AD7770 and is cleared by reading the general error register. This bit indicates that the power-on reset (POR) initialized correctly on the device. In addition, this bit can detect an unexpected device reset or glitch on the RESET pin. To reset this error signal in SPI control mode, toggle the SYNC_IN pin or read from the general error register, GEN_ERR_REG_2. To reset this error signal in pin control mode, toggle the SYNC_IN pin. Internal LDO Status The AD7770 has three internal LDOs to regulate the internal analog and digital supply rails. The LDOs have internal power supply monitors. Internal comparators monitor and flag errors with these supplies after they pass a predetermined limit. The ALDO1_PSM_ERR, ALDO2_PSM_ERR, and DLDO_PSM_ ERR bits indicate either an LDO malfunction, or, if the LDOs are bypassed, an incorrect external supply. The internal analog and digital voltage monitors can be disabled by appropriately selecting the LDO_PSM_TEST_EN bits. Use the SAR ADC to verify the error. In addition, the STATUS_REG_x registers have a bit that indicates if any internal error bit is set, ERROR. This bit clears if the error is no longer present and the register is read back. The INIT_COMPLETE bit in the STATUS_REG_3 indicates that the device is initialized correctly. This bit is not an error bit but an indicator. General Errors MCLK Switch Error (SPI Control Mode) After power-up, the AD7770 initiates a clocking handover sequence to pass clocking control to the external oscillator, or the CMOS clock. In SPI mode, if an error occurs in the handover, Additionally, the levels of the internal monitors can be manually triggered to check if the detector works correctly by appropriately setting the LDO_PSM_TRIP_TEST_EN bits. These bits increase the comparator window threshold above the LDO outputs, forcing the comparator to trigger. ROM and Memory Map CRC If an error is found at power-up during the ROM verification, or if the internal memory map is corrupted, the AD7770 generates an error and sets MEMMAP_CRC_ERR or ROM_ CRC_ERR, depending on the source of the error. The checker can be disabled by clearing the MEMMAP_ CRC_TEST_EN and ROM_CRC_TEST_EN bits. The device must be reset if any of these errors trigger. Rev. E | Page 47 of 97 AD7770 Data Sheet - ADC Errors Reference Detect (SPI Control Mode) Output Saturation In SPI control mode, the AD7770 includes on-chip circuitry to detect if there is a valid reference for conversions or calibrations. If the voltage between the selected REFx+ and REFx- pins goes below 0.7 V, the AD7770 detects that it no longer has a valid reference. CHx_ERR_REF_DET can be interrogated to identify the affected channel, which clears the bit register if the error is no longer present. The voltage detector can be disabled by clearing the REF_DET_TEST_EN bit. Use the - ADC diagnostic or the SAR ADC to verify the error. Overvoltage and Undervoltage Events The AD7770 includes on-chip overvoltage/undervoltage circuitry on each analog input pin. When the voltage on an analog input pin goes above AVDD1x + 40 mV, the CHx_ ERR_AINx_OV bit is set. The error disappears if the input voltage falls below AVDD1x - 40 mV. An output saturation event can occur when gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. The output does not wrap. Reading the CHx_ERR_OUTPUT_SAT bit clears the bit if the error corrects itself. The detection can be disabled by clearing OUTPUT_SAT_ TEST_EN bit. SPI Transmission Errors (SPI Control Mode) All SPI errors clear after reading GEN_ERR_REG_1, which contains the SPI errors. These errors are not recovered automatically and, consequently, the ALERT pin and bit remain set until the error register is read back, and a new SPI frame is generated. CRC Checksum Error If an undervoltage event occurs (AVSSx - 40 mV), the CHx_ ERR_AINx_UV bit is set. The error disappears if the input voltage increases to AVSSx + 40 mV. The CHx_ERR_AINM_UV, CHx_ERR_AINM_OV, CHx_ERR_ AINP_UV, and CHx_ERR_AINP_OV bits can be read back to verify the affected channel input, which clears the bits if the error is no longer present. The overvoltage and undervoltage detection can be disabled independently by clearing the AINM_ UV_TEST_EN, AINM_OV_TEST_EN, AINP_UV_TEST_EN, or AINP_OV_TEST_EN bits. The input voltage can be checked independently with the SAR ADC. Modulator Saturation The AD7770 includes modulator saturation detection on each of the - ADCs. If 20 consecutive codes for the modulator are either all 1s or 0s, this condition is flagged as a modulator saturation event. Reading the CHx_ERR_MOD_SAT register clears the bit if the error corrects itself. If the CRC checksum is enabled by setting the SPI_CRC_ TEST_EN bit, an error bit, SPI_CRC_ERR, is raised if the CRC message does not match the message computed by the AD7770 internal CRC block. If the CRC message does not match the internally computed message, the register is not updated. SCLK Counter If the number of clocks generated by the controller is not a multiple of 8 after CS is pulled high, an error bit, SPI_CLK_ COUNT_ERR is raised. The last command multiple of 8 is executed; however, the SCLK counter can be disabled by setting the SPI_CLK_COUNT_TEST_EN bit. Invalid Read When attempting to read back an invalid register address, the SPI_INVALID_READ_ERR bit is set. The invalid readback address detection can be disabled by setting the SPI_INVALID_READ_TEST_EN bit. Invalid Write When attempting to write to an invalid register address or a read only register, the SPI_INVALID_WRITE_ERR bit is set. Modulator saturation detection can be disabled by clearing the MOD_SAT_TEST_EN bit. The invalid write address detection can be disabled by setting the SPI_INVALID_WRITE_TEST_EN bit. Note that the modulator input voltage is attenuated internally, which means that a modulator output of all 1s or 0s represents a modulator that is out of bounds and that a RESET pulse is required. MONITORING USING THE AD7770 SAR ADC (SPI CONTROL MODE) Filter Saturation TheAD7770 includes digital filter saturation detection on each - ADC channel. This detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. Reading the CHx_ERR_ FILTER_SAT bit clears the bit if the error corrects itself. The detection can be disabled by clearing FILTER_SAT_TEST_ EN bit. The AD7770 contains an on-chip SAR ADC for chip diagnostics, system diagnostics, or measurement verification. The SAR ADC has a 12-bit resolution. The AVDD4 and AVSS4 pins operate in complete independence of the - ADC supplies and, therefore, can be used for chip diagnostics in systems where functional safety is important. The reference for the SAR conversion process is taken from the SAR ADC supply voltage (AVDD4/ AVSS4) and, therefore, the SAR analog input range is from AVSS4 to AVDD4. Rev. E | Page 48 of 97 Data Sheet AD7770 The SAR ADC has a maximum throughput rate of 256 kSPS. The CONVST_SAR pin initiates a conversion on the SAR ADC. The maximum allowable frequency of the CONVST_SAR pin is 256 kHz. If consecutive conversions are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted. The SAR ADC is only available in SPI control mode. To read conversion results from the SAR ADC, set the SAR_DIAG_ MODE_EN bit. After this bit is set, all data shifted out from the SDO pin originates from the SAR ADC conversion, as shown in Figure 106. The CONVST_SAR signal can be internally deglitched to avoid false triggers. Use the auxiliary inputs, AUXAIN+ and AUXAIN-, to validate the - measurements. While operating in SPI control mode, the AD7770 has three available GPIOx ports controlled via the SPI. The GPIOx pins can be used to control an external, dual 8:1 multiplexer, which, in turn, samples the eight - channels. Use this diagnostic in applications where functional safety is required. This diagnostic aids in removing the need for a secondary external ADC to validate primary measurements on the - channels. Temperature Sensor The internal die temperature can be measured with an accuracy of 2C. The differential voltage base emitter (DVBE) is proportional to the temperature measured referred to 25C. DVBE Table 30. SAR Synchronization and Deglitching CONVST_DEGLITCH_DIS (Register 0x013, Bits[7:6]) 11 10 Effect on CONVST_SAR CONVST_SAR goes directly to the SAR CONVST_SAR reaches the SAR when it is 1.5/MCLK cycles wide Increase the acquisition time by 1.5/MCLK when the deglitch circuitry is enabled. Prior to the SAR ADC, the AD7770 contains an internal multiplexer. This multiplexer can be configured over the SPI to set the inputs to the SAR ADC to be either internal circuit nodes (in the case of diagnostics) or to select the external AUXAIN+ and AUXAIN- pins. Along with converting external voltages, the SAR ADC can monitor the internal nodes on the AVDD, IOVDD, and DGND pins and the DLDO and analog LDO (ALDO) outputs. Some voltages are internally attenuated by 6, and the resulting voltage is applied to the SAR ADC, as shown in Table 31. This attenuation is useful because variations in the power supply voltage can be monitored. The input multiplexer of the SAR is controlled by the GLOBAL_ MUX_CONFIG register, and the different inputs available are described in Table 31. The SAR ADC also contains an SAR driver amplifier, as shown in Figure 107. This amplifier settles the SAR input to 12-bit accuracy within the t33 time. This driver amplifier helps minimize the kickback from the SAR converter to the global diagnostic mux input circuit nodes. AVDD 4 AVSS 4 ADCCODE 2n1 2n1 Temperature (C) = 25 DVBE 0.6 0.002 Table 31. SAR Mux Inputs SAR Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Positive Signal AUXAIN+ DVBE REF1+ REF2+ REF_OUT VCM AREG1CAP AREG2CAP DREGCAP AVDD1A AVDD1B AVDD2A AVDD2B IOVDD AVDD4 DGND DGND DGND AVDD4 REF1+ REF2+ AVSSx Negative Signal AUXAIN- AVSSx REF1- REF2- AVSSx AVSSx AVSSx AVSSx DGND AVSSx AVSSx AVSSx AVSSx DGND AVSSx AVSSx AVSSx AVSSx AVSSx AVSSx AVSSx AVDD4 Attenuation / 6 No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No No Yes SDI SDO SET BIT 5 GENERAL_USER_CONFIG_2 REG WRITE TO ADC MUX REGISTER WRITE TO ADC MUX REGISTER ADC CONVERSION RESULT REG ADC CONVERSION RESULT REG Figure 106. Configuring the AD7770 to Operate the SPI to Read from the SAR ADC Rev. E | Page 49 of 97 12538-123 CS AD7770 Data Sheet AVDD4 AVSS4 DEGLITCH CONVST_SAR AUXAIN+ REF AUXAIN- MUX SAR ADC FIFO CONTROL LOGIC SPI ON-CHIP DIAGNOSTICS 12538-122 SAR DRIVER Figure 107. SAR ADC Configuration and Control Table 32. - Diagnostic Input 0 1 2 3 4 5 6 7 8 9 Voltage Floating Floating 280 mV differential signal External reference, positive/negative External reference, negative/positive External reference, negative/negative Internal reference, positive/negative Internal reference, negative/positive Internal reference, positive/positive External reference, positive/positive Recommended Voltage Reference Not applicable Not applicable Internal/external External External External Internal Internal Internal External - ADC DIAGNOSTICS (SPI CONTROL MODE) The AD7770 - ADC diagnostic functions are accessible through the SPI. The internal mux placed before the PGA has different inputs, allowing the user to select a zero-scale, positive full-scale, or negative full-scale input to the - ADC, which can be converted to verify the correct operation of the - ADC channel. The diagnostic mux control signals are shared across all the - channels. Depending on the diagnostic selected, connect the - ADC reference to a different reference source to guarantee that the conversion is within the measurable range. Notes/Result Not applicable Not applicable PGA gain calibration Positive full scale Negative full scale Zero scale Positive full scale Negative full scale Zero scale Zero scale There are two different ways to enable the diagnostic mux, as follows: Setting the CHx_RX bit. This bit enables the input - mux. The multiplexer inputs are described in Table 32. The reference used during the conversions are controlled by the REF_MUX_CTRL bits. Setting CHx_REF_MONITOR. This bit has the same effect as enabling the CHx_RX bit and selects the VDD1x/AVSSx supplies as the main reference. If the AINx pin is connected to AVSSx, the input range is outside the range of AVSSx + 100 mV; therefore, results may differ slightly from the expected value. Alternatively, the inputs can be used to calibrate gain and offset errors. Rev. E | Page 50 of 97 Data Sheet AD7770 ADC CONVERSION OUTPUT--HEADER AND DATA ALERT The AD7770 - conversion results are output on the DOUT0 to DOUT3 pins or over the SPI, depending on the selected interface. If the DOUTx interface is selected, the AD7770 acts as the master in the transmission. If the SPI is selected, the controller is the master. Channel 0 1 2 3 4 5 6 7 DRDY 8-BITS ADC DATA N 12538-124 HEADER N 24-BITS In pin control mode, the header is fixed to the CRC while in SPI mode, and can be selected between CRC and error headers. CRC CRC CRC CRC CH_ID_2 0 0 0 0 1 1 1 1 CH_ID_1 0 0 1 1 0 0 1 1 CH_ID_0 0 1 0 1 0 1 0 1 The CRC generated is eight bits long; the 4 MSBs are placed on the header for the first channel in the pairing and the 4 LSBs on the header of the second channel in the pairing, as shown in Table 34. If a channel is disabled, the 24-bit output data for this channel is 0x000000. Table 34. 8-Bit CRC, Header Configuration (Channel 2) ALERT Figure 108. ADC Output--8-Bit Header Plus 24-Bit Conversion Data CH_ID_0 Table 33. Channel ID For each channel, the width is 32 bits long: 8 bits for the header and 24 bits for the - conversion, as shown in Figure 108. N-1 CH_ID_1 Figure 109. CRC Header The DRDY signal indicates the end of conversion independent of the interface selected to read back the - conversion. When the SPI reads back the - conversion, if a new conversion is completed (DRDY falling edge) before the previous conversion is read back, the results from previous conversion are overwritten and, consequently, the previous conversion data is corrupted. DOUTx CH_ID_2 12538-200 - OUTPUT DATA 0 1 0 CRC7 CRC6 CRC5 CRC4 Table 35. 8-Bit CRC, Header Configuration (Channel 3) ALERT 0 1 1 CRC3 CRC2 CRC1 CRC0 CRC Header The CRC header is the header generated in pin control mode or in SPI mode if DOUT_HEADER_FORMAT is set. As shown in Figure 109, the header consists of an alert bit, three bits for the ADC channel ID, as shown in Table 33, and four bits for the CRC. The chip error bit is set high if an error is detected in any channel, as explained in the General Errors section. The alert bit remains 1 until the error disappears. ERROR Header (SPI Control Mode) In SPI control mode, the default header can be replaced by an error header. If the - conversion is read back through the SPI, disable the CRC by clearing the SPI_CRC_TEST_EN bit. If the DOUTx interface is used, clear the DOUT_HEADER_ FORMAT bit. The error header provides information of common error sources specific for each channel, as shown in Table 36. Modulator and filter errors are indicated even if the checker for these errors are specifically disabled, as described in the - ADC Errors section. Table 36. Status Header Output Bits 7 Name Alert [6:4] 3 2 CH_ID_[2:0] RESET_DETECTED MODULATOR_SATURATE 1 FILTER_SATURATE 0 AIN_OV_UVERROR Description This bit is set high if any of the enabled diagnostic functions have detected an error, including an external clock not detected, a memory map bit flip, or an internal CRC error. This bit is not channel specific. The bit clears if the error is no longer present. These bits indicate which ADC channel the following conversion data came from (see Table 33). This bit indicates if a reset condition occurs. This bit is not channel specific. This bit indicates that the modulator output is 20 consecutive 0s or 1s. The bit resets automatically after the error is no longer present. This bit indicates that the filter output is out of bounds. The bit resets automatically after the error is no longer present. This bit indicates that there is an AINx overvoltage/undervoltage condition on the inputs. This bit is set until the appropriate register is read back and the error is no longer present. Rev. E | Page 51 of 97 AD7770 Data Sheet SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) The AD7770 implements a feature called the SRC on each - channel that allows the user to configure the output data rate or sampling frequency to any desired value, including noninteger values. The SRC achieves fine resolution control over the - ADC ODR. In applications where the ODR must change based on changes in the input signal to maintain sampling coherency, the SRC provides fine control over the ODR. For example, to achieve the highest classification standard, Class A, in power quality applications, coherency must be maintained for 0.01 Hz changes in the input power line. Use the SRC to achieve this sampling frequency accuracy. The GPIO1 and GPIO0 pins must be externally connected. If multiple AD7770 devices must be synchronized, the GPIO1 pin of one device can be connected to multiple devices. This synchronization method requires the use of a common MCLK signal for all the AD7770 devices connected, as shown in Figure 110. PULSE AD7770 GPIO2 MCLK SYNCHRONIZATION LOGIC GPIO1 DIGITAL FILTER GPIO0 In pin control mode, the decimation rate is fixed per the predefined pin control options. Consequently, a noninteger number cannot be selected, as shown in Table 13. AD7770 GPIO2 To set the ODR, the user must program up to four registers, depending on the decimation value: two registers to program the integer value, N (the effective decimation rate), and two registers to program the decimal value, the interpolation factor (IF). MCLK MCLK NC GPIO0 AD7770 GPIO2 As an example, if an output data rate of 2.8 kSPS is required, program the following decimation rate: MCLK SYNCHRONIZATION LOGIC In high resolution mode, (8192/4)/2.8 = 731.428 In low power mode, (4096/8)/2.8 = 182.857 GPIO1 NC GPIO0 NOTES 1. NC = NO CONNECT. 731 (decimal) = 0x2DB SRC_N_MSB, Bits[3:0] = 0x02 SRC_N_LSB, Bits[7:0] = 0xDB 0.428 (decimal) = 0.428 x 216 = 28049 (decimal) = 0x6D91 SRC_IF_MSB, Bits[7:0] = 0x6D SRC_IF_LSB, Bits[7:0] = 0x91 The ODR can be updated on-the-fly, but a new ODR is effective in three conversion cycles of the - ADCs. This condition guarantees a smooth transition with no conversion results out of range. There are two different ways to change the ODR after a new value is written in the SRC registers: via software or via hardware, depending on SRC_LOAD_SOURCE (SRC_UPDATE register, Bit 7). If the SRC_LOAD_SOURCE bit is clear, the new ODR value is updated by setting the SRC_LOAD_UPDATE bit to 1. This bit must be held high for at least two MLCK periods; return the bit to 0 before attempting another update. 12538-125 DIGITAL FILTER The register values for high resolution mode are as follows: GPIO1 DIGITAL FILTER The integer value registers are SRC_N_MSB, Bits[3:0] and SRC_N_LSB, Bits[7:0]. The decimal part value registers are SRC_IF_MSB, Bits[7:0] and SRC_IF_LSB, Bits[7:0]. SYNCHRONIZATION LOGIC Figure 110. Hardware ODR Update SRC Bandwidth The sinc3 filter architecture allows the user to select a noninteger value as the decimation range This versatility means that the filter notches must be adjusted dynamically: two notches at the variable frequency, and one fixed notch to remove the PGA chopping tone. Consequently, the traditional formula for -0.1 dB and -3 dB bandwidth must be adjusted depending on the selected decimation rate. The bandwidth transfer function is not linear but can be approximated by using a linear function. Figure 111 and Figure 112 show the correction factor for the -0.1 dB and -3 dB bandwidth, respectively, in high resolution. In low power mode, the offset must be divided by 4. For example, when the ODR = 1000 SPS in low power mode, the -0.1 dB point is If SRC_LOAD_SOURCE is set, the GPIO0 pin controls the ODR update externally. Apply a pulse in the GPIO2 pin, which is then internally synchronized with the external MCLK clock, and the resultant synchronous signal is output on the GPIO1 pin. Rev. E | Page 52 of 97 BW 0 . 0481 1000 47 .36 71 Hz 4 Data Sheet AD7770 1600 The latency is the contribution of the group delay and the calibration time. -0.1dB FREQUENCY (Hz) 1400 Latency = Group delay + tCAL 1200 where tCAL = 62 x tMCLK, with a maximum error of 2 x tMCLK, in high resolution mode; or 121 x tMCLK, with a maximum error of 4 x tMCLK, in low power mode. 1000 y = 0.0481x + 47.36 800 tMCLK is the modulator period, MCLK/4 in high resolution mode and MCLK/8 in low power mode. 600 400 Settling Time 0 0.1 5.1 10.1 15.1 20.1 ODR (kHz) 25.1 12538-126 200 30.1 9 The filter delay is defined as 3/ODR. In some extreme cases, as when an external pulse is applied, this value may increase to 4/ODR. 8 DATA OUTPUT INTERFACE 7 The - output data interface is defined by the CONVST_SAR, FORMAT0, and FORMAT1 pins in pin control mode at power-up. The FORMATx pins cannot be changed dynamically. Table 14 shows the available options for pin control mode. If the device is configured in SPI control mode, the SPI_SLAVE_MODE_ EN bit enables the SPI to transmit the - ADC conversion results, as shown in Table 23. Figure 111. -0.1 dB Correction Factor -3dB FREQUENCY (kHz) The settling time is defined by the contribution of all the internal stages, the filter delay, and the block calibration. 6 y = 0.2608x + 248.64 5 4 3 2 DOUT3 to DOUT0 Data Interface Standalone Mode 0 0.1 5.1 10.1 15.1 20.1 ODR (kHz) 25.1 30.1 12538-127 1 In standalone mode, the AD7770 interface acts as a master. There are three different DOUTx configurations, configurable through the FORMATx pins in pin control mode, as shown in Figure 113 through Figure 115, or via the DOUT_FORMAT bits, Bits[7:6], in SPI control mode, as described in Table 37. Figure 112. -3 dB Correction Factor SRC Group Delay and Latency The SRC group delay depends on the selected ODR and the power mode, and is defined by the following equation: Group delay = Figure 116, Figure 117, and Figure 118 show the expected data outputs for different DOUTx output modes. 8 SRC _ N SRC _ N ODR where: SRC_N is the integer value of the programmed ODR. ODR is the programmed output data rate. Table 37. DOUTx Channels DOUT_FORMAT Bits/FORMATx Pins 00 Number of DOUTx Lines Enabled 4 01 2 10 or 11 1 Rev. E | Page 53 of 97 Associated Channels DOUT0--Channel 0 and Channel 1 DOUT1--Channel 2 and Channel 3 DOUT2--Channel 4 and Channel 5 DOUT3--Channel 6 and Channel 7 DOUT0--Channel 0, Channel 1, Channel 2, and Channel 3 DOUT1--Channel 4, Channel 5, Channel 6, and Channel 7 DOUT0--Channel 0, Channel 1, Channel 2, Channel 3, Channel 4, Channel 5, Channel 6, and Channel 7 AD7770 Data Sheet AD7770 DRDY DCLK DOUT0 00 CH 1 0 CH 3 0 CH 5 CH 7 DGND FORMAT0 FORMAT1 DOUT1 DOUT2 DOUT3 12538-128 DOUT0: CH 0, DOUT1: CH 2, DOUT2: CH 4, DOUT3: CH 6, DAISY-CHAINING IS NOT POSSIBLE IN THIS FORMAT Figure 113. FORMATx Pin Configuration--FORMAT0 = 0, FORMAT1 = 0 AD7770 DRDY DCLK IOVDD 01 CH 0, CH 1, CH 2, CH 3 OUTPUT ON DOUT0 CH 4, CH 5, CH 6, CH 7 OUTPUT ON DOUT1 DOUT0 FORMAT0 FORMAT1 1 0 DOUT1 12538-129 DGND DAISY-CHAINING IS POSSIBLE IN THIS FORMAT Figure 114. FORMATx Pin Configuration--FORMAT0 = 1, FORMAT1 = 0 AD7770 DRDY DCLK DGND 10 CH 0 TO CH 7 OUTPUT ON DOUT0 FORMAT0 FORMAT1 0 1 DOUT0 12538-130 IOVDD DAISY-CHAINING IS POSSIBLE IN THIS FORMAT Figure 115. FORMATx Pin Configuration--FORMAT0 = 0, FORMAT1 = 1 DCLK SAMPLE N SAMPLE N + 1 DOUT0 CH0-S0 CH1-S0 CH0-S1 CH1-S1 DOUT1 CH2-S0 CH3-S0 CH2-S1 CH3-S1 DOUT0 CH4-S0 CH5-S0 CH4-S1 CH5-S1 DOUT1 CH6-S0 CH7-S0 CH6-S1 CH7-S1 12538-131 DRDY Figure 116. FORMAT0 = 0, FORMAT1 = 0--Each DOUTx Outputs Two ADC Conversions (S0 Means Sample 0 and S1 Means Sample 1) Rev. E | Page 54 of 97 Data Sheet AD7770 DCLK SAMPLE N SAMPLE N + 1 DRDY DOUT0 CH0-S0 CH1-S0 CH2-S0 CH3-S0 CH0-S1 CH1-S1 CH2-S1 CH3-S1 DOUT1 CH4-S0 CH5-S0 CH6-S0 CH7-S0 CH4-S1 CH5-S1 CH6-S1 CH7-S1 12538-132 DOUT2 DOUT3 Figure 117. FORMAT0 = 0, FORMAT1 = 1--Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1 (S0 Means Sample 0 and S1 Means Sample 1) DCLK SAMPLE N SAMPLE N + 1 SAMPLE N + 2 DRDY DOUT0 CH0-S0 CH1-S0 CH2-S0 CH...-S0 CH6-S0 CH7-S0 CH0-S1 CH1-S1 CH2-S1 CH...-S1 CH6-S1 CH7-S2 CH0-S2 CH1-S2 CH2-S2 CH...-S2 CH6-S2 CH7-S2 CH0-S3 DOUT1 12538-133 DOUT2 DOUT3 Figure 118. FORMAT0 = 1, FORMAT1 = 0--Channel 0 to Channel 7 Output on DOUT0 Only (S0 Means Sample 0 and S1 Means Sample 1) Rev. E | Page 55 of 97 AD7770 Data Sheet This feature is especially useful for reducing the component count and wiring connections in, for example, isolated multiconverter applications or for systems with a limited interfacing capacity. Daisy-Chain Mode Daisy-chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple ADCs from separate AD7770 devices. In daisy-chain configuration, only one device has a direct connection between the DOUTx interface and the digital host. For the AD7770, daisy-chain capability is implemented by cascading DOUT0 and DOUT1 through a number of devices, or by just using DOUT0 (the number of DOUTx pins available depends on the selected DOUTx mode). The ability to daisy-chain devices and the limit on the number of devices that can be handled by the chain is dependent on the selected DOUTx mode and the decimation rate employed. For daisy-chain operation, there are two different configurations possible, as described in Table 38. Using the FORMATx = 10 mode, DOUT2 acts as an input pin, as shown in Figure 119. In this case, the DOUT0 pin of the AD7770 devices is cascaded to the DOUT2 pin of the next device in the chain. Data readback is analogous to clocking a shift register where data is clocked on the rising edge of DCLK. When operating in daisy-chain mode, it is required that all AD7770 devices in the chain are correctly synchronized. See the Digital Reset and Synchronization Pins section for more information. Table 38. DOUTx Modes in Daisy-Chain Operation DOUT_FORMAT Bits/ FORMATx Pins 01 Number of DOUTx Lines Enabled 2 10 1 Associated Channels DOUT0--Channel 0 to Channel 3 and DOUT2 DOUT1--Channel 4 to Channel 7 and DOUT3 DOUT2--input channel DOUT3--input channel DOUT0--Channel 0 to Channel 7 and DOUT2 DOUT2--input channel U2 DOUT2/DIN0 U1 DOUT0 DOUT2/DIN0 DOUT0 DCLK U2 DOUT2/DIN0 0 0 0 0 0 U2 DOUT0 U2 S0 CH0 TO CH7 0 U2 S1 CH0 TO CH7 0 U2 S2 CH0 TO CH7 U1 DOUT2/DIN0 U2 S0 CH0 TO CH7 0 U2 S1 CH0 TO CH7 0 U2 S2 CH0 TO CH7 U1 DOUT0 U1 S0 CH0 TO CH7 U2 S0 CH0 TO CH7 U1 S1 CH0 TO CH7 U2 S1 CH0 TO CH7 U1 S2 CH0 TO CH7 12538-134 DRDY Figure 119. Daisy-Chain Connection Mode, FORMAT0 = 1, FORMAT1 = 0 (S0 Means Sample 0 and S1 Means Sample 1); When Connected in Daisy-Chain Mode, DOUT2 Acts as an Input Pin, Represented by DIN0 Rev. E | Page 56 of 97 Data Sheet AD7770 Minimum DCLKx Frequency Select the DCLKx frequency ratio in such a way that the data is completely shifted out before a new conversion is completed; otherwise the previous conversion is overwritten and the transmission becomes corrupt. The minimum DCLKx frequency ratio is defined by the decimation rate, the operation mode, and the lines enabled on the DOUT3 to DOUT0 data interfaces as described in the following equations. In standalone mode and high resolution mode, DCLKMIN_RATIO < Decimation/(8 x CHANNELS_PER_DOUT) In standalone mode and low power mode, DCLKMIN_RATIO < Decimation/(4 x CHANNELS_PER_DOUT) In daisy-chain mode and high resolution mode, DCLKMIN_RATIO < Decimation/(8 x Devices x DOUTx Channels) In daisy-chain mode and low power mode, DCLKMIN_RATIO < Decimation/(4 x Devices x DOUTx Channels) As an example, when operating in master interface mode, FORMATx = 01, the DOUT0 and DOUT1 pins shift out four - channels each and, assuming a maximum output rate in high resolution mode, the decimation = 128. DCLKMIN < 128/(8 x 4) = 4 If the DCLKMIN_RATIO is selected above the necessary minimum, a Logic 0 is continuously transmitted until a new sample is available. An example in daisy-chain mode, assuming FORMATx = 01, and with three devices connected and a decimation rate of 256 in high resolution mode, is as follows: Table 40. Maximum ODRs and Minimum DCLKx Frequencies in High Resolution Mode Decimation Rate 4095 2048 1024 512 256 128 64 ODR (kSPS) 0.500122 1 2 4 8 16 32 Minimum DCLKx (kHz) 1 x DOUTx 2 x DOUTx 4 x DOUTx 128 64 32 256 128 64 512 256 128 1024 512 256 2048 1024 512 4096 2048 1024 8192 4096 2048 Table 41. Maximum ODRs and Minimum DCLKx Frequencies in Low Power Mode Decimation Rate 2048 1024 512 256 128 64 ODR (kSPS) 0.25 0.5 1 2 4 8 Minimum DCLKx (kHz) 1 x DOUTx 2 x DOUTx 4 x DOUTx 64 32 16 128 64 32 256 128 64 512 256 128 1024 512 256 2048 1024 512 If the AD7770 operates in SPI control mode, it is possible to adjust the DOUTx strength, which can be selected in the DOUT_DRIVE_STR bits, as described in Table 42. Table 42. DOUTx Strength DCLKMIN_RATIO < 256/(8 x 3 x 4) = 2.66 = 2 The different ratios are summarized in Table 39. Table 39. Available DCLK Ratios DCLK_CLK_DIV (SPI Control Mode), DCLKx (Pin Control Mode) 000 001 010 011 100 101 110 111 There are maximum achievable ODRs and minimum DCLKx frequencies required for a given DOUTx pin configuration, as shown in Table 40 and Table 41. DCLKx Ratio 1 2 4 8 16 32 64 128 DOUT_DRIVE_STR 00 01 10 11 Mode Nominal Strong Weak Extra strong SPI Interface The SPI gives the user flexibility to read the conversion from the - ADC where the processor or microcontroller is the master. When a new conversion is completed, the DRDY signal is toggled to indicate that data can be accessed. When DRDY toggles, the internal channel counter is reset and the next SPI read originates from Channel 0 again. Conversely, after the last channel data is read, all successive reads before the next DRDY signal originate from Channel 7 (LSB). 12538-135 CS SDO Figure 120. SPI Readback, 16 Bits per Frame 12538-136 CS SDO Figure 121. SPI Readback, 24 Bits per Frame Rev. E | Page 57 of 97 AD7770 Data Sheet To replicate the polynomial division in hardware, remember that the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial, the 8-bit checksum. The SPI operates in multiples of 8 bits per frame; Figure 120 shows a readback example in 16 bits per frames, and Figure 121 shows a readback in 24 bits per frame. Note that if the device is configured in SPI control mode, the AD7770 generates a software reset if the SDI pin is sampled high for 64 consecutive clocks. To avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which generates a readback command that is ignored by the device, as explained in the - Data, ADC Mode section. CALCULATING THE CRC CHECKSUM Note that the AD7770 CRC block preset the input shift registers to 1, meaning that the 8 MSBs of user data must be inverted before compute the algorithm. The AD7770 implements two different CRC checksum generators, one for the - results and another for the SPI control mode. An example of the CRC calculation for 12-bit data is shown in Table 43. The AD7770 uses a CRC polynomial to calculate the CRC checksum value. The 8-bit CRC polynomial used is x8 + x2 + x + 1. Table 43. Example CRC Calculation for 12-Bit Data1 Data Process Data Polynomial 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 CRC 1 This table represents the division of the data; blank cells are for formatting purposes. Rev. E | Page 58 of 97 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 0 0 Data Sheet AD7770 - CRC Checksum SPI Control Mode Checksum The CRC message is calculated internally by the AD7770 on ADC pairs. The CRC is calculated using the ADC output data from two ADCs and Bits[7:4] from the header. Therefore, 56 bits are used to calculate the 8-bit CRC. This CRC is split between the two channel headers. The CRC data covers channel pairings as follows: Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, Channel 6, and Channel 7. The CRC message is calculated internally by the AD7770. The data transferred to the AD7770 uses the R/W bit, a 7-bit address, and 8 bits of data for the CRC calculation. To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 1s. The CRC is calculated from 56 bits across two consecutive/ channel pairings (Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, Channel 6, and Channel 7). The 56 bits consist of the alert bit, the 3 bits for the first ADC pairing channel, and the 24 bits of data of each pairing channel. For example, for the second channel pairing, Channel 2 and Channel 3, The CRC calculated and appended to the data that it is shifted out uses the previous transmitted R/W bit, the 7-bit register address, and the 8-bit data from the readback register. If the previous command was a write command, the 8 bits of data are 0s. If the SAR ADC is read back, the CRC algorithm uses a 0000b header and the 12 bits of SAR conversion data. 56 bits = alert bit + 3 ADC channel bits (010) + 24 data bits (Channel 2) + alert bit + 3 ADC channel bits (011) + 24 data bits (Channel 3) Rev. E | Page 59 of 97 AD7770 Data Sheet REGISTER SUMMARY Table 44. Register Summary Reg. 0x000 Name CH0_CONFIG Bits [7:0] 0x001 CH1_CONFIG [7:0] CH1_GAIN 0x002 CH2_CONFIG [7:0] CH2_GAIN 0x003 CH3_CONFIG [7:0] CH3_GAIN 0x004 CH4_CONFIG [7:0] CH4_GAIN 0x005 CH5_CONFIG [7:0] CH5_GAIN 0x006 CH6_CONFIG [7:0] CH6_GAIN 0x007 CH7_CONFIG [7:0] CH7_GAIN 0x008 CH_DISABLE [7:0] 0x009 CH0_SYNC_ OFFSET CH1_SYNC_ OFFSET CH2_SYNC_ OFFSET CH3_SYNC_ OFFSET CH4_SYNC_ OFFSET CH5_SYNC_ OFFSET CH6_SYNC_ OFFSET CH7_SYNC_ OFFSET GENERAL_ USER_CONFIG_1 [7:0] CH3_ DISABLE CH0_SYNC_OFFSET [7:0] GENERAL_ USER_CONFIG_2 GENERAL_ USER_CONFIG_3 DOUT_ FORMAT [7:0] [7:0] CONVST_ DEGLITCH_DIS DOUT_FORMAT ADC_MUX_ CONFIG GLOBAL_MUX_ CONFIG GPIO_CONFIG GPIO_DATA BUFFER_ CONFIG_1 [7:0] REF_MUX_CTRL 0x01A BUFFER_ CONFIG_2 [7:0] 0x01C CH0_OFFSET_ UPPER_BYTE CH0_OFFSET_ MID_BYTE CH0_OFFSET_ LOWER_BYTE [7:0] 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 0x01D 0x01E Bit 7 Bit 6 CH0_GAIN Bit 5 CH0_REF_ MONITOR CH1_REF_ MONITOR CH2_REF_ MONITOR CH3_REF_ MONITOR CH4_REF_ MONITOR CH5_REF_ MONITOR CH6_REF_ MONITOR CH7_REF_ MONITOR CH5_DISABLE Bit 4 CH0_RX Bit 3 Bit 2 Bit 1 RESERVED Bit 0 Reset 0x00 R/W R/W CH1_RX RESERVED 0x00 R/W CH2_RX RESERVED 0x00 R/W CH3_RX RESERVED 0x00 R/W CH4_RX RESERVED 0x00 R/W CH5_RX RESERVED 0x00 R/W CH6_RX RESERVED 0x00 R/W CH7_RX RESERVED 0x00 R/W 0x00 R/W 0x00 R/W CH1_SYNC_OFFSET 0x00 R/W [7:0] CH2_SYNC_OFFSET 0x00 R/W [7:0] CH3_SYNC_OFFSET 0x00 R/W [7:0] CH4_SYNC_OFFSET 0x00 R/W [7:0] CH5_SYNC_OFFSET 0x00 R/W [7:0] CH6_SYNC_OFFSET 0x00 R/W [7:0] CH7_SYNC_OFFSET 0x00 R/W 0x24 R/W SPI_SYNC 0x09 R/W CLK_QUAL_ DIS RESERVED 0x80 R/W 0x20 R/W 0x00 R/W RESERVED 0x00 R/W GPIO_OP_EN GPIO_WRITE_DATA RESERVED 0x00 0x00 0x38 R/W R/W R/W 0xC0 R/W CH0_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH0_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH0_OFFSET_ALL[7:0] 0x00 R/W [7:0] [7:0] CH7_ DISABLE CH6_ DISABLE ALL_ POWERMO CH_DIS_ DE MCLK_EN RESERVED [7:0] [7:0] [7:0] [7:0] PDB_VCM SAR_DIAG_ MODE_EN RESERVED DOUT_ HEADER_ FORMAT CH4_DISABLE PDB_ REFOUT_BUF PDB_ SAR SDO_DRIVE_STR SPI_SLAVE_ MODE_EN RESERVED CH2_ DISABLE PDB_ RC_OSC REF-BUFP_ PREQ REF-BUFN_ PREQ SOFT_RESET RESERVED DCLK_CLK_DIV MTR_MUX_CTRL RESERVED GPIO_READ_DATA REF_BUF_ POS_EN RESERVED REF_ BUF_ NEG_EN RESERVED Rev. E | Page 60 of 97 CH0_ DISABLE DOUT_DRIVE_STR GLOBAL_MUX_CTRL RESERVED RESERVED CH1_ DISABLE PDB_ ALDO1_ OVRDRV PDB_ ALDO2_ OVRDRV PDB_ DLDO_ OVRDRV Data Sheet Reg. 0x01F 0x020 0x021 0x022 0x023 0x024 0x025 0x026 0x027 0x028 0x029 0x02A 0x02B 0x02C 0x02D 0x02E 0x02F 0x030 0x031 0x032 0x033 0x034 0x035 0x036 0x037 0x038 0x039 0x03A 0x03B 0x03C 0x03D 0x03E 0x03F Name CH0_GAIN_ UPPER_BYTE CH0_GAIN_ MID_BYTE CH0_GAIN_ LOWER_BYTE CH1_OFFSET_ UPPER_BYTE CH1_OFFSET_ MID_BYTE CH1_OFFSET_ LOWER_BYTE CH1_GAIN_ UPPER_BYTE CH1_GAIN_ MID_BYTE CH1_GAIN_ LOWER_BYTE CH2_OFFSET_ UPPER_BYTE CH2_OFFSET_ MID_BYTE CH2_OFFSET_ LOWER_BYTE CH2_GAIN_ UPPER_BYTE CH2_GAIN_ MID_BYTE CH2_GAIN_ LOWER_BYTE CH3_OFFSET_ UPPER_BYTE CH3_OFFSET_ MID_BYTE CH3_OFFSET_ LOWER_BYTE CH3_GAIN_ UPPER_BYTE CH3_GAIN_ MID_BYTE CH3_GAIN_ LOWER_BYTE CH4_OFFSET_ UPPER_BYTE CH4_OFFSET_ MID_BYTE CH4_OFFSET_ LOWER_BYTE CH4_GAIN_ UPPER_BYTE CH4_GAIN_ MID_BYTE CH4_GAIN_ LOWER_BYTE CH5_OFFSET_ UPPER_BYTE CH5_OFFSET_ MID_BYTE CH5_OFFSET_ LOWER_BYTE CH5_GAIN_ UPPER_BYTE CH5_GAIN_ MID_BYTE CH5_GAIN_ LOWER_BYTE AD7770 Bits [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CH0_GAIN_ALL[23:16] Bit 2 Bit 1 Bit 0 Reset 0x00 R/W R/W [7:0] CH0_GAIN_ALL[15:8] 0x00 R/W [7:0] CH0_GAIN_ALL[7:0] 0x00 R/W [7:0] CH1_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH1_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH1_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH1_GAIN_ALL[23:16] 0x00 R/W [7:0] CH1_GAIN_ALL[15:8] 0x00 R/W [7:0] CH1_GAIN_ALL[7:0] 0x00 R/W [7:0] CH2_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH2_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH2_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH2_GAIN_ALL[23:16] 0x00 R/W [7:0] CH2_GAIN_ALL[15:8] 0x00 R/W [7:0] CH2_GAIN_ALL[7:0] 0x00 R/W [7:0] CH3_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH3_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH3_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH3_GAIN_ALL[23:16] 0x00 R/W [7:0] CH3_GAIN_ALL[15:8] 0x00 R/W [7:0] CH3_GAIN_ALL[7:0] 0x00 R/W [7:0] CH4_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH4_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH4_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH4_GAIN_ALL[23:16] 0x00 R/W [7:0] CH4_GAIN_ALL[15:8] 0x00 R/W [7:0] CH4_GAIN_ALL[7:0] 0x00 R/W [7:0] CH5_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH5_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH5_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH5_GAIN_ALL[23:16] 0x00 R/W [7:0] CH5_GAIN_ALL[15:8] 0x00 R/W [7:0] CH5_GAIN_ALL[7:0] 0x00 R/W Rev. E | Page 61 of 97 AD7770 Reg. 0x040 Data Sheet 0x04C Name CH6_OFFSET_ UPPER_BYTE CH6_OFFSET_ MID_BYTE CH6_OFFSET_ LOWER_BYTE CH6_GAIN_ UPPER_BYTE CH6_GAIN_ MID_BYTE CH6_GAIN_ LOWER_BYTE CH7_OFFSET_ UPPER_BYTE CH7_OFFSET_ MID_BYTE CH7_OFFSET_ LOWER_BYTE CH7_GAIN_ UPPER_BYTE CH7_GAIN_ MID_BYTE CH7_GAIN_ LOWER_BYTE CH0_ERR_REG [7:0] RESERVED 0x04D CH1_ERR_REG [7:0] RESERVED 0x04E CH2_ERR_REG [7:0] RESERVED 0x04F CH3_ERR_REG [7:0] RESERVED 0x050 CH4_ERR_REG [7:0] RESERVED 0x051 CH5_ERR_REG [7:0] RESERVED 0x052 CH6_ERR_REG [7:0] RESERVED 0x053 CH7_ERR_REG [7:0] RESERVED 0x054 CH0_1_SAT_ ERR [7:0] RESERVED CH1_ERR_ MOD_SAT CH0_ERR_ AINM_UV CH1_ERR_ AINM_UV CH2_ERR_ AINM_UV CH3_ERR_ AINM_UV CH4_ERR_ AINM_UV CH5_ERR_ AINM_UV CH6_ERR_ AINM_UV CH7_ERR_ AINM_UV CH1_ERR_ FILTER_SAT 0x055 CH2_3_SAT_ ERR [7:0] RESERVED CH3_ERR_ MOD_SAT CH3_ERR_ FILTER_SAT 0x056 CH4_5_SAT_ ERR [7:0] RESERVED CH5_ERR_ MOD_SAT CH5_ERR_ FILTER_SAT 0x057 CH6_7_SAT_ ERR [7:0] RESERVED CH7_ERR_ MOD_SAT CH7_ERR_ FILTER_SAT 0x058 CHX_ERR_ REG_EN [7:0] MOD_SAT_ TEST_EN AINM_UV_ TEST_EN 0x059 GEN_ERR_ REG_1 [7:0] OUTPUT_ FILTER_ SAT_TEST_ SAT_TEST_ EN EN RESERVED MEMMAP_ CRC_ERR ROM_CRC_ ERR 0x05A GEN_ERR_ REG_1_EN [7:0] RESERVED MEMMAP_ CRC_TEST_EN ROM_CRC_ TEST_EN 0x05B GEN_ERR_ REG_2 GEN_ERR_ REG_2_EN STATUS_REG_1 [7:0] RESERVED [7:0] RESERVED EXT_MCLK_ SWITCH_ERR RESERVED [7:0] RESERVED RESET_ DETECTED RESET_ DETECT_EN CHIP_ERROR 0x041 0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B 0x05C 0x05D Bits [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CH6_OFFSET_ALL[23:16] Bit 2 Bit 1 Bit 0 Reset 0x00 R/W R/W [7:0] CH6_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH6_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH6_GAIN_ALL[23:16] 0x00 R/W [7:0] CH6_GAIN_ALL[15:8] 0x00 R/W [7:0] CH6_GAIN_ALL[7:0] 0x00 R/W [7:0] CH7_OFFSET_ALL[23:16] 0x00 R/W [7:0] CH7_OFFSET_ALL[15:8] 0x00 R/W [7:0] CH7_OFFSET_ALL[7:0] 0x00 R/W [7:0] CH7_GAIN_ALL[23:16] 0x00 R/W [7:0] CH7_GAIN_ALL[15:8] 0x00 R/W [7:0] CH7_GAIN_ALL[7:0] 0x00 R/W 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0x00 R 0xFE R/W 0x00 R 0x3E R/W 0x00 R 0x3C R/W 0x00 R ERR_LOC_CH4 Rev. E | Page 62 of 97 CH0_ERR_ AINM_OV CH1_ERR_ AINM_OV CH2_ERR_ AINM_OV CH3_ERR_ AINM_OV CH4_ERR_ AINM_OV CH5_ERR_ AINM_OV CH6_ERR_ AINM_OV CH7_ERR_ AINM_OV CH1_ERR_ OUTPUT_ SAT CH3_ERR_ OUTPUT_ SAT CH5_ERR_ OUTPUT_ SAT CH7_ERR_ OUTPUT_ SAT AINM_OV_ TEST_EN CH0_ERR_ AINP_UV CH1_ERR_ AINP_UV CH2_ERR_ AINP_UV CH3_ERR_ AINP_UV CH4_ERR_ AINP_UV CH5_ERR_ AINP_UV CH6_ERR_ AINP_UV CH7_ERR_ AINP_UV CH0_ERR_ MOD_SAT CH0_ERR_ AINP_OV CH1_ERR_ AINP_OV CH2_ERR_ AINP_OV CH3_ERR_ AINP_OV CH4_ERR_ AINP_OV CH5_ERR_ AINP_OV CH6_ERR_ AINP_OV CH7_ERR_ AINP_OV CH0_ERR_ FILTER_SAT CH2_ERR_ MOD_SAT CH2_ERR_ FILTER_SAT CH4_ERR_ MOD_SAT CH4_ERR_ FILTER_SAT CH6_ERR_ MOD_SAT CH6_ERR_ FILTER_SAT AINP_UV_ TEST_EN AINP_OV_ TEST_EN SPI_CLK_ COUNT_ ERR SPI_CLK_ COUNT_ TEST_EN CH0_ERR_ REF_DET CH1_ERR_ REF_DET CH2_ERR_ REF_DET CH3_ERR_ REF_DET CH4_ERR_ REF_DET CH5_ERR_ REF_DET CH6_ERR_ REF_DET CH7_ERR_ REF_DET CH0_ERR_ OUTPUT_ SAT CH2_ERR_ OUTPUT_ SAT CH4_ERR_ OUTPUT_ SAT CH6_ERR_ OUTPUT_ SAT REF_DET_ TEST_EN SPI_ INVALID_ READ_ERR SPI_ INVALID_ READ_ TEST_EN RE-SERVED ALDO1_ PSM_ERR LDO_PSM_TEST_EN SPI_ SPI_CRC_ INVALID_ ERR WRITE_ERR SPI_ SPI_CRC_ INVALID_ TEST_EN WRITE_ TEST_EN ALDO2_ DLDO_ PSM_ERR PSM_ERR LDO_PSM_TRIP_TEST_EN ERR_LOC_ CH3 ERR_LOC_ CH1 ERR_LOC_ CH2 ERR_LOC_ CH0 Data Sheet AD7770 Reg. 0x05E Name STATUS_REG_2 Bits [7:0] 0x05F STATUS_REG_3 [7:0] 0x060 0x061 0x062 0x063 0x064 SRC_N_MSB SRC_N_LSB SRC_IF_MSB SRC_IF_LSB SRC_UPDATE [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 RESERVED Bit 5 CHIP_ERROR RESERVED CHIP_ERROR Bit 4 ERR_LOC_ GEN2 INIT_ COMPLETE Bit 3 ERR_LOC_ GEN1 ERR_LOC_ SAT_CH6_7 RESERVED SRC_ LOAD_ SOURCE SRC_N_ALL[7:0] SRC_IF_ALL[15:8] SRC_IF_ALL[7:0] RESERVED Rev. E | Page 63 of 97 Bit 2 Bit 1 ERR_ ERR_LOC_ LOC_CH7 CH6 ERR_LOC_S ERR_LOC_ AT_CH4_5 SAT_CH2_3 SRC_N_ALL[11:8] Bit 0 ERR_LOC_ CH5 ERR_LOC_ SAT_CH0_1 SRC_LOAD_ UPDATE Reset 0x00 R/W R 0x00 R 0x00 0x80 0x00 0x00 0x00 R/W R/W R/W R/W R/W AD7770 Data Sheet REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER Address: 0x000, Reset: 0x00, Name: CH0_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH0_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH0_REF_MONITOR (R/W) Channel used as Reference monitor [4] CH0_RX (R/W) Channel Meter Mux RX Mode Table 45. Bit Descriptions for CH0_CONFIG Bits [7:6] Bit Name CH0_GAIN Settings 00 01 10 11 5 4 [3:0] CH0_REF_MONITOR CH0_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W CHANNEL 1 CONFIGURATION REGISTER Address: 0x001, Reset: 0x00, Name: CH1_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH1_GAIN (R/W) AFE Gain 00: Gain = 1. 01: Gain = 2. 10: Gain = 4. 11: Gain = 8. [2:0] RESERVED [3] RESERVED [5] CH1_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH1_RX (R/W) Channel Meter Mux RX Mode Table 46. Bit Descriptions for CH1_CONFIG Bits [7:6] Bit Name CH1_GAIN Settings 00 01 10 11 5 4 [3:0] CH1_REF_MONITOR CH1_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Rev. E | Page 64 of 97 Data Sheet AD7770 CHANNEL 2 CONFIGURATION REGISTER Address: 0x002, Reset: 0x00, Name: CH2_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH2_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH2_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH2_RX (R/W) Channel Meter Mux RX Mode Table 47. Bit Descriptions for CH2_CONFIG Bits [7:6] Bit Name CH2_GAIN Settings 00 01 10 11 5 4 [3:0] CH2_REF_MONITOR CH2_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W CHANNEL 3 CONFIGURATION REGISTER Address: 0x003, Reset: 0x00, Name: CH3_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH3_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH3_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH3_RX (R/W) Channel Meter Mux RX Mode Table 48. Bit Descriptions for CH3_CONFIG Bits [7:6] Bit Name CH3_GAIN Settings 00 01 10 11 5 4 [3:0] CH3_REF_MONITOR CH3_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Rev. E | Page 65 of 97 AD7770 Data Sheet CHANNEL 4 CONFIGURATION REGISTER Address: 0x004, Reset: 0x00, Name: CH4_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH4_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH4_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH4_RX (R/W) Channel Meter Mux RX Mode Table 49. Bit Descriptions for CH4_CONFIG Bits [7:6] Bit Name CH4_GAIN Settings 00 01 10 11 5 4 [3:0] CH4_REF_MONITOR CH4_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W CHANNEL 5 CONFIGURATION REGISTER Address: 0x005, Reset: 0x00, Name: CH5_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH5_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH5_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH5_RX (R/W) Channel Meter Mux RX Mode Table 50. Bit Descriptions for CH5_CONFIG Bits [7:6] Bit Name CH5_GAIN Settings 00 01 10 11 5 4 [3:0] CH5_REF_MONITOR CH5_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Rev. E | Page 66 of 97 Data Sheet AD7770 CHANNEL 6 CONFIGURATION REGISTER Address: 0x006, Reset: 0x00, Name: CH6_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH6_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH6_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH6_RX (R/W) Channel Meter Mux RX Mode Table 51. Bit Descriptions for CH6_CONFIG Bits [7:6] Bit Name CH6_GAIN Settings 00 01 10 11 5 4 [3:0] CH6_REF_MONITOR CH6_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W Reset 0x0 Access R/W 0x0 0x0 0x0 R/W R/W R/W CHANNEL 7 CONFIGURATION REGISTER Address: 0x007, Reset: 0x00, Name: CH7_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] CH7_GAIN (R/W) AFE Gain 00: Gain 1. 01: Gain 2. 10: Gain 4. 11: Gain 8. [2:0] RESERVED [3] RESERVED [5] CH7_REF_MONITOR (R/W) Channel used as Reference m onitor [4] CH7_RX (R/W) Channel Meter Mux RX Mode Table 52. Bit Descriptions for CH7_CONFIG Bits [7:6] Bit Name CH7_GAIN Settings 00 01 10 11 5 4 [3:0] CH7_REF_MONITOR CH7_RX RESERVED Description AFE Gain Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel Used as Reference Monitor Channel Meter Mux Rx Mode Reserved Rev. E | Page 67 of 97 AD7770 Data Sheet DISABLE CLOCKS TO ADC CHANNEL REGISTER Address: 0x008, Reset: 0x00, Name: CH_DISABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH7_DISABLE (R/W) Channel 7 Disable [0] CH0_DISABLE (R/W) Channel 0 Disable [6] CH6_DISABLE (R/W) Channel 6 Disable [1] CH1_DISABLE (R/W) Channel 1 Disable [5] CH5_DISABLE (R/W) Channel 5 Disable [2] CH2_DISABLE (R/W) Channel 2 Disable [4] CH4_DISABLE (R/W) Channel 4 Disable [3] CH3_DISABLE (R/W) Channel 3 Disable Table 53. Bit Descriptions for CH_DISABLE Bits 7 6 5 4 3 2 1 0 Bit Name CH7_DISABLE CH6_DISABLE CH5_DISABLE CH4_DISABLE CH3_DISABLE CH2_DISABLE CH1_DISABLE CH0_DISABLE Settings Description Channel 7 Disable Channel 6 Disable Channel 5 Disable Channel 4 Disable Channel 3 Disable Channel 2 Disable Channel 1 Disable Channel 0 Disable Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W CHANNEL 0 SYNC OFFSET REGISTER Address: 0x009, Reset: 0x00, Name: CH0_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_SYNC_OFFSET (R/W) Channel Sync Offset Table 54. Bit Descriptions for CH0_SYNC_OFFSET Bits [7:0] Bit Name CH0_SYNC_OFFSET Settings Description Channel Sync Offset Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 1 SYNC OFFSET REGISTER Address: 0x00A, Reset: 0x00, Name: CH1_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_SYNC_OFFSET (R/W) Channel Sync Offset Table 55. Bit Descriptions for CH1_SYNC_OFFSET Bits [7:0] Bit Name CH1_SYNC_OFFSET Settings Description Channel Sync Offset CHANNEL 2 SYNC OFFSET REGISTER Address: 0x00B, Reset: 0x00, Name: CH2_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_SYNC_OFFSET (R/W) Channel Sync Offset Table 56. Bit Descriptions for CH2_SYNC_OFFSET Bits [7:0] Bit Name CH2_SYNC_OFFSET Settings Description Channel Sync Offset Rev. E | Page 68 of 97 Data Sheet AD7770 CHANNEL 3 SYNC OFFSET REGISTER Address: 0x00C, Reset: 0x00, Name: CH3_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_SYNC_OFFSET (R/W) Channel Sync Offset Table 57. Bit Descriptions for CH3_SYNC_OFFSET Bits [7:0] Bit Name CH3_SYNC_OFFSET Settings Description Channel Sync Offset Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 4 SYNC OFFSET REGISTER Address: 0x00D, Reset: 0x00, Name: CH4_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_SYNC_OFFSET (R/W) Channel Sync Offset Table 58. Bit Descriptions for CH4_SYNC_OFFSET Bits [7:0] Bit Name CH4_SYNC_OFFSET Settings Description Channel Sync Offset CHANNEL 5 SYNC OFFSET REGISTER Address: 0x00E, Reset: 0x00, Name: CH5_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_SYNC_OFFSET (R/W) Channel Sync Offset Table 59. Bit Descriptions for CH5_SYNC_OFFSET Bits [7:0] Bit Name CH5_SYNC_OFFSET Settings Description Channel Sync Offset CHANNEL 6 SYNC OFFSET REGISTER Address: 0x00F, Reset: 0x00, Name: CH6_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_SYNC_OFFSET (R/W) Channel Sync Offset Table 60. Bit Descriptions for CH6_SYNC_OFFSET Bits [7:0] Bit Name CH6_SYNC_OFFSET Settings Description Channel Sync Offset CHANNEL 7 SYNC OFFSET REGISTER Address: 0x010, Reset: 0x00, Name: CH7_SYNC_OFFSET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_SYNC_OFFSET (R/W) Channel Sync Offset Table 61. Bit Descriptions for CH7_SYNC_OFFSET Bits [7:0] Bit Name CH7_SYNC_OFFSET Settings Description Channel Sync Offset Rev. E | Page 69 of 97 AD7770 Data Sheet GENERAL USER CONFIGURATION 1 REGISTER Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 [7] ALL_CH_DIS__MCLK_EN (R/W) If all SD channels are disabled, setting this bit high allows DCLK to continue toggling [1:0] SOFT_RESET (R/W) Soft Reset 00: No Effect. 01: No Effect. 10: 2nd write. 11: 1st write. [6] POWERMODE (R/W) Power Mode 0: Low Power (1/4) 1: High Resolution. [2] PDB_RC_OSC (R/W) PowerDown signal for internal oscillator. Active Low [5] PDB_VCM (R/W) PowerDown VCM Buffer. Active Low [3] PDB_SAR (R/W) PowerDown SA. Active Low [4] PDB_REFOUT_BUF (R/W) PowerDown Internal Reference Output Buffer. Active Low Table 62. Bit Descriptions for GENERAL_USER_CONFIG_1 Bits 7 Bit Name ALL_CH_DIS_MCLK_EN 6 POWERMODE Settings 0 1 5 4 3 2 [1:0] PDB_VCM PDB_REFOUT_BUF PDB_SAR PDB_RC_OSC SOFT_RESET 00 01 10 11 Description If all - channels are disabled, setting this bit high allows DCLK to continue toggling. Power Mode. Low power (1/4). High resolution. Power Down VCM Buffer. Active low. Power Down Internal Reference Output Buffer. Active low. Power Down SAR. Active low. Power Down Signal for Internal Oscillator. Active low. Soft Reset. No effect. No effect. 2nd write. 1st write. Reset 0x0 Access R/W 0x0 R/W 0x1 0x0 0x0 0x1 0x0 R/W R/W R/W R/W R/W Reset 0x0 0x0 Access R/W R/W GENERAL USER CONFIGURATION 2 REGISTER Address: 0x012, Reset: 0x09, Name: GENERAL_USER_CONFIG_2 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 [7] RESERVED [0] SPI_SYNC (R/W) SYNC pulse generated thru SPI 0: This signal is ANDed with the value on STARTb pin in the control m odule, generate a pulse in /SYNC_IN pin. 1: This bit is ANDed with the value on STARTb pin in the control module. [6] RESERVED [5] SAR_DIAG_MODE_EN (R/W) Sets SPI interface to read back SAR result on SDO [2:1] DOUT_DRIVE_STR (R/W) DOUT Drive Strength 00: Nom inal. 01: Strong. 10: Weak. 11: Extra Strong. [4:3] SDO_DRIVE_STR (R/W) SDO Drive Strength 00: Nom inal. 01: Strong. 10: Weak. 11: Extra Strong. Table 63. Bit Descriptions for GENERAL_USER_CONFIG_2 Bits [7:6] 5 Bit Name RESERVED SAR_DIAG_MODE_EN Settings Description Reserved. Sets SPI to Read Back SAR Result on SDO. Rev. E | Page 70 of 97 Data Sheet Bits [4:3] Bit Name SDO_DRIVE_STR AD7770 Settings 00 01 10 11 [2:1] DOUT_DRIVE_STR 00 01 10 11 0 SPI_SYNC 0 1 Description SDO Drive Strength. Nominal. Strong. Weak. Extra strong. DOUTx Drive Strength. Nominal. Strong. Weak. Extra strong. SYNC Pulse Generated Through SPI. This signal is AND'ed with the value on the START pin in the control module and generates a pulse in the SYNC_IN pin. This bit is AND'ed with the value on START pin in the control module. Reset 0x1 Access R/W 0x0 R/W 0x1 R/W Reset 0x2 Access R/W 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W GENERAL USER CONFIGURATION 3 REGISTER Address: 0x013, Reset: 0x80, Name: GENERAL_USER_CONFIG_3 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:6] CONVST_DEGLITCH_DIS (R/W) Dis able deglitching of CONVST pin 00: Reserved. 01: Reserved. 10: CONVST_SAR Deglitch 1.5 MCLK. 11: No deglitch circuit. [0] CLK_QUAL_DIS (R/W) Disables the clock qualifier check if the user requires to use an MCLK signal < 265kHz. [1] RESERVED [3:2] RESERVED [5] RESERVED [4] SPI_SLAVE_MODE_EN (R/W) Enable to SPI slave m ode to read back ADC on SDO Table 64. Bit Descriptions for GENERAL_USER_CONFIG_3 Bits [7:6] Bit Name CONVST_DEGLITCH_DIS Settings 00 01 10 11 5 4 [3:2] 1 0 RESERVED SPI_SLAVE_MODE_EN RESERVED RESERVED CLK_QUAL_DIS Description Disable deglitching of CONVST_SAR pin. Reserved. Reserved. CONVST_SAR deglitch 1.5/MCLK. No deglitch circuit. Reserved. Enable to SPI slave mode to read back ADC on SDO. Reserved. Reserved. Disables the clock qualifier check if the user requires to use an MCLK signal <265 kHz. Rev. E | Page 71 of 97 AD7770 Data Sheet DATA OUTPUT FORMAT REGISTER Address: 0x014, Reset: 0x20, Name: DOUT_FORMAT 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 [7:6] DOUT_FORMAT (R/W) Data out format 00: 4 DOUT Lines. 01: 2 DOUT Lines. 10: 1 DOUT Lines. 11: 1 DOUT Lines. [0] RESERVED [5] DOUT_HEADER_FORMAT (R/W) Dout header form at 0: Status Header. 1: CRC Header. [4] RESERVED [3:1] DCLK_CLK_DIV (R/W) Divide MCLK 000: Divide by 1. 001: Divide by 2. 010: Divide by 4. 011: Divide by 8. 100: Divide by 16. 101: Divide by 32. 110: Divide by 64. 111: Divide by 128. Table 65. Bit Descriptions for DOUT_FORMAT Bits [7:6] Bit Name DOUT_FORMAT Settings 00 01 10 11 5 DOUT_HEADER_FORMAT 0 1 4 [3:1] RESERVED DCLK_CLK_DIV 000 001 010 011 100 101 110 111 0 RESERVED Description Data Out Format 4 DOUTx lines 2 DOUTx lines 1 DOUTx lines 1 DOUTx lines DOUTx Header Format Status header CRC header Reserved Divide MCLK Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 Reserved Rev. E | Page 72 of 97 Reset 0x0 Access R/W 0x1 R/W 0x0 0x0 R/W R/W 0x0 R/W Data Sheet AD7770 MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER Address: 0x015, Reset: 0x00, Name: ADC_MUX_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] REF_MUX_CTRL (R/W) SD ADC Reference Mux 00: External Reference REFx+/REFx01: Internal Reference. 10: External Supply AVDD1x/AVSSx. 11: External Reference REFx-/REFx+. [1:0] RESERVED [5:2] MTR_MUX_CTRL (R/W) SD ADC Meter Mux 0010: 280mV. 0011: External Reference REFx+/REFx0100: External Reference REFx-/REFx+. 0101: External Reference REFx-/REFx0110: Internal Reference +/0111: Internal Reference -/+. 1000: Internal Reference +/+. 1001: External Reference REFx+/REFx+. Table 66. Bit Descriptions for ADC_MUX_CONFIG Bits [7:6] Bit Name REF_MUX_CTRL Settings 00 01 10 11 [5:2] MTR_MUX_CTRL 0010 0011 0100 0101 0110 0111 1000 1001 [1:0] RESERVED Description - ADC Reference Mux External reference REFx+/REFx- Internal reference. External supply AVDD1x/AVSSx External reference REFx-/REFx+ - ADC Meter Mux 280 mV External reference REFx+/REFx- External reference REFx-/REFx+ External reference REFx-/REFx- Internal reference +/- Internal reference -/+ Internal reference +/+ External reference REFx+/REFx+ Reserved Rev. E | Page 73 of 97 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W AD7770 Data Sheet GLOBAL DIAGNOSTICS MUX REGISTER Address: 0x016, Reset: 0x00, Name: GLOBAL_MUX_CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:3] GLOBAL_MUX_CTRL (R/W) Global SAR diagnostics m ux control 00000: AUXAin+ AUXAin00001: DVBE AVSSx. 00010: REF1P REF1N. ... 10011: REF1+ AVSSx. 10100: REF2+ AVSSx. 10101: AVSSx AVDD4. Attenuated. [2:0] RESERVED Table 67. Bit Descriptions for GLOBAL_MUX_CONFIG Bits [7:3] Bit Name GLOBAL_MUX_CTRL Settings Description Global SAR Diagnostics Mux Control. AUXAIN+/AUXAIN-. DVBE/AVSSx. REF1+/REF1-. REF2+/REF2-. REF_OUT/AVSSx. VCM/AVSSx. AREG1CAP/AVSSx. AREG2CAP/AVSSx. DREGCAP/DGND. AVDD1A/AVSSx. AVDD1B/AVSSx. AVDD2A/AVSSx. AVDD2B/AVSSx. IOVDD/DGND. AVDD4/AVSSx. DGND/AVSSx. DGND/AVSSx. DGND/AVSSx. AVDD4/AVSSx. REF1+/AVSSx. REF2+/AVSSx. AVSSx/AVDD4. Attenuated. Reserved. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 [2:0] RESERVED Reset 0x0 Access R/W 0x0 R/W GPIO CONFIGURATION REGISTER Address: 0x017, Reset: 0x00, Name: GPIO_CONFIG [7:3] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [2:0] GPIO_OP_EN (R/W) GPIO input/output Table 68. Bit Descriptions for GPIO_CONFIG Bits [7:3] [2:0] Bit Name RESERVED GPIO_OP_EN Settings Description Reserved GPIO Input/Output Reset 0x0 0x0 Rev. E | Page 74 of 97 Access R/W R/W Data Sheet AD7770 GPIO DATA REGISTER Address: 0x018, Reset: 0x00, Name: GPIO_DATA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [2:0] GPIO_WRITE_DATA (R/W) Value sent to GPIO pins [5:3] GPIO_READ_DATA (R) Data read from GPIO pins Table 69. Bit Descriptions for GPIO_DATA Bits [7:6] [5:3] [2:0] Bit Name RESERVED GPIO_READ_DATA GPIO_WRITE_DATA Settings Description Reserved Data Read from the GPIO Pins Value Sent to the GPIO Pins Reset 0x0 0x0 0x0 Access R/W R R/W BUFFER CONFIGURATION 1 REGISTER Address: 0x019, Reset: 0x38, Name: BUFFER_CONFIG_1 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 [7] RESERVED [0] RESERVED [6] RESERVED [1] RESERVED [5] RESERVED [2] RESERVED [4] REF_BUF_POS_EN (R/W) Reference buffer positive enable [3] REF_BUF_NEG_EN (R/W) Reference buffer negative enable Table 70. Bit Descriptions for BUFFER_CONFIG_1 Bits [7:5] 4 3 [2:0] Bit Name RESERVED REF_BUF_POS_EN REF_BUF_NEG_EN RESERVED Settings Description Reserved Reference Buffer Positive Enable Reference Buffer Negative Enable Reserved Reset 0x0 0x1 0x1 0x0 Access R/W R/W R/W R/W Reset 0x1 0x1 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W BUFFER CONFIGURATION 2 REGISTER Address: 0x01A, Reset: 0xC0, Name: BUFFER_CONFIG_2 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 [7] REFBUFP_PREQ (R/W) Reference buffer pos itive precharge enable [6] REFBUFN_PREQ (R/W) Reference buffer negative precharge enable [0] PDB_DLDO_OVRDRV (R/W) DRegCap Overdrive Enable. [1] PDB_ALDO2_OVRDRV (R/W) AReg2Cap Overdrive Enable [2] PDB_ALDO1_OVRDRV (R/W) AReg1Cap Overdrive Enable [5:3] RESERVED Table 71. Bit Descriptions for BUFFER_CONFIG_2 Bits 7 6 [5:3] 2 1 0 Bit Name REFBUFP_PREQ REFBUFN_PREQ RESERVED PDB_ALDO1_OVRDRV PDB_ALDO2_OVRDRV PDB_DLDO_OVRDRV Settings Description Reference Buffer Positive Precharge Enable Reference Buffer Negative Precharge Enable Reserved AREG1CAP Overdrive Enable AREG2CAP Overdrive Enable DREGCAP Overdrive Enable Rev. E | Page 75 of 97 AD7770 Data Sheet CHANNEL 0 OFFSET UPPER BYTE REGISTER Address: 0x01C, Reset: 0x00, Name: CH0_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[23:16] (R/W) Com bined Offset register Channel 0 Table 72. Bit Descriptions for CH0_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH0_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 0 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 0 OFFSET MIDDLE BYTE REGISTER Address: 0x01D, Reset: 0x00, Name: CH0_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[15:8] (R/W) Com bined Offset register Channel 0 Table 73. Bit Descriptions for CH0_OFFSET_MID_BYTE Bits [7:0] Bit Name CH0_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 0 CHANNEL 0 OFFSET LOWER BYTE REGISTER Address: 0x01E, Reset: 0x00, Name: CH0_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_OFFSET_ALL[7:0] (R/W) Com bined Offs et regis ter Channel 0 Table 74. Bit Descriptions for CH0_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH0_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 0 CHANNEL 0 GAIN UPPER BYTE REGISTER Address: 0x01F, Reset: 0x00, Name: CH0_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[23:16] (R/W) Combined gain register Channel 0 Table 75. Bit Descriptions for CH0_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH0_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 0 CHANNEL 0 GAIN MIDDLE BYTE REGISTER Address: 0x020, Reset: 0x00, Name: CH0_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 0 Table 76. Bit Descriptions for CH0_GAIN_MID_BYTE Bits [7:0] Bit Name CH0_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 0 Rev. E | Page 76 of 97 Data Sheet AD7770 CHANNEL 0 GAIN LOWER BYTE REGISTER Address: 0x021, Reset: 0x00, Name: CH0_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH0_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 0 Table 77. Bit Descriptions for CH0_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH0_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 0 Reset 0x0 Access R/W CHANNEL 1 OFFSET UPPER BYTE REGISTER Address: 0x022, Reset: 0x00, Name: CH1_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 1 Table 78. Bit Descriptions for CH1_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH1_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 1 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 1 OFFSET MIDDLE BYTE REGISTER Address: 0x023, Reset: 0x00, Name: CH1_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 1 Table 79. Bit Descriptions for CH1_OFFSET_MID_BYTE Bits [7:0] Bit Name CH1_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 1 CHANNEL 1 OFFSET LOWER BYTE REGISTER Address: 0x024, Reset: 0x00, Name: CH1_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 1 Table 80. Bit Descriptions for CH1_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH1_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 1 Rev. E | Page 77 of 97 AD7770 Data Sheet CHANNEL 1 GAIN UPPER BYTE REGISTER Address: 0x025, Reset: 0x00, Name: CH1_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[23:16] (R/W) Combined gain register Channel 1 Table 81. Bit Descriptions for CH1_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH1_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 1 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 1 GAIN MIDDLE BYTE REGISTER Address: 0x026, Reset: 0x00, Name: CH1_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 1 Table 82. Bit Descriptions for CH1_GAIN_MID_BYTE Bits [7:0] Bit Name CH1_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 1 CHANNEL 1 GAIN LOWER BYTE REGISTER Address: 0x027, Reset: 0x00, Name: CH1_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 1 Table 83. Bit Descriptions for CH1_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH1_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 1 CHANNEL 2 OFFSET UPPER BYTE REGISTER Address: 0x028, Reset: 0x00, Name: CH2_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 2 Table 84. Bit Descriptions for CH2_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH2_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 2 Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 2 OFFSET MIDDLE BYTE REGISTER Address: 0x029, Reset: 0x00, Name: CH2_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 2 Table 85. Bit Descriptions for CH2_OFFSET_MID_BYTE Bits [7:0] Bit Name CH2_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 2 Rev. E | Page 78 of 97 Data Sheet AD7770 CHANNEL 2 OFFSET LOWER BYTE REGISTER Address: 0x02A, Reset: 0x00, Name: CH2_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 2 Table 86. Bit Descriptions for CH2_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH2_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 2 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 2 GAIN UPPER BYTE REGISTER Address: 0x02B, Reset: 0x00, Name: CH2_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[23:16] (R/W) Combined gain register Channel 2 Table 87. Bit Descriptions for CH2_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH2_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 2 CHANNEL 2 GAIN MIDDLE BYTE REGISTER Address: 0x02C, Reset: 0x00, Name: CH2_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[15:8] (R/W) Com bined gain register Channel 2 Table 88. Bit Descriptions for CH2_GAIN_MID_BYTE Bits [7:0] Bit Name CH2_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 2 CHANNEL 2 GAIN LOWER BYTE REGISTER Address: 0x02D, Reset: 0x00, Name: CH2_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 2 Table 89. Bit Descriptions for CH2_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH2_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 2 CHANNEL 3 OFFSET UPPER BYTE REGISTER Address: 0x02E, Reset: 0x00, Name: CH3_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 3 Table 90. Bit descriptions for CH3_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH3_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 3 Rev. E | Page 79 of 97 Reset 0x0 Access R/W AD7770 Data Sheet CHANNEL 3 OFFSET MIDDLE BYTE REGISTER Address: 0x02F, Reset: 0x00, Name: CH3_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 3 Table 91. Bit Descriptions for CH3_OFFSET_MID_BYTE Bits [7:0] Bit Name CH3_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 3 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 3 OFFSET LOWER BYTE REGISTER Address: 0x030, Reset: 0x00, Name: CH3_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 3 Table 92. Bit Descriptions for CH3_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH3_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 3 CHANNEL 3 GAIN UPPER BYTE REGISTER Address: 0x031, Reset: 0x00, Name: CH3_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[23:16] (R/W) Combined gain register Channel 3 Table 93. Bit Descriptions for CH3_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH3_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 3 CHANNEL 3 GAIN MIDDLE BYTE REGISTER Address: 0x032, Reset: 0x00, Name: CH3_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[15:8] (R/W) Combined gain register Channel 3 Table 94. Bit Descriptions for CH3_GAIN_MID_BYTE Bits [7:0] Bit Name CH3_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 3 CHANNEL 3 GAIN LOWER BYTE REGISTER Address: 0x033, Reset: 0x00, Name: CH3_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 3 Table 95. Bit Descriptions for CH3_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH3_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 3 Rev. E | Page 80 of 97 Data Sheet AD7770 CHANNEL 4 OFFSET UPPER BYTE REGISTER Address: 0x034, Reset: 0x00, Name: CH4_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 4 Table 96. Bit Descriptions for CH4_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH4_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 4 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 4 OFFSET MIDDLE BYTE REGISTER Address: 0x035, Reset: 0x00, Name: CH4_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 4 Table 97. Bit Descriptions for CH4_OFFSET_MID_BYTE Bits [7:0] Bit Name CH4_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 4 CHANNEL 4 OFFSET LOWER BYTE REGISTER Address: 0x036, Reset: 0x00, Name: CH4_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 4 Table 98. Bit Descriptions for CH4_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH4_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 4 CHANNEL 4 GAIN UPPER BYTE REGISTER Address: 0x037, Reset: 0x00, Name: CH4_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[23:16] (R/W) Combined gain register Channel 4 Table 99. Bit Descriptions for CH4_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH4_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 4 CHANNEL 4 GAIN MIDDLE BYTE REGISTER Address: 0x038, Reset: 0x00, Name: CH4_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[15:8] (R/W) Combined gain register Channel 4 Table 100. Bit Descriptions for CH4_GAIN_MID_BYTE Bits [7:0] Bit Name CH4_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 4 Rev. E | Page 81 of 97 AD7770 Data Sheet CHANNEL 4 GAIN LOWER BYTE REGISTER Address: 0x039, Reset: 0x00, Name: CH4_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 4 Table 101. Bit Descriptions for CH4_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH4_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 4 Reset 0x0 Access R/W CHANNEL 5 OFFSET UPPER BYTE REGISTER Address: 0x03A, Reset: 0x00, Name: CH5_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 5 Table 102. Bit Descriptions for CH5_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH5_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 5 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 5 OFFSET MIDDLE BYTE REGISTER Address: 0x03B, Reset: 0x00, Name: CH5_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 5 Table 103. Bit Descriptions for CH5_OFFSET_MID_BYTE Bits [7:0] Bit Name CH5_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 5 CHANNEL 5 OFFSET LOWER BYTE REGISTER Address: 0x03C, Reset: 0x00, Name: CH5_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 5 Table 104. Bit Descriptions for CH5_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH5_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 5 CHANNEL 5 GAIN UPPER BYTE REGISTER Address: 0x03D, Reset: 0x00, Name: CH5_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[23:16] (R/W) Combined gain register Channel 5 Table 105. Bit Descriptions for CH5_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH5_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 5 Rev. E | Page 82 of 97 Data Sheet AD7770 CHANNEL 5 GAIN MIDDLE BYTE REGISTER Address: 0x03E, Reset: 0x00, Name: CH5_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[15:8] (R/W) Combined gain register Channel 5 Table 106. Bit Descriptions for CH5_GAIN_MID_BYTE Bits [7:0] Bit Name CH5_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 5 Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 5 GAIN LOWER BYTE REGISTER Address: 0x03F, Reset: 0x00, Name: CH5_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 5 Table 107. Bit Descriptions for CH5_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH5_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 5 CHANNEL 6 OFFSET UPPER BYTE REGISTER Address: 0x040, Reset: 0x00, Name: CH6_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 6 Table 108. Bit Descriptions for CH6_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH6_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 6 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 6 OFFSET MIDDLE BYTE REGISTER Address: 0x041, Reset: 0x00, Name: CH6_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 6 Table 109. Bit Descriptions for CH6_OFFSET_MID_BYTE Bits [7:0] Bit Name CH6_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 6 CHANNEL 6 OFFSET LOWER BYTE REGISTER Address: 0x042, Reset: 0x00, Name: CH6_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 6 Table 110. Bit Descriptions for CH6_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH6_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 6 Rev. E | Page 83 of 97 AD7770 Data Sheet CHANNEL 6 GAIN UPPER BYTE REGISTER Address: 0x043, Reset: 0x00, Name: CH6_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[23:16] (R/W) Combined gain register Channel 6 Table 111. Bit Descriptions for CH6_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH6_GAIN_ALL[23:16] Settings Description Combined Gain Register Channel 6 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 6 GAIN MIDDLE BYTE REGISTER Address: 0x044, Reset: 0x00, Name: CH6_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[15:8] (R/W) Combined gain register Channel 6 Table 112. Bit Descriptions for CH6_GAIN_MID_BYTE Bits [7:0] Bit Name CH6_GAIN_ALL[15:8] Settings Description Combined Gain Register Channel 6 CHANNEL 6 GAIN LOWER BYTE REGISTER Address: 0x045, Reset: 0x00, Name: CH6_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_GAIN_ALL[7:0] (R/W) Com bined gain regis ter Channel 6 Table 113. Bit Descriptions for CH6_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH6_GAIN_ALL[7:0] Settings Description Combined Gain Register Channel 6 CHANNEL 7 OFFSET UPPER BYTE REGISTER Address: 0x046, Reset: 0x00, Name: CH7_OFFSET_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[23:16] (R/W) Com bined offs et regis ter Channel 7 Table 114. Bit Descriptions for CH7_OFFSET_UPPER_BYTE Bits [7:0] Bit Name CH7_OFFSET_ALL[23:16] Settings Description Combined Offset Register Channel 7 Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 7 OFFSET MIDDLE BYTE REGISTER Address: 0x047, Reset: 0x00, Name: CH7_OFFSET_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[15:8] (R/W) Com bined offs et register Channel 7 Table 115. Bit Descriptions for CH7_OFFSET_MID_BYTE Bits [7:0] Bit Name CH7_OFFSET_ALL[15:8] Settings Description Combined Offset Register Channel 7 Rev. E | Page 84 of 97 Data Sheet AD7770 CHANNEL 7 OFFSET LOWER BYTE REGISTER Address: 0x048, Reset: 0x00, Name: CH7_OFFSET_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_OFFSET_ALL[7:0] (R/W) Com bined offs et regis ter Channel 7 Table 116. Bit Descriptions for CH7_OFFSET_LOWER_BYTE Bits [7:0] Bit Name CH7_OFFSET_ALL[7:0] Settings Description Combined Offset Register Channel 7 Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W CHANNEL 7 GAIN UPPER BYTE REGISTER Address: 0x049, Reset: 0x00, Name: CH7_GAIN_UPPER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[23:16] (R/W) Com bined gain regis ter Channel 7 Table 117. Bit Descriptions for CH7_GAIN_UPPER_BYTE Bits [7:0] Bit Name CH7_GAIN ALL[23:16] Settings Description Combined Gain Register Channel 7 CHANNEL 7 GAIN MIDDLE BYTE REGISTER Address: 0x04A, Reset: 0x00, Name: CH7_GAIN_MID_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[15:8] (R/W) Com bined gain regis ter Channel 7 Table 118. Bit Descriptions for CH7_GAIN_MID_BYTE Bits [7:0] Bit Name CH7_GAIN ALL[15:8] Settings Description Combined Gain Register Channel 7 CHANNEL 7 GAIN LOWER BYTE REGISTER Address: 0x04B, Reset: 0x00, Name: CH7_GAIN_LOWER_BYTE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_GAIN ALL[7:0] (R/W) Com bined gain register Channel 7 Table 119. Bit Descriptions for CH7_GAIN_LOWER_BYTE Bits [7:0] Bit Name CH7_GAIN ALL[7:0] Settings Description Combined Gain Register Channel 7 Rev. E | Page 85 of 97 AD7770 Data Sheet CHANNEL 0 STATUS REGISTER Address: 0x04C, Reset: 0x00, Name: CH0_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH0_ERR_REF_DET (R) Channel 0 - Reference detect error [4] CH0_ERR_AINM_UV (R) AIN0- undervoltage error [1] CH0_ERR_AINP_OV (R) AIN0+ overvoltage error [3] CH0_ERR_AINM_OV (R) AIN0- overvoltage error [2] CH0_ERR_AINP_UV (R) AIN0+ undervoltage error Table 120. Bit Descriptions for CH0_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH0_ERR_AINM_UV CH0_ERR_AINM_OV CH0_ERR_AINP_UV CH0_ERR_AINP_OV CH0_ERR_REF_DET Settings Description Reserved Channel 0--AIN0- Undervoltage Error Channel 0--AIN0- Overvoltage Error Channel 0--AIN0+ Undervoltage Error Channel 0--AIN0+ Overvoltage Error Channel 0--Reference Detect Error Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R CHANNEL 1 STATUS REGISTER Address: 0x04D, Reset: 0x00, Name: CH1_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH1_ERR_AINM_UV (R) AIN1- undervoltage error [3] CH1_ERR_AINM_OV (R) AIN1- overvoltage error [0] CH1_ERR_REF_DET (R) Channel 1 - Reference detect error [1] CH1_ERR_AINP_OV (R) AIN1+ overvoltage error [2] CH1_ERR_AINP_UV (R) AIN1+ undervoltage error Table 121. Bit Descriptions for CH1_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH1_ERR_AINM_UV CH1_ERR_AINM_OV CH1_ERR_AINP_UV CH1_ERR_AINP_OV CH1_ERR_REF_DET Settings Description Reserved Channel 1--AIN1- Undervoltage Error Channel 1--AIN1- Overvoltage Error Channel 1--AIN1+ Undervoltage Error Channel 1--AIN1+ Overvoltage Error Channel 1--Reference Detect Error Rev. E | Page 86 of 97 Data Sheet AD7770 CHANNEL 2 STATUS REGISTER Address: 0x04E, Reset: 0x00, Name: CH2_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH2_ERR_REF_DET (R) Channel 2 - Reference detect error [4] CH2_ERR_AINM_UV (R) AIN2- undervoltage error [1] CH2_ERR_AINP_OV (R) AIN2+ overvoltage error [3] CH2_ERR_AINM_OV (R) AIN2- overvoltage error [2] CH2_ERR_AINP_UV (R) AIN2+ undervoltage error Table 122. Bit Descriptions for CH2_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH2_ERR_AINM_UV CH2_ERR_AINM_OV CH2_ERR_AINP_UV CH2_ERR_AINP_OV CH2_ERR_REF_DET Settings Description Reserved Channel 2--AIN2- Undervoltage Error Channel 2--AIN2- Overvoltage Error Channel 2--AIN2+ Undervoltage Error Channel 2--AIN2+ Overvoltage Error Channel 2--Reference Detect Error Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R CHANNEL 3 STATUS REGISTER Address: 0x04F, Reset: 0x00, Name: CH3_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH3_ERR_AINM_UV (R) AIN3- undervoltage error [3] CH3_ERR_AINM_OV (R) AIN3- overvoltage error [0] CH3_ERR_REF_DET (R) Channel 3 - Reference detect error [1] CH3_ERR_AINP_OV (R) AIN3+ overvoltage error [2] CH3_ERR_AINP_UV (R) AIN3+ undervoltage error Table 123. Bit Descriptions for CH3_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH3_ERR_AINM_UV CH3_ERR_AINM_OV CH3_ERR_AINP_UV CH3_ERR_AINP_OV CH3_ERR_REF_DET Settings Description Reserved Channel 3--AIN3- Undervoltage Error Channel 3--AIN3- Overvoltage Error Channel 3--AIN3+ Undervoltage Error Channel 3--AIN3+ Overvoltage Error Channel 3--Reference Detect Error Rev. E | Page 87 of 97 AD7770 Data Sheet CHANNEL 4 STATUS REGISTER Address: 0x050, Reset: 0x00, Name: CH4_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH4_ERR_REF_DET (R) Channel 4 - Reference detect error [4] CH4_ERR_AINM_UV (R) AIN4- undervoltage error [1] CH4_ERR_AINP_OV (R) AIN4+ overvoltage error [3] CH4_ERR_AINM_OV (R) AIN4- overvoltage error [2] CH4_ERR_AINP_UV (R) AIN4+ undervoltage error Table 124. Bit Descriptions for CH4_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH4_ERR_AINM_UV CH4_ERR_AINM_OV CH4_ERR_AINP_UV CH4_ERR_AINP_OV CH4_ERR_REF_DET Settings Description Reserved Channel 4--AIN4- Undervoltage Error Channel 4--AIN4- Overvoltage Error Channel 4--AIN4+ Undervoltage Error Channel 4--AIN4+ Overvoltage Error Channel 4--Reference Detect Error Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R CHANNEL 5 STATUS REGISTER Address: 0x051, Reset: 0x00, Name: CH5_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH5_ERR_AINM_UV (R) AIN5- undervoltage error [3] CH5_ERR_AINM_OV (R) AIN5- overvoltage error [0] CH5_ERR_REF_DET (R) Channel 5 - Reference detect error [1] CH5_ERR_AINP_OV (R) AIN5+ overvoltage error [2] CH5_ERR_AINP_UV (R) AIN5+ undervoltage error Table 125. Bit Descriptions for CH5_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH5_ERR_AINM_UV CH5_ERR_AINM_OV CH5_ERR_AINP_UV CH5_ERR_AINP_OV CH5_ERR_REF_DET Settings Description Reserved Channel 5--AIN5- Undervoltage Error Channel 5--AIN5- Overvoltage Error Channel 5--AIN5+ Undervoltage Error Channel 5--AIN5+ Overvoltage Error Channel 5--Reference Detect Error Rev. E | Page 88 of 97 Data Sheet AD7770 CHANNEL 6 STATUS REGISTER Address: 0x052, Reset: 0x00, Name: CH6_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] CH6_ERR_REF_DET (R) Channel 6 - Reference detect error [4] CH6_ERR_AINM_UV (R) AIN6- undervoltage error [1] CH6_ERR_AINP_OV (R) AIN6+ overvoltage error [3] CH6_ERR_AINM_OV (R) AIN6- overvoltage error [2] CH6_ERR_AINP_UV (R) AIN6+ undervoltage error Table 126. Bit Descriptions for CH6_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH6_ERR_AINM_UV CH6_ERR_AINM_OV CH6_ERR_AINP_UV CH6_ERR_AINP_OV CH6_ERR_REF_DET Settings Description Reserved Channel 6--AIN6- Undervoltage Error Channel 6--AIN6- Overvoltage Error Channel 6--AIN6+ Undervoltage Error Channel 6--AIN6+ Overvoltage Error Channel 6--Reference Detect Error Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R R R R R Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R CHANNEL 7 STATUS REGISTER Address: 0x053, Reset: 0x00, Name: CH7_ERR_REG 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] CH7_ERR_AINM_UV (R) AIN7- undervoltage error [3] CH7_ERR_AINM_OV (R) AIN7- overvoltage error [0] CH7_ERR_REF_DET (R) Channel 7 - Reference detect error [1] CH7_ERR_AINP_OV (R) AIN7+ overvoltage error [2] CH7_ERR_AINP_UV (R) AIN7+ undervoltage error Table 127. Bit Descriptions for CH7_ERR_REG Bits [7:5] 4 3 2 1 0 Bit Name RESERVED CH7_ERR_AINM_UV CH7_ERR_AINM_OV CH7_ERR_AINP_UV CH7_ERR_AINP_OV CH7_ERR_REF_DET Settings Description Reserved Channel 7--AIN7- Undervoltage Error Channel 7--AIN7- Overvoltage Error Channel 7--AIN7+ Undervoltage Error Channel 7--AIN7+ Overvoltage Error Channel 7--Reference Detect Error Rev. E | Page 89 of 97 AD7770 Data Sheet CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER Address: 0x054, Reset: 0x00, Name: CH0_1_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] CH0_ERR_OUTPUT_SAT (R) Channel 0 - ADC conversion has exceeded lim its and has been clam ped [5] CH1_ERR_MOD_SAT (R) Channel 1 - Modulator output saturation error [1] CH0_ERR_FILTER_SAT (R) Channel 0 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [4] CH1_ERR_FILTER_SAT (R) Channel 1 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH0_ERR_MOD_SAT (R) Channel 0 - Modulator output saturation error [3] CH1_ERR_OUTPUT_SAT (R) Channel 1 - ADC conversion has exceeded lim its and has been clam ped Table 128. Bit Descriptions for CH0_1_SAT_ERR Bits [7:6] 5 4 Bit Name RESERVED CH1_ERR_MOD_SAT CH1_ERR_FILTER_SAT 3 2 1 CH1_ERR_OUTPUT_SAT CH0_ERR_MOD_SAT CH0_ERR_FILTER_SAT 0 CH0_ERR_OUTPUT_SAT Settings Description Reserved Channel 1--Modulator output saturation error Channel 1--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 1--ADC conversion has exceeded limits and is clamped Channel 0--Modulator output saturation error Channel 0--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 0--ADC conversion has exceeded limits and is clamped Reset 0x0 0x0 0x0 Access R R R 0x0 0x0 0x0 R R R 0x0 R Reset 0x0 0x0 0x0 Access R R R 0x0 0x0 0x0 R R R 0x0 R CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER Address: 0x055, Reset: 0x00, Name: CH2_3_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] CH3_ERR_MOD_SAT (R) Channel 3 - Modulator output saturation error [4] CH3_ERR_FILTER_SAT (R) Channel 3 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [3] CH3_ERR_OUTPUT_SAT (R) Channel 3 - ADC conversion has exceeded lim its and has been clam ped [0] CH2_ERR_OUTPUT_SAT (R) Channel 2 - ADC conversion has exceeded lim its and has been clam ped [1] CH2_ERR_FILTER_SAT (R) Channel 2 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH2_ERR_MOD_SAT (R) Channel 2 - Modulator output saturation error Table 129. Bit Descriptions for CH2_3_SAT_ERR Bits [7:6] 5 4 Bit Name RESERVED CH3_ERR_MOD_SAT CH3_ERR_FILTER_SAT 3 2 1 CH3_ERR_OUTPUT_SAT CH2_ERR_MOD_SAT CH2_ERR_FILTER_SAT 0 CH2_ERR_OUTPUT_SAT Settings Description Reserved Channel 3--Modulator output saturation error Channel 3--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 3--ADC conversion has exceeded limits and is clamped Channel 2--Modulator output saturation error Channel 2--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 2--ADC conversion has exceeded limits and is clamped Rev. E | Page 90 of 97 Data Sheet AD7770 CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER Address: 0x056, Reset: 0x00, Name: CH4_5_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] CH4_ERR_OUTPUT_SAT (R) Channel 4 - ADC conversion has exceeded lim its and has been clam ped [5] CH5_ERR_MOD_SAT (R) Channel 5 - Modulator output saturation error [1] CH4_ERR_FILTER_SAT (R) Channel 4 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [4] CH5_ERR_FILTER_SAT (R) Channel 5 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH4_ERR_MOD_SAT (R) Channel 4 - Modulator output saturation error [3] CH5_ERR_OUTPUT_SAT (R) Channel 5 - ADC conversion has exceeded lim its and has been clam ped Table 130. Bit Descriptions for CH4_5_SAT_ERR Bits [7:6] 5 4 Bit Name RESERVED CH5_ERR_MOD_SAT CH5_ERR_FILTER_SAT 3 2 1 CH5_ERR_OUTPUT_SAT CH4_ERR_MOD_SAT CH4_ERR_FILTER_SAT 0 CH4_ERR_OUTPUT_SAT Settings Description Reserved Channel 5--Modulator output saturation error Channel 5--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 5--ADC conversion has exceeded limits and is clamped Channel 4--Modulator output saturation error Channel 4--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 4--ADC conversion has exceeded limits and is clamped Reset 0x0 0x0 0x0 Access R R R 0x0 0x0 0x0 R R R 0x0 R Reset 0x0 0x0 0x0 Access R R R 0x0 0x0 0x0 R R R 0x0 R CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER Address: 0x057, Reset: 0x00, Name: CH6_7_SAT_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] CH7_ERR_MOD_SAT (R) Channel 7 - Modulator output saturation error [4] CH7_ERR_FILTER_SAT (R) Channel 7 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [3] CH7_ERR_OUTPUT_SAT (R) Channel 7 - ADC conversion has exceeded lim its and has been clam ped [0] CH6_ERR_OUTPUT_SAT (R) Channel 6 - ADC conversion has exceeded lim its and has been clam ped [1] CH6_ERR_FILTER_SAT (R) Channel 6 - Filter result has exceeded a reasonable level, before offset and gain calibration has been applied. [2] CH6_ERR_MOD_SAT (R) Channel 6 - Modulator output saturation error Table 131. Bit descriptions for CH6_7_SAT_ERR Bits [7:6] 5 4 Bit Name RESERVED CH7_ERR_MOD_SAT CH7_ERR_FILTER_SAT 3 2 1 CH7_ERR_OUTPUT_SAT CH6_ERR_MOD_SAT CH6_ERR_FILTER_SAT 0 CH6_ERR_OUTPUT_SAT Settings Description Reserved Channel 7--Modulator output saturation error Channel 7--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 7--ADC conversion has exceeded limits and is clamped Channel 6--Modulator output saturation error Channel 6--Filter result has exceeded a reasonable level, before offset and gain calibration are applied Channel 6--ADC conversion has exceeded limits and is clamped Rev. E | Page 91 of 97 AD7770 Data Sheet CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER Address: 0x058, Reset: 0xFE, Name: CHX_ERR_REG_EN 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 0 [7] OUTPUT_SAT_TEST_EN (R/W) ADC conversion error test enable [0] REF_DET_TEST_EN (R/W) Reference detect test enable [6] FILTER_SAT_TEST_EN (R/W) Filter saturation error test enable [1] AINP_OV_TEST_EN (R/W) AINx+ overvoltage test enable [5] MOD_SAT_TEST_EN (R/W) Enable error flag for Modulator saturation [2] AINP_UV_TEST_EN (R/W) AINx+ undervoltage test enable [4] AINM_UV_TEST_EN (R/W) AINx- undervoltage test enable [3] AINM_OV_TEST_EN (R/W) AINx- overvoltage test enable Table 132. Bit Descriptions for CHX_ERR_REG_EN Bits 7 6 5 4 3 2 1 0 Bit Name OUTPUT_SAT_TEST_EN FILTER_SAT_TEST_EN MOD_SAT_TEST_EN AINM_UV_TEST_EN AINM_OV_TEST_EN AINP_UV_TEST_EN AINP_OV_TEST_EN REF_DET_TEST_EN Settings Description ADC Conversion Error Test Enable Filter Saturation Test Enable Enable Error Flag for Modulator Saturation AINx- Undervoltage Test Enable AINx- Overvoltage Test Enable AINx+ Undervoltage Test Enable AINx+ Overvoltage Test Enable Reference Detect Test Enable Reset 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W GENERAL ERRORS REGISTER 1 Address: 0x059, Reset: 0x00, Name: GEN_ERR_REG_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] MEMMAP_CRC_ERR (R) A CRC of the memory map contents is run periodically to check for errors [4] ROM_CRC_ERR (R) A CRC of the fuse contents is run periodically to check for errors in the fuses [0] SPI_CRC_ERR (R) SPI CRC error [1] SPI_INVALID_WRITE_ERR (R) SPI invalid write address [2] SPI_INVALID_READ_ERR (R) SPI invalid read address [3] SPI_CLK_COUNT_ERR (R) SPI clock counter error Table 133. Bit Descriptions for GEN_ERR_REG_1 Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED MEMMAP_CRC_ERR ROM_CRC_ERR SPI_CLK_COUNT_ERR SPI_INVALID_READ_ERR SPI_INVALID_WRITE_ERR SPI_CRC_ERR Settings Description Reserved A CRC of the memory map contents is run periodically to check for errors A CRC of the fuse contents is run periodically to check for errors in the fuses SPI clock counter error SPI invalid read address SPI invalid write address SPI CRC error Rev. E | Page 92 of 97 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R Data Sheet AD7770 GENERAL ERRORS REGISTER 1 ENABLE Address: 0x05A, Reset: 0x3E, Name: GEN_ERR_REG_1_EN Table 134. Bit Descriptions for GEN_ERR_REG_1_EN Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED MEMMAP_CRC_TEST_EN ROM_CRC_TEST_EN SPI_CLK_COUNT_TEST_EN SPI_INVALID_READ_TEST_EN SPI_INVALID_WRITE_TEST_EN SPI_CRC_TEST_EN Settings Description Reserved Memory Map CRC Error Enable Fuse CRC Test Enable SPI Clock Counter Test Enable SPI Invalid Read Address Test Enable SPI Invalid Write Address Test Enable SPI CRC Error Test Enable Reset 0x0 0x1 0x1 0x1 0x1 0x1 0x0 Access R R/W R/W R/W R/W R/W R/W Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R GENERAL ERRORS REGISTER 2 Address: 0x05B, Reset: 0x00, Name: GEN_ERR_REG_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] DLDO_PSM_ERR (R) DRegCap power supply error [5] RESET_DETECTED (R) Res et detected [4] EXT_MCLK_SWITCH_ERR (R) Clock not switched over [3] RESERVED [1] ALDO2_PSM_ERR (R) AReg2Cap power supply error [2] ALDO1_PSM_ERR (R) AReg1Cap power supply error Table 135. Bit Descriptions for GEN_ERR_REG_2 Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED RESET_DETECTED EXT_MCLK_SWITCH_ERR RESERVED ALDO1_PSM_ERR ALDO2_PSM_ERR DLDO_PSM_ERR Settings Description Reserved Reset Detected Clock Not Switched Over Reserved AREG1CAP Power Supply Error AREG2CAP Power Supply Error DREGCAP Power Supply Error Rev. E | Page 93 of 97 AD7770 Data Sheet GENERAL ERRORS REGISTER 2 ENABLE Address: 0x05C, Reset: 0x3C, Name: GEN_ERR_REG_2_EN 7 6 5 4 3 2 1 0 0 0 1 0 1 1 0 0 [7:6] RESERVED [1:0] LDO_PSM_TRIP_TEST_EN (R/W) LDO PSM trip test enable 0: 00 - No trip detect test enabled. 1: 01 - Run trip detect test on AReg1Cap. 10: 10 - Run trip detect test on AReg2Cap. 11: 11 - Run trip detect test on DRegCap. [5] RESET_DETECT_EN (R/W) Reset detect enable [4] RESERVED [3:2] LDO_PSM_test_EN (R/W) LDO PSM test EN 0: 00 - No power supply monitor test enabled. 1: 01 - Run power supply monitor test on ARegxCap. 10: 10 - Run power supply monitor test on DRegCap. 11: 11 - Run power supply monitor test on all LDOs. Table 136. Bit Descriptions for GEN_ERR_REG_2_EN Bits [7:6] 5 4 [3:2] Bit Name RESERVED RESET_DETECT_EN RESERVED LDO_PSM_TEST_EN Settings 0 1 10 11 [1:0] LDO_PSM_TRIP_TEST_EN 0 1 10 11 Description Reserved Reset Detect Enable Reserved LDO PSM Test EN 00--no power supply monitor test enabled 01--run power supply monitor test on AREGxCAP 10--run power supply monitor test on DREGCAP 11--run power supply monitor test on all LDOs LDO PSM Trip Test Enable 00--no trip detect test enabled 01--run trip detect test on AREG1CAP 10--run trip detect test on AREG2CAP 11--run trip detect test on DREGCAP Reset 0x0 0x1 0x1 0x3 Access R R/W R/W R/W 0x0 R/W Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R ERROR STATUS REGISTER 1 Address: 0x05D, Reset: 0x00, Name: STATUS_REG_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_CH0 (R) An error specific to CH0_ERR_REG is active [5] CHIP_ERROR (R) Set high if any error bit is high [4] ERR_LOC_CH4 (R) An error specific to CH4_ERR_REG is active [3] ERR_LOC_CH3 (R) An error specific to CH3_ERR_REG is active [1] ERR_LOC_CH1 (R) An error specific to CH1_ERR_REG is active [2] ERR_LOC_CH2 (R) An error specific to CH2_ERR_REG is active Table 137. Bit Descriptions for STATUS_REG_1 Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED CHIP_ERROR ERR_LOC_CH4 ERR_LOC_CH3 ERR_LOC_CH2 ERR_LOC_CH1 ERR_LOC_CH0 Settings Description Reserved Set this bit high if any error bit is high An error specific to CH4_ERR_REG is active An error specific to CH3_ERR_REG is active An error specific to CH2_ERR_REG is active An error specific to CH1_ERR_REG is active An error specific to CH0_ERR_REG is active Rev. E | Page 94 of 97 Data Sheet AD7770 ERROR STATUS REGISTER 2 Address: 0x05E, Reset: 0x00, Name: STATUS_REG_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_CH5 (R) An error specific to CH5_ERR_REG is active [5] CHIP_ERROR (R) Set high if any error bit is high [1] ERR_LOC_CH6 (R) An error specific to CH6_ERR_REG is active [4] ERR_LOC_GEN2 (R) An error specific to GEN_ERR_REG_2 is active [2] ERR_LOC_CH7 (R) An error specific to CH7_ERR_REG is active [3] ERR_LOC_GEN1 (R) An error specific to GEN_ERR_REG_1 is active Table 138. Bit Descriptions for STATUS_REG_2 Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED CHIP_ERROR ERR_LOC_GEN2 ERR_LOC_GEN1 ERR_LOC_CH7 ERR_LOC_CH6 ERR_LOC_CH5 Settings Description Reserved Set high if any error bit is high An error specific to GEN_ERR_REG_2 is active An error specific to GEN_ERR_REG_1 is active An error specific to CH7_ERR_REG is active An error specific to CH6_ERR_REG is active An error specific to CH5_ERR_REG is active Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R ERROR STATUS REGISTER 3 Address: 0x05F, Reset: 0x00, Name: STATUS_REG_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [0] ERR_LOC_SAT_CH0_1 (R) An error specific to CH0_1_SAT_ERR reg is active [5] CHIP_ERROR (R) Set high if any error bit is high [1] ERR_LOC_SAT_CH2_3 (R) An error specific to CH2_3_SAT_ERR reg is active [4] INIT_COMPLETE (R) Fuse initialization is com plete. Device is ready to receive commands [2] ERR_LOC_SAT_CH4_5 (R) An error specific to CH4_5_SAT_ERR reg is active [3] ERR_LOC_SAT_CH6_7 (R) An error specific to CH6_7_SAT_ERR reg is active Table 139. Bit Descriptions for STATUS_REG_3 Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED CHIP_ERROR INIT_COMPLETE ERR_LOC_SAT_CH6_7 ERR_LOC_SAT_CH4_5 ERR_LOC_SAT_CH2_3 ERR_LOC_SAT_CH0_1 Settings Description Reserved Set high if any error bit is high. Fuse initialization is complete. Device is ready to receive commands. An error specific to CH6_7_SAT_ERR register is active. An error specific to CH4_5_SAT_ERR register is active. An error specific to CH2_3_SAT_ERR register is active. An error specific to CH0_1_SAT_ERR register is active. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R DECIMATION RATE (N) MSB REGISTER Address: 0x060, Reset: 0x00, Name: SRC_N_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3:0] SRC_N_ALL[11:8] (R/W) SRC N Com bined Table 140. Bit Descriptions for SRC_N_MSB Bits [7:4] [3:0] Bit Name RESERVED SRC_N_ALL[11:8] Settings Description Reserved SRC N Combined Reset 0x0 0x0 Rev. E | Page 95 of 97 Access R R/W AD7770 Data Sheet DECIMATION RATE (N) LSB REGISTER Address: 0x061, Reset: 0x80, Name: SRC_N_LSB 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] SRC_N_ALL[7:0] (R/W) SRC N Combined Table 141. Bit Descriptions for SRC_N_LSB Bits [7:0] Bit Name SRC_N_ALL[7:0] Settings Description SRC N Combined Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 0x0 0x0 Access R/W R R/W DECIMATION RATE (IF) MSB REGISTER Address: 0x062, Reset: 0x00, Name: SRC_IF_MSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SRC_IF_ALL[15:8] (R/W) SRC IF ALL Table 142. Bit Descriptions for SRC_IF_MSB Bits [7:0] Bit Name SRC_IF_ALL[15:8] Settings Description SRC IF All DECIMATION RATE (IF) LSB REGISTER Address: 0x063, Reset: 0x00, Name: SRC_IF_LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] SRC_IF_ALL[7:0] (R/W) SRC IF ALL Table 143. Bit Descriptions for SRC_IF_LSB Bits [7:0] Bit Name SRC_IF_ALL[7:0] Settings Description SRC IF All SRC LOAD SOURCE AND LOAD UPDATE REGISTER Address: 0x064, Reset: 0x00, Name: SRC_UPDATE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SRC_LOAD_SOURCE (R/W) Select which option to load an SRC update [0] SRC_LOAD_UPDATE (R/W) Ass ert bit to load SRC registers into SRC [6:1] RESERVED Table 144. Bit Descriptions for SRC_UPDATE Bits 7 [6:1] 0 Bit Name SRC_LOAD_SOURCE RESERVED SRC_LOAD_UPDATE Settings Description Selects which option to load an SRC update Reserved Asserts bit to load SRC registers into SRC Rev. E | Page 96 of 97 Data Sheet AD7770 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 9.10 9.00 SQ 8.90 0.30 0.25 0.18 49 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 64 1 48 0.50 BSC 7.70 7.60 SQ 7.50 EXPOSED PAD 33 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004396 SEATING PLANE 0.45 0.40 0.35 16 32 17 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 04-10-2017-A PIN 1 INDICATOR Figure 122. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body and 0.75 mm Package Height (CP-64-15) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7770ACPZ AD7770ACPZ-RL EVAL-AD7770FMCZ EVAL-SDP-CH1Z 1 Temperature Range -40C to +125C -40C to +125C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board SDP Controller Board Z = RoHS Compliant Part. (c)2016-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12538-5/20(E) Rev. E | Page 97 of 97 Package Option CP-64-15 CP-64-15