Page 1 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
PE42542
UltraCMOS® SP4T RF Switch
9 kHz–18 GHz
Product Specification
Features
HaRP technology enhanced
Fast settling time
No gate and phase lag
No drift in insertion loss and phase
Low insertion loss
1.10 dB @ 3 GHz
2.10 dB @ 13.5 GHz
2.50 dB @ 16 GHz
3.10 dB @ 18 GHz
High isolation
55 dB @ 3 GHz
33 dB @ 13.5 GHz
29 dB @ 16 GHz
26 dB @ 18 GHz
ESD performance
3500V HBM on all pins
150V MM on all pins
500V CDM on all pins
Product Description
The PE42542 is a HaRP™ technology-enhanced
absorptive SP4T RF switch designed for use in Test/
ATE, microwave and other wireless applications. This
broadband general purpose switch maintains excellent
RF performance and linearity from 9 kHz through
18 GHz. The PE42542 exhibits low insertion loss,
high isolation performance and has fast settling time.
No blocking capacitors are required if DC voltage is
not present on the RF ports.
The PE42542 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate.
Peregrine’s HaRP technology enhancements deliver high
linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
Figure 1. Functional Diagram
Figure 2. Package Type
29-lead 4 4 mm LGA
DOC-62642
Product Specification
PE42542
Page 2 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Electrical Specifications @ 25°C (ZS = ZL = 50Ω), unless otherwise noted
Normal Mode1: VDD = 3.3V, VSS_EXT = 0V or Bypass Mode2: VDD = 3.4V, VSS_EXT = –3.4V
Parameter Path Condition Min Typ Max Unit
Operating frequency 9 k 18 G Hz
Insertion loss RFC–RFX
9 kHz–10 MHz
10–3000 MHz
3000–7500 MHz
7500–10000 MHz
10000–13500 MHz
13500–16000 MHz
16000–18000 MHz
0.70
1.10
1.50
1.75
2.10
2.50
3.10
0.90
1.40
1.95
2.20
2.40
2.80
4.10
dB
dB
dB
dB
dB
dB
dB
Isolation RFX–RFX
9 kHz–10 MHz
10–3000 MHz
3000–7500 MHz
7500–10000 MHz
10000–13500 MHz
13500–16000 MHz
16000–18000 MHz
80
53
46
42
35
30
26
90
55
48
44
37
31
27
dB
dB
dB
dB
dB
dB
dB
Isolation RFC–RFX
9 kHz–10 MHz
10–3000 MHz
3000–7500 MHz
7500–10000 MHz
10000–13500 MHz
13500–16000 MHz
16000–18000 MHz
80
54
41
36
31
27
24
90
55
42
38
33
29
26
dB
dB
dB
dB
dB
dB
dB
Return loss
(active and common port) RFC–RFX 9 kHz–10 MHz
10–3000 MHz
3000–18000 MHz 25
15
13 dB
dB
dB
Return loss
(terminated port) RFX 9 kHz–18000 MHz 16 dB
Input 0.1dB compression point3 RFC–RFX Fig. 4 dBm
Input IP2 RFC–RFX 10–18000 MHz 118 dBm
Input IP3 RFC–RFX 10–18000 MHz 58 dBm
Settling time 50% CTRL to 0.05 dB final value 7 10 µs
Switching time 50% CTRL to 90% or 10% of final value 3 4.5 µs
Notes: 1. Normal mode: connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to enable internal negative voltage generator.
2. Bypass mode: use VSS_EXT (pin 29) to bypass and disable internal negative voltage generator.
3. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PMAX (50Ω).
Product Specification
PE42542
Page 3 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 3. Pin Configuration (Top View)
Pin # Pin
Name Description
1, 3–6, 8–11,
13–16,
18–21, 23,
25, 26
GND Ground
2 RF21 RF port 2
7 RF41 RF port 4
12 RFC1 RF common
17 RF31 RF port 3
22 RF11 RF port 1
24 VDD Supply voltage (nominal 3.3V)
27 V2 Digital control logic input 2
28 V1 Digital control logic input 1
29 VSS_EXT 2 External VSS negative voltage control
Pad GND Exposed pad: Ground for proper operation
Table 2. Pin Descriptions
Notes: 1. RF pins 2, 7, 12, 17, and 22 must be at 0 VDC. The RF pins do not
require DC blocking capacitors for proper operation if the 0 VDC
requirement is met.
2. Use
VSS_EXT (pin 29) to bypass and disable internal negative voltage
generator. Connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to enable
internal negative voltage generator.
Table 3. Operating Ranges
Parameter Symbol Min Typ Max Unit
Normal mode1 (VSS_EXT = 0V)
Supply voltage VDD 2.3 5.5 V
Supply current IDD 120 200 uA
Bypass mode2 (VSS_EXT = –3.4V)
Supply voltage
(VDD ≥ 3.4V for Table 1
full spec. compliance) VDD 2.7 3.4 5.5 V
Supply current IDD 50 80 uA
Negative supply voltage VSS_EXT –3.6 –3.2 V
Negative supply current ISS –40 –16 uA
Normal or Bypass mode
Digital input high
(V1, V2) VIH 1.17 3.6 V
Digital input low
(V1, V2) VIL –0.3 0.6 V
RF input power, CW
(RFC–RFX)3
9 kHz–2.9 MHz
≥ 2.9 MHz–18 GHz
PMAX,CW
Fig. 4
30
dBm
dBm
RF input power, pulsed
(RFC–RFX)4
9 kHz–2.9 MHz
≥ 2.9 MHz–18 GHz
PMAX,PULSED
Fig. 4
32
dBm
dBm
RF input power into
terminated ports, CW
(RFX)3
9 kHz–1.4 MHz
≥ 1.4 MHz–18 GHz
PMAX,TERM
Fig. 4
20
dBm
dBm
Operating temperature
range TOP –40 +25 +85 °C
Notes: 1. Normal mode: connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to
enable internal negative voltage generator
2. Bypass mode: use VSS_EXT (pin 29) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50Ω
4. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
Product Specification
PE42542
Page 4 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Switching Frequency
The PE42542 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 29 = GND). Switching frequency
describes the time duration between switching
events. Switching time is the duration between
the point the control signal reaches 50% of the
final value and the point the output signal reaches
within 10% or 90% of its target value.
Table 5. Truth Table
State V1 V2
RF1 on 0 0
RF2 on 1 0
RF3 on 0 1
RF4 on 1 1
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42542 in the 29-lead 4 4 mm LGA package is
MSL3.
Optional External VSS Control (VSS_EXT)
For proper operation, the VSS_EXT control pin must
be grounded or tied to the VSS voltage specified in
Table 3. When the VSS_EXT control pin is
grounded, FETs in the switch are biased with an
internal negative voltage generator. For
applications that require the lowest possible spur
performance, VSS_EXT can be applied externally to
bypass the internal negative voltage generator.
Table 4. Absolute Maximum Ratings
Parameter/Condition Symbol Min Max Unit
Supply voltage VDD –0.3 5.5 V
Digital input voltage (V1, V2) VCTRL –0.3 3.6 V
RF input power, CW
(RFC-RFX)1
9 kHz–2.9 MHz
≥ 2.9 MHz–18 GHz
PMAX,CW
Fig. 4
33
dBm
dBm
RF input power, pulsed
(RFC-RFX)2
9 kHz–2.9 MHz
≥ 2.9 MHz–18 GHz
PMAX,PULSED
Fig. 4
34
dBm
dBm
RF input power into
terminated ports, CW (RFX)1
9 kHz–1.4 MHz
≥ 1.4 MHz–18 GHz
PMAX,TERM
Fig. 4
22
dBm
dBm
Storage temperature range TST –65 +150 °C
ESD voltage HBM,3 all pins VESD,HBM 3500 V
ESD voltage MM4, all pins VESD,MM 150 V
ESD voltage CDM5, all pins V ESD,CDM 500 V
Notes: 1. 100% duty cycle, all bands, 50Ω
2. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
3. Human Body Model (MIL_STD 883 Method 3015)
4. Machine Model (JEDEC JESD22-A115)
5. Charged Device Model (JEDEC JESD22-C101)
Spurious Performance
The typical spurious performance of the PE42542
is –150 dBm when VSS_EXT = 0V (pin 29 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting VSS_EXT = –3.4V.
Hot Switching
The maximum hot switching capability of the
PE42542 is 20 dBm from 1.4 MHz to 18 GHz. The
maximum hot switching capability below 1.4 MHz
does not exceed the maximum RF CW terminated
power, see Figure 4. Hot switching occurs when
RF power is applied while switching between RF
ports.
Product Specification
PE42542
Page 5 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
‐5
0
5
10
15
20
25
30
35
InputPower(dBm)
Frequency(MHz)
P0.1dBCompression@25°CAmbient
Max.RFInputPower,Pulsed(≥2.7MHz,25°CAmbient)
Max.RFInputPower,CW(≥2.7MHz,25°CAmbient)
Max.RFInputPower,CW&Pulsed(<2.7MHz,25°CAmbient)
Max.RFTerminatedPower,CW@25°CAmbient
‐5
0
5
10
15
20
25
30
35
InputPower(dBm)
Frequency(MHz)
P0.1dBCompression@85°CAmbient
Max.RFInputPower,Pulsed(≥2.9MHz,85°CAmbient)
Max.RFInputPower,CW(≥2.9MHz,85°CAmbient)
Max.RFInputPower,CW&Pulsed(<2.9MHz,85°CAmbient)
Max.RFTerminatedPower,CW@85°CAmbient
Figure 4a. Power De-rating Curve for 9 kHz–18 GHz @ 25°C Ambient (50Ω)
Figure 4b. Power De-rating Curve for 9 kHz–18 GHz @ 85°C Ambient (50Ω)
Product Specification
PE42542
Page 6 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V (ZS = ZL = 50Ω), unless otherwise noted
Figure 5. Insertion Loss (RFC–RFX)
Figure 6. Insertion Loss vs. Temp (RFC–RFX) Figure 7. Insertion Loss vs. VDD (RFC–RFX)
Product Specification
PE42542
Page 7 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V (ZS = ZL = 50Ω), unless otherwise noted
Figure 10. Active Port Return Loss vs. Temp
Figure 8. RFC Port Return Loss vs. Temp Figure 9. RFC Port Return Loss vs. VDD
Figure 11. Active Port Return Loss vs. VDD
Product Specification
PE42542
Page 8 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V (ZS = ZL = 50Ω), unless otherwise noted
Figure 12. Terminated Port Return Loss vs. Temp Figure 13. Terminated Port Return Loss vs. VDD
Product Specification
PE42542
Page 9 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V (ZS = ZL = 50Ω), unless otherwise noted
Figure 14. Isolation vs. Temp (RFX–RFX)* Figure 15. Isolation vs. VDD (RFX–RFX)*
Note: * RF1 adjacent to RF3
RF2 adjacent to RF4
RF1 and RF3 opposite to RF2 and RF4
Figure 14. Isolation vs. Temp (RFX–RFX)* Figure 15. Isolation vs. VDD (RFX–RFX)* Figure 14. Isolation vs. Temp (RFX–RFX)*
Product Specification
PE42542
Page 10 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Typical Performance Data @ 25°C and VDD = 3.3V (ZS = ZL = 50Ω), unless otherwise noted
Figure 16. Isolation vs. Temp
(RFC–RFX, RF1 or RF2 Active)* Figure 17. Isolation vs. VDD
(RFC–RFX, RF1 or RF2 Active)*
Figure 18. Isolation vs. Temp
(RFC–RFX, RF3 or RF4 Active)* Figure 19. Isolation vs. VDD
(RFC–RFX, RF3 or RF4 Active)*
Note: * RF1 adjacent to RF3
RF2 adjacent to RF4
RF1 and RF3 opposite to RF2 and RF4
Product Specification
PE42542
Page 11 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The SP4T switch evaluation board was designed
to ease customer evaluation of Peregrine’s
PE42542. The RF common port is connected
through a 50Ω transmission line via the SMA
connector, J1. RF1, RF2, RF3 and RF4 ports are
connected through 50Ω transmission lines via
SMA connectors J4, J3, J2 and J5, respectively.
A 50Ω through transmission line is available via
SMA connectors J6 and J7, which can be used to
de-embed the loss of the PCB. J13 provides DC
and digital inputs to the device.
The board is constructed of a four metal layer
material with a total thickness of 62 mils. The top
RF layer is Rogers 4360 material with a thickness
of 32 mils and the r = 6.4. The middle layers
provide ground for the transmission lines. The
transmission lines were designed using a
coplanar waveguide with ground plane model
using a trace width of 18 mils, trace gaps of 7 mils
and metal thickness of 2.1 mils.
For the true performance of the PE42542 to be
realized, the PCB should be designed in such a
way that RF transmission lines and sensitive DC
I/O traces are heavily isolated from one another.
High frequency insertion loss and return loss can
be further improved by external series inductive
tuning traces in the customer application board
layout. For example, to improve 12–18 GHz
performance, use ~180 pH for RFX ports and
~50 pH for RFC port.
Vector de-embed is recommended to more
accurately calculate the performance of the
DUT. Refer to Application Note 39 “Vector De-
embedding of the PE42542 and PE42543 SP4T
RF Switches” for additional information. The half
thru line data file can be downloaded from
Peregrine’s website to facilitate the vector de-
embedding.
Figure 20. Evaluation Board Layout
PRT-09205
Product Specification
PE42542
Page 12 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Figure 21. Evaluation Board Schematic
DOC-12227
THRU
50 OHM
50 OHM
50 OHM
50 OHM
50 OHM 50 OHM
C3
DNI
C7
DNI
C4
DNI
11
33
55
77
2
24
46
68
810
10 12
12 14
14
13 13
99
11 11
J13
C5
DNI
C6
DNI
R5
DNI
R8
0OHM
J
1
J
3
J2
J4
J
5J7 J6
1GND
2RF2
3GND
4GND
5GND
6GND
7RF4
8GND
9GND
10 GND
11 GND
12 RFC
13 GND
14 GND
15 GND
16
GND 17
RF3 18
GND 19
GND 20
GND 21
GND 22
RF1 23
GND
24
VDD 25
DGND 26
TMGND
27
V2 28
V1 29
VSS
30 GND
31 GND
32 GND
33 GND
U1
PE42542
R7
0OHM
R6
DNI
R1
DNI
R2
DNI
R3
DNI
R4
DNI
VDD
CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD).
Product Specification
PE42542
Page 13 of 14
Document No. DOC-12214-4 │www.psemi.com ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
TOP VIEW BOTTOM VIEW
SIDE VIEW
RECOMMENDED LAND PATTERN
A
(2X)
C
SEATING PLANE
B
(2X)
PIN #1 CORNER 4.00
4.00
1.13
(x4) 1.13
(x4)
0.40
0.4684
0.4284
0.4646
0.4948
0.10
(x29)
0.4484
0.70±0.05
0.20 x45°
Chamfer
1.13 1.13
0.26x0.30
(x6)
0.33x0.34
(x18)
0.30x0.30
(x5)
0.40
3.80
3.80
0.24
(x4)
0.24
(x4)
(x5)
0.4284
0.4684
0.4684
0.4484
Note:
- Dimensions con ce rning Pad pitch are all
mirrored across the Y-axis
0.91±0.10
0.4484
0.4484
0.4684
0.4284
0.4484
0.24
(x4)
0.24
(x4)
0.4284
0.4684
0.4684
0.4484
0.4484
0.4484
Figure 22. Package Drawing
29-lead 4 4 mm LGA
DOC-50743
Figure 23. Top Marking Specification
42542
YYWW
ZZZZZ
DOC-51207-2
= Pin 1 designator
YYWW = Date code, last two digits of assembly year and work week
ZZZZZ = Last five characters of the assembly lot code
Product Specification
PE42542
Page 14 of 14
Document No. DOC-12214-4 │ UltraCMOS® RFIC Solutions ©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 6. Ordering Information
Order Code Description Package Shipping Method
PE42542A-X PE42542 SP4T RF switch 29-lead 4 4 mm LGA 500 units / T&R
EK42542-02 PE42542 Evaluation kit Evaluation kit 1 / Box
Advance Information:
The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification:
The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product.
Product Specification:
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The informatio n in this datasheet i s believed to b e reliable. Ho wever, Peregrin e assume s no liability for the us e
of this inf o r m ati o n. U s e s hal l b e ent i rel y at th e u se r’ s o w n ri sk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
followi n g U. S. P at e nt s: http://patents.psemi.com.
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Figure 24. Tape and Reel Drawing
