December 2007 Rev 3 1/61
1
SMSxxxAF
SMSxxxFF, SMSxxxBF
64 MByte, 128 MByte, 256 MByte
512 MByte and 1 GByte, 3.3V Supply Secure Digital™ Card
Features
■SD Memory Card Specification Version 1.01-
compliant
■Up to 1 Gbyte of Formatted Data Storage
■Bus Mode
– SD Protocol (1 to 4 Data Lines)
– SPI Protocol
■Operating Voltage Range:
– Basic Communication (CMD0, CMD15,
CMD55 and ACMD41): 2.0V to 3.6V
– O t h e r C o m m a n d s a n d M e m o r y A c c e s s :
2.7V to 3.6V
■Variable Clock Rate: 0 to 25 MHz
■Read Access (using 4 Data Lines)
– Sustained Multiple Block: 6.3 Mb/s
■Write Access (using 4 Data Lines)
– Sustained Multiple Block: 3.0 Mb/s
■Maximum Data Rate with up to 10 Cards
■Aimed at Portable and Stationary Applications
■Communication Channel Protocol Attributes:
– Six-wire communication channel (clock,
command, 4 data lines)
– Error-proof data transfer
– Single or Multiple block oriented data
transfer
■Memory Field Error Correction
■Safe Card Removal during Read
■Write Protect Feature using Mechanical Switch
■Built-in Write Protection Features (Permanent
and Temporary)
■SD, MiniSD and MicroSD Packages
– ECOPACK® compliant
– Halogen free
– Antimony free
SD
miniSD
SD Secure Digital
MiniSD MicroSD
Table 1. Device summary
Part Number Package Form Factor Operating Voltage Range
SMS128AF
SD (full size)
2.7V to 3.6V
SMS256AF
SMS512AF
SMS01GAF
SMS064BF MiniSD
SMS128BF
SMS064FF
MicroSD
SMS128FF
SMS256FF
SMS512FF
www.numonyx.com
Contents SMSxxxAF, SMSxxxFF, SMSxxxBF
2/61
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Secure digital memory card interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Secure digital memory card bus topology . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 SD bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 SD Memory Card Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Card Identification Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 SD memory card hardware interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 SD memory card bus circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Hot Insertion/Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Power Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Card registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 OCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 CID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 CSD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4 RCA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 DSR Register (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6 SCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Command and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1 Card Identification and Operating Conditions Timings . . . . . . . . . . . . . 35
6.1.2 Card Relative Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SMSxxxAF, SMSxxxFF, SMSxxxBF Contents
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6.1.3 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4 Last Card Response, Next Host Command Timings . . . . . . . . . . . . . . . 36
6.1.5 Last Host Command, Next Host Command Timings . . . . . . . . . . . . . . . 37
6.2 Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.1 Single Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.2 Multiple Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1 Single Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.2 Multiple Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4 STOP_TRANSMISSION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4.1 Erase, Set and Clear Write Protect Timings . . . . . . . . . . . . . . . . . . . . . 41
6.4.2 Re-selecting a busy card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.5 Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Serial peripheral interface (SPI) mode . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 SPI bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 SPI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.2 Bus Transfer Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.3 Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.4 Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.5 Erase & Write Protect Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.6 Read CID/CSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.7 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.8 Memory Array Partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.9 Card Lock/Unlock Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.10 Application Specific Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3 SPI Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4 Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.4.1 R1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.4.2 R1b Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.4.3 R2 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.4.4 R3 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.5 Clearing Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6 SPI Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.1 Data Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Contents SMSxxxAF, SMSxxxFF, SMSxxxBF
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7.6.2 Data Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Appendix A Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SMSxxxAF, SMSxxxFF, SMSxxxBF List of tables
5/61
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. System reliability and maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Memory array structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Full-size SD Memory Card pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. MicroSD Contact Pad Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Card States vs. Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. SD Card Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Response R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Response R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Response R3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Response R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. Bus Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. Bus Signal Condition - I/O Signal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Bus Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. SD Memory Card Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. OCR Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. CID Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22. CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11 . . . . . . . . 33
Table 23. SCR Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24. Timing Diagram Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 26. Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Command Classes in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. SPI Timing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 29. SPI Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 30. Full-Size Secure Digital Memory Card Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. MiniSD package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. MicroSD package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 33. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
List of figures SMSxxxAF, SMSxxxFF, SMSxxxBF
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List of figures
Figure 1. Write Protection hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Full size Secure Digital Memory Card form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. MicroSD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Secure Digital Memory Card system bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. "No Response" and "No Data" operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. (Multiple) Block Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. (Multiple) Block Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Command Token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. response token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Data Packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. SD Memory Card State Diagram (Card Identification Mode) . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. SD Memory Card State Diagram (Data Transfer Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Full Size SD Memory Card Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Power-Up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Bus Signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Data Input/Output Timings Referenced to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Identification Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SEND_RELATIVE_ADDRESS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Response (Data Transfer Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Response End To Next CMD Start (Data Transfer Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Command Sequence (All Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Single Block Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. Multiple Block Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. STOP_TRANSMISSION Command (CMD12, Data Transfer Mode) . . . . . . . . . . . . . . . . . 38
Figure 25. Block Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26. Multiple Block Write Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 27. STOP_TRANSMISSION During Data Transfer From The Host . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. STOP_TRANSMISSION During CRC Status Transfer From Card. . . . . . . . . . . . . . . . . . . 40
Figure 29. STOP_TRANSMISSION Received After Last Data Block with Card Busy . Programming40
Figure 30. STOP_TRANSMISSION Received After Last Data Block with Card Idle . . . . . . . . . . . . . . 41
Figure 31. SD Memory Card System SPI Mode Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32. Read Operation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 33. Multiple Block Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 34. Read Data Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 35. Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 36. Erase & Write Protect Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 37. Host Command to Card Response - Card is Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 38. Host Command to Card Response - Card is Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 39. Card Response to Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 40. Single Block Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 41. STOP_TRANSMISSION between Blocks During Multiple Block Read . . . . . . . . . . . . . . . 50
Figure 42. STOP_TRANSMISSION within a Block During Multiple Block Read . . . . . . . . . . . . . . . . 51
Figure 43. CSD Register Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 44. Single Block Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 45. Multiple Block Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 46. Full-Size Secure Digital Memory Card Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 47. mini Secure Digital Card Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 48. MicroSD card mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Description SMSxxxAF, SMSxxxFF, SMSxxxBF
8/61
1 Description
The Secure Digital Memory Card (SD Memory Card) is a Flash-Based Memory Card. It is
specifically designed to meet the security, capacity, performance and environmental
requirements of the latest-generation audio and video consumer electronic devices, that is
mobile phones, digital cameras, digital recorders, PDAs, organizers, electronic toys, etc.
The Secure Digital Memory Card is a high-mobility, high-performance, low-cost and low-
power consumption device that features high data throughput at the memory card interface.
It includes a copyright protection mechanism that complies with the security of the SDMI
(Secure Digital Music Initiative) standard. The Secure Digital Memory Card security system
uses mutual authentication and a “cipher algorithm” that protects the card from illegal use.
Unsecured access to the user's personal content is also available.
The Secure Digital Memory Cards have an advanced communication interface designed to
operate in a low voltage range. The full-size Secure Digital Memory Card has a 9-pin
interface whereas the Mini Secure Digital Memory Card has a 11-pin interface but can be
fitted with a 9-pin adapter. Only the 9-pin interface is described in this document. The
MicroSD Memory Card has an 8-pin interface, and can also be fitted with a 9-pin adapter.
Ta bl e 2 , Ta b l e 3 , Ta b l e 4 , Ta bl e 5 , and Ta b l e 6 give an overview of the Secure Digital
Memory Card features.
In order to meet environmental requirements, the devices are offered in ECOPACK®
packages. ECOPACK packages are Lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
The SD, MiniSD and MicroSD packages are also Halogen free and Antimony free.
Related documentation
●Secure Digital Memory Card Specifications: Part 1 Physical Layer Specification,
Version 1.01
●MiniSd Memory Card Specifications: Addendum to SD Memory Card Specifications
Part 1 Physical layer Specification, Version 1.02
●MicroSD Memory Card Specifications: Addendum to SD Memory Card Specifications
Part 1, Physical Layer Specification, Version 1.00
Table 2. System performance
System performance Max. Typ. Unit
Sleep to Ready 30 µs
Sustained Multiple Block Read(1)
1. 43X, 20X, 12X and 5X Speed grade markings where 1X = 150 KBytes/s.
6.3 (43X) MBytes/s
Burst Single Block Read(1) 1.8 (12X) MBytes/s
Sustained Multiple Block Write(1) 3.0 (20X) MBytes/s
Burst Single Block Write(1) 0.8 (5X) MBytes/s
Power-up to Ready 150 ms
SMSxxxAF, SMSxxxFF, SMSxxxBF Description
9/61
Table 3. Power consumption(1)
1. TA= 25°C, VDD= 3.6V.
Mode Max. Current Consumption
Standby 200 µA
Read 30 mA
Write 30 mA
Table 4. Environmental specifications(1)
1. NA = Not Applicable; RH = Relative Humidity; ESD = ElectroStatic Discharge
Environmental
specifications Operating Non-Operating
Temperature − 25°C to
85°C − 40°C to 85°C
Humidity (non- condensing) NA 85°C - 85%RH
ESD
Protection
Contact Pads NA ±4kV, Human body model according to
ANSI EOS/ESD-S5.1-1998
Other
±8kV (coupling plane discharge)
±15kV (air discharge) Human body model per
IEC61000-4-2
Salt Water Spray NA TA = 35 °C 3% NaCl (MIL Std Method 1009)
Vibration (peak-to-peak) NA 15 Gmax
Shock NA 1,000G
Drop
NA
2000G
Bending 20N (middle of the card)
20N (border of the card)
UV light exposure 254nm, 15Ws/cm2
Table 5. Physical dimensions
Parameter SD MiniSD MicroSD Unit
Width 24 20 11 mm
Height 32 21.5 15 mm
Thickness 2.1 1.4
Inter Connect
Area 0.7±0.1
mm
Max. Card
Thickness 0.95
Max. Pull Area
1.0±0.1
Weight Approx. 2 Approx. 1 <1 g
Number of Pins 9 11 8 N/A
Description SMSxxxAF, SMSxxxFF, SMSxxxBF
10/61
Table 6. System reliability and maintenance
MTBF(1)
1. MTBF = Mean Time Between Failures.
>1,000,000hrs
Preventive Maintenance None
Data Reliability 1 non-recoverable bit in 1014 bit read
Endurance >2,000,000 Program/Erase Cycles
SMSxxxAF, SMSxxxFF, SMSxxxBF Memory array partitioning
11/61
2 Memory array partitioning
The basic unit of data transfer to/from the SD Memory Card is the Byte. The memory array
is divided into several structures as described below and summarized in Ta bl e 1 7 .
Block
The Block is the unit structure related to block-oriented read and write commands. Its size is
the number of Bytes that are transferred when a block-oriented read or write command is
sent by the host. The SD Memory Card Block size is either programmable or fixed. The
information about allowed block sizes and programmability is stored in the CSD Register.
The details of the Memory Array Structure and the number of addressable Blocks are shown
in Ta b l e 1 7 .
Sector
The sector is the unit structure related to the erase commands. Its size is the number of
blocks that are erased at any one time. The sector size is fixed for each device. The
information about the sector size (in blocks) is stored in the CSD register.
Write Protect Group (WP-Group)
The WP-Group is the smallest structure that may be individually protected. Its size is the
number of Sectors that are Write Protected with one bit. The information about the Write
Protect Group size is stored in the CSD Register.
Table 7. Memory array structures
Type of
Structure
Number of structures in device
Unit 32 MByte
Devices
64 MByte
Devices
128 MByte
Devices
256 MByte
Devices
512 MByte
Devices
1 GByte
Devices
Blocks 512 Bytes 59776 122624 248320 499712 1002496 1999872
Sector Block 128 128 128 128 128 128
WP-Groups Sector 1 2 4 8 16 32
Memory array partitioning SMSxxxAF, SMSxxxFF, SMSxxxBF
12/61
Figure 1. Write Protection hierarchy
Memory Card
ai10041
Write Protect Group 1
Write Protect Group 2
Write Protect Group 0
Sector 1
Sector 3
Sector 2
Block 1 Block 2
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
13/61
3 Secure digital memory card interface
This section applies to the full-size SD Memory Card only, or to the MiniSD and MicroSD
card when used with an adapter.
Details on the 11-pin communication interface of the MiniSD card used without an adapter
are still to be announced. Figure 3: MicroSD pin assignment shows the MicroSD pinout.
The Secure Digital Memory Card has an advanced 9-pin communication interface (Clock,
Command, 4 Data pins and 3 Power Supply pins) designed to operate in a low voltage
range. The Secure Digital Card has its nine pins exposed on one side (see Figure 2). The
signal/pin assignments are listed in Ta bl e 8 The pin types are Power Supply, Input, Output
and Push-Pull. The signals include six communication lines CMD, DAT0, DAT1, DAT2, DAT3,
CLK and three supply lines VDD, VSS1 and VSS2.
Figure 2. Full size Secure Digital Memory Card form factor
Table 8. Full-size SD Memory Card pin assignment
Pin #
SD mode SPI mode
Name Type(1)
1. S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers.
Description Name Type Description
1CD/DAT3
(2)
2. The extended DAT lines (DAT1-DAT3) are input on power-up. They start to operate as DAT lines after SET_BUS_WIDTH
command.
I/O/PP(3)
3. After power-up this line is input with 50kW pull-up (can be used for card detection or SPI mode selection). The pull-up
should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.
Card Detect / Data Line [Bit 3] CS I Chip Select (active Low)
2 CMD PP Command/Response DI I Data In
3V
SS1 S Supply voltage ground VSS S Supply voltage ground
4V
DD S Supply voltage VDD S Supply voltage
5 CLK I Clock SCLK I Clock
6V
SS2 S Supply voltage ground VSS2 S Supply voltage ground
7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP Data Out
8DAT1
(2) I/O/PP Data Line [Bit 1] Reserved
9DAT2
(2) I/O/PP Data Line [Bit 2] Reserved
ai10029
SD Memory
Card
12345678
9
Write Enable (Up)
Write Protect (Down)
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
14/61
Figure 3. MicroSD pin assignment
Table 9. MicroSD Contact Pad Assignment
Pin
SD Mode SPI Mode
Name Type(1)
1. S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers.
Description Name Type Description
1 DAT2 I/O/PP Data Line [Bit 2] RSV Reserved
2 CD/DA
T3(2)
2. The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after
SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while
they are not used. It is defined so, in order to keep compatibility to MultiMediaCards.
I/O/PP
(3)
3. After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode
selection). The pull-up should be disconnected by the user, during regular data transfer, with
SET_CLR_CARD_DETECT (ACMD42) command.
Card Detect / Data Line
[Bit 3] CS I Chip Select (neg true)
3 CMD PP Command/Response DI I Data In
4 VDD S Supply voltage VDD S Supply voltage
5 CLK I Clock SCLK I Clock
6 VSS S Supply voltage ground VSS S Supply voltage ground
7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP Data Out
8 DAT1 RSV Reserved
Ai11728
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
15/61
3.1 Secure digital memory card bus topology
The Secure Digital Memory Card system defines two alternative communications protocols:
SD and SPI that correspond to two operating modes.
Either mode can be selected in the application, mode selection is transparent to the host.
The host automatically detects the operating mode of the card by issuing the Reset
command (refer to Section 7.2.1: Mode Selection) and will expect all further
communications to use the same mode. Therefore, applications that use only one
communication mode do not have to be aware of the other.
The SD bus includes the following signals:
●CLK: Host to card clock signal
●CMD: Bi-directional Command/Response signal
●DAT0 - DAT3: 4 Bi-directional data signals.
●VDD, VSS1, VSS2: Power and ground signals.
The SD Memory Card bus has a synchronous star topology (refer to Figure 4: Secure Digital
Memory Card system bus topology) with a single master (the application) and multiple
slaves (the cards). The Clock, power and ground signals are common to all cards. The
command (CMD) and data (DAT0 - DAT3) signals are dedicated to the cards, they provide
continuous point-to-point connection to all the cards.
During the initialization process, commands are sent to each card individually, allowing the
application to detect the cards and assign logical addresses to the physical slots. Data is
always sent (received) to (from) each card individually. However, in order to simplify the
handling of the card stack, after the initialization process, all commands may be sent
concurrently to all cards. Addressing information is provided in the command packet.
The SD bus allows dynamic configuration of the number of data lines. After power-up the SD
Memory Card defaults to using only DAT0 for data transfer. After initialization the host can
change the bus width (number of active data lines). This feature is an easy trade off between
hardware cost and system performance.
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
16/61
Figure 4. Secure Digital Memory Card system bus topology
1. DAT1 and DAT2 not connected.
3.2 SD bus protocol
Communication over the SD bus is based on command and data bit streams which are
initiated by a start bit and terminated by a stop bit.
●Command: a command is a token which starts an operation. A command is sent from
the host either to a single card (addressed command) or to all connected cards
(broadcast command). Commands are transferred serially on the CMD line. See
Figure 5: "No Response" and "No Data" operations.
The Command token format is shown in Figure 8
●Response: a response is a token which is sent from an addressed card, or
(simultaneously) from all connected cards, to the host, as an answer to a previously
received command. Responses are transferred serially on the CMD line. A response is
illustrated in Figure 5: "No Response" and "No Data" operations.
The Response token format is shown in Figure 9
●Data: data can be transferred from the card to the host or from the host to the card.
Data is transferred via the data lines. See Figure 6: (Multiple) Block Read operation for
an illustration.
The Data Packet format is shown in Figure 10
Card addressing is implemented using a session address assigned to the card during the
initialization phase (See SD Memory Card Specification, Chapter 4). The basic transaction
on the SD bus is the command/response transaction. In this type of bus transactions, the
information is directly transferred within the command or response structure. In addition,
some operations have a data token. Data transfers to/from the SD Memory Card are done in
blocks. Data blocks are always followed by CRC bits.
Single and Multiple Block operations are supported. Note that the Multiple Block operation
mode improves the speed of write operations. A Multiple Block transmission is terminated by
issuing a STOP_TRANSMISSION command on the CMD line (See Figure 6 and Figure 7).
CLK
VDD
VSS
DAT0-DAT3(A)
CMD(A)
CLK
VDD
VSS
DAT0-DAT3 CMD
SD Memory
Card (A)
CLK
VDD
VSS
DAT0-DAT3 CMD
SD Memory
Card (B)
DAT0-DAT3(B)
CMD(B)
CLK
VDD
VSS
DAT0, CS, CMD(1)
DAT0-DAT3(C)
CMD(C)
MultiMediaCard
(C)
ai10029
HOST
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
17/61
Data transfer can be configured by the host to use single or multiple data lines (provided that
the card supports this feature).
A busy signal on DAT0 is used to indicate that a Block Write operation is ongoing (see
Figure 7). The same busy signaling is used regardless of the number of data lines used to
transfer the data.
Response tokens (see Figure 9) have four coding schemes depending on their content. The
token length is either 48 or 136 bits (See SD Memory Card Specification, Chapter 4.5 for
detailed definitions of the commands and responses). The CRC protection algorithm for
data block is a 16-bit CCITT polynomial (see SD Memory Card Specification, chapter 4.5).
On the CMD line, the MSB bit is transmitted first and the LSB bit last. When the wide bus
option is used, the data is transferred 4 bits at a time (refer to Figure 10). Start bits, End bits
and CRC bits, are transmitted on all the DAT lines used. CRC bits are calculated and
checked for every DAT line individually. The CRC status response and Busy indication are
sent by the card to the host on DAT0 only (DAT1-DAT3 are Don’t Care).
Figure 5. "No Response" and "No Data" operations
Figure 6. (Multiple) Block Read operation
Command Response
CommandCMD
DAT
ai10031
Operation
(no response)
Operation
(no data)
from Card
to Host
from Host
to Card
from Host
to Card
Response
CommandCMD
DAT
ai10032
Block Read operation Data Stop operation
Response
Command
Data Block CRC Data Block CRC Data Block CRC
Multiple Block Read operation
from Card
to Host
from Host
to Card Data from
Card to Host
STOP_TRANSMISSION command
stops data transfer
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
18/61
Figure 7. (Multiple) Block Write operation
Figure 8. Command Token format
Figure 9. response token format
Response
CommandCMD
DAT
ai10033
Block Write operation Data Stop operation
Response
Command
Data Block CRC
Multiple Block Write operation
from Card
to Host
from Host
to Card
Data from
Host to
Card
STOP_TRANSMISSION command
stops data transfer
busy Data Block CRC busy
CRC all right
response
and busy
from Card
Total Length = 48 bits
Start Bit
always '0'
Transmitter Bit
'1' = command from Host
0 1 CONTENT CRC 1
Command content: command and address
information or parameter, protected by 7 bit CRC checksum
ai10034
End bit always '1'
ai10035b
Total Length = 48 bits
Start Bit
always '0'
Transmitter Bit
'0' = Card response
0 0 CONTENT CRC 1
Response content: mirrored command and status
information (R1 response), OCR Register (R3 response)
or RCA (R6 response)protected by 7 bit CRC checksum
End bit always '1'
Total Length = 136 bits
0 0 CONTENT = CID or CSD CRC 1
R1, R3, R6
R2
End bit always '1'
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
19/61
Figure 10. Data Packet format
3.3 SD Memory Card Functional Description
All communications between the host and the cards are controlled by the host (master).
The host sends commands of two types:
●Broadcast commands which are intended for all cards. Some of these commands
require a response.
●Addressed (point-to-point) commands that are sent to the addressed card and are
followed by a response from the card.
3.4 Operation Modes
Figure 11 and Figure 12 show an overview of the command flow for the Card Identification
mode and the Data Transfer mode, respectively.
Ta bl e 1 0 shows the relationship between operation modes and card states. Each state in the
SD Memory Card state diagram (see Figure 16 and Figure 17) is associated with one
operation mode.
ai10036b
Block Length
Start Bit
always '0'
MSB (bit 4095)
0 CONTENT CRC 1
End bit always '1'
Standard bus (only DAT0 used)
LSB (bit 0)
Block Length / 4
Start Bit
always '0'
MSB Number
0 CONTENT CRC 1
End bit always '1'
Wide bus (all four data lines used)
LSB Number
0 CONTENT CRC 1
0 CONTENT CRC 1
0 CONTENT CRC 1
DAT0
DAT2
DAT3
DAT1
4095
4093
4094
4092
3
2
1
0
Table 10. Card States vs. Operation Modes
Card state Operation mode
Inactive State Inactive
Idle State
Card Identification ModeReady State
Identification State
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
20/61
3.4.1 Card Identification Mode
The host enters the Card Identification mode after reset and remains in this mode until it has
finished searching for new cards on the bus.
Cards enter the Card Identification mode after reset and remain in this mode until they
receive the SEND_RCA command (CMD3) (or the SET_RCA command for
MultiMediaCards).
While in Card Identification mode the host resets all the cards that are in Card Identification
mode, validates the operation voltage range, identifies every card and asks them to publish
their Relative Card Addresses (RCA). This operation is done separately for each card on its
own CMD line. In this mode, all data communications use the command line (CMD) only.
The host starts the card identification process at the identification clock rate fOD. The SD
Memory Card has push-pull CMD line output drives.
Once the bus has been activated the host asks each card to send their valid operation
conditions (ACMD41 preceded by APP_CMD - CMD55 with RCA=0000h).
The response to ACMD41 is the Operation Condition Register of the card. The same
command is sent to all the new cards in the system. Incompatible cards are switched to
Inactive State.
The host then issues the ALL_SEND_CID command (CMD2), to every card to get their
unique card identification (CID) numbers. All unidentified cards (which are in Ready State)
answer by sending their CID numbers (on the CMD line) and switch to the Identification
State. Then the host issues a CMD3 (SEND_RELATIVE_ADDR) command to ask the cards
to publish a relative card address (RCA). The RCA is shorter than the CID, and will be used
to address the card (typically at a clock rate higher than fOD) once this is in Data Transfer
mode. Once the RCA is received the card state changes to Standby. At this point, the host
may ask the card to publish another RCA number by sending another
SEND_RELATIVE_ADDR command to the card. The last published RCA is the actual RCA
of the card.
The host repeats the identification process, that is the cycles with CMD2 and CMD3, for
each card in the system. Once all the SD Memory Cards have been initialized, the host
initializes the MultiMediaCards that are in the system (if any) by issuing CMD2 and CMD3
as explained in the MultiMediaCard specification. Note that in the SD system all the cards
are connected separately so each MultiMediaCard has to be initialized individually.
Stand-by State
Data Transfer Mode
Transfer State
Sending-data State
Receive-data State
Programming State
Disconnect State
Table 10. Card States vs. Operation Modes (continued)
Card state Operation mode
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
21/61
Figure 11. SD Memory Card State Diagram (Card Identification Mode)
3.4.2 Data Transfer Mode
Cards enter the Data Transfer mode once their Relative Card Addresses (RCA) have been
published.
The host enters the Data Transfer mode after identifying all the cards on the bus.
The host issues SEND_CSD (CMD9) to obtain the contents of the Card Specific Data (CSD)
Register for each card. The CSD Register contains information like the block length and the
card storage.
Until the host knows the contents of all the CSD Registers, the fPP clock rate must remain at
fOD because some cards may have operating frequency limitations.
The broadcast command SET_DSR (CMD4) configures the driver stages of all identified
cards. It programs their Driver Stage Registers (DSR) according to the application bus
layout (length), the number of cards on the bus and the data transfer frequency. The clock
rate is changed from fOD to fPP at that point. The SET_DSR command is an option for the
card and the host.
CMD7 is used to select one card and switch it to the Transfer State. Only one card can be in
Transfer State at a given time. If a previously selected card is still in Transfer State when the
host uses CMD7 to switch another card to the Transfer state, then the connection between
the previously selected card and the host is released and the card reverts to the Standby
State.
SPI Operation
Mode
CMD0 +
CS asserted
Idle State
(Idle) CMD0 from all states
except for (ina)
ACMD41
Ready State
(ready)
CMD2
Identification State
(ident)
CMD3
Stand-by State
(stby)
Power-on
Inactive State
(ina) CMD15
Card with
incompatible
voltage range
Card is busy or
host omitted
voltage range
Start MultiMediaCard
initialization process
starting at CFM1
No response (invalid command),
must be a MultiMediaCard
Card responds
with new RCA
CMD0
Card Responds
with new RCA
from all states in
Data Transfer mode
Card Identification mode
Data Transfer mode
ai10037
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
22/61
When CMD7 is issued with the reserved relative card address "0000h", all cards revert to
the Standby State. This function may be used before identifying new cards, to avoid
resetting already registered cards. When in Standby state the cards that already have an
RCA do not respond to identification commands (CMD41, CMD2, CMD3).
Note that a card is deselected when it receives a CMD7 with an RCA that does not match.
Card deselection is automatic if another card in a system is selected and the cards share
the same CMD lines.
So, in an SD Memory Card system, the host may either have a common CMD line for all SD
Memory Cards (in which case card deselection is automatic just like in a MultiMediaCard
system) or the host may have separate CMD lines, in which case it must be aware of the
necessity of deselecting cards.
All data communications in the Data Transfer Mode are point-to point between the host and
the selected card (using addressed commands). All addressed commands are
acknowledged by a response on the CMD line.
The relationships between the various states in the Data Transfer mode are summarized
below (see Figure 12):
●All Data Read commands (CMD17, CMD18, CMD30, CMD56, ACMD51) can be
aborted at any time using the Stop command (CMD12). The data transfer will terminate
and the card will return to the Transfer State.
●All Data Write commands (CMD24,CMD25, CMD26, CMD27, CMD42, CMD56) can be
aborted at any time using the Stop command (CMD12). The write commands must be
stopped prior to deselecting the card using CMD7.
●As soon as the data transfer has completed, the card switches from the Data Write
state to either the Programming state (if the transfer was successful) or the Transfer
state (if the transfer failed).
●If a Block Write operation is stopped and the block length and CRC of the last block are
valid, the data will be programmed.
●The card can provide buffering during Block Write. This means that the data to be
programmed to the next block can be sent to the card while the previous block is being
programmed.
If all write buffers are full, the DAT0 line will remain Low (BUSY) as long as the card is in the
Programming state (see Figure 12).
●There is no buffering option for Write CSD, Write CID, Write Protection and erase. This
means that while the card is busy with any one of these commands, no other Data
Transfer command will be accepted. The DAT0 line will remain Low as long as the card
is busy and in the Programming state.
●Parameter Set commands (CMD16, CMD32, CMD33) are not allowed while the card is
programming.
●Read commands are not allowed while the card is programming.
●Switching another card from the Standby to the Transfer state (using CMD7) will not
terminate erase and programming operations. The card will switch to the Disconnect
state and release the DAT line.
●A card in the Disconnect state can be reselected using CMD7. The card will then revert
to the Programming state and reactivate the busy signaling.
●Resetting a card (using CMD0 or CMD15) will terminate any pending or ongoing
programming operation. This may result in the loss of card contents. It is up to the host
to prevent possible data loss.
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
23/61
Figure 12. SD Memory Card State Diagram (Data Transfer Mode)
3.5 Commands
Four types of commands are used to control the SD Memory Card:
1. Broadcast commands (bc), no response: The broadcast feature is available only if
all the CMD lines are interconnected at the level of the host. If they are not
interconnected then each individual card will accept the command in turn.
2. Broadcast commands with response (bcr): Since there is no Open Drain mode in
SD Memory Cards, this type of command is used only if the host does not use a
common CMD line. The command is accepted by every individual Card and the
responses from all cards are sent simultaneously.
3. addressed (point-to-point) commands (ac): There is no data transfer on DAT.
4. addressed (point-to-point) data transfer commands (adtc): There is a data transfer
on DAT.
All commands have a fixed code length of 48 bits for a transmission time of 2.4µs at 20MHz.
All commands and responses are sent over the CMD line of the SD Memory Card.
Command transmission always starts with the most significant bit (MSB) of the command
codeword. All commands are protected by a CRC. All Command codewords are terminated
by the end bit (always '1'). Ta b l e 1 1 shows the command format. All commands and their
arguments are specified in the SD Memory Card Specification.
CMD3 CMD15 CMD0
Card Identification mode
Data Transfer mode from all states
in Data Transfer mode
CMD13, CMD55
no state transition
in Data Transfer mode
Standby State
(stby)
CMD4,
CMD9
CMD10
"Operation
Complete"
Disconnect State
(dis)
CMD7
Programming
State (prg)
CMD7
CMD7
Transfer State
(tran)
CMD7
CMD28,
CMD29
CMD38
"Operation
Complete"
CMD24,CMD25
CMD26,CMD27
CMD42,CMD56(w)
Receive Data
State (rcv)
CMD12 or
Transfer End
CMD17,CMD18
CMD30,CMD56(r)
ACMD51
Sending Data
State (data)
CMD12,
"Operation
Complete"
ai10038
Secure digital memory card interface SMSxxxAF, SMSxxxFF, SMSxxxBF
24/61
Table 11. SD Card Command Format
3.6 Responses
All responses are sent via the command line CMD. Response transmission always starts
with the leftmost bit of the response codeword. The code length depends on the response
type. A response always starts with a start bit (always '0'), followed by the bit indicating the
direction of transmission (from card = '0').
A value denoted by 'X' in Ta bl e 1 2 , Ta bl e 1 3 , Ta b l e 1 4 and Ta b le 1 5 indicates a variable
entry.
All responses (except for R3 Responses) are protected by a CRC. All response codewords
are terminated by the end bit (always '1').
There are five types of responses. Their formats are defined as follows:
1. R1 (normal response command): the code length is 48 bits. Bits 45 to 40 indicate the
index of the command to respond to. The index is a binary coded number (between 0
and 63). The status of the card is coded in 32 bits (see Tab l e 1 2 ).
Note that if data transfer to the card takes place, then a busy signal may appear on the
data line after the transmission of each block of data. The host has to check for busy
after data block transmission.
2. R1b is identical to R1 with an optional busy signal transmitted on the data line. The
card may become busy after receiving these commands, depending on the state it was
in prior to receiving the command. The Host has to check for busy in the response.
3. R2 (CID, CSD Register): the code length is 136 bits. The contents of the CID Register
are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD
Register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD
Registers are transferred, the reserved bit [0] of these registers is replaced by the end
bit of the response (see Ta bl e 1 3 ).
4. R3 (OCR register): the code length is 48 bits. The contents of the OCR register are
sent as a response to ACMD41 (see Section Table 14. on page 25).
5. R6 (Published RCA response): the code length is 48 bits. Bits 45 to 40 indicate the
index of the command to respond to. In this case it is '000011' (together with bit 5 in the
status bits it means = CMD3) as shown in Tab l e 1 5 The 16 MSB bits of the argument
field are used for the Published RCA number.
For more details about Response formats, please refer to the SD Memory Card
Specification.
Bit position 47 46 45:40 39:8 7:1 0
Width1163271
Value '0 ''1 'x x x '1'
Description Start bit Transmission
bit
Command
index Argument CRC7 End bit
SMSxxxAF, SMSxxxFF, SMSxxxBF Secure digital memory card interface
25/61
Table 12. Response R1
Table 13. Response R2
Table 14. Response R3
Table 15. Response R6
Bit Position 47 46 [45:40] [39:8] [7:1] 0
Width (bits) 1 1 6 32 7 1
Value ‘0’ ‘0’ X X X ‘1’
Description Start Bit Transmission
Bit
Command
Index Card Status CRC7 End Bit
Bit Position 135 134 [133:128] [127:1] 0
Width (bits) 1 1 6 127 1
Value ‘0’ ‘0’ ‘111111’ X ‘1’
Description Start Bit Transmission Bit Reserved
CID or CSD
register incl.
internal CRC7
End Bit
Bit Position 47 46 [45:40] [39:8] [7:1] 0
Width (bits) 1 1 6 32 7 1
Value ‘0’ ‘0’ ‘111111’ X ‘111111’ ‘1’
Description Start Bit Transmission
Bit Reserved OCR Register Reserved End Bit
Bit Position 47 46 [45:40] [39:8] Argument Field [7:1] 0
Width (bits) 1 1 6 16 16 7 1
Value ‘0’ ‘0’ X X X X ‘1’
Description Start Bit Transmissio
n Bit
Command
Index
(‘000011’)
New
published
RCA [31:16]
of the card
[15:0] Card
Status Bits:
23, 22, 19
and 12 to 0
CRC7 end bit
SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF
26/61
4 SD memory card hardware interface
4.1 SD memory card bus circuitry
Figure 13 shows the internal bus circuitry required for the Full Size SD Memory Card.
The SD Memory Card may also feature two additional contacts, that are not part of the
internal circuitry. When present in the device, these contacts are located at the level of the
Write Protect/Card Detect switch in the socket, and should be connected as illustrated in
Figure 13.
When DAT3 is used for card detection, the RDAT resistor connected to DAT3 should be
disconnected and another resistor should be connected to Ground.
RDAT and RCMD are pull-up resistors used to protect the DAT and CMD lines, respectively,
against bus floating when no card is inserted or when all card drivers are high impedance.
RWP is used to protect the Write Protect/Card Detection switch.
Figure 13. Full Size SD Memory Card Circuitry
SD Memory Card
Host
SD Memory
Card
912345678
CLK
DAT0-DAT3
CMD
Write Protect
R
DAT
R
CMD
R
WP
C1 C2 C3
V
DD
V
DD
V
DD
V
SS
ai10042
SMSxxxAF, SMSxxxFF, SMSxxxBF SD memory card hardware interface
27/61
4.2 Power-Up
The power-up of the SD Memory Card bus is handled locally in each SD Memory Card and
in the bus master. After power-up (or after hot insertion) the SD Memory Card enters the
Idle state. When in this state, the SD Memory Card ignores all bus transactions until
ACMD41 is received (ACMD command type should always be preceded by CMD55).
ACMD41 is a special synchronization command used to negotiate the operating voltage
range and to poll the cards until they are out of their power-up sequence. In addition to the
operating voltage profile of the cards, the response to ACMD41 contains a busy flag that
indicates that the power-up sequence has not completed and the card is not ready for
identification. The host has to wait (and continue polling the cards in turn) until the bit is
cleared (‘0’). The power-up sequence of an individual card should not exceed 1 second.
After power-up the host starts the clock and sends the initializing sequence on the CMD line.
This sequence is a contiguous stream of logical 1's. It does not exceed 1ms, 74 clocks or
the supply-ramp-up-time.
Note that the maximum duration is fixed to 74 clocks which is ten clock cycles more than the
64 clocks after which the card is normally ready for communication to eliminate all power-up
synchronization problems.
Figure 14. Power-Up Diagram
1. Initialization delay = 1ms (max) + 74 clock cycles + supply ramp-up time.
2. Timeout value for initialization process is 1s.
VDDmin
ai10043
VDDmax
Bus master
supply voltage
Valid voltage
range for CMD0,
CMD15, CMD55
and ACMD41
commands
Valid voltage
range for all other
commands and
memory access
Power up
time
Supply ramp up
time
Initialization
sequence
ACMD
41
Initialization
delay(1)
ACMD
41
ACMD
41 CMD2
NCC NCC
NCC
Optional repetitions of
ACMD41, until no card
responds with the busy bit set.
Time out value for
initialization process(2)
Supply voltage
time
SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF
28/61
4.3 Hot Insertion/Removal
To guarantee a reliable initialization during hot insertion, some measures must be taken on
by the host.
For example, a special hot-insertion capable card connector may be used to guarantee the
sequence of the card pin connection.
The card contacts are connected in three steps:
1. Ground VSS (pin 3) and supply voltage VDD (pin 4).
2. CLK, CMD, DAT0, DAT1, DAT2 and VSS (pin 6).
3. CD / DAT3 (pin 1).
Pins 3 and 4 should be connected first on insertion, and be disconnected last on extraction.
Another method is a switch which could ensure that the power is switched on only after all
card pads are connected.
Inserting a Card in or removing it from the SD Memory Card bus with the power on will not
damage the card. Data transfer operations are protected by CRC codes, therefore any bit
changes induced by card insertion and removal can be detected by the SD Memory Card
bus master.
●The inserted card must be properly reset even when the clock frequency is fPP
.
●Each card should be fitted with a protection from the power supply to prevent damage
to the card (and host).
●Data transfer failures induced by removal/insertion are detected by the bus master.
They must be corrected by the application, which may repeat the issued command.
4.4 Power Protection
Cards have to be inserted in or removed from the bus without being damaged. If one of the
supply pins (VDD or VSS) is not connected properly, then the current is drawn through a data
line. All the card outputs should also be able to withstand shortcuts to either supply. If the
hot insertion feature is implemented in the host, then the host has to be able to withstand an
instant shortcut between VDD and VSS without being damaged.
4.5 Electrical Specifications
Ta bl e 1 6 defines the Bus Operating Conditions for the SD Memory Card. The total
capacitance CL of the CLK line of the SD Memory Card bus is the sum of the bus master
capacitance CHOST
, the bus capacitance CBUS and the capacitances CCARD of all the cards
connected to this line.
CL = CHOST + CBUS + N × CCARD, where:
●N is the number of cards connected to the line.
●CHOST + CBUS must be lower than 30pF for up to 10 cards and lower than 40pF for up
to 30 cards.
●The values in Ta b le 1 6 should not be exceeded.
As the bus can be supplied with a variable supply voltage, all signal levels are related to the
supply voltage. See Figure 15: Bus Signal levels and Table 17: Bus Signal Condition - I/O
Signal Voltages.
SMSxxxAF, SMSxxxFF, SMSxxxBF SD memory card hardware interface
29/61
Figure 15. Bus Signal levels
Table 16. Bus Operating Conditions
Symbol Parameter Min Max. Unit Remark
Peak voltage on all lines −0.3 VDD+0.3 V
Input Leakage Current −10 10 A
Output Leakage Current −10 10 A
VDD Supply voltage 2.0 3.6 V
Supply voltage specified in OCR register
VSS1, VSS2 Supply voltage differentials −0.3 0.3 V
power-up time 250 ms
RCMD, RDAT Pull-up resistance 10 100 KΩ
CLBus signal line capacitance
250 pF fPP < 5MHz
21 Cards
100 pF fPP < 20MHz
21 Cards
CCARD Single Card capacitance 10 pF
Maximum signal line Inductance 16 nH fPP < 20MHz
RDAT3 Pull-up resistance inside card (pin1) 10 90 KΩ
Low
Input Level
High
Input Level
Low
Output Level
High
Output Level
Undefined
V
t
VDD
VOH
VIH
VIL
VOL
VSS ai10044
Table 17. Bus Signal Condition - I/O Signal Voltages
Symbol Parameter Conditions Min Max. Unit
VOH HIGH Output voltage IOH = −100µA at VDD min 0.75VDD V
VOL LOW Output voltage IOL = 100µA at VDD min 0.125VDD V
VIH HIGH Input voltage 0.625VDD VDD + 0.3 V
VIL LOW Input voltage VSS − 0.3 0.25VDD V
SD memory card hardware interface SMSxxxAF, SMSxxxFF, SMSxxxBF
30/61
Figure 16. Data Input/Output Timings Referenced to Clock
Input
Output VALID
ai10045
tKLKL
tKLKH
tf tr
tKHKL
tKLDV
tQVKH tKHQX
tKLDX
VALID
Table 18. Bus Timings (1)
Symbol Alt Parameter Condition Min Max. Unit
tKLKL fPP Clock frequency Data Transfer Mode CL = 100pF (7 cards) 0 25 MHz
fOD
Clock Frequency Identification Mode
(the low frequency is required for
MultiMediaCard compatibility).
CL = 250pF (21 cards) 0 400 kHz
tKLKH tWL Clock low time CL = 100pF (7 cards) 10 ns
CL = 250pF (21 cards) 50 ns
tKHKL tWH Clock high time CL = 100pF (7 cards) 10 ns
CL = 250pF (21 cards) 50 ns
trtTLH Clock rise time CL = 100pF (7 cards) 10 ns
CL = 250pF (21 cards) 50 ns
tftTHL Clock fall time CL = 100pF (7 cards) 10 ns
CL = 250pF (21 cards) 50 ns
Inputs CMD, DAT (referenced to CLK)
tQVKH tISU Input set-up time CL = 25pF (1 card) 5 ns
tKHQX tIH Input hold time CL =25pF (1 card) 5 ns
Outputs CMD, DAT (referenced to CLK)
tKLDX
tKLDV
tODLY Output Delay time CL =25pF (1 card) 14 ns
1. Clock CLK: All values are referred to min (VIL) and max (VIH).
SMSxxxAF, SMSxxxFF, SMSxxxBF Card registers
31/61
5 Card registers
Six registers are defined in the card interface: OCR, CID, CSD, RCA, DSR and SCR. See
Ta bl e 1 9 for a description.
The registers are accessed by using the corresponding commands. The OCR, CID, CSD
and SCR registers contain the card/content specific information, whereas the RCA and DSR
registers are configuration registers that store the actual configuration parameters.
For more details about the register structure, please refer to the SD Memory Card
Specification v.1.01.
Table 19. SD Memory Card Registers
5.1 OCR Register
The 32-bit Operation Conditions Register contains the VDD voltage profile of the card. It also
includes a status information bit that goes High (set to ‘1’) once the card power-up sequence
has completed. The OCR register is used by the cards that do not support the full operating
voltage range of the SD Memory Card bus, or by cards whose power-up sequence does not
match the definition given in Figure 14: Power-Up Diagram.
Name Width Description
CID 128 Card IDentification number register. It contains the card’s individual
identification number. It is mandatory.
RCA(1)
1. The RCA Register is not used (available) in SPI mode.
16
Relative Card Address register. It contains the local system address of the
card, that is dynamically suggested by the card and approved by the host during
initialization. It is mandatory.
DSR 16 Driver Stage Register. It is used to configure the card's output drivers. It is
optional.
CSD 128 Card Specific Data register. It contains the information about the card’s
operation conditions. It is mandatory.
SCR 64 SD Configuration Register. It contains the information about the SD Memory
Card's Special Feature capabilities. It is mandatory
OCR 32 Operation Condition Register. It is mandatory.
Table 20. OCR Register Definition
OCR Bit Position VDD Voltag e Range
0-3 reserved
4 1.6V to 1.7V
5 1.7V to 1.8V
6 1.8V to 1.9V
7 1.9V to 2.0V
8 2.0V to 2.1V
Card registers SMSxxxAF, SMSxxxFF, SMSxxxBF
32/61
5.2 CID Register
The Card IDentification (CID) Register contains the card identification information used
during the card identification phase. Each Flash memory card should have a unique
identification number. The structure of the CID register is defined in Figure 16.
9 2.1V to 2.2V
10 2.2V to 2.3V
11 2.3V to 2.4V
12 2.4V to 2.5V
13 2.5V to 2.6V
14 2.6V to 2.7V
15 2.7V to 2.8V
16 2.8V to 2.9V
17 2.9V to 3.0V
18 3.0V to 3.1V
19 3.1V to 3.2V
20 3.2V to 3.3V
21 3.3V to 3.4V
22 3.4V to 3.5V
23 3.5V to 3.6V
24-30 reserved
31 Card Power-up Status bit (busy). This bit is Low during the card power-up
routine. It goes High on completion
Table 20. OCR Register Definition (continued)
OCR Bit Position VDD Voltag e Range
Table 21. CID Fields
Name Field Width CID-slice
Manufacturer ID MID 8 [127:120]
OEM/Application ID OID 16 [119:104]
Product name PNM 40 [103:64]
Product revision PRV 8 [63:56]
Product serial number PSN 32 [55:24]
Reserved -- 4 [23:20]
Manufacturing date MDT 12 [19:8]
CRC7 checksum CRC 7 [7:1]
not used, always '1’ -- 1 [0:0]
SMSxxxAF, SMSxxxFF, SMSxxxBF Card registers
33/61
5.3 CSD Register
The Card Specific Data Register provides information on how to access the card contents.
The CSD Register defines the data format, error correction type, maximum data access
time, data transfer speed, whether the DSR register can be used etc. The programmable
register parameters (entries with cell type W or R, listed in Ta b l e 2 2 ) can be changed using
CMD27.
Table 22. CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11
Name Field Width Cell Type(1) CSD-slice
CSD structure CSD_STRUCTURE 2 R [127:126]
reserved - 6 R [125:120]
data read access-time-1 TAAC 8 R [119:112]
data read access-time-2 in CLK cycles
(NSAC*100) NSAC 8 R [111:104]
Max. data transfer rate TRAN_SPEED 8 R [103:96]
card command classes CCC 12 R [95:84]
Max. read data block length READ_BL_LEN 4 R [83:80]
partial blocks for read allowed READ_BL_PARTIAL 1 R [79:79]
write block misalignment WRITE_BLK_MISALIGN 1 R [78:78]
read block misalignment READ_BLK_MISALIGN 1 R [77:77]
DSR implemented DSR_IMP 1 R [76:76]
reserved - 2 R [75:74]
device size C_SIZE 12 R [73:62]
Max. read current @VDD min VDD_R_CURR_MIN 3 R [61:59]
Max. read current @VDD max VDD_R_CURR_MAX 3 R [58:56]
Max. write current @VDD min VDD_W_CURR_MIN 3 R [55:53]
Max. write current @VDD max VDD_W_CURR_MAX 3 R [52:50]
device size multiplier C_SIZE_MULT 3 R [49:47]
erase single block enable ERASE_BLK_EN 1 R [46:46]
sector size SECTOR_SIZE 7 R [45:39]
write protect group size WP_GRP_SIZE 7 R [38:32]
write protect group enable WP_GRP_ENABLE 1 R [31:31]
reserved for MultiMediaCard
compatibility - 2 R [30:29]
write speed factor R2W_FACTOR 3 R [28:26]
Max. write data block length WRITE_BL_LEN 4 R [25:22]
partial blocks for write allowed WRITE_BL_PARTIAL 1 R [21:21]
reserved - 5 R [20:16]
File format group FILE_FORMAT_GRP 1 R/W(1) [15:15]
copy flag (OTP) COPY 1 R/W(1) [14:14]
permanent write protection PERM_WRITE_PROTECT 1 R/W(1) [13:13]
Card registers SMSxxxAF, SMSxxxFF, SMSxxxBF
34/61
5.4 RCA Register
The writable 16-bit Relative Card Address Register contains the card address published by
the card during the identification phase. This address is used for addressed host-card
communications after the card identification phase. The default value of the RCA register is
0000h. This value is reserved, the CMD7 command uses it to set all the cards to the
Standby state.
5.5 DSR Register (Optional)
The 16-bit Driver Stage Register is not used in Numonyx Cards.
5.6 SCR Register
The SD Card Configuration Register (SCR) is a configuration register. The SCR provides
information on the special features that are configured in the SD Memory Card. The size of
SCR Register is 64 bit.
This register is programmed in the factory by the SD Memory Card manufacturer. Ta bl e 2 3
describes the SCR contents.
temporary write protection TMP_WRITE_PROTECT 1 R/W [12:12]
File format FILE_FORMAT 2 R/W(1) [11:10]
reserved - 2 R/W [9:8]
CRC CRC 7 R/W [7:1]
not used, always'1 - 1 - [0:0]
1. R = readable, W(1) = can be written once, W = can be written several times.
Table 22. CSD Fields Compatible with CSD Structure V1 / MM Card Specification V2.11
Name Field Width Cell Type(1) CSD-slice
Table 23. SCR Fields
Description Field Width Cell Type(1) SCR Slice
SCR Structure SCR_STRUCTURE 4 R [63:60]
SD Memory Card - Specification.
Version SD_SPEC 4 R [59:56]
data_status_after erases DATA_STAT_AFTER_ERASE 1 R [55:55]
SD Security Support SD_SECURITY 3 R [54:52]
DAT Bus width supported SD_BUS_WIDTHS 4 R [51:48]
reserved - 16 R [47:32]
reserved for manufacturer usage - 32 R [31:0]
1. R = readable.
SMSxxxAF, SMSxxxFF, SMSxxxBF Timings
35/61
6 Timings
The symbols listed in Ta bl e 2 4 are used in all timing diagrams.
The difference between P-bits and Z-bits is that P-bits are actively driven to High by the card
or the host output driver whereas Z-bits are driven to High and kept High by the pull-up
resistors RCMD and RDAT. P-bits, which are actively driven High, are less sensitive to noise.
All timing values are defined in Tab l e 2 5
6.1 Command and Response
The host command and the card response are both clocked out on the rising edge of the
host clock.
6.1.1 Card Identification and Operating Conditions Timings
The timings for CMD2 (ALL_SEND_CID) and ACMD41 are shown in Figure 17 The
command is followed by two Z-bits (to leave time for the bus to switch direction) and then by
P-bits pushed up by the responding card. The card response to the host command starts
after NID clock cycles.
Table 24. Timing Diagram Symbols
Symbol Description
S Start bit (= ‘0’)
T Transmitter bit (Host = '1', Card = '0')
P One-cycle pull-up (= '1')
E End bit (=1)
Z High impedance state (-> = '1')
D Data bits
X Don't Care data bits (from card)
* Repetition
CRC Cyclic redundancy check bits (7 bits)
Card active
Host active
Timings SMSxxxAF, SMSxxxFF, SMSxxxBF
36/61
Figure 17. Identification Sequence
6.1.2 Card Relative Address Timings
The SD Memory Card timings for CMD3 (SEND_RELATIVE_ADDR) are given in Figure 18.
The minimum delay between the host command and the card response is NCR clock cycles.
Figure 18. SEND_RELATIVE_ADDRESS Command
6.1.3 Data Transfer Mode
After publishing its RCA the card switches to the Data Transfer mode. The command is
followed by two Z-bits (to leave time for the bus to switch direction) and then by P-bits
pushed by the responding card as shown in Figure 19. The timing diagram presented in
Figure 19 applies to all host commands followed by card responses, and to ACMD41 and
CMD2 commands.
Figure 19. Response (Data Transfer Mode)
6.1.4 Last Card Response, Next Host Command Timings
After receiving the last card response, the host can start the next command transmission
after NRC clock cycles as shown in Figure 20. The timing diagram presented in Figure 20
applies to any host command.
Figure 20. Response End To Next CMD Start (Data Transfer Mode)
S T CONTENT CRC E Z Z P *** P S T CONTENT Z Z Z
Host Command CID or OCRNID Cycles
ai10046
CMD
S T CONTENT CRC E Z Z P *** P S T Z Z Z
Host Command ResponseNCR Cycles
ai10047
CONTENT CRC ECMD
S T CONTENT CRC E Z Z P *** P S T Z Z Z
Host Command ResponseNCR Cycles
ai10047
CONTENT CRC ECMD
S T CONTENT CRC E Z ****** Z S T
Response Host CommandNRC Cycles
ai10048
CONTENT CRC E
CMD
SMSxxxAF, SMSxxxFF, SMSxxxBF Timings
37/61
6.1.5 Last Host Command, Next Host Command Timings
The host can send a new command NCC clock cycles after sending the previous one as
shown in Figure 21.
Figure 21. Command Sequence (All Modes)
6.2 Data Read
6.2.1 Single Block Read
The host selects one card for the data read operation by issuing CMD7, and sets the valid
block length for oriented data transfer by issuing CMD16. Figure 22 shows the timings for a
basing bus read operation. The sequence starts with a Single Block Read command
(CMD17) which specifies the start address in the argument field. The response is sent on
the CMD line.
Data transmission from the card starts NAC after the end bit of the read command, where
NAC is the access time. CRC check bits are appended to the data bits to allow the host to
check for transmission errors.
Figure 22. Single Block Read Command
6.2.2 Multiple Block Read
In Multiple Block Read mode, the card responds to the read command from the host by
sending a continuous flow of data blocks. The data flow is terminated by a
STOP_TRANSMISSION command (CMD12). Figure 23 describes the Multiple Block Read
command followed by the data blocks and Figure 24, the response to a
STOP_TRANSMISSION command. The data transmission stops two clock cycles after the
end bit of the STOP_TRANSMISSION command.
S T CONTENT CRC E Z ****** Z S T
Host Command Host CommandNCC Cycles
ai10049
CONTENT CRC E
CMD
S T CONTENT CRC E Z *** P S T
Host Command ResponseNCR Cycles
ai10050
CONTENT CRC ECMD Z P
Z **** ZZ Z ZZZZ Z P********** P S D ***
D D
NAC Cycles Read Data
DAT
Timings SMSxxxAF, SMSxxxFF, SMSxxxBF
38/61
Figure 23. Multiple Block Read Command
Figure 24. STOP_TRANSMISSION Command (CMD12, Data Transfer Mode)
6.3 Data Write
6.3.1 Single Block Write
The host selects one card for the data write operation by issuing CMD7. The host sets the
valid block length for block oriented data transfer by issuing CMD16. Figure 25 shows the
timings of a basic bus write operation. The sequence starts with a Single Block Write
command (CMD24) which determines (in the argument field) the start address. The card
responds on the CMD line.
Data transfer from the host starts NWR clock cycles after the card response is received.
CRC check bits are appended to the data sent by the host to allow the card to check for
transmission errors. The card returns the CRC check result as a CRC status token on the
DAT0 line. If a transmission error occurred, the card returns a negative CRC status ('101'). If
the transmission completed successfully, the card returns a positive CRC status ('010') and
starts programming the data.
If an error occurred while programming the Flash memory, the card ignores all further data
blocks. In this case the card will not send any CRC response and so, there will be no CRC
start bit on the bus and the three CRC status bits will read ('111').
Note that the CRC response is always output two clock cycles after the data.
If the card does not have any Data Receive buffer available, it indicates this condition by
pulling the DAT0 data line to Low. It will stop pulling DAT0 to Low as soon as at least one
Data Receive buffer for the defined data transfer block length becomes available. The level
of DAT0 does not give any information about the data write status. The host can obtain this
information by issuing a CMD13 (SEND_STATUS) to the card.
S T CONTENT CRC E Z * P S T
Host Command Response
NCR
Cycles
ai10051
CONTENT CRC ECMD Z P
Z **** ZZ Z ZZZ Z Z P******* P S D D D
NAC Cycles Read Data
DAT
ZZ P PP P PPPPP
CONTENT CRC E P******* SD D
P P PP
P
NAC Cycles Read Data
S T CONTENT CRC E Z * * * P S T
Host Command ResponseNCR Cycles
ai10052
CONTENT CRC ECMD Z P
D * * * * * * * * DD D DDEZ Z * * * * * * * * * * * * * * * * * * * *
DAT
SMSxxxAF, SMSxxxFF, SMSxxxBF Timings
39/61
Figure 25. Block Write Command
6.3.2 Multiple Block Write
In Multiple Block Write mode, the write command from the host is followed by a continuous
flow of data blocks from the host. The data flow is terminated by a STOP_TRANSMISSION
command (CMD12).
As in the case of a Single Block Write operation, CRC check bits are appended to the data
sent to allow the card to check for transmission errors. The card returns the CRC check
result as a CRC status token on the DAT0 line.
If a transmission error occurred, the card returns a negative CRC status ('101'). If the
transmission completed successfully, the card returns a positive CRC status ('010') and
starts programming the data.
If an error occurred while programming the Flash memory, the card ignores all further data
blocks. In this case the card will not send any CRC response and so, there will be no CRC
start bit on the bus and the three CRC status bits will read ('111').
Figure 26 describes a Multiple Block data transmission with and without a card busy signal.
Figure 26. Multiple Block Write Command
6.4 STOP_TRANSMISSION Command
The STOP_TRANSMISSION command works in the same way as in the read mode.
Figure 27 to Figure 30 describe the timings of the STOP_TRANSMISSION command in
different card states.
The card will consider that a data block was successfully received and is ready for
programming only if the CRC data of the block was validated and the CRC status token,
returned to the host.
Figure 28 is an example of an interrupted (by a STOP_TRANSMISSION command from the
host) attempt to transmit the CRC status token. The result is the same as in other examples
S
EZ * P S T
Host
Command Card Response
NCR
ai10053
CONTENT CRC E
CMD Z P
Z * * * * * * * ZZ ZZ Z * * * P * P L * L EZ
NWR
DAT0
ZZ P
X X
PPPP
CONTENT CRC E Z E S
P P PP
Status
Busy
Write Data
* * * * * * * * * * * * * * * * * *
ZZZZS
SZ * * * * * * * ZZ ZZ Z * * * P * P XZDAT1-DAT3 CONTENT CRC E Z X XZZZZXXX X
CRC Status
EZ
Card
Response
ai1005
CMD Z
NWR
DAT
PP P PPP P PP
Write Data
* * * * * * * * * * * * * * * * * *
CRC Status
P P PPP* * * * * * * * * * * * * * * * * * P
P * P SE ZStatusSSZ P * P Data+CRC E ZZZ L * L EE SStatusSData+CRC E Z ZZP * P
NWR
Write Data CRC Status
NWR
Busy
Timings SMSxxxAF, SMSxxxFF, SMSxxxBF
40/61
where the STOP_TRANSMISSION command is implemented: the end bit of the
STOP_TRANSMISSION command from the host is followed, on the data line, by one more
data bit, then an end bit and two Z-bits. The two Z-bits, which correspond to two clock
cycles, are used to switch the bus direction. The received data block is considered
incomplete and will not be programmed.
In the previous Stop Transmission examples, the host stopped the data transmission during
an active data transfer.
In Figure 29 and Figure 30 the STOP_TRANSMISSION command is received by the card
after all the data blocks have been sent.
In Figure 29, the card is busy programming the last block when the STOP_TRANSMISSION
command is received whereas in Figure 30 the card is idle but the input buffers still contain
data blocks to be programmed. In the second case, the card starts programming the blocks
upon reception of the STOP_TRANSMISSION command and activates the busy signal.
Figure 27. STOP_TRANSMISSION During Data Transfer From The Host
Figure 28. STOP_TRANSMISSION During CRC Status Transfer From Card
1. The card CRC status response was interrupted by the host.
Figure 29. STOP_TRANSMISSION Received After Last Data Block with Card Busy Programming
ai09518
S T CONTENT CRC E Z * * * * * * PPST
Host Command Host Command
Card Response
NCR Cycles
CONTENT S T CONTENTCRC ECMD Z P
DDDDDD DDDD E ZZ LS Z Z Z
Card is programming
DAT E Z Z ZZZ* * * * * * * * * * * * * * * * * * * * * *
ai10062
S T CONTENT CRC E Z P * * * * * * P S T
Host Command Host
Command
Card Response
NCR Cycles
CONTENT S T CONTENT
CRC E
CMD Z P
DZDDDDZS
Status
EZZ LSZZZ
Card is programming
DAT E Z Z ZZZ* * * * * * * * * * * * * * * * * * * * * *
Data
Block
CRC
Status(1)
ai10063
S T CONTENT CRC E Z * * * ST
Host Command Host
Command
Card Response
NCR Cycles
CONTENT S T CONTENT
CRC ECMD Z P
LS Z ZZ
Card is programming
DAT E Z Z ZZZ
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
P
L
SMSxxxAF, SMSxxxFF, SMSxxxBF Timings
41/61
Figure 30. STOP_TRANSMISSION Received After Last Data Block with Card Idle
6.4.1 Erase, Set and Clear Write Protect Timings
The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be
erased. The Erase command (CMD38), once issued, will erase all the selected write blocks.
Similarly, Set and Clear Write Protect commands start a programming operation as well.
The card will signal "busy" (by pulling the DAT line Low) for the duration of the erase or
program operation. The bus transaction timings are the same as those given for the
STOP_TRANSMISSION Command in Figure 30.
6.4.2 Re-selecting a busy card
When a busy card in Disabled state is reselected, it restores its busy signaling on the data
line. The timing diagram for this command / response / busy transaction is the same as that
for STOP_TRANSMISSION command illustrated in Figure 30.
6.5 Timing Values
Figure 25 gives all timings.
ai10064
S T CONTENT CRC E Z * * * ST
Host Command Host
Command
Card Response
NCR Cycles
CONTENT S T CONTENT
CRC ECMD Z P
LS ZZZ
Card is programming
DAT E Z Z ZZZ
* * * * * * * * * * * * * * * * * * * * *
P
L
ZZZ
Z Z ZZZ ZZZ
Table 25. Timing Values
Parameter Min Max Unit
NCR 2 64 clock cycle
NID 5 5 clock cycle
NAC 2T
AAC + NSAC clock cycle
NRC 8 - clock cycle
NCC 8 - clock cycle
NWR 2 - clock cycle
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
42/61
7 Serial peripheral interface (SPI) mode
The SPI mode is a secondary communication protocol, which is available in Flash memory-
based SD Memory Cards. The SD Memory Card SPI implementation uses a subset of the
SD Memory Card protocol and command set. The advantage of the SPI mode is the
capability of using off-the-shelf host, hence reducing the design-in effort to a minimum. The
disadvantage is the loss of performance (e.g., Single data line and hardware CS signal per
card). The SPI mode is selected during the first Reset command after power-up (CMD0)
and cannot be changed once the part is powered on.
7.1 SPI bus topology
The SPI compatible communication mode of the SD Memory Card is designed to
communicate with an SPI channel, commonly found in various microcontrollers on the
market. The SPI standard defines the physical link only, and not the complete data transfer
protocol. The SD Memory Card SPI and SD modes use the same command set.
Like all SPI devices, the SD Memory Card SPI channel uses the four following signals:
●CS: Host to card Chip Select signal.
●CLK: Host to card clock signal
●DataIn: Host to card data signal.
●DataOut: Card to host data signal.
All data tokens are multiples of Bytes (8 bits) and always Byte-aligned to the CS signal. The
card identification and addressing methods are replaced by a hardware Chip Select (CS)
signal. There are no broadcast commands. For every command, a card (slave) is selected
by asserting (active Low) the CS signal (see Figure 31: SD Memory Card System SPI Mode
Bus Topology).The CS signal must be continuously active for the duration of the SPI
transaction. The only exception occurs during card programming, when the host can de-
assert the CS signal without affecting the programming process. The SPI interface uses 7
out of the 9 SD signals (DAT1 and DAT2 are not used, DAT3 is the CS signal) of the SD bus.
SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode
43/61
Figure 31. SD Memory Card System SPI Mode Bus Topology
7.2 SPI Bus Protocol
Whereas the SD channel is based on command and data bit streams initiated by a start bit
and terminated by a stop bit, the SPI channel is Byte-oriented. Every command or data
block is built up with 8-bit Bytes and is Byte-aligned to the CS signal (that is, the length is a
multiple of 8 clock cycles).
Like in the SD protocol, messages in the SPI protocol consist of command, response and
data-block tokens. All communications between host and cards are controlled by the host
(master). The host starts every bus transaction by asserting the CS signal Low.
The response behaviors in SPI mode and SD mode differ in three ways. In the SPI mode:
●the selected card always responds to the command.
●two additional (8 & 16 bit) response structures are used
●when the card encounters a data retrieval problem, it sends an error response in place
of the expected data block (in the SD mode the card does not respond but implements
a timeout).
In addition to returning a response for every command received, the card returns a special
data response token for every data block received during write operations.
7.2.1 Mode Selection
The SD Memory Card wakes up in the SD mode. It will enter the SPI mode if the CS signal
is asserted (Low) when the Reset command (CMD0) is received.
The only way to return to the SD mode is to start a new power-down/power-up sequence.
In SPI mode, the SD Card protocol state machine does not apply.
CS(A)
V
DD
V
SS
CS
V
DD
V
SS
CLK, DataIN, DataOut
SD Memory
Card (A)
(SPI mode)
CS
V
DD
V
SS
CLK, DataIN, DataOut
SD Memory
Card (B)
(SPI mode)
CLK
DataIN
DataOut
CS
V
DD
V
SS
CLK, DataIN, DataOut
MultiMediaCard
(C)
(SPI mode)
ai10065
HOST
CS(B)
CS(B)
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
44/61
7.2.2 Bus Transfer Protection
On entering the SPI mode the card defaults to the non-protected mode where there is no
CRC (Cyclic Redundancy Check). So systems using reliable data links are not obliged to
have the hardware and firmware necessary to implement CRC functions.
In non-protected mode, the CRC bits are still present but are Don't Care. The CRC option
can be turned on and off by the host through the CRC_ON_OFF command (CMD59).
7.2.3 Data Read
Single and Multiple Block Read operations are supported in SPI mode. The main difference
with the SD mode is that in SPI mode data and responses to the host are both sent on the
DataOut line. As a consequence the data transfer may be interrupted and the last data
block, replaced by the response to a STOP_TRANSMISSION command.
The basic unit of data transfer is the block. The maximum size of a block is defined in the
CSD Register (READ_BL_LEN).
If READ_BL_PARTIAL is set, smaller blocks entirely contained in a physical block (as
defined by READ_BL_LEN) may also be transmitted. Single Block Read operations are
initiated by issuing the READ_SINGLE_BOCK command (CMD17). The start address can
be any Byte in the valid address range of the card. Every block, however, must be contained
in a single physical card sector.
Multiple Block Read operations are initiated by issuing the READ_MULTIPLE_BLOCK
command (CMD18) and every transferred block has a 16-bit CRC appended to it. The
STOP_TRANSMISSION command (CMD12) will actually stop the data transfer operation
(just like in the SD mode).
Figure 32. Read Operation Mechanism
Figure 33. Multiple Block Read Operation
Command Command
Data in
Data out
ai10066
from Card
to Host
from Host
to Card
next command
Response Data Block CRC
data from Card
to Host
Command STOP_TRANSMISSION
Command
Data in
Data out
ai10067
from Card
to Host
from Host
to Card
next command
Response Data Block CRC
data from Card
to Host
Data Block CRC Data B. Response
SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode
45/61
Figure 34. Read Data Error
7.2.4 Data Write
Single and Multiple Block Write operations are supported in SPI mode.
Upon reception of a valid write command, the card sends a response token and waits for a
data block to be sent from the host. Write operations, as illustrated in <Blue>Figure 35.,
follow the same rules as Read operations (refer to Section 7.2.4: Data Write) as regards the
CRC, block length and start address.
After receiving a data block, the card returns a data response token. If the data block
received contains no error, it is programmed. Throughout the programming operation the
card sends a continuous stream of busy tokens to the host (by holding the DataOut line
Low).
Figure 35. Write Operation
7.2.5 Erase & Write Protect Management
The erase and write protect management procedures are the same in the SPI and SD
modes.
While the card is erasing or changing the write protection bits, it remains in the busy state
and holds the DataOut line Low.
Figure 36. Erase & Write Protect Operations
Command Command
Data in
Data out
ai10068
from Card
to Host
from Host
to Card
next command
Response Data Error
Data Error message
from Card to Host
Command
Data in
Data out
ai10069
from Card
to Host
from Host
to Card
Response Data
Response Busy
data from
Host
to Card
Data Block
>
Data
Response Busy
Data Block
> >
Data start
token Data Response
and Busy
from Card
data from Host
to Card Data stop
token
Command Command
Data in
Data out
ai10070
from Card
to Host
from Host
to Card
from Host
to Card
Response Response
from Card
to Host
Busy
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
46/61
7.2.6 Read CID/CSD Registers
In SPI mode the CID and CSD Registers use a Block Read operation. When a Read
command is issued, the card returns a response message followed by a 16 Byte data block
with a 16-bit CRC.
As TAAC, the Data Read Access Time, is stored in the CSD Register, it cannot be used as
the read latency of the CSD Register. NCR (see Table 25: Timing Values) is used instead.
7.2.7 Reset Sequence
The SD Memory Card requires a defined reset sequence. After power-on reset or CMD0
(software reset) the card enters an idle state. When idle, the only host commands the card
will accept are CMD1 (SEND_OP_COND), ACMD41 (SD_SEND_OP_COND) and CMD58
(READ_OCR).
In SPI mode CMD1 and ACMD41 have the same function. The host must poll the card (by
repeatedly sending CMD1 or ACMD41) until the 'in-idle-state' bit in the card response
switches to Low, thus indicating that the card has completed its initialization process and is
ready for the next command.
In the SPI mode, as opposed to the SD mode, CMD1 (and ACMD41) has no operands and
does not return the contents of the OCR register. Instead, the host may use CMD58
(available in SPI mode only) to read the OCR register.
Also it is up to the host to pay attention not to gain access to cards that do not support its
voltage range. The use of CMD58 is not restricted to the initializing phase, it can be issued
at any time.
7.2.8 Memory Array Partitioning.
It is the same as in the SD mode.
7.2.9 Card Lock/Unlock Commands.
In the SPI mode, the Lock and Unlock commands are the same as in the SD mode.
7.2.10 Application Specific Commands.
The only difference between the SD and SPI modes is the APP_CMD status bit, which is not
available in the SPI mode.
7.3 SPI Mode Commands
All the SPI commands are 6 Bytes long. The command always starts with the MSB of the
string, which corresponds to the command code. See Ta bl e 2 6 for details of the command
format.
Like in the SD mode, the commands in the SPI mode are divided into classes. However, the
classes supported by the two modes are different. See Ta bl e 2 7 For details.
The commands supported in the SPI mode are described in detail in Ta b l e 2 7 If no
argument is required in the command, the value of the field should be set to '0'. Reserved
commands are reserved in both the MultiMediaCard and SPI modes. The contents of the
SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode
47/61
command index field are binary: for example, it is '000000' for CMD0 and '100111' for
CMD39.
For more details about commands and arguments, please refer to the SD Memory Card
Specification.
Table 26. Command Format
Table 27. Command Classes in SPI Mode
7.4 Responses
There are several types of response tokens. As in the SD mode, all are transmitted MSB
first.
7.4.1 R1 Format
The card sends this response token after every command except for the SEND_STATUS
command.
R1 Format Responses are one Byte long. The MSB is always zero and the other bits
indicate errors, an error being indicated by a '1'.
Bit Position 47 46 [45:40] [39:8] [7:1] 0
Width (bits) 11 6 3271
Value 01 x x x1
Descriptions Start Bit Transmission Bit Command Index Argument CRC7 End Bit
Card CMD
Class
(CCC)
Class Description
Supported Commands
0 1 9 1012131617182425272829303233384255565859
Class 0 Basic ++++++ ++
Class 1 Not supported in SPI
Class 2 Block Read + + +
Class 3 Not supported in SPI
Class 4 Block Write + + +
Class 5 Erase + + +
Class 6 Write Protection
(optional) +++
Class 7 Lock Card (optional) +
Class 8 Application specific + +
Class 9 Not supported in SPI
Class 10 -
Class 11 Reserved
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
48/61
7.4.2 R1b Format
This response token is similar to the R1 Format response token but for the option of adding
the busy signal.
The busy signal token can be any number of Bytes. A zero value indicates that the card is
busy. A non-zero value indicates that the card is ready for the next command.
7.4.3 R2 Format
This response token is two Bytes long. It is sent as a response to the SEND_STATUS
command.
7.4.4 R3 Format
This response token is sent by the card when a READ_OCR command is received. The
response length is 5 Bytes. The structure of the first Byte is identical to that of the R1 Format
response. The other four Bytes contain the OCR register.
For more details about responses, please refer to the SD Memory Card Specification v.1.01.
7.5 Clearing Status Bits
In the SPI mode, as described in the previous paragraphs, status bits are reported to the
host in three different formats: R1 Format response, R2 Format response and data error
token (the same bits may exist in several response types - e.g. Card ECC failed).
As in the SD mode, error bits are cleared when read by the host, regardless of the response
format.
State indicators are cleared either when read by the host or in accordance with the card
state. For more details, please refer to the SD Memory Card Specification.
7.6 SPI Bus Timings
Figure 38 illustrates the basic Command/Response transaction in SPI mode (that is, when
the card is ready).
Figure 39 describes a Command/ Response transaction when the card is busy (R1b
response format). For timings, refer to Ta bl e 2 5 .
Table 28. SPI Timing Symbols
S Start Bit (=0)
T Transmitter Bit (Host = 1, Card = 0)
P One-Cycle Pull-up (=1)
E End Bit (= 1)
Z High impedance stage
D Data Bits
* Repeater
SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode
49/61
Figure 37. Host Command to Card Response - Card is Ready
Figure 38. Host Command to Card Response - Card is Busy
Table 29. SPI Timing Values
Timing Min Max Unit
NCS 0 8 clock cycles
NCR 1 8 8 clock cycles
NCX 0 8 8 clock cycles
NRC 1 8 clock cycles
NAC 1Specified in CSD
Register 8 clock cycles
NWR 1 8 clock cycles
NEC 0 8 clock cycles
NDS 0 8 clock cycles
NBR 1 1 8 clock cycles
HL L L * * * * * * * * * * * * * * * * * * * * *
CS
XHX H HHH X XXData In
LLL
* * * * * * * * * * H * * H
L H HH
NEC
H
H * * H 6 Byte Command
ai10071
Z HZ H HHHHZZ1 or 2 Byte ResponseH * * H* * * * * * * * *Data Out Z HHH H
NCS
NEC
LL L * * * * * * * * * * * * * * * * * * * * *CS
XHH HHH XXData In
LLL
H * * H
L L HH
NEC
H
H * * H 6 Byte Command
ai10072
Z ZZ H HZHHZResponseH * * H* * * * * * * * *Data Out HHH H
NCS
NCR
HHHLL LLL
HHHH X * X H H H * HH
Busy BusyZL
NDS NEC
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
50/61
Figure 39. Card Response to Host Command
7.6.1 Data Read Timings
The timing diagram for deselecting the card by de-asserting CS after the last card response
corresponds to a standard command-to-response timing diagram as illustrated in Figure 39
During open-ended Multiple Block Read operations, the STOP_TRANSMISSION command
may be sent while the card is transmitting data to the host. In this case, the card stops
transmitting the data block within two clock cycles (the bits in the first Byte may not all be set
to '1') and returns the response message after a time measured in numbers of clock cycles
(NCR). See Figure 40., for details. For timings, refer to Ta bl e 2 5 .
Figure 40. Single Block Read Operation
Figure 41. STOP_TRANSMISSION between Blocks During Multiple Block Read
L L L L * * * * * * * * * * * * * * * * * * * * *CS
HHH HHH XXXData In
L
* * * * * * * * * *
L H HHL
6 Byte Command
ai10073
H HH H HHHZZ
1 or 2 Byte Response H * * H * * * * * * * * *
Data Out HHH
NRC
H HHH H HHH
L L L * * * * * * * * * * * * * * * * * * * * *CS
XH
H
HHH XXXData In
H
* * * * * * * * * * * *
H H HHH
Read Command
ai10074
Z HZ H HHZZZCard ResponseH * * H* * * * * * *
Data Out HHH
NCR
HX
LLL
H * * H H * H
Data BlockH * * H
NCS NEC
NAC
L L * * * * * * * * * * * * * * * * * * * * *CS
X HH HHData In
L L L LLH
H * H Read
Command
ai10075
Z Z Card
Response
* * * *Data Out HHH
NCS
NCR
H
HH
HHHHHH
H * H
H
H * H
* * * * * * * * * * *
STOP_TRAN.
CMD
Data Block H * HH * H
Data Block
Card
Response
NAC NAC NCR
SMSxxxAF, SMSxxxFF, SMSxxxBF Serial peripheral interface (SPI) mode
51/61
Figure 42. STOP_TRANSMISSION within a Block During Multiple Block Read
Figure 43. CSD Register Read Operation
7.6.2 Data Write Timings
The host may deselect a card at any moment during Single and Multiple Block Write
operations. The card will release the DataOut line one clock cycle after it is deselected (CS
High). To check whether the card is still busy, the host must reselect it by driving CS Low.
The card will then take control of the DataOut line one clock cycle after being reselected. In
Multiple Block Write operations, the timings from the command being issued to the first data
block being transmitted by the card are the same as for Single Block Write operations (see
Figure 44 for details). The timing of Stop Tran prefixes is the same as that of data blocks.
After the card receives the STOP_TRANSMISSION command, the data on the DataOut line
is undefined for one Byte (NBR), then a busy message may be sent by the card. For timings,
refer to Ta bl e 2 5 .
Figure 44. Single Block Write Operation
L L * * * * * * * * * * * * * * * * * * * * *
CS
XHHHH
Data In
L L L LLH
H * H Read
Command
ai10076
Z Z Card
Response
* * * *Data Out HHH
NCS
NCR
X
HH
HHHHHH
H * H
H
H * H
* * * * * * * *
STOP_TRAN.
CMD
DataH * H
Data Block
Card
Response
NAC NAC NCR
HH HH
HH * *X
L L * * * * * * * * * * * * * * * * * * * * *
CS
XXX
Data In
L H H HHH
H * * H Read Command
ai10077
Z Z Card Response* * * * * *
Data Out HHH
NCS
NCR
X X
HHHH
ZZ
H * H
ZH * * H
* * * * * * * * * *
Data Block
H
HHH
LL L
H HH * * H
NCX
NEC
LL* * * * * * * * * * * * * * * * * * * * *
CS
XHHData In
H L L LLH
H * H Write Command
ai10078
Z Z Card
Response
* * * *Data Out HHH
NCS
NCR
H HH HHH
H
X * X
H * H
Busy
H
ZZZ
LH H
L
Data
Response
NCX
NDS
L L L LL
L L
HH H * H H * HHHHHData Block
Busy
HHHHH HH
NWR NEC
Serial peripheral interface (SPI) mode SMSxxxAF, SMSxxxFF, SMSxxxBF
52/61
Figure 45. Multiple Block Write Operation
L* * * * * * * * * * * * * * * * * * * * *
CS
HHHData In
L L L LLL
ai10079
H H Data
Response
Data Out HHH
NBR
H HH HHH
X * X
H
LL L
L L L LL
L L
HH H * H HHHHData Block
Busy
HHHHH HH
NWR
L L LL
Data Block
STOP_TR
CMD
H * H
HH HH
Busy
Data
Response
Busy
HH
HH HH
NWR
SMSxxxAF, SMSxxxFF, SMSxxxBF Package mechanical data
53/61
8 Package mechanical data
Figure 46. Full-Size Secure Digital Memory Card Dimensions
1. Drawing is not to scale.
Table 30. Full-Size Secure Digital Memory Card Mechanical Data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A 2.100 2.050 2.250 0.0827 0.0807 0.0886
D 32.000 31.900 32.100 1.2598 1.2559 1.2638
E 24.000 23.900 24.100 0.9449 0.9409 0.9488
E1 15.000 – – 0.5906 – –
FD 4.000 3.900 4.100 0.1575 0.1535 0.1614
FE 4.000 3.900 4.100 0.1575 0.1535 0.1614
SE 8.125 – – 0.3198 – –
T1 – 1.400 – – 0.0551 –
T9 – 1.400 – – 0.0551 –
T8 – 0.900 – – 0.0353 –
T7 – 1.100 – – 0.04331 –
TD1 – – 1.600 – – 0.06299
TD2 – 5.000 – – 0.19685 –
A
MMC-002
E1 E
TD1
TD2
T7
FE
FD
SE
D
1
2
3
4
5
6
7
9
8
T8
T1
T9
Package mechanical data SMSxxxAF, SMSxxxFF, SMSxxxBF
54/61
Figure 47. mini Secure Digital Card Dimensions
MINI SD CARD
A
G3 D3
M2
A1
M1
A2
A3 A3 C
A4
a e
B1
B2
B6
B4
B3 B9
B7
B8 B5
J3
J2
G1G4
G2
B
R4
R
R2
R2
R1
R1
R3
R1
R2
R2
Θ
R3
R1
Table 31. MiniSD package mechanical data
Symbol
millimeters inches
Note
Typ Min Max Typ Min Max
A 20 19.90 20.10 0.7874 0.7834 0.7913
A1 18.50 18.35 18.65 0.7283 0.7244 0.7322
A2 0.60 0.50 0.70 0.0236 0.0216 0.0255
A3 - 1.45 2.05 0.0748 0.0708 0.0767
A4 2.75 - - 0.1082 0.1062 0.1102
a 1.00 0.85 1.15 0.0393 0.0374 0.0413
B 21.50 21.40 21.60 0.8464 0.8425 0.8503
B1 7.70 7.60 7.80 0.3031 0.3011 0.3051
B2 5.50 5.40 5.60 0.2165 0.2145 0.2185
B3 0.50 - - 0.0196 0.0177 0.0216
B4 0.20 - - 0.0078 - -
B5 3.8 - - 0.1496 0.1476 0.1515
B6 4.10 - - 0.1614 0.1594 0.1633
B7 1.00 - - 0.0393 0.0374 0.0413
B8 5.00 - - 0.1968 0.2342 0.1988
B9 4.50 - - 0.1771 0.1751 0.1791
C 1.4 1.3 1.5 0.0551 0.0511 0.0590
SMSxxxAF, SMSxxxFF, SMSxxxBF Package mechanical data
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D3 - - - 0.1929 0.1909 0.1948
e 1.30 0.0511 0.0492 0.0531
G1 0.60 - - 0.0236 0.0216 0.0255
G2 - 0.60 - 0.0255 0.0236 0.0275
G3 - 10 - 0.4015 0.3976 0.4055
G4 - - - 0.0078 - -
J2 1 0.90 1.10 0.0393 0.0374 0.0413
J3 1.20 1.00 1.40 0.0472 0.0452 0.0492
M1 3.00 - - 0.1181 0.1161 0.1200
M2 3.60 - - 0.1417 0.1397 0.1437
R 0.50 - - 0.0196 - - Radius
R1 0.30 - - 0.0118 - - Radius
R2 0.10 - - 0.0039 - - Radius
R3 0.20 - - 0.0078 - - Radius
R4 1.00 - - 0.0393 - - Radius
Θ45 --45--
Table 31. MiniSD package mechanical data (continued)
Symbol
millimeters inches
Note
Typ Min Max Typ Min Max
Package mechanical data SMSxxxAF, SMSxxxFF, SMSxxxBF
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Figure 48. MicroSD card mechanical dimensions
MICRO SD
A
A1
A2
A4 C2
A5
A3
B1
B11
B10
B8
B5
B
R6
R3
R5
R19
R4
R1
R2
R17
1
3
5
4
5
˚
A8 C
B7
R18
R7
R11
˚
C3
C1
R10
B3
B2
B4
Table 32. MicroSD package mechanical data
Symbol
millimeters inches
Min Typ Max Min Typ Max
A 10.90 11.00 11.10 0.429 0.433 0.437
A1 9.60 9.70 9.80 0.378 0.382 0.386
A2–3.85– –0.152–
A3 7.60 7.70 7.80 0.299 0.303 0.307
A4–1.10– –0.043–
A5 0.75 0.80 0.85 0.030 0.031 0.033
A8 0.60 0.70 0.80 0.024 0.028 0.031
B 14.90 15.00 15.10 0.587 0.591 0.594
B1 6.30 6.40 6.50 0.248 0.252 0.256
B2 1.64 1.84 2.04 0.065 0.072 0.080
B3 1.30 1.50 1.70 0.051 0.059 0.067
B4 0.42 0.52 0.62 0.017 0.020 0.024
B5 2.80 2.90 3.00 0.110 0.114 0.118
B7 0.20 0.30 0.40 0.008 0.012 0.016
B8 1.00 1.10 1.20 0.039 0.043 0.047
B10 7.80 7.90 8.00 0.307 0.311 0.315
B11 1.10 1.20 1.30 0.043 0.047 0.051
SMSxxxAF, SMSxxxFF, SMSxxxBF Package mechanical data
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c 0.17 0.21 0.25 0.007 0.008 0.010
C1 0.60 0.70 0.80 0.024 0.028 0.031
C2 0.20 0.30 0.40 0.008 0.012 0.016
C3 0.90 1.00 1.10 0.035 0.039 0.043
R1 0.20 0.40 0.60 0.008 0.016 0.024
R2 0.20 0.40 0.60 0.008 0.016 0.024
R3 0.70 0.80 0.90 0.028 0.031 0.035
R4 0.70 0.80 0.90 0.028 0.031 0.035
R5 0.70 0.80 0.90 0.028 0.031 0.035
R6 0.70 0.80 0.90 0.028 0.031 0.035
R7 29.50 30.00 30.50 1.161 1.181 1.201
R10 - 0.20 - - 0.008 -
R11 - 0.20 - - 0.008 -
R17 0.10 0.20 0.30 0.004 0.008 0.012
R18 0.20 0.40 0.60 0.008 0.016 0.024
R19 0.05 - 0.20 0.002 - 0.008
Table 32. MicroSD package mechanical data (continued)
Symbol
millimeters inches
Min Typ Max Min Typ Max
Part numbering SMSxxxAF, SMSxxxFF, SMSxxxBF
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9 Part numbering
Table 33. Ordering Information Scheme
Note: Other digits may be added to the ordering code for preprogrammed parts or other options.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For further information on any aspect of the device, please contact the nearest Numonyx
Sales Office.
Example: SMS 256 A F A 5 E
Memory Card Standard
SMS = Storage Medium, Secure Digital
Density
064 = 64 MBytes
128 = 128 MBytes
256 = 256 MBytes
512 = 512 MBytes
01G = 1GByte
Options of the Standard
A = SD full size
B = MiniSD (reduced size)
F = MicroSD
Memory Type
F = Flash Memory
Card Version
A = Version depending on device mix.
Temperature Range
5 = −25 to 85°C
Packing
E = ECOPACK package, standard packing (tray)
SMSxxxAF, SMSxxxFF, SMSxxxBF Power supply decoupling
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Appendix A Power supply decoupling
The VSS1, VSS2 and VDD lines supply the card with the operating voltage. To do this,
decoupling capacitors for buffering current peak are used. These capacitors are placed on
the bus side corresponding to Figure 49.
Figure 49. Power supply decoupling
The host controller includes a central buffer capacitor for VDD. Its value is 1 µF/slot.
SD Memory Card
Ai11729
C
VSS1
VSS
VSS2
Lmax = 13 mm
single card slot
single card slot
C=100 nF
Revision history SMSxxxAF, SMSxxxFF, SMSxxxBF
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10 Revision history
Table 34. Document Revision History
Date Rev. Description of Revision
28-Jul-2006 1 First issue.
15-Dec-2006 2
Added SD, miniSD and MicroSD available in Halogen free and Antimony free
packages.
Information on power dissipation removed from Features section.
VDD updated in Note 1 below Table 3: Power consumption.
Figure 10: Data Packet format and Figure 11: SD Memory Card State
Diagram (Card Identification Mode) updated.
10-Dec-2007 3 Applied Numonyx branding.
SMSxxxAF, SMSxxxFF, SMSxxxBF
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