PIC16F785-E/SO - Microchip Technology, Inc.

PIC16F785/HV785

Data Sheet

20-Pin Flash-Based, 8-Bit

CMOS Microcontroller with

Two-Phase Asynchronous Feedback PWM

Dual High-Speed Comparators and

Dual Operational Amplifiers

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PIC16F785/HV785

High-Performance RISC CPU:

• Only 35 Instructions to Lea rn:

- All single-cycle instructions except branches

• Ope rati ng Speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt Capability

• 8-Level Seep Hardware Stack

• Direct, Indirect and Relative Addressing modes

S pecial Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of

8 MHz to 32 kHz

- Softwa re tunab le

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power saving s

• Power-Saving Sleep mode

• Wide Operating Voltage Range (2.0V-5.5V)

• Indus tri al and Extended Tem pe r atu re Ra nge

• Power-on Reset (P OR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-ou t Reset (BOR) with Softwa re Control

Option

• Enhanced Low-Current Watchdog Timer (WDT)

with on-chip Oscillator (software selectable

nominal 268 seconds wit h full prescaler) with

Software Enable

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• High-Endurance Flash/EEPROM cell:

- 10 0,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

Low-Power Features:

• Standby Current:

- 30 nA @ 2.0V, typical

• Ope rati ng Curren t:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

-1μA @ 2.0V, typical

• Timer1 Oscillator Current:

-2μA @ 32 kHz, 2.0V, typical

Peripheral Feat ures:

• High-Speed Comparator module with:

- Two independent analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- 1.2V band gap voltage reference

- Comparator inputs and outputs externally

accessible

- < 40 ns prop aga tio n dela y

- 2 mv offset, typical

• Operational Amplifier module with 2 independent

Op Amps:

- 3 MHz GBWP, typical

- All I/O pins externally accessible

• Two-Phase Asynchronous Feedback PWM

module:

- Complementary output with programmable

dead band delay

- Infinite resolution analog duty cycle

- Sync Output/Input for multi-phase PWM

-F

OSC/2 maximum PWM frequency

• A/D Converter:

- 10-bit resolution and 14 channels (2 internal)

• 17 I/O pins and 1 Input-only Pin:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator, if INTOSC mode

selected

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

• Cap ture , Comp a r e, PWM mo dul e:

- 1 6-bit Capture, max resolution 12.5 n s

- Compare, max resolution 200 ns

- 10-bit PWM with 1 output channel, max

frequency 20 kHz

• In-Circuit Serial ProgrammingTM (ICSPTM) via two

pins

• Shunt Voltage Regulator (PIC16HV785 only):

- 5 volt regulati on

- 4 mA to 50 mA shunt range

20-Pin Flash-Based 8-Bit CMOS Microcontroller

PIC16F785/HV785

Dual in Line Pin Diagram

TABLE 1: DUAL IN LINE PIN SUMMARY

Device

Program

Memory Data Memory

I/O 10-bit

A/D (ch) Op

Amps Comparators CCP Two-

Phase

PWM

Timers

8/16-bit Shunt

Reg.

Flash

(words) SRAM

(bytes) EEPROM

(bytes)

PIC16F785 2048 128 256 17+1 12+2 2 2 1 1 2/1 0

PIC16HV785 2048 128 256 17+1 12+2 2 2 1 1 2/1 1

I/O Pin Analog Comp. Op

Amps PWM Timers CCP Interrupt Pull-ups Basic

RA0 19 AN0 C1IN+ — — — — IOC YICSPDAT

RA1 18 AN1/VREF C12IN0- — — — — IOC Y ICSPCLK

RA2 17 AN2 C1OUT — — T0CKI —INT/IOC Y —

RA3(1) 4— — ————IOC Y MCLR/VPP

RA4 3AN3 — — — T1G —IOC YOSC2/CLKOUT

RA5 2 — — — — T1CKI — IOC Y OSC1/CLKIN

RB4 13 AN10 —OP2- — — — — — —

RB5 12 AN11 — OP2+ — — — — — —

RB6(2) 11 — — — — — — — — —

RB7 10 — — — SYNC — — — — —

RC0 16 AN4 C2IN+ — — — — — — —

RC1 15 AN5 C12IN1- — PH1 — — — — —

RC2 14 AN6 C12IN2- OP2 — — — — — —

RC3 7 AN7 C12IN3- OP1 — — — — — —

RC4 6 — C2OUT —PH2 — — — — —

RC5 5 — — — — — CCP1 — — —

RC6 8AN8 —OP1- — — — — — —

RC7 9 AN9 — OP1+ — — — — — —

— 1 — — — — — — — — VDD

—20 — — — — — — — — VSS

Note 1: Input only.

2: Open drain.

20-pin PDIP, SOIC, SSOP

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5/CCP1

RC4/C2OUT/PH2

RC3/AN7/C12IN3-/OP1

RC6/AN8/OP1-

RC7/AN9/OP1+

RB7/SYNC

VSS

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RB4/AN10/OP2-

RB5/AN11/OP2+

RB6

PIC16F785/HV785

QFN (4x4x0.9) Pin Diagram

TABLE 2: QFN PIN SUMMARY

I/O Pin Analog Comp. Op

Amps PWM Timers CCP Interrupt Pull-ups Basic

RA0 16 AN0 C1IN+ — — — — IOC YICSPDAT

RA1 15 AN1/VREF C12IN0- — — — — IOC Y ICSPCLK

RA2 14 AN2 C1OUT — — T0CKI —INT/IOC Y —

RA3(1) 1— — — ———IOC Y MCLR/VPP

RA4 20 AN3 — — — T1G —IOC YOSC2/CLKOUT

RA5 19 — — — — T1CKI — IOC Y OSC1/CLKIN

RB4 10 AN10 —OP2- — — — — — —

RB5 9 AN11 — OP2+ — — — — — —

RB6(2) 8 — — — — — — — — —

RB7 7 — — — SYNC — — — — —

RC0 13 AN4 C2IN+ — — — — — — —

RC1 12 AN5 C12IN1- — PH1 — — — — —

RC2 11 AN6 C12IN2- OP2 — — — — — —

RC3 4 AN7 C12IN3- OP1 — — — — — —

RC4 3 — C2OUT —PH2 — — — — —

RC5 2 — — — — — CCP1 — — —

RC6 5AN8 —OP1- — — — — — —

RC7 6 AN9 — OP1+ — — — — — —

—18 — — — — — — — — VDD

—17 — — — — — — — — VSS

Note 1: Input only.

2: Open drain.

511

RC3/AN7/C12IN3-/OP1

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5/CCP1

RC4/C2OUT/PH2

RC6/AN8/OP1-

RC7/AN9/OP1+

RB7/SYNC

VSS

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RB4/AN10/OP2-

RB5/AN11/OP2+

RB6

20-PIN QFN

PIC16F785/HV785

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory O rganization................................................................................................................................................................... 9

3.0 Clock Sources............................................................................................................................................................................ 23

4.0 I/O Ports ... ..................... ........................... ........................... ............................ ........................................................................... 35

5.0 Timer0 Module ........................................................................................................................................................................... 49

6.0 Timer1 Module with Gate Control............................................................................................................................................... 51

7.0 Timer2 Module ........................................................................................................................................................................... 55

8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 57

9.0 Comparator Module.............................. .... .... .... ......... .... .... .. .... ........... .. .... .... ......... .... .... ............................................................. 63

10.0 Voltage References..................... .. ....... .. .... .. .. .... ....... .. .. .... .. .... ....... .. .. .... .. .. ....... .... .. .. .... ............................................................. 70

11.0 Operational Amplifier (OPA) Module.......................................................................................................................................... 75

12.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 79

13.0 Two-Phase PWM ...................... ..................... ............................ ..................... .................. ......................................................... 91

14.0 Dat a EEP R OM Mem o ry......................... ..................... ........................... ..................... ............................................................. 103

15.0 Special Features of the CPU....... ............................ ..................... ..................... ....................................................................... 107

16.0 Voltage Regulator............................... .. .... .. .. .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. .. .. .... ..... .. .. .... .. ............................................................. 126

17.0 Instruction Set Summary.......................................................................................................................................................... 127

18.0 Development Support. .............................................................................................................................................................. 137

19.0 Electrical Specifications............................................................................................................................................................ 141

20.0 DC and AC Characteristics Graphs and Tables...................................................... .... .... ........... .... ... ....................................... 163

21.0 Packa g i n g In fo rmation............................ ..................... ........................... ..................... ............................................................. 187

Appendix A: Data Sheet Revision History........................................................ .... ........... .... .... ........................................................... 193

Appendix B: Migrating from other PIC® Devices..................... ..................... ..................... ..................... ..................... ....................... 193

Index .................................................................................................................................................................................................. 195

The Micro chip Web Site.................... ..................... ........................... ............................ ..................................................................... 201

Customer Change Notification Service .............................................................................................................................................. 201

Customer Support.................................................... ................. ...... ................. ................. ................................................................. 201

Reader Response.............................................................................................................................................................................. 202

Product Identification System............................................................................................................................................................. 203

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Customer No tific atio n Syst em

PIC16F785/HV785

1.0 DEVICE OVERVIEW

This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r

the PIC16F785/HV785. It is available in 20-pin PDIP,

SOIC, SSOP and QFN packages. Figure 1-1 shows a

block diagram of the PIC16F785/HV785 device.

Table 1-1 shows the pinout description.

FIGURE 1-1: PIC16F785/HV785 BLOCK DIAGRAM

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

RAM

File

Registers

Direct Ad dr 7

RAM Addr 9

ADDR MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

OSC1/CLKIN

OSC2/CLKOUT

PORTA

8-Level Stack 128 bytes

2k X 14

(13-bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Reset

2 Analog

Timer0 Timer1

Data

EEPROM

256 bytes

EEDATA

EEADDR

Comparators

AN0

AN1

AN2

AN3

C1IN-

C1IN+

C1OUT

T0CKI

INT

T1CKI

Configuration

VREF

T1G

PORTB

AN4

AN5

AN6

AN7

VDD

Timer2

C2IN-

C2IN+

C2OUT

CCP

CCP1

AN3

AN8

AN9

AN10

AN11

RB4

RB5

RB6

RB7

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RA0

RA1

RA2

RA3

RA4

RA5

Analog-to-Digital Converter

OP1

OP1+

OP1-

OP2

OP2+

OP2-

Dual

Op Amps

PH1

PH2

SYNC

Two-Phase

PWM

Voltage

Reference

Instruction

Decode and

Control

Timing

Generation

8 MHz Internal

Oscillator

32 kHz Internal

Oscillator

PIC16F785/HV785

TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS PORTA I/O wi th prog. pull-up and interrupt-on-change

AN0 AN — A/D Channel 0 input

C1IN+ AN — Comparator 1 non-inverting input

ICSPDAT ST CMOS Serial Programming Data I/O

RA1/AN1/C12IN0-/VREF/

ICSPCLK RA1 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN1 AN — A/D Channel 1 input

C12IN0- AN — Comparator 1 and 2 inverting input

VREF AN AN External V olt age Reference for A/D, buf fered reference

output

ICSPCLK ST — Serial Programming Clock

RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN2 AN — A/D Channel 2 input

T0CKI ST — T im er0 cl ock inpu t

INT ST — External Interrupt

C1OUT — CMOS Compara tor 1 outpu t

RA3/MCLR/Vpp RA3 TTL — PORTA input with prog. pull-up and interrupt-on-

change

MCLR ST — Master Clear with internal pull-up

VPP HV — Programming voltage

RA4/AN3/T1G/OSC2/

CLKOUT RA4 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN3 AN — A/D Channel 3 input

T1G ST — Timer1 gat e

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS FOSC/4 output

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O with prog. pull-up and interrupt-on-change

T1CKI ST — Timer1 cl ock

OSC1 XTAL — Crystal/Resonator

CLKIN ST — External clock input/RC oscillator connection

RB4/AN10/OP2- RB4 TTL CMOS PORTB I/O

AN10 AN — A/D Channel 10 input

OP2- — AN Op Amp 2 inverting input

RB5/AN11/OP2+ RB5 TTL CMOS PORTB I/O

AN11 AN — A/D Channel 11 input

OP2+ — AN Op Amp 2 non-inverting input

RB6 RB6 TTL OD PORTB I/O. Open drain output

RB7/SYNC RB7 TTL CMOS PORTB I/O

SYNC ST CMOS Master PWM Sync output or slave PWM Sync input

RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O

AN4 AN — A/D Channel 4 input

C2IN+ AN — Comparator 2 non-inverting input

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output,

HV = High Voltage

PIC16F785/HV785

RC1/AN5/C12IN1-/PH1 RC1 TTL CMOS PORTC I/O

AN5 AN — A/D Channel 5 input

C12IN1- AN — Comparator 1 and 2 inverting input

PH1 — CMOS PWM phase 1 output

RC2/AN6/C12IN2-/OP2 RC2 TTL CMOS PORTC I/O

AN6 AN — A/D Channel 6 input

C12IN2- AN — Comparator 1 and 2 inverting input

OP2 — AN Op Amp 2 output

RC3/AN7/C12IN3-/OP1 RC3 TTL CMOS PORTC I/O

AN7 AN — A/D Channel 7 input

C12IN3- AN — Comparator 1 and 2 inverting input

OP1 — AN Op Amp 1 output

RC4/C2OUT/PH2 RC4 TTL CMOS PORTC I/O

C2OUT — CMOS Compara tor 2 outpu t

PH2 — CMOS PWM phase 2 output

RC5/CCP1 RC5 TTL CMOS PORTC I/O

CCP1 ST CMOS Capture input/Compare output

RC6/AN8/OP1- RC6 TTL CMOS PORTC I/O

AN8 AN — A/D Channel 8 input

OP1- AN — Op Amp 1 inverting input

RC7/AN9/OP1+ RC7 CMOS PORTC I/O

AN9 AN — A/D Channel 9 input

OP1+ AN — Op Amp 1 non-inverting input

VSS VSS Pow er — Grou nd reference

VDD VDD Power — Positi ve suppl y

TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output,

HV = High Voltage

PIC16F785/HV785

NOTES:

PIC16F785/HV785

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F785/HV785 has a 13-bit program counter

capable of addressing an 8k x 14 program memory

space. Only the first 2k x 14 (0000h-07FFh) for the

PIC16F7 85/HV 785 is ph ysic ally i mplemen ted . Acces s-

ing a location above these boundaries will cause a

wrap around within the first 2k x 14 space. The Reset

vector is at 0000h and the interrupt vector is at 0004h

(see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F785/HV785

2.2 Data Memor y Organization

The data memory (see Figure 2-2) is partitioned into

four banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank. Register locations

20h-7Fh in Ban k 0 and A0 h-BFh i n B ank 1 a re Ge neral

Purpose Registers, implemented as static RAM. The

last sixteen register locations in Bank 1 (F0h-FFh),

Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to

addresses 70h-7Fh in Bank 0. All other RAM is

unimpl em ente d and retu rns ‘0’ w hen read.

Seven address bits are required to access any location

in a dat a memory bank. T wo additional bit s are required

to access the four banks. When data memory is

accessed directly, the seven Least Significant address

bits are contained within the opcode and the two Most

Significant bits are contained in the STATUS register.

RP0 and RP1 bits of the STATUS register are the two

Most Significant data memory address bits and are

also known as the bank select bits. Table 2-1 lists how

to access the four banks of registers.

TABLE 2-1: BANK SELECTION

2.2.1 GENERAL PURPOSE REGISTER

FILE

The register file banks are organized as 128 x 8 in the

PIC16F785/HV785. Each register is accessed, either

directly, by seven address bits within the opcode, or

indirectly, through the File Select Register (FSR).

When the FSR is used to access data memory, the

eight Least Significant data memory address bits are

contained in the FSR and the ninth Most Significant

address bit is contained in the IRP bit in the STATUS

INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-2). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

assoc iated with th e “core” are d escribed in this sectio n.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

PC<12:0>

0000h

0004

0005

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

RP1 RP0

Bank 0 00

Bank 1 01

Bank 2 10

Bank 3 11

PIC16F785/HV785

FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F785/HV785

Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h PORTA 105h TRISA 185h

PORTB 06h TRISB 86h PORTB 106h TRISB 186h

PORTC 07h TRISC 87h PORTC 107h TRISC 187h

08h 88h 108h 188h

09h 89h 109h 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch 10Ch PIE1 18Ch

0Dh 8Dh 10Dh 18Dh

TMR1L 0Eh PCON 8Eh 10Eh 18Eh

TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh

T1CON 10h OSCTUNE 90h PWMCON1 110h 190h

TMR2 11h ANSEL0 91h PWMCON0 111h 191h

T2CON 12h PR2 92h PWMCLK 112h 192h

CCPR1L 13h ANSEL1 93h PWMPH1 113h 193h

CCPR1H 14h 94h PWMPH2 114h 194h

CCP1CON 15h WPUA 95h 115h 195h

16h IOCA 96h 116h 196h

17h 97h 117h 197h

WDTCON 18h REFCON 98h 118h 198h

19h VRCON 99h CM1CON0 119h 199h

1Ah EEDAT 9Ah CM2CON0 11Ah 19Ah

1Bh EEADR 9Bh CM2CON1 11Bh 19Bh

1Ch EECON1 9Ch OPA1CON 11Ch 19Ch

1Dh EECON2(1) 9Dh OPA2CON 11Dh 19Dh

ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

96 Bytes

20h General

Purpose

32 Bytes

A0h

BFh

120h 1A0h

6Fh

C0h

EFh 16Fh 1EFh

70h accesses

Bank 0 F0h accesses

Bank 0 170h accesses

Bank 0 1F0h

7Fh FFh 17Fh 1FFh

Bank 0Bank 1Bank 2Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

File

Address File

Address

PIC16F785/HV785

TABLE 2-2: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114

01h TMR0 Timer0 Module’s Register xxxx xxxx 49,114

02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114

03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 15,114

04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114

05h PORTA(1) —— RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 35,114

06h PORTB(1) RB7 RB6 RB5 RB4 — — — — xx00 ---- 42,114

07h PORTC(1) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 00xx 0000 45,114

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114

0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 17,114

0Ch PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 19,114

0Dh —Unimplemented — —

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 52,114

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 52,114

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 53,114

11h

TMR 2 Timer2 Module R egister 0000 0000 55,114

12h

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55,114

13h CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 58,114

14h CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 58,114

15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58,114

16h —Unimplemented — —

17h —Unimplemented — —

18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 122,114

19h —Unimplemented — —

1Ah —Unimplemented — —

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result xxxx xxxx 81,114

1Fh ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 83,114

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

PIC16F785/HV785

TABLE 2-3: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17,114

82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 15,114

84h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114

85h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 35,114

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 ————1111 ---- 42,114

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 45,114

88h —Unimplemented — —

89h —Unimplemented — —

8Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114

8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 17,114

8Ch PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 18,114

8Dh —Unimplemented — —

8Eh PCON — — — SBOREN ——PORBOR ---1 --qq 20,114

8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS -110 q000 33,114

90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 28,114

91h ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 82,114

92h PR2 Timer2 Module Period Register 1111 1111 55,114

93h ANSEL1 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 82,114

94h —Unimplemented — —

95h WPUA —— WPUA5 WPUA4 WPUA3(2) WPUA2 WPUA1 WPUA0 --11 1111 36,114

96h IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 37,114

97h —Unimplemented — —

98h REFCON —— BGST VRBB VREN VROE CVROE —--00 000- 73,114

99h VRCON C1VREN C2VREN VRR — VR3 VR2 VR1 VR0 000- 0000 72,114

9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 103,114

9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 103,114

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 104,114

9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 104,114

9Eh ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx 81,114

9Fh ADCON1 — ADCS2 ADCS1 ADCS0 ————-000 ---- 84,114

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown , q = value depends on condition, shaded = unimplemented

Note 1: Bit resets to ‘0’ with Two-Sp eed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this

bit resets to ‘1’.

2: RA3 pull- up is enable d wh en MCL RE is ‘1’ in Configuration Word.

PIC16F785/HV785

TABLE 2-4: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Addr Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114

101h T MR0 Timer0 Module’s Register xxxx xxxx 49,114

102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114

103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 15,114

104h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114

105h PORTA(1) —— RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 35,114

106h PORTB(1) RB7 RB6 RB5 RB4 — — — — xx00 ---- 42,114

107h PORTC(1) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 00xx 0000 45,114

108h —Unimplemented — —

109h —Unimplemented — —

10Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114

10Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 17,114

10Ch —Unimplemented — —

10Dh —Unimplemented — —

10Eh —Unimplemented — —

10Fh —Unimplemented — —

110h

PWMCON1 — COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0 -000 0000 101,114

111h

PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 93,114

112h

PWMCLK PWMASE PWMP1 PWMP0 PER4 PER3 PER2 PER1 PER0 0000 0000 94,114

113h PWMPH1 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 95,114

114h PWMPH2 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 96,114

115h —Unimplemented — —

116h —Unimplemented — —

117h —Unimplemented — —

118h —Unimplemented — —

119h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 65,114

11Ah CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 67,114

11Bh CM2CON1 MC1OUT MC2OUT ———— T1GSS C2SYNC 00-- --10 68,114

11Ch OPA1CON OPAON — — — — — — — 0--- ---- 76,114

11Dh OPA2CON OPAON — — — — — — — 0--- ---- 76,114

11Eh —Unimplemented — —

11Fh —Unimplemented — —

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

PIC16F785/HV785

TABLE 2-5: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Page

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22,114

181h OPTION_RE

GRAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17,114

182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 21,114

183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 15,114

184h FSR Indirect Data Memory Address Pointer xxxx xxxx 22,114

185h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 36,114

186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 42,114

187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 45,114

188h —Unimplemented — —

189h —Unimplemented — —

18Ah PCLATH ——— Write Buffer for Upper 5 bits of Program Counter ---0 0000 21,114

18Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 17,114

18Ch —Unimplemented — —

18Dh —Unimplemented — —

18Eh —Unimplemented — —

18Fh —Unimplemented — —

190h —Unimplemented — —

191h —Unimplemented — —

192h —Unimplemented — —

193h —Unimplemented — —

194h —Unimplemented — —

195h —Unimplemented — —

196h —Unimplemented — —

197h —Unimplemented — —

198h —Unimplemented — —

199h —Unimplemented — —

19Ah —Unimplemented — —

19Bh —Unimplemented — —

19Ch —Unimplemented — —

19Dh —Unimplemented — —

19Eh —Unimplemented — —

19Fh —Unimplemented — —

Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

PIC16F785/HV785

2.2.2.1 STATUS Register

The STATUS register contains arithmetic status of the

ALU, the Reset statu s an d th e bank selec t bi t s fo r da t a

memory ( SRAM).

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits, see Section 17.0

“Instruction Set Summary”.

Note: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for Indirect addressing)

1 = Bank 2,3 (100h-1FFh)

0 = Bank 0,1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for Direct addressing)

11 = Bank 3 (180h-1FFh)

10 = Bank 2 (100h-17Fh)

01 = Bank 1 (80h-FFh)

00 = Bank 0 (00h-7Fh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digi t Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder

bit of the source register.

PIC16F785/HV785

2.2.2.2 OPTION_REG Register

The Option register is a readable and writable register,

which contains various control bits to configure the

TMR0/WDT prescaler, the external RA2/INT interrupt,

the TMR0 and t he weak pull-ups on PORTA.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by

setting PSA bit to ‘1’ in the OPTION Reg-

ister. See Section 5.4 “Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull- ups are disabled

0 = PORTA pull-ups are enabled by individual port latch values in WPUA register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/AN2/T0CKI/INT/C1OUT pin

0 = Interrupt on falling edge of RA2/AN2/T0CKI/INT/C1OUT pin

bit 5 T0CS: TMR0 Clock Source S ele ct bit

1 = Transition on RA2/AN2/T0CKI/INT/C1OUT pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/AN2/T0CKI/INT/C1OUT pin

0 = Increment on low-to-high transition on RA2/AN2/T0CKI/INT/C1OUT pin

bit 3 PSA: Prescaler Ass ig nment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Note 1: A dedicated 16- bit WDT postscaler is av ailable for the PIC16F785/HV785.

See Section 15.5 “Watchdog Timer (WDT)” for more information.

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate(1)

PIC16F785/HV785

2.2.2.3 INTCON Register

The Interrupt Control register is a readable and writable

for TMR0 register overflow , PORT A change and external

RA2/INT pin interrupts.

Note: Interru pt flag bit s are set w hen an interr upt

condition occurs, regardless of th e state of

its corresponding enable bit or the global

enable bit , GIE bit of the INTCO N register.

User sof tware sh ould ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RAIE(1) T0IF(2) INTF RAIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Enable bit

1 = Enables the RA2/AN2/T0CKI/INT/C1OUT external interrupt

0 = Disables the RA2/AN2/T0CKI/INT/C1OUT external interrupt

bit 3 RAIE: PORTA Change Interrupt Enable bit(1)

1 = Enables the PORTA change interrupt

0 = Disables the PORTA change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)

1 = TM R0 register has overflowed (must be cleare d in so ftwa re)

0 = TM R0 register did no t overfl ow

bit 1 INTF: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Flag bit

1 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt occurred (must be cleared in software)

0 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt did not occur

bit 0 RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)

0 = None of the PORTA <5:0> pins have changed state

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when T imer0 rolls over . T imer0 is unchanged on Reset and should be initialized before clear-

ing T0IF bit.

PIC16F785/HV785

2.2.2.4 PIE1 Regist er

The Peripheral Interrupt Enable Register 1 cont ains the

interrupt enable bits, as shown in Register 2-4.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt

0 = Disables the Comparator 2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt

0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt

0 = Disables the Oscillator Fail interrupt

bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

PIC16F785/HV785

2.2.2.5 PIR1 Register

The Peripheral Interrupt Register 1 contains the

interr upt fla g bit s .

Note: Interru pt flag bi ts are s et when an interrupt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit or the global

enable bit, GIE, in the INTCON Register).

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Interrupt Flag bit

1 = A/D conversion complete

0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register captu re occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator 2 output has changed (must be cleared in software)

0 = Comparator 2 output has not changed

bit 3 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator 1 output has changed (must be cleared in software)

0 = Comparator 1 output has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock operating

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

PIC16F785/HV785

2.2.2.6 PCON Register

The Power Control register contains flag bits to allow

differentiation between a Power-on Reset (POR), a

Brown-out Reset (BOR), a Watchdog Timer (WDT)

Reset (WDT) and an external MCLR Reset.

U-0 U-0 U-0 R/W-1 U-0 U-0 R/W-0 R/W-x

— — — SBOREN(1) ——POR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 SBOREN: Software BOR Enable bit(1)

1 = BOR enabled

0 = BOR disabled

bit 3-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01 in Configuration Word for this bit to control the BOR.

PIC16F785/HV785

2.3 PCL and PCLATH

The Progra m Counter (PC) specifies the address of th e

instruction to fetch for execution. The program counter

is 13 bit s wide. The low byte is c all ed th e PCL regi ste r.

The PCL register is readable and writable. The high

byte of t he PC Re gister is ca lled th e PCH reg ister. This

readable or writable. All updates to the PCH register

goes through the PCLATH register.

On any Re se t, the PC is clea red. Figure 2-3 shows th e

two situations for loading the PC. The upper example

of F igu re 2-3 shows how th e PC is l oaded on a w ri te to

PCL in the PCLA TH Register→ PCH. The lower exam-

ple of Figure 2-3 shows how the PC is loaded d uring a

CALL or GOTO instruction in the PCLATH Register→

PCH).

2.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

content s of th e PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desire d upper 5 bit s to the PCLATH register.

When th e lower 8 bits are w ritten to the PCL register, all

13 bit s of the program cou nter will chang e to the values

contained in the PCLATH register and those being

written to the PCL register.

A comput ed GOTO is acc om pli sh ed by adding a n offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2 PROGRAM MEMORY PAGING

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When using a CALL or GOTO instruction,

the Mo st Signi ficant bit s o f the addre ss a re pro vided by

PCLATH<4:3> (page select bits). When using a CALL

or GOTO i nstruction, the use r must ensure t hat the page

select bits are pro grammed so that th e desired des tina-

tion program memory page is addressed. When the

CALL instruction (or interrupt) is executed, the entire

13-bit PC return address is PUSHed onto the stack.

Therefore, manipulation of the PCLATH<4:3> bits are

not required for the RETURN or RETFIE instructions

(which POPs the address from the stack).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.3 STACK

The PIC16F785/HV785 family has an 8-level deep x

13-bit w i de hard w are stack ( see Fi gure 2-1). T he stack

space is not part of either program or data space and

the Stack Poin ter is no t readable or w ri t ab le . Th e PC is

PUSHed onto the stack when a CALL instruction is

executed or an interrupt causes a branch. The stack is

POPe d in the even t of a RETURN, RETLW or RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The st ack operates as a circular buf fer . This means that

af ter the st ack ha s be en PUSHed ei ght time s, th e nin th

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interr upt add res s.

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

PIC16F785/HV785

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addressin g

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit in the

STATUS Register, as shown in Figure 2-4.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESS ING

FIGURE 2-4: DIRECT/INDI RECT ADDRESSING PIC16F785/HV785

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;increment pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

Note: For memory map detail see Figure 2-2.

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1RP0 60

From Opcode IRP File Select Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00H

7FH

Bank 0 Bank 1 Bank 2 B ank 3

PIC16F785/HV785

3.0 CLOCK SOURCES

3.1 Overview

The PIC16F785/HV785 has a wide variety of clock

sources and selection features to allow it to be used in

a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 3-1

illustrates a block diagram of the PIC16F785/HV785

clock sources.

Clock sources can be configured from external oscilla-

tors, quart z crys tal reso nator s, cera mic r eson ator s and

Resistor-Capacitor (RC) circuits. In addition, the sys-

tem clock source can be configured from one of two

internal oscillators, with a choice of speeds selectable

via s oftware. Additional cloc k features include:

• Selectable system clock source between external

or internal via so ftwa re.

• Two-Speed Clock Start-up mode, which mini-

mizes lat enc y betw e en external osc ill ato r start-up

and code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch to the

internal oscillator.

The PIC16F785/HV785 can be configured in one of

eight clock modes.

1. EC – External clock with I/O on RA4.

2. LP – 32.768 kHz Watch Crystal or Ceramic

Reso nator Oscil lator mode.

3. XT – Medium Gain Crystal or Ceramic

Reso nator Oscil lator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on RA4

6. RCIO – External Resistor-Capacitor with I/O on

RA4.

7. INTO SC – Internal Oscill ator with FOSC/4 outp ut

on RA4 and I/O on RA5.

8. INTOSCIO – Internal Oscillator with I/O on RA4

and RA5.

Clock Source modes are configured by the

FOSC<2:0> bits in the Configuration Word (see

Section 15.0 “Special Feat ures of th e CPU”). Once

the PIC16F785/HV785 is programmed and the Clock

Source mode configured, it cannot be changed in the

software.

FIGURE 3-1: PIC16F78 5/HV 78 5 CLOCK SOURCE BLOCK DIAGRAM

(CP U and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, RCIO, EC

System Clock

Postscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

IRCF<2:0>

111

110

101

100

011

010

001

000

31 kHz

Power-up Timer (PWRT)

FOSC<2:0>

(Configuration Word)

SCS

(OSCCON<0>)

Internal Oscillator

(OSCCON<6:4>)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

HFINTOSC

8 MHz

LFINTOSC

31 kHz

PIC16F785/HV785

3.2 Clock Source Modes

Clock Source modes can be classified as external or

internal.

• Extern al C lock m odes re ly on exte rnal c ircuitry fo r

the clock source. Examples are oscillator modules

(EC mode), quartz crystal resonators or ceramic

resonators (LP, XT, and HS modes) and resistor-

cap acitor (RC mode) circui t s .

• Internal clock sources are contained internally

within the PIC16F785/HV785. The PIC16F785/

HV785 has two internal oscillators; the 8 MHz

High-frequency Internal Oscillator (HFINTOSC)

and 31 kHz Low-frequenc y Internal Oscillato r

(LFINTOSC).

The syste m cl oc k can be selected betw ee n ex tern al or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 3.5 “Clock Switching”).

3.3 External Clock Modes

3.3.1 OSCILLATOR START-UP TIMER

(OST)

When the PIC16F785/HV785 is configured for any of

the Crystal Oscillator modes (LP, XT or HS), the Oscil-

lator Start-up Timer (OST) is enabled, which extends

the Reset period to allow the oscillator additional time

to stabilize. The OST counts 1024 clock periods pres-

ent on the OSC1 pin following a Power-on Reset

(POR), a wake from Sleep, or when the Power-up

Timer (PWRT) has expired (if the PWRT is enabled).

During this time, the program counter does not incre-

ment and program execution is suspended. The OST

ensures that the os cill ator ci rcu it, us ing a quartz cry sta l

resonator or ceramic resonator, has started and is pro-

viding a stable s ys tem cl oc k to the PIC 16F 785 /H V78 5.

Table 3-1 shows exam ples where the osci llator delay is

invoked.

In order to mi nimize laten cy between externa l oscillator

start-up and code execution, the Two-Speed Clock

S tart -up mode can be s elected (see Section 3.6 “T wo-

Speed Clock Start-up Mode”).

TABLE 3-1: OSCILLATOR DELAY EXAMPLES

3.3.2 EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source.

When operating in this mode, an external clock source

is connected to OSC1 pin and the RA4 pin is available

for general purpose I/O. Figure 3-2 shows the pin

connec tio ns for EC mode.

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC16F785/HV785 design is

fully static, stopping the external clock input will have

the effect of halting the device while leaving all data

intact. Upon restarting the external clock, the device

will resume operation as if no time had elapsed.

FIGURE 3-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Switch Fr om Switch

To Frequency Oscillator Delay Comme nts

Sleep/POR INTRC

INTOSC 31 kHz

125 kHz-8 MHz 5μs-10 μs (approx.)

CPU Start-up(1) Following a wake-up from Sleep mode or

POR, CPU st art-up is invoked to allow the

CPU to become ready for code execution.

Sleep EC, RC DC – 20 MHz

LFINTOSC

(31 kHz) EC, RC DC – 20 MHz

Sleep/POR LP, XT,

HS 31 kHz-20 MHz 1024 Clock Cycles

(OST)

LFINTOSC

(31 kHz) INTOSC 125 kHz-8 MHz 1 μs (approx.)

Note 1: The 5 μs-10 μs start-up delay is based on a 1 MHz System Clock.

OSC1/CLKIN

I/O (OSC2)

RA4

Clock from

Ext. System PIC16F785/HV785

PIC16F785/HV785

3.3.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

the OSC1 and OSC2 pins (Figure 3-1). The mode

selects a low, medium or high gain setting of the inter-

nal inverter-amplifier to support various resonator

types and speed.

LP Oscillator mode selects the lowest gain setting of

the internal inverter-amplifier. LP mode current con-

sumption is the least of the three modes. This mode is

best suited to drive resonators with a low drive level

specification, for example, tuning fork type crystals.

XT Oscillator mode selects the intermediate gain set-

ting of the internal inverter-amplifier. XT mode current

consumption is the medium of the three modes. This

mode i s b es t suit e d t o dr i ve re so na tor s wi th a medi um

drive level specification, for example, AT-cut quartz

crystal re sonat ors.

HS Oscillator mode selects the highest gain setting of

the internal inverter-amplifier. HS mode current con-

sumpti on is the hig hes t of the thre e mo des . This mod e

is best suited for resonators that require a high drive

setting, for example, AT-cut quartz crystal resonators or

ceramic resonators.

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 3-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 3-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

TABLE 3-2: CERAMIC RESONATORS

Note 1: Quartz crystal characteristics vary

according to type, package and manufac-

turer. The user should consult the manu-

facturer data sheets for specifications

and recommended application.

2: Always veri fy os ci lla tor pe rform an ce ov er

the VDD and temperature range that is

expected for the application.

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

Quartz

OSC2

RS(1)

OSC1

RF(2) Sleep

To Internal

Logic

Crystal

PIC16F785/HV785

Mode Freq. OSC1 (C1) OSC2 (C2)

XT 455 kHz

2.0 MHz 68-100 pF

15-68 pF 68-100 pF

15-68 pF

HS 4.0 MHz

8.0 MHz

16.0 MHz

10-68 pF

15-68 pF

10-22 pF

10-68 pF

15-68 pF

10-22 pF

Note: These values are for design guidance

only. See notes following this table.

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation (typical value 1 MΩ).

C2 Ceramic

OSC2

RS(1)

OSC1

RF(2) Sleep

To Internal

Logic

RP(3)

Resonator

PIC16F785/HV785

TABLE 3-3: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

3.3.4 EXTERNAL RC MODES

The External Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes, RC and RCIO.

In RC mode, the RC circuit connects to the OSC1 pin.

The OSC2/CLKOUT pin outputs the RC oscillator

frequency divided by 4. This signal may be used to

provide a clock for external circuitry, synchronization,

calibration, test or other application requirements.

Figure 3-5 shows the RC mode connections.

FIGURE 3-5: RC MODE

In RCIO mode, the RC circuit is connected to the OSC1

pin. The OSC2 pin becomes an additional general

purpose I/O pin. The I/O pin becomes bit 4 of PORTA

(RA4). Figure 3-6 shows the RCIO mode connections.

FIGURE 3-6: RCIO MODE

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT)

values and the operating temperature. In addition to

this, the oscillator frequency will vary from unit-to-unit

due to normal threshold voltage. Furthermore, the dif-

ference in lead frame capacitance between package

types will also affect the oscillation frequency or low

CEXT values. The user also needs to take into account

vari ation d ue to to leranc e of ext ernal R C compone nts

used.

Osc Type Crystal

Freq. Cap. Range

C1 Cap. Range

LP 32 kHz 15-33 pF 15-33 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15-33 pF 15-33 pF

4 MHz 15-33 pF 15-33 pF

HS 4 MHz 15-33 pF 15-33 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

Note: These values are for design guidance

only. See notes following this table.

Note 1: Hi gher capacit ance incr eases the st ability

of the oscillator, but also increases the

start - up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

3: RS may be required to avoid overdriving

crystals with low dr iv e lev el spe ci fic ati on.

OSC2/CLKOUT

CEXT

REXT OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3. 0 V)

CEXT > 20 pF

PIC16F785/HV785

CEXT

REXT

OSC1 Internal

Clock

VDD

VSS I/O (OSC2)

RA4

PIC16F785/HV785

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)

CEXT > 20 pF

PIC16F785/HV785

3.4 Internal Clock Modes

The PIC16F785/HV785 has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-frequency Internal Oscil-

lator) is factory calibrated and operates at

8 MHz. The f requenc y o f the HFINT OSC can be

user adjusted ±12% via software using the

OSCTUNE register (Register 3-1).

2. The LFINTOSC (Low-frequency Internal

Oscillator) is uncalibrated and operates at

approximately 31 kHz.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select (IRCF)

bits.

The syste m cl oc k can be selected betw ee n ex tern al or

inte rna l clock sources via the Syst em Clock S ele ction

(SCS) bit (see Section 3.5 “Clock Switching”).

3.4.1 INTRC AND INTRCIO MODES

The INTRC and INTRCIO modes conf igure th e internal

oscill ator s as th e system cloc k sou rce when the devic e

is programmed using the Oscillator Selection (FOSC)

bits i n the Configur ation Word (Register 12 -1).

In INTRC mode, the OSC1 pin is available for general

purpose I/O. The OSC2/CLKOUT pin outputs the

select ed internal osci lla tor freq uen cy div ide d by 4. The

CLKOUT signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements.

In INTRCIO mode, the OSC1 and OSC2 pins are

available for general purpose I/O.

3.4.2 HFINTOSC

The High-frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered

approxi matel y ±12% via sof tware us ing the OSCTUN E

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). One of seven

frequencies can be selected via software using the

IRCF bits (see Section 3.4.4 “Frequency Select Bits

(IRCF)”).

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz (IRCF ≠ 000) as the

system clock source (SCS = 1) or when Two-Speed

Start-up is enabled (IESO = 1 and IRCF ≠ 000).

The HF Internal Oscillator (HTS) bit, in the OSCCON

Regis ter, indicat es w het her the HFINT O SC is s t ab le or

not.

3.4.2.1 Calibration Bits

The 8 MHz High-frequency Internal Oscillator (HFIN-

TOSC) is factory calibrated. The HFINTOSC calibra-

tion bits are stored in the Calibration Word (CALIB)

located in program memory location 2008h. The Cali-

bration Word is not erased using the specified bulk

erase sequence in the “PIC16F785/HV785 Memory

Programming Specification” (DS41237) and does not

require reprogramming. Reference the “PIC16F785/

HV785 Memory Programming Specification”

(DS41237) for more information on the Calibration

Word register.

Note: Address 2008h is beyond the user program

memory space. It belongs to the special

Configuration Memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/HV785

Memory Programming Specification”

(DS41237) fo r more in formatio n.

PIC16F785/HV785

3.4.2.2 OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

The OSCTUNE register has a nominal tuning range of

±12%. The default value of the OSCTUNE register is

‘0’. The valu e is a 5-bit two’ s comple ment numbe r . Due

to process variation, the monotonicity and frequency

step cannot be specified.

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. The HFINTOSC clock will stabilize within

1 ms. Code executi on continues during this sh ift. The re

is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by

the change in frequency.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximu m frequency

01110 =

•

00001 =

00000 = Center frequency. Oscillator module is running at the calibrated frequency.

11111 =

•

10000 = Minimum frequency

PIC16F785/HV785

3.4.3 LFINTOSC

The Low-frequency Internal Oscillator (LFINTOSC) is

an uncalibrated (approximate) 31 kHz internal clock

source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). 31 kHz can be

selected via software using the IRCF bits (see

Section 3.4.4 “Frequency Select Bits (IRCF)”). The

LFINTOSC is also the frequency for the Power-up

Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe

Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF = 000) as the s ystem cloc k sourc e (SCS = 1), or

when any of the following are enabled:

• Two-Speed Start-up (IESO = 1 and IRCF = 000)

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit, in the OSCCON

not.

3.4.4 FREQUENCY SELECT BITS (IRCF)

The outpu t of the 8 MHz HFINT OSC and 31 kHz LFIN-

TOSC connect to a postscaler and multiplexer (see

Figure 3-1). The Internal Oscillator Frequency select

bits IRCF<2 :0> in the OSCCON Register select the fre-

quency output of the internal oscillators. One of eight

frequencies can be selected via software:

•8 MHz

• 4 MHz (Default after Reset)

•2 MHz

•1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

•31 kHz

3.4.5 HF AND LF INTOSC CLOCK

SWITCH TIMING

When switching between the LFINTOSC and the HFIN-

T OSC, the ne w osc il lat or ma y al read y be shut down to

save power. If this is the case, there is a 10 μs delay

after the IRCF bits are modified before the frequency

selection take s place. The LTS/HTS bits will refl ect the

current active status of the LFINTOSC and the HFIN-

TOSC oscillators. The timing of a frequen cy selection i s

as follows:

1. IRCF bits are modified.

2. If the new clock is shut down, a 10 μs clock start-

up delay is started.

3. Clock swi tch circu itry waits for a fallin g edge of

the cu rrent clock.

4. CLKOUT is held low and the clock switch

circuit ry w ai t s for a rising edg e in the new clock.

5. CLKOUT is now connected with the new clock.

HTS/LTS bits are updated as required.

6. Clock swi tch is complete.

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and the new frequencies are derived from the

HFINTOSC via the postscaler and multiplexer.

Note: Foll owin g any Reset , t he IRC F bit s are s et

to ‘110’ and the frequency selection is

forc ed to 4 MHz. T he us er can mo dif y the

IRCF bits to select a different frequency.

Note: Care must be taken to ensure an invalid

voltage or frequency selection is not

selected. An example of an invalid config-

uration is selecting 8 MHz when VDD is

2.0V.

PIC16F785/HV785

3.5 Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit.

3.5.1 SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit, in the OSCCON

for the CPU and peripherals.

• When SCS = 0, the system clock source is deter-

mined by c onfiguration of the FOSC<2:0> bits in

Configuration Word (CONFIG).

• When SCS = 1, the system clock source is cho-

sen by the internal oscillator frequency selected

by t h e IRCF bits. After a Reset, SCS is always

cleared.

3.5.2 O SCIL LATOR START-UP TIME-OU T

STATUS BIT

The Oscillator Start-up Time-out Status (OSTS) bit,

(OSCCON<3>), indicates whether the system clock is

running from the external clock source as defined by

the FOSC bits, or from internal clock source. In partic-

ular, OSTS indicates that the Oscillator Start-up Timer

(OST) has timed out for LP, XT or HS modes.

3.6 Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

S tar t-up will remove the extern al oscillat or start-up time

from the time spent awake and can reduce the overall

power consumption of the device.

This mode allows the application to wake-up from

Sleep, p erfor m a f ew inst ructio ns us ing th e IN TO SC as

the clock source and go back to Sleep without waiting

for the primary oscillator to become stable.

When the PIC16F785/HV785 is configured for LP, XT

or HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 3.3.1 “Oscillator Start-up

Timer (OST)”). The OST timer will suspend program

execution until 1024 oscillations are counted. Two-

Spee d S tart-up mod e minim izes the delay in code ex e-

cution by operating from the internal oscillator as the

OST is counting. When the OST count reaches 1024

and the OSTS bit in the OSCCON Register is set, pro-

gram execution switches to the external oscillator.

3.6.1 TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the follow-

ing settings:

• IESO = 1 (CONFIG<10>) Internal/External Switch

Over bit.

•SCS = 0.

•FOSC configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Pow er-on Reset (POR) and, if enabl ed, after

PWRT has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be any-

thing other than LP, XT or HS mode, then Two-Speed

St art -up is disa bled. This is beca us e the ex tern al cl oc k

oscillator does not require any stabilization time after

POR or an exit from Sleep.

3.6.2 TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscill ator at the frequency s et in the I RCF bits (in

the OSCCON Register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the inter-

nal oscillator.

5. OSTS is set.

6. System cloc k held lo w until the next fallin g edg e

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

3.6.3 CHE CKI NG EXTERNA L/I NTERNA L

CLOCK STATUS

Checking the state of the OSTS bit in the OSCCON

ning from the external clock source as defined by the

FOSC bits in the Configuration Word (CONFIG) or the

internal oscillator.

Note: Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bit. The user can monitor the

OSTS (OSCCON<3>) to determine the

current system cl ock source.

Note: Executing a SLEEP instruction will abort

the Osci llator Start-up Time and wil l ca use

the OSTS bit in the OSCCON Register to

remain clear.

PIC16F785/HV785

FIGURE 3-7: TWO-SPEED START-UP

3.7 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to

allow the device to continue to operate in the event of

an oscillator failure. The FSCM can detect oscillator

failure at any point after the device has exited a Reset

or Sleep condition and the Oscillator Start-up Timer

(OST) has expired.

FIGURE 3-8: FSCM BLOCK DIAGRAM

The FSCM function is enabled by setting the FCMEN

bit in Configuration Word (CONFIG). It is applicable to

all external clock options (LP, XT, HS, EC, RC or I/O

modes).

In the event of an external clock failure, the FSCM will

set the OSFIF bit in the PIR1 Register an d generate an

oscill ato r fail int errup t if th e O SFIE bi t in th e PIE1 Reg-

ister is set. The d evice will t hen switch the system clock

to the internal oscillator . The system clock will continue

to come from the internal oscillator unless the external

clock recovers and the Fail-Safe condition is exited.

The frequency of the internal oscillator will depend

upon the value contained in the IRCF bits

(OSCCON<6:4>). Upon entering the Fail-Safe condi-

tion, the OSTS bit in the OSCCON Register is automat-

ically cleared to reflect that the internal oscillator is

active and the WDT is cleared. The SCS bit in the OSC-

CON Regi ster is not u pdated. Ena bling FSCM does not

affect the LTS bit.

The FSCM sample clock is generated by dividing the

LFINTOSC clock by 64. This will allow enough time

between FSCM sample clocks for a system clock edge

to occur. Figure 3-8 shows the FSCM block diagram.

On the rising edge of the sample clock, the monitoring

latch ( CM = 0) will be cleared. On a falling edge of the

primary system clock, the monitoring latch will be set

(CM = 1). In th e e ve nt t hat a fal ling edge o f th e s am pl e

clock occurs, and the monitoring latch is not set, a clock

failure has been detected. The assigned internal

oscillator is enabled when FSCM is enabled as

reflected by the IRCF bits.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

0 1 1022 1023

PC PC + 1 PC + 2

TOSTT

INTOSC

OSC1

OSC2

Program Counter

System C loc k

Primary

LFINTOSC ÷ 64

31 kHz

(~32 μs) 488 Hz

(~2 ms )

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Oscillator

Clock

Note: Two-Speed Start-up is automatically

enabled when the Fail-Safe Clock Monitor

mode is enabled.

PIC16F785/HV785

3.7.1 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the

execution of a SLEEP instruction, or a modification of

the SCS bit. While in Fail-Safe condition, the

PIC16F785/HV785 uses the internal oscillator as the

system clock source. The IRCF bits in the OSCCON

frequency without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the

OSFIF flag can be cleared.

FIGURE 3-9: FSCM TIMING DIAGRAM

3.7.2 RESET OR WAKE - UP FROM SLEE P

The FS CM is designed to detect osc illator failu re at any

point after the device has exited a Reset or Sleep

condition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

For LP, XT or HS mode, the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time; a false clock failure may be

detected (see Figure 3-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable (the

OST has timed out). This is identical to Two-Speed

Start-up mode. Once the external oscillator is stable,

the LFINTOSC returns to its role as the FSCM source.

OSCFIF

CM Output

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The system clock is normally at a much higher frequency tha n the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test CM Test CM Test

Note: Due to the wide ran ge of osc illator st art-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount o f tim e, the u se r sh oul d ch ec k th e

OSTS bit in the OSCCON Register to ver-

ify the oscillator start-up and system clock

switchover has successfully completed.

PIC16F785/HV785

U-0 R/W-1 R/W-1 R/W-0 R-q R-0 R-0 R/W-0

— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits

000 =31kHz

001 =125kHz

010 =250kHz

011 =500kHz

100 =1MHz

101 =2MHz

110 =4MHz

111 =8MHz

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Device is running from the external system clock defined by FOSC<2:0>

0 = Device is running fro m the internal system clock (HFINTOSC or LFINTOSC)

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 HTS: HFINTOSC ( High Frequency – 8 MHz to 125 kHz) Status bit

1 = HFINTOSC is stable

0 = HFINTOSC is not stable

bit 1 LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

1 = LFINTOSC is stable

0 = LFINTOSC is not stable

bit 0 SCS: Syste m Clock Select bit

1 = Internal oscillator is used for system clock

0 = Clock source defined by FOSC<2:0>

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled, otherwise this bit resets to ‘1’

PIC16F785/HV785

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 q000

OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’, q = value depends on condition. Shaded cells

are not used by oscillators.

Note 1: See Register 15.2 for operation of all Configuration Word bits.

PIC16F785/HV785

4.0 I/O PORTS

There are seventee n general p urpose I/O pins an d one

input only pin available. Depending on which peripher-

als are enabled, some or all of the pins may not be

available as general purpose I/O. In general, when a

peripheral is enabled, the associated pin may not be

used as a general purpose I/O pin.

4.1 PORTA and TRISA Registers

PORTA is a 6-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA (Register 4-2).

Setting a TRISA bit (= 1) will make the corresponding

PORTA pin an input (i.e., put the corresponding out put

driver in a High-Impedance mode). Clearing a TRISA bit

(= 0) will make the corresponding PORTA pin an output

(i.e., put the contents of the output latch on the selected

pin). The exception is RA3, which is input only and its

TRIS bit will always read as ‘1’. Example 4-1 shows how

to initialize PORTA.

Reading the PORTA register (Register 4-1) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read; this value is modified and then

written to the port data latch. RA3 reads ‘0’ when

MCLRE = 1.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

inputs. I/O pins configured as analog inputs always

read ‘0’.

When R A1 is conf igured as a voltage ref erence outpu t,

the RA1 digital output driver will automatically be

disabled while not affecting the TRISA<1> value.

EXAMPLE 4-1: INITIALIZI NG PORTA

Note: The AN SEL0 (91h) registe r must be initia l-

ized to configure an analog channel as a

digital input. Pins configured as analog

inputs will read ‘0’.

BCF STATUS,RP0 ;Bank 0

BCF STATUS,RP1 ;

CLRF PORTA ;Init PORTA

MOVLW F8h ;Set RA<2:0> to

ANDWF ANSEL0,f ; digital I/O

BSF STATUS,RP0 ;Bank 1

MOVLW 0Ch ;Set RA<3:2> as inputs

MOVWF TRISA ; and set RA<5:4,1:0>

; as outputs

BCF STATUS,RP0 ;Bank 0

U-0 U-0 R/W-x R/W-x(1) R/W-x R/W-x(1) R/W-x(1) R/W-x(1)

— — RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘ 0’

bit 5-0 RA<5:0>: PORTA I/O Pin bits

1 = Port pin is greater than VIH

0 = Port pin is less than VIL

Note 1: Data latches are un kno wn af ter a POR, but each port bit reads ‘0’ when the corresponding

analog select bit is ‘1’ (see Register 12-1).

PIC16F785/HV785

4.2 Additional Pin Functions

Every PORTA pin on the PIC16F785/HV785 has an

interrupt-on-change option and a weak pull-up option.

The next three sections describe these functions.

4.2.1 WEAK PULL-UPS

Each of the PORT A pins has an individually configurable

internal weak pull-up. Control bits WPUAx enable or

disable each pull-up. Refe r to Register 4-3. Each w eak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are disabled on a

Power-on Reset by the RAPU bit in the (OPTION

enabled when RA3 is configured as MCLR.

U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1

— — TRISA5(2) TRISA4(2) TRISA3(1) TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit(1), (2)

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— WPUA5(4) WPUA4(4) WPUA3(3) WPUA2 WPUA1 WPUA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISA = 0).

3: The R A3 pul l-up is au tomatically enabled when configured as MCLR in the Confi guration Word.

4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

PIC16F785/HV785

4.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as

an interrupt-on-change pin. Control bits IOCAx enable

or disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

comp ared w ith the old value la tched on the last rea d of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d t ogether to s et , t he PORTA Change Interrupt fla g

bit (RAIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the inter-

rupt by:

a) Any read or write of PORTA. This will end the

mismatch condition, then,

b) Clear the flag bit RAIF.

A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RA IF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared. The latch holding the

last read value is neither affected by an MCLR nor BOR

Reset. Af ter these reset s, the RAIF flag will continu e to

be set if a mismatch is present.

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——IOCA5

(2) IOCA4(2) IOCA3 IOCA2 IOCA1 IOCA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bits(2)

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

PIC16F785/HV785

4.2.3 PORTA PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTA pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individ-

ual functions such as the comparator or the A/D, refer

to the appropriate section in this Data Sheet.

4.2.3.1 RA0/AN0/C1IN+/ICSPDAT

Figure 4-1 shows th e diagr am for thi s pin. Th e RA0 pi n

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

• Analog input to Comparator 1

• In-Circuit Serial Programming™ data

FIGURE 4-1: BLOCK DIAGRAM OF RA0

4.2.3.2 RA1/AN1/C12IN0-/VREF/ICSPCLK

Figur e 4-1 sh ows the di agram fo r this pi n. The RA1 pi n

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

• Analog input to Comparators 1 and 2

• Voltage reference input for the A/D

• Buffered or unbuffered voltage reference output

• In-Circuit Serial Programming clock

FIGURE 4-2: BLOCK DIAGRAM OF RA1

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

RD PORTA

PORTA

TRISA

IOCA

To Comparator

To A/D Converter

ANS0

RAPU

ANS0

Interrupt-on-

change

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

PORTA

TRISA

IOCA

Interrupt-on-

To Comparato rs

To A/D Converter

RAPU

ANS1

CVROE

VROE*VREN

VROUT

RD PORTA

change

PIC16F785/HV785

4.2.3.3 RA2/AN2/T0CKI/INT/C1OUT

Figure 4-3 shows th e diagr am f or this pin. Th e RA2 pi n

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

• Clock input for TMR0

• External edge triggered interrupt

• Digital output from Comparator 1

FIGURE 4-3: BLOCK DIAGRAM OF RA2

4.2.3.4 RA3/MCLR/VPP

Figur e 4-4 sh ows the di agram fo r this pi n. The RA3 pi n

is configurable to function as one of the following:

• General purpose input

• Master Clear Reset with weak pull-up

FIGURE 4-4: BLOCK DIAGRAM OF RA3

I/O pin

VDD

VSS

VDD

Weak

ANS2

Data Bus

WPUA

PORTA

TRISA

IOCA

To A/D Converter

To INT

To TMR0

ANS2

RAPU

Interrupt-on-

Change

C1OUT

C1OE

RD PORTA

Input

VSS

PORTA

IOCA

Reset MCLRE

TRISA VSS

MCLRE

VDD

Weak

MCLRE

Interrupt-on-

Change

RD PORTA

Data Bus

WPUA

WPUA RAPU

PIC16F785/HV785

4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT

Figure 4-5 shows th e diagr am for thi s pin. Th e RA4 pi n

is configurable to function as one of the following:

• General purpose I/O

• Analog input for the A/D

• TMR 1 gate input

• Crystal/resonator connection

• Clock output

FIGURE 4-5: BLOCK DIAGRAM OF RA4

4.2.3.6 RA5/T1CKI/OSC1/CLKIN

Figur e 4-6 sh ows the di agram fo r this pi n. The RA5 pi n

is configurable to function as one of the following:

• General purpose I/O

• TMR1 clock input

• Crystal/resonator connection

• Clock input

FIGURE 4-6: BLOCK DIAGRAM OF RA5

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

PORTA

TRISA

IOCA

FOSC/4

To A/D Converter

Oscillator

Circuit

OSC1

CLKOUT

Enable

ANS3

RAPU

To T1G

INTOSC/

RC/EC(2)

CLK(1)

Modes

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option.

Interrupt-on-

CHANGE

ANS3

RD PORTA

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

PORTA

TRISA

IOCA

To TMR1 or CLKGEN

INTOSC

Mode

INTOSC

Mode

RAPU

OSC2

(2)

Note 1: CLK modes are XT, HS, LP and LPTMR1.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

CLK modes(1)

Interrupt-on-

Change

Oscillator

Circuit

RD PORTA

PIC16F785/HV785

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

othe r Resets

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000

CM2CON1 MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

REFCON — — BGST VRBB VREN VROE CVROE —--00 000- --00 000-

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000

TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

WPUA —— WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC16F785/HV785

4.3 PORTB and TRISB Registers

PORTB is a 4-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB (Register 4-

6). Setting a TRISB bit (= 1) will make the correspond-

ing PORTB pin an input (i.e., put the corresponding

output driver in a High-Impedance mode). Clearing a

TRISB bit (= 0) will make the corresponding PORTB

pin an output (i.e., put the contents of the output latch

on the se lec t e d pi n). Ex am pl e 4-2 shows how to initial-

ize PORTB.

Reading the PORTB register (Register 4-5) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then writ-

ten to the port data latch.

Pin RB6 is an o pe n dra in out put. All other PORTB pins

have full CMOS output drivers.

The TRISB register controls the direction of the

PORTB pins, even when they are being used as ana-

log inputs. The user must ensure the bits in the TRISB

input s. I/O pin s co nfigure d as analo g inpu t alw ays read

‘0’.

EXAMPLE 4-2: INITIALIZING PORTB

Note: The AN SEL1 (93h) registe r must be initia l-

ized to configure an analog channel as a

digital input. Pins configured as analog

inputs will read ‘0’.

BCF STATUS,RP0 ;Bank 0

BCF STATUS,RP1 ;

CLRF PORTB ;Init PORTB

BSF STATUS,RP0 ;Bank 1

BCF ANSEL1,2 ;digital I/O - RB4

BCF ANSEL1,3 ;digital I/O - RB5

MOVLW 30h ;Set RB<5:4> as inputs

MOVWF TRISB ;and set RB<7:6>

;as outputs

BCF STATUS,RP0 ;Bank 0

R/W-x R/W-x R/W-x(1) R/W-x(1) U-0 U-0 U-0 U-0

RB7 RB6 RB5 RB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 RB<7:4>: PORTB Gene ra l Purp os e I/O Pi n bits

1 = Port pin is gr eater than VIH

0 = Port pin is le ss than VIL

bit 3-0 Unimplemented: Re ad as ‘0’

Note 1: Data latches are un known after a PO R, but each port bit reads ‘ 0’ when the cor respond ing analog se lect bit is

‘1’ (see Reg i st er 12-2 on page 82).

R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0

TRISB7 TRISB6 TRISB5 TRISB4 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)

0 = PORTB pin configured as an output

bit 3-0 Unimplemented: Re ad as ‘0’

PIC16F785/HV785

4.3.1 PORTB PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTB pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individ-

ual functions such as the PWM, operational amplifier,

or the A/D, refer to the appropriate section in this Data

Sheet.

4.3.1.1 RB4/AN10/OP2-

The RB4/AN10/OP2- pin is configurable to function as

one of the following:

• General purpose I/O

• Analog input to the A/D

• Analog input to Op Amp 2

4.3.1.2 RB5/AN11/OP2+

The RB5/AN11/OP2+ pin is confi gu r abl e to fun ct ion as

one of the following:

• General purpose I/O

• Analog input to the A/D

• Analog input to Op Amp 2

FIGURE 4-7: BLOCK DIAGRAM OF RB4

AND RB5

4.3.1.3 RB6

The RB6 pin is configurable to f unction as the fo llowing:

• Open drain general purpose I/O

FIGURE 4-8: BLOCK DIAGRAM OF RB6

4.3.1.4 RB7/SYNC

The RB7/SYNC pin is configurable to function as one

of the fo llowing:

• General purpose I/O

• PWM synchron ization input and ou tput

FIGURE 4-9: BLOCK DIAGRAM OF RB7

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

To A/D Converter

PORTB

ANS10 (RB4)

ANS11 (RB5 )

To Op Amp 2

I/O Pin

VSS

Data Bus

PORTB

TRISB

VSS

PORTB

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

Sync out

PWM Master

to PWM Sync Input

PH1EN

PH2EN

PORTB

PIC16F785/HV785

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

ANSEL1 — — — —ANS11ANS10ANS9 ANS8 ---- 1111 ---- 1111

OPA2CON OPAON — — — — — — — 0--- ---- 0--- ----

PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----

PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 0000 0000

TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

PIC16F785/HV785

4.4 PORTC and TRISC Registers

PORTC is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISC (Register 4-

8). Setting a TRISC bit (= 1) will make the correspond-

ing PORTC pin an input (i.e., put the corresponding

output driver in a High-Impedance mode). Clearing a

TRISC bit (= 0) will make the corresponding PORTC

pin an output (i.e., put the contents of the output latch

on the se lec t e d pi n). Ex am pl e 4-3 shows how to initial-

ize PORTC.

Reading the PORTC register (Register 4-7) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the port data latch.

The TRISC register controls the direction of the

PORTC pins, even when they are being used as

analog inputs. The user must ensure the bits in the

TRISC regis ter are main tai ned s et wh en usin g t hem a s

analog inputs. I/O pins configured as analog input

always read ‘0’.

When RC4 or RC5 is configured as an op amp output,

the corres po ndi ng R C 4 o r RC5 dig it a l output driver w il l

automatically be disabled regardless of the TRISC<4>

or TRISC<5> value.

EXAMPLE 4-3: INITIALIZING PORTC

Note: The ANSEL0 (91h) and ANSEL1 (93h)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

BCF STATUS,RP0 ;Bank 0

BCF STATUS,RP1

CLRF PORTC ;Init PORTC

BSF STATUS,RP0 ;Bank 1

CLRF ANSEL0 ;digital I/O

CLRF ANSEL1 ;digital I/O

MOVLW 0Ch ;Set RC<3:2> as inputs

MOVWF TRISC ; and set RC<5:4,1:0>

; as outputs

BCF STATUS,RP0 ;Bank 0

R/W-x(1) R/W-x(1) R/W-x R/W-x R/W-x(1) R/W-x(1) R/W-x(1) R/W-x(1)

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is greater than VIH

0 = Port pin is less than VIL

Note 1: Data la t ch es are unk no w n afte r a PO R , bu t ea ch po rt bi t r ea ds ‘0’ when the corresponding analog select bit

is ‘1’ (s e e R e gi st ers 12-1 and 12-2 on page 82).

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

PIC16F785/HV785

4.4.1 PORTC PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTC pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individ-

ual functions such as the comparator or the A/D, refer

to the appropriate section in this Data Sheet.

4.4.1.1 RC0/AN4/C2IN+

The RC0 is configurable to function as one of the

following:

• General purpose I/O

• Analog input for t he A/ D Converter

• Non-inverting input to C omparator 2

4.4.1.2 RC6/AN8/OP1-

The RC6/AN8/OP1- pin is configurable to function as

one of the following:

• General purpose I/O

• Analog input for the A/D

• Inverting input for Op Amp 1

4.4.1.3 RC7/AN9/OP1+

The RC7/AN9/OP1+ pin is configurable to function as

one of the following:

• General purpose I/O

• Analog input for the A/D

• Non-inverting input for Op Amp 1

FIGURE 4-10: BLOCK DIAGRAM OF

RC0, RC6 AND RC7

4.4.1.4 RC1/AN5/C12IN1-/PH1

The RC1 is configurable to function as one of the

following:

• General purpose I/O

• Analog input fo r the A/D C onverter

• Analog input to Comparators 1 and 2

• Digital output from the Two-Phase PWM

FIGURE 4-11: BLOCK DIAGRAM OF RC1

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To A/D Converter

ANS4 (RC0)

ANS8 (RC6)

To Comparators (RC0)

To Op Amp1 (RC6, RC7)

PORTC

ANS9 (RC7)

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To A/D Converter

ANS5

To Comparators

PH1

PH1EN

PORTC

PIC16F785/HV785

4.4.1.5 RC2/AN6/C12IN2-/OP2

The RC2 is configurable to function as one of the

following:

• General purpose I/O

• Analog input for t he A/ D Converter

• Analog input to Comparators 1 and 2

• Analog outp ut fr om Op A mp 2

4.4.1.6 RC3/AN7/C12IN3-/OP1

The RC3 is configurable to function as one of the

following:

• General purpose I/O

• Analog input for t he A/ D Converter

• Analog input to Comparators 1 and 2

• Analog output for Op Amp 1

FIGURE 4-12: BLOCK DIAGRAM OF RC2

AND RC3

4.4.1.7 RC4/C2OUT/PH2

The RC4 is configurable to function as one of the

following:

• General purpose I/O

• Digital ou tput from Compa rator 2

• Digital output from the Two-Phase PWM

FIGURE 4-13: BLOCK DIAGRAM OF RC4

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

To A/D Converter

ANS6 (RC2)

ANS7 (RC3)

To Comparators

Op Amp out

OPAON

PORTC

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PH2

C2OUT

PH2EN

C2OE

PORTC

PIC16F785/HV785

4.4.1.8 RC5/CCP1

The RC5 is configurable to function as one of the

following:

• General purpose I/O

• Digital input for the capture/compare

• Digital output for the CCP

FIGURE 4-14: BLOCK DIAGRAM OF RC5

TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

CCP out

CCP1CON<3>

CCP1CON<1>

to CCP Capture Input

PORTC

CCP1CON<2>

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

ANSEL1 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111

CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

OPA1CON OPAON — — — — — — — 0--- ---- 0--- ----

OPA2CON OPAON — — — — — — — 0--- ---- 0--- ----

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F785/HV785

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 5-1 is a bl ock diagram of the T imer0 m odule and

the prescaler shared with the WDT.

5.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit of the

OPTION Register. In Timer mode, the Timer0 module

will increment every instruction cycle (without pres-

caler). If TMR0 is written, the increment is inhibited for

the follow i ng two ins truc t i on cy cl es . The us er can work

around this by writing an adjusted value to the TMR0

Counte r mode is selec ted by setting the T0CS bit of the

OPTION Regi ster. In this mode, the T im er0 module will

increment either on every rising or falling edge of pin

RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge

is determined by the source edge (T0SE) control bit of

the OPTION Register . Clearing the T0SE bit select s the

rising edge.

5.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0

overflow set s th e T0IF bit of t he IN TCON Re giste r. The

interrupt can be masked by clearing the T0IE bit of the

INTCON Register . The T0IF bit must be cleared in soft-

ware by the Timer0 module Interrupt Service Routine

before re-enabling this interrupt. The Timer0 interrupt

cannot wake the processor from Sleep since the timer

is sh ut-o ff during Sleep.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note 1: Cou nte r m ode ha s s pe ci fic ex tern al cl oc k

requirements.

2: The ANSEL0 (91h) register must be ini-

tialize d to confi gure an analog c hannel a s

a digital input. Pins configured as analog

inputs will read ‘0’.

T0SE(1)

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS<0:2>(1)

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS(1)

Note 1: T0SE, T0CS, PS A, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3).

2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2).

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA(1)

16-bit

Prescaler 16

WDTPS<3:0>(2)

31 kHz

INTRC

SWDTEN

RA2/AN2/T0CKI/INT/C1OUT

PIC16F785/HV785

5.3 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex ternal clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI, with the internal phase clocks, is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2TOSC (and

a small RC delay of 20 ns) and low for at least 2TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

5.4 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this Data Sheet. The prescaler

assignment is controlled in software by the control bit

PSA of the OPTION Register. Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

selectable via the PS<2:0> bits of the OPTION Regis-

ter.

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

5.4.1 SWITCHI NG PRESC ALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). To avoid an unintended device

Reset, the following instruction sequence (Example 5-

1 and Example 5-2) must be executed when changing

the prescaler assignment between Timer0 and WDT.

EXAMPLE 5-1: CHANGING PRESCALER

(TIMER0→WDT)

To change prescaler from the WDT to the TMR0

module , use the se quence sh own in Exa mple 5-2. This

preca ution mus t be t aken even if the WDT is disabled.

EXAMPLE 5-2: CHANGING PRESCALER

(WDT→TIMER0)

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

BCF STATUS,RP0 ;Bank 0

BCF STATUS,RP1 ;

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

; prescaler

BSF STATUS,RP0 ;Bank 1

MOVLW b’00101111’ ;Required if desired

MOVWF OPTION_REG ; PS2:PS0 is

CLRWDT ; 000 or 001

;

MOVLW b’00101xxx’ ;Set postscaler to

MOVWF OPTION_REG ; desired WDT rate

BCF STATUS,RP0 ;Bank 0

CLRWDT ;Clear WDT and

; prescaler

BSF STATUS,RP0 ;Bank 1

BCF STATUS,RP1 ;

MOVLW b’xxxx0xxx’ ;Select TMR0,

; prescale, and

; clock source

MOVWF OPTION_REG ;

BCF STATUS,RP0 ;Bank 0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

other Resets

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u = uncha nge d, x = unknown. Shaded cells are not used by the Timer0 module.

PIC16F785/HV785

6.0 T IMER1 MO DULE WITH GATE

CONTROL

The Timer1 module is the 16-bit counter of the

PIC16F785/HV785. Figure 6-1 shows the basic block

diagram of the Timer1 module. Timer1 has the follow-

ing features:

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optiona l external en able input:

- Selectable gate source; T1G or C2 output

(T1GSS)

- Selec table gate polarity (T1GINV)

• Optional LP oscillator

The Timer1 Control register (T1CON), shown in

select the various features of the Timer1 module.

FIGURE 6-1: TIMER1 ON THE PIC16F785/HV785 BLOCK DIAGRAM

TMR1H TMR1L

Oscillator

T1SYNC

TMR1CS T1CKPS<1:0> Sleep input

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow TMR1(1)

TMR1ON

TMR1GE

TMR1ON

TMR1GE

INTOSC T1OSCEN

Without CLKOUT

SYNCC2OUT(2)

T1GSS

T1GINV

To C2 Comparator Module

TMR1 Clock

*ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI.

Note 1: T imer1 increments on the rising edge.

2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9- 2 on 66).

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

Sleep

PIC16F785/HV785

6.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bi t Timer with presc ale r

• 16-bit Synchronous counter

• 16-bit Asynchronous counter

In Timer mode, Timer1 is incremented on every instruc-

tion cycle. In Counter mode, Timer1 is incremented on

the rising edge of the external clock input T1CKI. In

addition , the Counter mode clock can be synchronized

to the microcontroller system clock or run

asynchronously.

In Count er and Tim er mo dul es , the counter/timer cl oc k

can be gated by the Timer1 gate, which can be

select ed as either the T1G pin or Comp arator 2 outp ut.

If an external clock oscillator is needed (and the

microcontroller is using the LP oscillator or INTOSC

without CLKOUT), Timer1 can use the LP oscillator as

a clock source.

6.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 Register

is set. To enable the interrupt on rollover, you must set

these bits:

• Timer1 Interrupt Enable bit of the PIE1 Register

• PEIE bit of the INTCON Regi ste r

• GIE bit of the INTCON Register

The interrupt is cleared by clearing the TMR1IF in the

Interrupt Service Routine.

6.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits, of the

T1CON Register, control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

6.4 Timer1 Gate

Timer1 gate source is software configurable to be T1G

pin or the output of Comparator 2. This allows the

device to directly time external events using T1G or

analog events using Comparator 2. See CM2CON1

(Register 9-3) for selecting the Timer1 gate source.

This feature can simplify the software for a Delta-Sigma

A/D Converter and many other applications. For more

information on Delta-Sigma A/D Converters, see the

Microchip web site (www.microchip.com).

Timer1 gate can be inverted using the T1GINV bit of

the T1CON Register, whether it originates from the

T1G pin or Comparator 2 output. This configures

Timer1 to measure either the active high or active low

time between events.

FIGURE 6-2: TIMER1 INCREMENTING EDGE

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions.

• Timer1 enabled after POR Reset

• Write to TMR1H or TMR1L

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is hig h then Tim er1 is

enabled (TMR1ON = 1) when T1CKI

is low. See Fig ure 6-2.

Note: The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

Note: TMR1GE bit, of the T1CON Register , must

be set to us e ei ther T1G or C2OUT as the

Timer1 gate source. See Register 9-3 for

more information on selecting the Timer1

gate sou rce .

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: See note box in Section 6.1 “Timer1 Modes of Operation ”.

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 T1GINV: Timer1 Gate Invert bit (1)

1 = Timer1 gate is high true (see bit 6)

0 = Timer1 gate is low true (see bit 6)

bit 6 TMR1GE: Timer1 Gate Enable bit (2)

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 is on if Timer1 gate is true (see bit 7)

0 = Timer1 is on independent of Timer1 gate

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Se lect bits

11 = 1:8 P rescale Value

10 = 1:4 P rescale Value

01 = 1:2 P rescale Value

00 = 1:1 P rescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If System Clock is INTOSC without CLKOUT or LP mode:

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

Else:

This bit is ignored

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from T1CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as

a Timer1 gate source.

PIC16F785/HV785

6.5 Timer1 Operation in

Asynchronous Counter Mode

If con trol bit T 1SYNC of the T1 CON Register i s set, the

external clock i nput is not sy nchroniz ed. The timer co n-

tinues t o incremen t asynch ronous to th e internal p hase

clocks. The timer will continue to run during Sleep and

can gen erate an int errupt on overfl ow, wh ich w ill wak e-

up the processor. However, special precautions in

software are needed to read/write the timer

(Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

6.5.1 READING AND WRITING T IMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an e xternal asy nchronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n min d that re ading t he 16-b it time r in tw o

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For write s, it is re comm ended that the us er simply stop

the timer and write the desired values. A write conten-

tion may occur by writing to the timer registers, while

the register is incrementing. This may produce an

unpredictable value i n the timer register.

6.6 Timer1 Oscillator

A crystal oscillator circuit is built-in between pins OSC1

(input) and OSC2 (amplifier output). It is enabled by

setting control bit T1OSCEN of the T1CON Register.

The osci ll ator is a low pow er oscillator rated for 32 .768

kHz. It will continue to run during Sleep. It is primarily

intended for a 32.768 kHz tuning fork crystal.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is also the LP oscillator or is

derived from the internal oscillator. As with the system

LP oscillator, the user must provide a software time

delay to ensure proper oscillator start-up.

Sleep mode will no t di sa ble the s ys tem c loc k wh en the

system clock and Timer1 share the LP oscillator.

TRISA<5> an d TRISA<4> bits are set when the T imer1

oscillator is enabled. RA5 and RA4 read as ‘0’ and

TRISA<5> and TRISA<4> bits read as ‘1’.

6.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynch ronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To setup the timer to wake the device:

• Timer1 of the T1CON Register must be on

• TMR1IE bit of the PIE1 Register must be set

• PEIE bit of the INTCON Register must be set

The devi ce will wake-u p on an overflow . If the GIE bi t of

the INTCON Register is set, the device will wake-up

and jump to the Interrupt Service Routine (0004h) on

an overflow. If the GIE bit is clear, execution will con-

tinue with the next instruction.

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1

Note: The ANSEL0 (91h) register must be initial-

ized to configure an analog channel as a

digital input. Pins configured as analog

inputs will read ‘0’.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

other R esets

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM2CON1 MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

Legend: – x = unkno wn, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC16F785/HV785

7.0 TIMER2 MODULE

The Timer2 module timer is an 8-bit timer with the

following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16

by 1’s)

• Interrupt on TMR2 match with PR2

Timer2 has a control register shown in Register 7-1.

TMR2 can b e shut-off by cl earing control bit TM R 2ON ,

of the T2CON Register, to minimize power consump-

tion. Figure 7-1 is a simplified block diagram of the

T ime r2 module . The pres caler an d post scaler selectio n

of Timer2 a re controlled by th is register.

7.1 Timer2 Operation

Timer2 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

Reset. The i npu t clo ck (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits

T2CKPS<1:0> o f th e T2 CON Re gister. The match out-

put of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a

TMR2 interru pt (latched in flag bit TMR2IF), of the PIR1

The prescaler and postscaler counters are cleared

when any of the following occurs:

• A write to the TMR2 register

• A write to the T2CON register

• Any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output P ostscale Selec t bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder

bit of the source register.

PIC16F785/HV785

7.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon Reset.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2

Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOR Value on all

othe r Resets

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

PR2 Timer2 Module Period register 1111 1111 1111 1111

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

Legend: – x = unkno wn, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Comparator

TMR2 Sets Fl ag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

PIC16F785/HV785

8.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The Cap ture /C ompare/PWM (C CP ) m od ule co nt ai ns a

16-bit register which can operate as a:

• 16-bit Capture register

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Capture/Compare/PWM Register 1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP. The special event trigger is

generated by a compare match and will clear both

TMR1H and TMR1L registers .

TABLE 8-1: CCP MODE – TIMER

RESOURCES REQUIR ED

CCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’.

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M<3:0>: CCP Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP module)

0001 = Unused (reserved)

0010 = Compare mode, toggle output on match (CCP1IF bit is set)

0011 = Unused (reserved)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mod e, set outp ut on mat ch (CCP 1IF bit is set)

1001 = Compare mode, clear output on match (CC P1IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin

is unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set; TMR1 is reset, and A/D conversion

is started if the A/D module is enabled. CCP1 pin is unaffected.)

110x = PWM mode: CCP1 output is high true.

111x = PWM mode: CCP1 output is low true.

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder

bit of the source register.

PIC16F785/HV785

8.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit val ue of the TMR1 register when an event occu rs

on pin RC5/CCP1. An event is defined as one of the

following and is configured by CCP1CON<3:0>:

• Every falling edge

• Every rising edge

• Ever y 4th rising edg e

• Every 16th rising edge

When a capture is made, the interrupt request flag bit

CCP1IF of the PIR1 Register is set. The interrupt flag

must be cleared in software. If another capture occurs

befor e the value in re gister CCPR1 is read, the old cap-

tured value is overwritten by the new captured value.

8.1.1 CCP1 PIN CONFIGURATION

In Capt ure m od e, th e R C5/CCP1 pin should be co nfi g-

ured as an inpu t by setti ng the TRISC<5 > bit.

FIGURE 8-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

8.1.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture ope ration may not work.

8.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE of the PIE1 Register clear to avoid false inter-

rupts and should clear the flag bit CCP1IF of the PIR1

8.1.4 CCP PRESCALER

There are four prescaler settings specified by bits

CCP1M<3:0> of the CCP1CON Register. Whenever

the CCP module is turned off, or the CCP module is not

in Captu re mode, the presca ler count er is clea red. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d, therefore , the first cap ture may be from

a non-zero prescaler. Example 8-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 8-1: CHANGING BETWEEN

CAPTURE PRESCALERS

8.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC5/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> of the CCP1CON Register. At the

same time, i nterrupt flag b it CCP1IF of the PIR1 Regis-

ter is set.

FIGURE 8-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

Note: If the RC5/CCP1 pin is configured as an

output, a write to the port can cause a

capture co ndition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1<5>)

Capture

Enable

Q’s CCP1CON<3:0>

Prescaler

÷ 1, 4, 16

and

Edge Detect

RC5/CCP1

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<5>)

Match

TRISC<5>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• clear TMR1H and TMR1L registers

• NOT set interrupt flag bit TMR1F (PIR1<0>)

• set the GO/DONE bit (ADCON0<1>)

RC5/CCP1 4

PIC16F785/HV785

8.2.1 CCP1 PIN CONFIGURATION

The user must configure the RC5/CCP1 pin as an

output by clearing the TRISC<5> bit.

8.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not

affected. The CCP1IF bit of the PIR1 Register is set,

causin g a CC P inte rrupt (if enabl ed). See Reg ister 8-1.

8.2.4 SPECIAL EVENT TRIGGER

In this mode (CCP1M<3:0> = 1011), an internal

hardware trigger is generated, which may be used to

initiate an action. See Register 8-1.

The special event trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and CCPR1H, CCPR1L register

pair . The TMR1H, TMR1L register pair is not reset until

the next ris ing edg e of the TMR1 clock. This allow s the

CCPR1H, CCPR1L register pair to effectively provide a

16-bit programmable period register for Timer1. The

special event trigger output also starts an A/D

conversion provided that the A/D module is enabled.

TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Note: Clearing the CCP1CON register will force

the RC5/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

Note 1: The special event trigger from the CCP

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

2: Removing the match condition by chang-

ing the contents of the CCPR1H and

CCPR1L register pair between the clock

edge that generates the special event

trigger and the cloc k ed ge tha t gene rate s

the TMR1 Reset, will preclude the Rese t

from occurring .

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

other R esets

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx uuuu uuuu

CM2CON1 MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u = un ch an ge d , x = unknown. Shaded cells are not used by the Capture, Compare or Timer1

module.

PIC16F785/HV785

8.3 CCP PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP

module produce s up to a 10 -bit resol ution PWM outp ut

on the RC5/CCP1 pin. Since the RC5/CCP1 pin is

multiplex ed wi th the PORTC data latc h, the TRISC< 5>

must b e cleared to make th e RC5/C CP1 pin an output .

Figure 8-3 shows a simplified block diagram of PWM

operation.

For a st ep by step pr ocedure on h ow to set up the CCP

module for PWM operation, see Section 8.3.5 “Setup

for PWM Operatio n”.

FIGURE 8-3: SIMPLIFIED PWM BLOCK

DIAGRAM

The PWM output (Figure 8-4) has a time base

(period) and a time that the output stays high (duty

cycle). The frequency of the PWM is the inverse of

the period (1/period).

FIGURE 8-4: CCP PWM OUTPUT

8.3.1 PW M PE RIOD

The PWM period is specified by writing to the PR2

formula of Equat ion 8-1.

EQUATION 8-1: PWM PERIOD

PWM frequency is defined as 1/[PWM period].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

• The RC5/CCP1 pin is set. (exception: if PWM

duty cycle = 0%, the pin will not be set)

• The PWM duty cycl e is latche d from CCPR1L in to

CCPR1H

Note: Clearing the CCP1CON register will force

the PWM output latch to the default

inactive levels. This is not the PORTC I/O

data l atch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

PR2

(1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer2,

toggle PWM pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concate-

nated with the 2-bit internal Q clock, or 2 bits

of the prescaler, to create the 10-bit time

base.

TRISC<5>

RC5/CCP1

Comparator

Period

Duty Cycle

TMR2 = 0

TMR2 = Duty Cycle

TMR2 = PR2

Note: The Timer2 postscaler (see Section 7.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM peri od PR2()1+[]4TOSC •••=

(TMR2 prescale value)

PIC16F785/HV785

8.3.2 PWM DUTY CYCL E

The PWM duty cycle is specified by writing to the

CCPR1L register and to the DC1B<1:0> bits of the

CCP1CON register. Up to 10 bits of resolution is avail-

able. The CCPR1L contains the eight MSbs and the

DC1B<1:0> contains the two LSbs. In PWM mode,

CCPR1H is a read-only register.

Equation 8-2 is used to calculate the PWM duty cycle

in time.

EQUATION 8-2: PWM DUTY CYCLE

CCPR1L and DC1B<1:0> can be written to at any time,

but the duty cycle value is not latched into CCPR1H

until after a match between PR2 and TMR2 occurs

(i.e. the period is complete). In PWM mode, CCPR1H

is a read- only register.

The CCPR1H register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for gl itchless PWM operation.

Because of the buffering, the module waits until the

timer resets, instead of starting immediately. This

means that enhanced PWM waveforms do not exactly

match the standard PWM waveforms, but are instead

offset by one full instructi on cycle (4 TOSC).

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the RC5/CCP1 pin is cleared.

The maximum PWM resolution is a function of PR2 as

shown by Equation 8-3.

EQUATION 8-3: PWM RESOLUTION

TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM duty cycle CCPR1L:CCP1CON<5:4>() •=

TOSC •(TMR2 prescale value)

Note: If the PWM duty cycle value is longer than

the PWM p eriod, the assigned PWM pin(s)

will remain unchanged.

Resolution 4PR2 1+()[]log 2()log

------------------------------------------ bits=

PWM Frequency 1.22 kHz(1) 4.88 kHz(1) 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

Note 1: Changing duty cycle will cause a glitch.

PIC16F785/HV785

8.3. 3 OPERATION IN SLEEP MODE

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the RC5/CCP1 pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state.

8.3.3.1 OPERATION WITH FAIL-SAFE

CLOCK MONITOR

If the Fai l-Safe Cl ock Monito r is enabl ed, a clo ck failu re

will force the CCP to be clocked from the internal

oscillator clock source, which may have a different

clock frequency than the primary clock.

See Section 3.0 “Clock Sources” for additional

details.

8.3.4 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

8.3.5 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Configure the PWM pin (R C5/CCP1) as an input

by setting the TRISC<5> bit.

2. Set the PWM period by loading the PR2 register .

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

4. Set the PWM du ty cycle by loading the CCPR1 L

5. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit of the PIR1 Register.

• Set the TMR2 prescale value by loading the

T2CKPS bits of the T2CON Register.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON Register.

6. Enable PW M ou tput af ter a new PWM c ycle has

started:

• Wait until TMR 2 overfl ows ( TMR2IF bit is

set).

• Enable the RC5/CCP1 pin output by clearing

the TRISC<5> bit.

TABLE 8-4: REGISTERS ASSOCIATED WITH CCP AND TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOR Value on all

othe r Resets

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

CCPR1L Captur e/Co mpare /P WM R egist er 1 Low Byte xxxx xxxx uuuu uuuu

CCPR1H Cap tur e/Co mpare /P W M Register 1 High Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

PR2 Timer2 Module Period Register 1111 1111 1111 1111

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TMR2 Timer2 Module Register 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.

PIC16F785/HV785

9.0 COMPARATOR MODULE

The Comparator module has two separate voltage

comparators: Comparator 1 (C1) and Comparator 2

(C2).

Each comparator offers the following list of features:

• Control and Configuration register

• Comparator output available externally

• Programmable output polarity

• Interru pt-o n-c han ge fla gs

• Wake-up from Sleep

• Configurable as feedback input to the PWM

• Programmable four input multiplexer

• Programmable two input reference selections

• Programmable speed/power

• Output synchronization to Timer1 clock input

(Comparator C2 only)

9.1 Control Registers

Both comparat ors h ave s eparate contro l and Confi gu-

ration registers: CM1CON0 for C1 and CM2CON0 for

C2. In addition, Comparator C2 has a second control

simultaneous reading of both comparator outputs.

9.1.1 COMPARATOR C1 CONTROL

The CM1CON0 register (shown in Register 9-1)

contains the control and Status bits for the following:

• Comparator enable

• Comparator input selection

• Comparator reference selection

• Outp ut mo de

• Comparator speed

Setting C1ON (CM1CON0<7>) enables Comparator

C1 for operat ion.

Bits C1CH<1:0> of the CM1CON0 Register select the

comp arator input fro m the four analog p ins AN<7:5,1>.

Setting C1R of the CM1CON0 Register selects the

C1VREF output of the comparator voltage reference

module as the reference voltage for the comparator.

Clearing C1R selects the C1IN+ input on the RA0/AN0/

C1IN+/ICSPDAT pin.

The ou t pu t of th e co mpar at or is av ai l abl e in t e rna ll y via

the C1OUT flag of the CM1CON0 Register. To make

the output available for an external connection, the

C1OE bit of the CM1CON0 Register must be set.

The polarity of the comparator output can be inverted

by setting the C1POL bit of the CM1CON0 Register.

Clearing C1POL results in a non-inverted output.

A complete table showing the output state versus input

conditions and the polarity bit is shown in Table 9-1.

TABLE 9-1: C1 OUTPUT STATE VERSUS

INPUT CONDITIONS

C1SP of th e CM 1C ON 0 Reg is ter c on fig ures th e s pee d

of the comparator. When C1SP is set, the comparator

operates at its normal speed. Clearing C1SP operates

the comparator in a slower, low-power mode.

Note: To use AN<7:5,1> as analog inputs the

appropriate bits must be programmed to

‘1’ in the ANSEL0 register.

Input Condition C1POL C1OUT

C1VN > C1VP 00

C1VN < C1VP 01

C1VN > C1VP 11

C1VN < C1VP 10

Note 1: The internal output of the comparator is

latched at the end of each instruction

cycl e. External ou tputs a re not latched .

2: The C1 interrupt will operate correctly

with C1OE set or cleared.

3: To output C1 on RA2/AN2/T0CKI/INT/

C1OUT:(C1OE = 1) and (C1ON = 1) and

(TRISA<2> = 0).

PIC16F785/HV785

FIGURE 9-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Output shown for reference only. For more detail, see Figure 4-3.

MUX

C1POL

C1OUT

To PW M Logic

C1ON(1)

C1SP

C1CH<1:0>2

C1R C1OE

C1VREF MUX

RD_CM1CON0

Set C1IF

C1VN

C1VP

RA2/AN2/T0CKI/INT/C1OUT(2)

RA1/AN1/C12IN0-/VREF/ICSPCLK

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RC3/AN7/C12IN3-/OP1

RA0/AN0/C1IN+/ICSPDAT

Q1 Data Bus

C1POL

Q3*RD_CM1CON0

NRESET

PIC16F785/HV785

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C1ON: Comparator C1 Enable bit

1 = C1 Comparator is ena ble d

0 = C1 Comparator is dis ab led

bit 6 C1OUT: Comparator C1 Output bit

If C1POL = 1 (inverted polarity):

C1OUT = 1, C1VP < C1VN

C1OUT = 0, C1VP > C1VN

If C1POL = 0 (non-inverted polarity):

C1OUT = 1, C1VP > C1VN

C1OUT = 0, C1VP < C1VN

bit 5 C1OE: Comparator C1 Output Enable bit

1 = C1OUT is present on the RA2/AN2/T0CKI/INT/C1OUT pin(1)

0 = C1OUT is internal only

bit 4 C1POL: Comparator C1 Output Polarity Select bit

1 = C1OUT logic is inverted

0 = C1OUT logic is not inverted

bit 3 C1SP: Comparator C1 Speed Select bit

1 = C1 operates in normal speed mode

0 = C1 operates in low-power, slow speed mode

bit 2 C1R: Comparator C1 Referenc e Select bit (non-in v ert ing input )

1 = C1VP connects to C1VREF output

0 = C1VP connects to RA0/AN0/C1IN+/ICSPDAT

bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bits

00 = C1VN of C1 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK

01 = C1VN of C1 connects to RC1/AN5/C12IN1-/PH1

10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2

11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1

Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0).

PIC16F785/HV785

9.1.2 COMPARATOR C2 CONTROL

REGISTERS

The CM2CON0 register is a functional copy of the

CM1CON0 register described in Section 9.1.1 “Com-

p arator C1 Control Register”. A second control regis-

ter, CM2CON1, is also present for control of an

additional synchronizing feature, as well as mirrors of

both comparator outputs.

9.1.2.1 Control Register CM2CON0

The CM2CON0 register, shown in Register 9-2,

cont ains the con trol and Status bits for Comparat or C2.

Setting C2ON of the CM2CON0 Register enables

Comparator C2 for operation.

Bits C2CH<1:0> of the CM2CON0 Register select the

comparator input from the four analog pins, AN<7:5,1>.

C2R of the CM2CON0 Register selects the reference

to be used with the comparator. Setting C2R of the

CM2CON0 Register selects the C2VREF output of the

comp a rator voltag e ref erence modul e as the refer enc e

voltage for the comparator. Clearing C2R selects the

C2IN+ input on the RC0/AN4/C2IN+ pin.

The output of the comparator is available internally via

the C2 OUT bit of the CM 2CON 0 Regis ter. To make the

output available for an external connection, the C2OE

bit of the CM2CON0 Register must be set.

The comparator output, C2OUT, can be inverted by

setting the C2POL bit of the CM2CON0 Register.

Clearing C2POL results in a non-inverted output.

A complete table showing the output state versus input

conditions and the polarity bit is shown in Table 9-2.

TABLE 9-2: C2 OUTPUT STATE VERSUS

INPUT CONDITIONS

C2SP of th e CM 2C ON 0 Reg is ter c on fig ures th e s pee d

of the comparator. When C2SP is set, the comparator

operates at its normal speed. Clearing C2SP operates

the comparator in low-power mode.

FIGURE 9-2: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

Note: To use AN<7:5,1> as analog inputs, the

appropria te bit s m ust be program med t o 1

in the ANSEL0 register.

Input Condition C2POL C2OUT

C2VN > C2VP 00

C2VN < C2VP 01

C2VN > C2VP 11

C2VN < C2VP 10

Note 1: The internal output of the comparator is

latched at the end of each instruction

cycl e. External ou tputs a re not latched .

2: The C2 interrupt will operate correctly

with C2OE set or cleared. An external

output i s no t re qu ired for the C 2 int errup t.

3: For C2 output on RC4/C2OUT/PH2:

(C2OE = 1) and (C2ON = 1) and

(TRISA<4> = 0).

MUX

C2POL

C2OUT To PWM Logic

C2CH<1:0> 2

C2R

From TMR1

Clock

Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

2: T imer1 gate control (see Figure 6-1).

3: Output shown for reference only. For more detail, see Figure 4-13.

C20E

C2VREF MUX

RD_CM2CON0

Q3*RD_CM2CON0

Set C2IF

NRESET

C2VN

C2VP

RC4/C2OUT/PH2(3)

RC0/AN4/C2IN+

RA1/AN1/C12IN0-/VREF/ICSPCLK

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RC3/AN7/C12IN3-/OP1

C2SYNC

SYNCC2OUT(2)

C2POL

Data Bus

MUX

C2ON(1)

C2SP

PIC16F785/HV785

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2ON: Comparator C2 Enable bit

1 = C2 Comparator is ena ble d

0 = C2 Comparator is dis ab led

bit 6 C2OUT: Comparator C2 Output bit

If C2POL = 1 (inverted polarity):

C2OUT = 1, C2VP < C2VN

C2OUT = 0, C2VP > C2VN

If C2POL = 0 (non-inverted polarity):

C2OUT = 1, C2VP > C2VN

C2OUT = 0, C2VP < C2VN

bit 5 C2OE: Comparator C2 Output Enable bit

1 = C2OUT is present on RC4/C2OUT/PH2(1)

0 = C2OUT is internal only

bit 4 C2POL: Comparator C2 Output Polarity Select bit

1 = C2OUT logic is inverted

0 = C2OUT logic is not inverted

bit 3 C2SP: Comparator C2 Speed Select bit

1 = C2 operates in normal speed mode

0 = C2 operates in low power, slow speed mode.

bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)

1 = C2VP connects to C2VREF

0 = C2VP connects to RC0/AN4/C2IN+

bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits

00 = C2VN of C2 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK

01 = C2VN of C2 connects to RC1/AN5/C12IN1-/PH1

10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2

11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1

Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0).

PIC16F785/HV785

9.1.2.2 Control Register CM2CON1

Comparator C2 has one additional feature: its output

can be synchronized to the Timer1 clock input. Setting

C2SYNC of the CM2CON1 Register synchronizes the

output o f Compa rator 2 to the fa lling edge of the T imer1

clock input (see Figure 9-2 and Register 9-3).

The CM2CON1 register also contains mirror copies of

both comparator outputs, MC1OUT and MC2OUT of

the CM2CON1 Register. The ability to read both out-

puts simultaneously from a single register eliminates

the timing skew of reading separate registers.

Note: Obtaining the statu s of C1OUT or C2OU T

by reading CM2CON1 does not affect the

comparator interrupt mismatch registers.

R-0 R-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0

MC1OUT MC2OUT — — — — T1GSS C2SYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 MC1OUT: Mirror Copy of C1OUT bit (CM1CON0<6>)

bit 6 MC2OUT: Mirror Copy of C2OUT bit (CM2CON0<6>)

bit 5-2 Unimplemented: Read as ‘0’

bit 1 T1GSS: Timer1 Gate Source Select bit

1 = Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT

0 = Timer1 gate source is SYNCC2OUT.

bit 0 C2SYNC: C2 Output Synchronous Mode bit

1 = C2 output is synchronous to falling edge of TMR1 clock

0 = C2 output is asynchronous

PIC16F785/HV785

9.2 Comparator Outputs

The comparator outputs are read through the

CM1CON0, COM2CON0 or CM2CON1 registers.

CM1CON0 and CM2CON0 each contain the individual

comp arator outp ut of Comp arat or 1 a nd Comp arato r 2,

respectively. CM2CON 2 co nt a ins a mi rror c opy of bo th

comparator outputs facilitating a simultaneous read of

both comparators. These bits are read-only. The

comparator outputs may also be directly output to the

RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2

I/O p ins. When enab led, mult iplexers in the outpu t path

of the RA2 and RC4 pins will switch and the output of

each pin will be t he u nsy nc hro niz ed output of the com-

parator. The uncertainty of each of the comparators is

related to the input offset voltage and the response time

given in the specifications. Figure 9-1 and Figure 9-2

show t he output bl ock diag rams for Comp arators 1 and

2, respec tively.

The TRIS bits will still function as an output enable/

disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/

C2OUT/PH2 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C1POL and C2POL bits of the CMxCON0

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS

bit of the C M2CON1 Reg ister. The T imer1 gate feature

can be used to time the duration or interval of analog

events. The output of Comparator 2 can also be syn-

chroniz ed with T im er1 by set ting th e C2SYNC bi t of the

CM2CON1 Register. When enabled, the output of

Comparator 2 is latched on the falling edge of the

T ime r1 clock sou rce. If a prescaler is used with Timer1,

Comparator 2 is latche d after the pres cal er. To prevent

a race cond ition, t he Com pa rator 2 o utput is l atched on

the falling edge of the Timer1 clock source and Timer1

increments on the rising edge of its clock source. See

the Comparator 2 Block Diagram (Figure 9-2) and the

Timer1 Block Diagram (Figure 6-1) for more

information.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

9.3 Comparator Interrupts

The comparator interrupt flags are set whenever there

is a change in the output value of it s respective compar-

ator. Software will need to maintain information about

the status of the output bits, as read from

CM2CON0<7:6>, to determine the actual change that

has occurred. The CxIF bits, PIR1<4:3>, are the

Comparator Interrupt Flags. Each comparator interrupt

bit mu st b e r ese t in so ft ware by cl e ari ng it t o ‘0’. Since

it is also possible to write a ‘1’ to this register, a

simulated interrupt may be initiated.

The CxIE bits of the PIE1 Register and the PEIE bit of

the INTCON Register must be set to enable the inter-

rupts . In add ition, t he GIE b it mus t also be set . If any of

these bits are cleared, the interrupt is not enabled,

though the CxIF bits will still be set if an interrupt con-

dition occurs.

The comparator interrupt of the PIC16F785/HV785

diff ers from previ ous desi gns i n that th e inte rrupt fla g is

set by the mismatch edge and not the mismatch level.

This means that the interrupt flag can be reset without

the additional step of reading or writing the CMxCON0

misma tch register s are not cleared, an interrupt will not

occur when the comparator output returns to the

previous state. When the mismatch registers are

cleared, an interrupt will occur when the comparator

returns to the previous state.

9.4 Effect s of Reset

A Reset forces all registers to their Reset state. This

disabl es both compara tors .

Note 1: If a change in the CMxCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cy cle), the n the CxIF of the PI R1 Reg-

ister interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is sta-

ble. Allo w about 1 μs for bias settling then

clear the mismatch condition and inter-

rupt flags before enabling comparator

interrupts.

PIC16F785/HV785

10.0 VOLTAGE REFERENCE S

There are two voltage references available in the

PIC16F785/HV785: The voltage referred to as the

comparator reference (CVREF) is a variable voltage

base d on VDD; The volt age refe rred to as the VR refer-

ence (VR ) is a f ixed vol t age d erived from a st able band

gap source. Each source may be individually routed

internally to the comparators or output, buffered or

unbuffered, on the RA1/AN1/C12IN0-/VREF/ICSPCLK

pin.

10.1 Comparator Reference

The comparator module also allows the selection of an

internally generated voltage reference for one of the

comparator input s. The VRCON register (Register 10-1)

controls the voltage reference module shown in

Figure 10-1.

10.1.1 CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The follow ing equati on determin es the output volt ages:

EQUATION 10-1: CVREF OUTPUT VOLTAGE

10.1.2 VOLTAGE REFERENCE

ACCURACY/ERROR

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 10-1) keep CVREF from approaching VSS or

VDD. The exception is when the module is disabled by

clearing all CVROE, C1VREN and C2VREN bits. When

disabled with VR<3:0> = 0000 and VRR = 1 the refer-

ence voltage will be VSS. This allows the comparators

to detect a zero-crossing and not consume CVREF

module current.

The volt age reference is VDD derived and therefore, the

CVREF output changes with fluctuations in VDD. The

tested absolute accuracy of the comparator voltage

reference can be found in Table 19-8.

VRR = 1 (low range):

CVREF = VR<3:0> x VDD/24

VRR = 0 (high range):

CVREF = (VDD/4) + (VR<3:0> x VDD/32)

PIC16F785/HV785

FIGURE 10-1: COMPARATOR VO LTAGE REFERENCE BLOCK DIAGRAM

VRR

VR3:VR0

16-1 Analog

8RRR RR

C1VREF to

16 Stages

Comparator 1

Input

CVREN(1)

VDD

MUX

C2VREF to

Comparator 2

Input 0

1VR

1.2 V

C2VREN

C1VREN

CVREF

CVROE

Note 1: See Register 10-1, bits 3-0.

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

C1VREN(1) C2VREN(1) VRR —VR3VR2VR1VR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit(1)

1 = CVREF circuit powered on and routed to C1VREF input of comparator 1

0 = 1.2 V o lt VR routed to C 1 VREF input of comparator 1

bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit(1)

1 = CVREF circuit powered on and routed to C2VREF input of comparator 2

0 = 1.2 V o lt VR routed to C 2 VREF input of comparator 2

bit 5 VRR: Comparator Voltage Reference CVREF Range Selection bit

1 = Low Range

0 = High Range

bit 4 Unimplemented: Read as ‘0’

bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1 and CVREN = 1: CVREF = (VR<3:0> x VDD/24)

When VRR = 0 and CVREN = 1: CVREF = (VDD/4) + (VR<3:0> x VDD/32)

When CxVREN = 0 and VREN = 1: CxVREF = 1.2V from VR module

Note 1: When C1VREN, C2VREN a nd CVROE (Reg ister 10-2) are all low, the CV REF circuit is po wered down and

does not contribute to IDD current.

PIC16F785/HV785

10.2 VR Reference Module

The VR Reference module generates a 1.2V nominal

output voltage for use by the ADC and comparators.

The outpu t voltage ca n al so be brought out to th e VREF

pin for user applications. This module uses a bandgap

as a reference. See Table 19-9 for detailed specifica-

tions. Register 10-2 shows the control register for the

VR module.

U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

—— BGST VRBB VREN VROE CVROE —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 BGST: Band Gap Reference Voltage Stable Flag bit

1 = Reference is stable

0 = Reference is not stable

bit 4 VRBB: Voltage Reference Buffer Bypass bit

1 = VREF output is not buffered. Power is removed from buffer amplifier.

0 = VREF output is buffered(1)

bit 3 VREN: Voltage Reference Enable bit (VR = 1.2V nominal)(2)

1 = VR reference is enabled

0 = VR reference is disabled and does not consume any current

bit 2 VROE: Voltage Reference Output Enable bit

If CVROE = 0:

1 = VREF output on RA1/ AN1/C12IN0 -/VREF/ICSPCLK pin is 1.2 volt VR analog reference

0 = Disabled, 1.2 volt VR analog reference is used internally only

If CVROE = 1:

VROE has no effect .

bit 1 CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10-2)

1 = VREF output on RA1/ AN1/C12IN0 -/VREF/ICSPCLK pin is CV REF voltage

0 = VREF output on RA1/ AN1/C12IN0 -/VREF/ICSPCLK pin is controlled by VROE

bit 0 Unimplemented: Read as ‘0’

Note 1: Buffer amplifier common mode limitations require VREF ≤ (VDD - 1.4)V for buffered output.

2: VREN is fixed high for PIC16HV785 device.

PIC16F785/HV785

10.2.1 VR STABILIZATION PERIOD

When the Voltage Reference module is enabled, it will

require some time for the reference and its amplifier

circuits to stabilize. The user program must include a

small delay routine to allow the module to settle. See

Section 19.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 10-2: VR REFE REN CE BLOCK DIAGRAM

TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR AND VOLTAGE REFERENCE

MODULES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

other R esets

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000

CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 ---0 0000 ---0

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 ---0 0000 ---0

PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

REFCON —— BGST VRBB VREN VROE CVROE —--00 000- --00 000-

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

VRCON C1VREN C2VREN VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

RA1/AN1/C12IN0-/VREF

VREN

Voltage

Reference

RDY To CVREF MUX

BGST

01X

Analog

Buffer

CVREF VRBB(1)

VROUT

CVROE

(CVROE + (VREN*VROE ))

VRIN

Note 1: Buffered output requires VRIN = (VDD - 1.4)V.

2: VREN is fixed high for PIC16HV785 device.

PIC16F785/HV785

11.0 OPERATIONAL AMPLIFIER

(OPA) MODUL E

The OPA module has the following features:

• Two independent Operational Amplifiers

• External connections to all ports

• 3 MHz Gain Bandwidth Product (GBWP)

11.1 Control Registers

The OPA1CON register, shown in Register 11-1,

controls OPA1. OPA2CON, shown in Register 11-2,

controls OPA2.

11.2 OPAxCON Regi ster

The OPA module is enabled by setting the OPAON bit

of the OPAxCON Register. When enabled, OPAON

forces the output driver of RC3/AN7/C12IN3-/OP1 for

OPA1, and RC2/AN6/C12IN2-/OP2 for OPA2, into

tristate to prevent contention between the driver and

the OPA output. The AD C and comp arator inpu ts which

share the op amp pins operate normally when the op

amp is enabl ed.

FIGURE 11-1: OPA MODULE BLOCK DIAGRAM

Note: When OPA1 or OPA2 is enabled, the

RC3/AN7/C12 IN3-/OP1 pin , or

RC2/AN6/C12IN2-/OP2 pin, respectively,

is d riv en b y t h e o p amp ou t pu t , no t by t he

PORTC dr iver . Refer to Table 19-1 1 for the

electrical specifications for the op amp

output d rive capabi lity.

OPA1

OPA1CON<OPAON>

TO ADC and Comparator MUXs

RC7/AN9/OP1+

RC6/AN8/OP1-

RC3/AN7/C12IN3-/OP1

OPA2

OPA2CON<OPAON>

TO ADC and Comparator MUXs

RB5/AN11/OP2+

RB4/AN10/OP2-

RC2/AN6/C12IN2-/OP2

PIC16F785/HV785

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

OPAON — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OPAON: Op Amp Enable bit

1 = Op Amp 1 is enabled

0 = Op Amp 1 is disabled

bit 6-0 Unimplemented: Read as ‘0’

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

OPAON — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OPAON: Op Amp Enable bit

1 = Op Amp 2 is enabled

0 = Op Amp 2 is disabled

bit 6-0 Unimplemented: Read as ‘0’

PIC16F785/HV785

11.3 Effects of a Reset

A device Reset forces all registers to their Reset state.

This disables both op amps.

11.4 OPA Module Performance

Common AC and DC performance specifications for

the OPA module:

• Common Mode Voltage Range

• Leakage Current

• Input Offset Voltage

• Open Loop Gain

• Gain Bandwidth Product (GBWP)

Common mo de volta ge range is the specified voltage

range for the OP A+ and OP A- inp uts, for which the OPA

module will perform to within its specifications. The

OPA module is d esign ed to opera te with inp ut voltages

between 0 and VDD-1.4V. Behavior for common mode

voltages greater than VDD-1.4V, or below 0V, are

bey ond the normal operating range.

Leakage current is a measure of the small source or

sink currents on the OPA+ and OPA- inputs. To mini-

mize the effect of leakage currents, the effectiv e imped-

ances connected to the OPA+ and OPA- inputs should

be kept as small as possible and equal.

Input offset voltage is a me asu re of th e vol tag e dif f er-

ence between the OPA+ and OPA- inputs in a closed

loop circuit with the OPA in its linear region. The offset

volt age wil l appear a s a DC of fset in t he output equal to

the input offset voltage, multiplied by the gain of the

circuit. The input offset voltage is also affected by the

common mode voltage.

Open loop ga in is the ratio of th e output volt age to th e

differential input voltage, (OPA+) - (OPA-). The gain is

greatest at DC and falls off with frequency.

Gain Bandwidth Product or GBWP is the frequency

at which the open loop gain falls off to 0 dB.

11.5 Effects of Sleep

When enabled, the op amps continue to operate and

consum e cu rrent wh ile the processo r is in Sl eep m ode.

TABLE 11-1: REGISTERS ASSOCIATED WITH THE OPA MODULE

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

ANSEL1 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111

OPA1CON OPAON — — — — — — — 0--- ---- 0--- ----

OPA2CON OPAON — — — — — — — 0--- ---- 0--- ----

TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA module.

PIC16F785/HV785

NOTES:

PIC16F785/HV785

12.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analo g-to-digital converter (A/D) allows conversion

of an analog input signal to a 10-bit binary representa-

tion of that signal. The PIC16F785/HV785 has twelve

analog I/O inputs, plus two internal inputs, multiplexed

into one sample and hold circuit. The output of the sam-

ple and hold is connected to the input of the converter.

The conv erter gene rates a bi nary res ult via success ive

approxi ma tio n and stores th e res ul t in a 10-bit registe r.

The voltage reference used in the conversion is soft-

ware selectable to either VDD or a voltage applied by

the VREF pin. Figure 12-1 shows the block diagram of

the A/D on the PIC16F785 /H V78 5.

FIGURE 12-1: A/D BLOCK DIAGRAM

A/D

VDD

VREF

ADON(1)

GO/DONE

VCFG = 1

VCFG = 0

CHS<3:0>

ADRESH ADRESL

ADFM

VSS

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RA4/AN3/T1G/OSC2/CLKOUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RC3/AN7/C12IN3-/OP1

RC6/AN8/OP1-

RC7/AN9/OP1+

RB4/AN10/OP2-

RB5/AN11/OP2+

CVREF

Note 1: When ADON = 0 all input channels are disconnected from ADC (no loading).

PIC16F785/HV785

12.1 A/D Configuration and Operation

There are four registers available to control the

functionality of the A/D module:

1. ANSEL0 (Regi ster 12-1)

2. ANSEL1 (Regi ster 12-2)

3. ADCON0 (Register 12- 3)

4. ADCON1 (Register 12- 4)

12.1.1 ANALOG PORT PINS

The ANS<11:0> bits, of the ANSEL1 and ANSEL0

Registers, and the TRISA<4,2:0>, TRISB<5:4> and

TRISC<7:6,3:0>> bits control the operation of the A/D

port pins. Set the corresp onding TRISx bit s to ‘1’ to set

the pin output driver to its high-impedance state. Like-

wise, set the correspo nding ANSx b it to disable the dig-

ital input buffer.

12.1.2 CHANNEL SELECTION

There are fourteen analog channels on the PIC16F785/

HV785. The CHS<3:0> bits of the ADCON0 Register

control which channel is connected to the sample and

hold circuit.

12.1.3 VOLTAGE REFERENCE

There are two options for the voltage reference to the

A/D converter: either VDD is used or an analog voltage

applied to VREF is u se d. T he VC FG bi t of th e ADC ON 0

VCFG is set, then the volt age on the VREF pin i s the ref-

erence; othe rw is e, VDD is the reference.

12.1.4 CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits of the ADCON1 Register. There are seven

possible clock options:

•F

OSC/2

•FOSC/4

•F

OSC/8

•F

OSC/16

•FOSC/32

•FOSC/64

•F

RC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selecte d to ensure a mi nimum TAD of

1.6 μs. Table 12-1 shows a few TAD calculations for

selected frequencies.

TABLE 12-1: TAD VS. DEVICE OPERATING FREQUENCIES

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

A/D Clock Source (TAD) Device Frequ ency

Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz

2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 μs

4 TOSC 100 200 ns(2) 800 ns(2) 1.0 μs(2) 3.2 μs

8 TOSC 001 400 ns(2) 1.6 μs2.0 μs6.4 μs

16 TOSC 101 800 ns(2) 3.2 μs4.0 μs12.8 μs(3)

32 TOSC 010 1.6 μs6.4 μs8.0 μs(3) 25.6 μs(3)

64 TOSC 110 3.2 μs12.8 μs(3) 16.0 μs(3) 51.2 μs(3)

A/D RC x11 2-6 μs(1), (4) 2-6 μs(1), (4) 2-6 μs(1), (4) 2-6 μs(1), (4)

Legend: Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be perf ormed during S leep.

PIC16F785/HV785

12.1.5 STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6>)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

registers wil l not be u pdated with the p ar tially comp lete

A/D conversion sample. Instead, the

ADRESH:ADRESL registers wi ll re t ai n the va lue of th e

previous conversion. After an aborted conversion, a

AD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

FIGURE 12-2: A/D CONVE RSION TAD CYCLES

12.1.6 CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right jus tified. The ADFM bit of the ADCON0 reg ister

controls the output format. Figure 12-3 shows the out-

put formats.

FIGURE 12-3: 10-BIT A/D RESULT FORMAT

Note: The G O/DONE bit sh ould n ot be set in th e

same instruction that turns on the A/D.

TAD1TAD2 TAD3 TAD4 TAD5 TAD6

7 T

TAD9

Set GO bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD10 TAD11

b1 b0

TCY to TAD

Conversion Starts

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

ADRESH (ADDRESS:1Eh) ADRESL (ADDRESS:9Eh)

(ADFM = 0)MSB LSB

bit 7bit 0bit 7bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7bit 0bit 7bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

PIC16F785/HV785

TABLE 12-2: ANALOG SELECT CROSS REFERENCE

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1 = Analog input. Pin is assigned as analog input.(1)

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter-

rupt-on-c hange, if av ailable. The corresp onding TRIS bi t must be s et to Input mode in order to allow exte r-

nal control of the voltage on the pin. Port reads of pins configured assigned as analog inputs will read as

‘0’.

U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1

— — — — ANS11 ANS10 ANS9 ANS8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 ANS<11:8>: Analog Select bits

Analog select between analog or digital function on pins AN<11:8>, respectively.

1 = Analog input. Pin is assigned as analog input.(1)

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter-

rupt-on-c hange, if av ailable. The corresp onding TRIS bi t must be s et to Input mode in order to allow exte r-

nal control of the voltage on the pin. Port reads of pins assigned as analog inputs will read as ‘0’.

Mode Reference

Analog

Select ANS11 ANS10 ANS9 ANS8 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

Analog

Channel AN11AN10AN9AN8AN7AN6AN5AN4AN3AN2AN1AN0

I/O Pin RB5 RB4 RC7 RC6 RC3 RC2 RC1 RC0 RA4 RA2 RA1 RA0

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Formed Select bit

1 = Right justified

0 = Left justified

bit 6 VCFG: Voltage Reference bit

1 = VREF pin

0 = VDD

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 00 (AN0)

0001 = Channel 01 (AN1)

0010 = Channel 02 (AN2)

0011 = Channel 03 (AN3)

0100 = Channel 04 (AN4)

0101 = Channel 05 (AN5)

0110 = Channel 06 (AN6)

0111 = Channel 07 (AN7)

1000 = Channel 08 (AN8)

1001 = Channel 09 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

1100 =CV

REF

1101 =VR

1110 = Reserved. Do not use.

1111 = Reserved. Do not use.

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion c ompleted/not in progress

bit 0 ADON: A/D Enab le bit

1 = A/D converter module is enabl ed

0 = A/D converter is shut-off and consumes no operating current

PIC16F785/HV785

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— ADCS2 ADCS1 ADCS0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conversi on C loc k Sele ct bits

000 =F

OSC/2

001 =F

OSC/8

010 =F

OSC/32

x11 =F

RC (clock derived from a dedicated internal oscillator = 500 kHz max)

100 =F

OSC/4

101 =F

OSC/16

110 =F

OSC/64

bit 3-0 Unimplemented: Read as ‘0’

PIC16F785/HV785

12.1.7 CONFIGURING THE A/D

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

To determine sample time, see Table 19-16 and

Table 19-17. After this sample time has elapsed, the

A/D conversion can be started.

These s te p s sh ould be fol low e d f or a n A/D c onvers io n:

1. Conf igure the A/D modul e:

• Configure analog/digital I/O (ANSx)

• Select A/D conversion clock in the ADCON1

• Configure voltage reference in the ADCON0

• Select A/D input channel in the ADCON0

• Select result format in the ADCON0 Register

• Turn on A/D m odu le i n the ADCON 0 Reg is ter

2. Configu re A/D int err upt (if de sired):

• Clear ADIF bit of the PIR1 Register

• Set ADIE bit of the PIE1 Register

• Set PEIE and GIE bits of the INTCON Regis-

ter

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(with interrupts disabled); OR

• Waiting for the A/D interrupt

6. Read A/D Resul t reg ister pair

(ADRESH:ADRESL), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition star t s .

EXAMPLE 12-1: A/D CONVER SI ON

;This code block configures the A/D

;for polling, Vdd reference, R/C clock

;and RA0 input.

;

;Conversion start and wait for complete

;polling code included.

;

BCF STATUS,RP1 ;Bank 1

BSF STATUS,RP0 ;

MOVLW B’01110000’ ;A/D RC clock

MOVWF ADCON1

BSF TRISA,0 ;Set RA0 to input

BSF ANSEL0,0 ;Set RA0 to analog

BCF STATUS,RP0 ;Bank 0

MOVLW B’10000001’ ;Right, Vdd Vref, AN0

MOVWF ADCON0

CALL SampleTime ;Wait min sample time

BSF ADCON0,GO ;Start conversion

BTFSC ADCON0,GO ;Is conversion done?

GOTO $-1 ;No, test again

MOVF ADRESH,W ;Read upper 2 bits

MOVWF RESULTHI

BSF STATUS,RP0 ;Bank 1

MOVF ADRESL,W ;Read lower 8 bits

BCF STATUS,RP0 ;Bank 0

MOVWF RESULTLO

PIC16F785/HV785

12.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 12-4. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance va ries ov er the dev ice vol tag e

(VDD), see Figure 12-4. The maximum recom-

mended im pedance for ana log sources is 10 kΩ. As

the impedance is decreased, the acquisition time may

be decreased. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time,

Equation 12-1 may be used. This equation assumes

that 1/2 LS b error is used (1024 st eps for the A/D). The

1/2 LSb er ror is the ma ximu m error allow ed for the A/D

to meet its specified resolution.

EQUATION 12-1: ACQUISITION TIME EXAMPLE

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

TACQ Amplifier Settling Time Hold Cap acitor Charging Time Temperatu re C oefficient++=

TAMP Tc TCOFF++=

5µs Tc Temperature - 25°C()0.05µs/°C()[]++=

TcCHOLD Ric Rss Rs++() ln(1/2047)–=

10pF 1k

10k

++()– ln(0.0004885)=

1.37

=µs

Tacq 5µs 1.37µs 50°C- 25°C()0.05µs/°C()[]++=

7.62µs=

VAPPLIED 1e

Tc–

---------

–

⎝⎠

⎜⎟

⎛⎞

VAPPLIED 11

2047

------------–

⎝⎠

⎛⎞

VAPPLIED 11

2047

------------–

⎝⎠

⎛⎞

VCHOLD=

VAPPLIED 1e

TC–

----------

–

⎝⎠

⎜⎟

⎛⎞

VCHOLD=

;[1] Vchold charged to wi thin 1/2 lsb

;[2] Vchold charge response to Vapplied

;Co mb ini ng [1] and [2]

The value for Tc can be approximated with the following equations:

Solving for Tc:

Therefore:

Temperature 50°C and external impedance of 10k

5.0 V V DD=

Assumptions:

PIC16F785/HV785

FIGURE 12-4: ANALOG INPUT MODEL

RSS

CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V ILEAKAGE

RIC ≤ 1k

Sampling

Switch

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(kΩ)

VDD

= 10 pF

± 500 nA

RSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage

I LEAKAGE = Leakage current at the pin due to various junctions

RIC = Interconnect Resistance

SS = Sam pling Sw itch

CHOLD = Sample/Hold Capacitance (from DAC)

PIC16F785/HV785

12.3 A/D Operation During Sleep

The A/D Converter module can operate during Sleep.

This req uire s t he A/D clock s ourc e to be se t to t he F RC

option. When the RC clock source is selected, the A/D

waits one instruction before starting the conversion.

This allows the SLEEP instruction to be executed, thus

eliminating much of the switching noise from the con-

version. When the conversion is complete, the GO/

DONE bit is cleared and the result is loaded into the

ADRESH:ADRESL registers. If the A/D interrupt is

enabled (AD IE and PEIE bi t s s et), the d ev ice awak en s

from Sleep. If the GIE bit of the INTCON Register is se t,

the program counter is set to the interrupt vector

(0004h). I f GIE is clea r , the next in struction is executed.

If the A/D interrupt is not enabled, the A/D module is

turned off, although the ADON bit remains set.

When the A/D clock source is something other than

RC, a SLEEP instruction causes the present conversion

to be aborted and the A/D module is turned off. The

ADON bit remains set.

FIGURE 12-5: A/D TRANSFER FUNCTION

3FFh

3FEh

A/D Outpu t Code

3FDh

3FCh

004h

003h

002h

001h

000h

Full-Scale

3FBh

1 LSb ideal

0V Zero-Scale

Transition VREF

Transition

1 LSb ideal

Full-Scale Range

Analog Input Voltage

PIC16F785/HV785

12.4 Effects of Reset

A device Reset forces all registers to their Reset state.

Thus, the A/D module is turned off and any pending

conversion is aborted. The ADRESH:ADRESL

registers are unchanged.

12.5 Use of the CCP Trigger

An A/D convers ion can be st arted by the “special event

trigger” of the CCP module. This requires that the

CCP1M3:CCP1M0 bits of the CCP1CON Register be

programmed as ‘1011’ and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion

and the Timer1 counter will be reset to zero. Timer1 is

reset to autom atica lly re peat th e A/D acquisi tion p eriod

with minimal software overhead (moving the

ADRESH:ADRESL to the desired locatio n).

The appropriate analog input channel must be selected

and the minimum acquisition done before the “special

event trigger” sets the GO/DONE bit (starts a

conversion).

If the A/D module is not enabled (ADON is cleared), then

the “special event trigger” will be ignored by the A/D

module, but will still reset the Timer1 counter. See

Section 8.0 “Capture/Compare/PWM (CCP) Module”

for more information.

TABLE 12-3: SUMMARY OF A/D REGISTERS

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000

ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----

ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result xxxx xxxx uuuu uuuu

ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx uuuu uuuu

ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

ANSEL1 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module.

PIC16F785/HV785

NOTES:

PIC16F785/HV785

13.0 TWO-PHASE PWM

The two-phase PWM (Pulse Width Modulator) is a

stand-alone peripheral that supports:

• Single or dual-phase PWM

• Si ngl e com pl eme nt ary output PWM with ov erla p/

delay

• Sync input/output to cascade devices for

additional phases

Sett i ng eit h er, or both , of th e P H1 E N or PH 2 EN b its of

the PWMCON0 register will activate the PWM module

(see Register 13-1). If PH1 is used then TRISC<1>

must be cleared to configure the pin as an output. The

same is true for TRISC<4> when using PH2. Both

PH1EN and PH2EN must be set when using

Complementary mode.

13.1 PWM Period

The PWM period is derived from the main clock (FOSC),

the PWM prescaler and the period counter (see

Figure 13-1). The prescale bits of the PWMP Register,

(see Register 13-2) determine the value of the clock

divider which divides the system clock (FOSC) to the

pwm_clk. This pwm_clk is used to drive the PWM

counter. In Master mode, the PWM counter is reset

when the count reaches the period count of the PER

frequency of the PWM. The relationship between the

PWM freque ncy, prescale and period cou nt is shown in

Equation 13-1.

EQUATION 13-1: P WM FREQUENCY

The maximum PWM frequency is FOSC/2, since the

period count must be greater than zero.

In Slave mode, the pe riod counter i s reset by the SYN C

input, which is the master device period counter reset.

For proper operation, the slave period count should be

equal to or greater than that of the master.

13.2 PWM Phase

Each enabled phase output is driven active when the

phase counter matches the correspond ing PWM phase

count in the PH Register (see Register 13-3 and

Regis ter 13-4). The ph ase output rem ains true until t er-

minated by a feedback signal from either of the com-

parators or the auto-shutdown activates.

Phase granularity is a function of the period count

value. For example, if PER<4:0> = 3, each output can

be shifted i n 90° steps (see Equation 13-2).

EQUATION 13-2: PHASE RESOLUTION

13.3 PWM Duty Cycle

Each PWM output is driven inactive, terminating the

drive period, by asynchronous feedback through the

internal comparators. The duty cycle resolution is in

effect infinitely adjustable. Either or both comparators

can be used to reset the PWM by setting the corre-

sponding comparator enable bit (CxEN, see

by suppressing the feedback which would otherwise

terminate the pulse.

The comparator outputs can be “held off”, or blanked,

by enabling the corresponding BLANK bit (BLANKx,

see Register 13-1) for each phase. The blank bit

disables the comparator outputs for 1/2 of a system

clock ( FOSC), thus ensuring at least TOSC/2 active time

for the PWM output. Blanking avoids early termination

of the PWM output which may result due to switching

transients at the beginning of the cycle.

13.4 Master/Slave Operat ion

Multiple chips can operate together to achieve addi-

tional phases by operating one as the master and the

others as slaves. When the PWM is configured as a

master, the RB7/SYNC pin is an output and generates

a high output f or one pwm_ clk period at the end of each

PWM period (see Figure 13-4).

When the PWM is configured as a slave, the RB7/

SYNC pin is an input. The high input from a master in

this configuration resets the PWM period counter which

synchronizes the slave unit at the end of each PWM

period. Proper operation of a slave device requires a

comm on exte rn al FOSC cloc k sourc e to dr ive t he mas-

ter and slave. The PWM prescale value of the slave

device must also be identical to that of the master. As

mentioned previously, the slave period count value

must be greater than or equal to that of the master.

The PWM Counter will be reset and held at zero when

both PH1EN and PH2EN of the PWMCON0 Register

are false. If the PWM is configured as a slave, the PWM

Counter will remain reset at zero until the first SYNC

input is received.

PWM FREQ = FOSC

(2PWMP • (PER + 1)

PhaseDEG = (PER + 1)

360

PIC16F785/HV785

13.5 Active PWM Output Level

The PWM output signal can be made active-high or

active-low by setting or resetting the corresponding

POL bit (see Register 13-3 and Register 13-4). When

POL is ‘1’ the active output state is VOL. When POL is

‘0’ the active output state is VOH.

13.6 Auto-Shutdown and Auto-Restart

When the PWM is enabled, the PWM outputs may be

configu red for auto-shutdown by s etti ng th e PASEN bit

(see Register 13-1). VIL on the RA2/AN2/T0CKI/INT/

C1OUT pin will cause a shutdown event if auto-shut-

down is enabl ed. An auto -shut dow n event im media tel y

places the PWM outputs in the inactive state (see

Section 13.5 “Active PWM Output Level”) and the

PWM phase and period counters are reset and held to

zero.

The PWMASE bit (see Register 13-2) is set by hard-

ware when a shutdown event occurs. If automatic

restarts are not enabled (PRSEN = 0, see

PWMASE bit is cleared by firmware after the shut down

condition clears. The PWMASE bit can not be cleared

as long as the shutdown condition exists. If automatic

restarts are not enabled, the auto-shutdown mode can

be forced by writing a ‘1’ to the PWMASE bit.

If automatic restarts are enabled (PRSEN = 1), the

PWMASE bit is automatically cleared and PWM

operation resumes when the auto-shutdown event

clears (VIH on the RA2/AN2/T0CKI/INT/C1OUT pin).

FIGURE 13-1: TWO-PHA SE PWM SIMPLIFIED BLOCK DIAGRAM

Prescale

PWMPH1<C1EN>

PWMPH1<C2EN>

PWMPH1<POL>

PWMPH1<4:0>

Phase

Counter

FOSC

C1OUT

C2OUT

PWMP<1:0>

PER<4:0>

pwm_clk

5pwm_count

pha1

÷1,2,4,8 0

R(1)

PWMASE MASTER

Res

SHUTDOWN

BLANK1

PWMPH2<C1EN>

PWMPH2<C2EN>

PWMPH2<POL>

PWMPH2<4:0> pha2

R(1) QSHUTDOWN

BLANK2

PH1EN

PH2EN

PH1EN

PH2EN

PASEN SHUTDOWN

RB7/SYNC

RC1/AN5/C12IN1-/PH1

RC4/C2OUT/PH2

Note 1: Reset dominant.

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown condi-

tion goes away. The PWM restarts automatically.

0 = Upon auto-shutdown, the PWMASE must be cleared in firmware to restart the PWM.

bit 6 PASEN: PWM Auto-Shutdown Enable bit

0 = PWM auto-shut d ow n is disab led

1 =V

IL on INT pin will cause auto-shutdown event

bit 5 BLANK2: PH2 Blanking bit(1)

1 = The PH2 pin is active for a minimum of 1/2 of an FOSC clo c k period after it is set

0 = The PH2 pin is reset as soon as the comparator trigger is active

bit 4 BLANK1: PH1 Blanking bit(1)

1 = The PH1 pin is active for a minimum of 1/2 of an FOSC clo c k period after it is set

0 = The PH1 pin is reset as soon as the comparator trigger is active

bit 3-2 SYNC<1:0>: SYNC Pin Function bits

0X = SYNC pin not u sed for PWM . PWM act s as i ts own master. RB7/SYN C pin i s av ailabl e for gen-

eral purpose I/O.

10 = SYNC pin acts as system slave, receiving the PWM counter reset pulse

11 = SYNC pin acts as system m aster, driving the PWM counter reset puls e

bit 1 PH2EN: PH2 Pin Enabled bit

1 = The PH2 pin is driven by the PWM signal

0 = The PH2 pin is not used for PWM functions

bit 0 PH1EN: PH1 Pin Enabled bit

1 = The PH1 pin is driven by the PWM signal

0 = The PH1 pin is not used for PWM functions

Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PWMASE PWMP1 PWMP0 PER4 PER3 PER2 PER1 PER0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PWMASE: PWM Auto-Shutdown Event Status bit

0 = PWM outputs are operating

1 = A shutdown event has occured. PWM outputs are inactive.

bit 6-5 PWMP<1:0>: PWM Clock Prescaler bits

00 =pwm_clk = F

OSC ÷ 1

01 =pwm_clk = F

OSC ÷ 2

10 =pwm_clk = F

OSC ÷ 4

11 =pwm_clk = F

OSC ÷ 8

bit 4-0 PER<4:0>: PWM Period bits

00000 = Not used. (Period = 1/pwm_clk)

00001 = Period = 2/pwm_clk2

0•••• =• • •

01111 = Period = 16/pwm_clk

10000 = Period = 17/pwm_clk

1•••• =• • •

11110 = Period = 31/pwm_clk

11111 = Period = 32/pwm_clk

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

POL C2EN C1EN PH4 PH3 PH2 PH1 PH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 POL: PH1 Output Polarity bit

1 = PH1 Pin is active-low

0 = PH1 Pin is active-high

bit 6 C2EN: Comparator 2 Enable bit

When COMOD<1:0> = 00(1)

1 = PH1 is reset when C2OUT goes high

0 = PH1 ignores Comparator 2

When COMOD<1:0> = X1(1)

1 = Complementary drive terminates when C2OUT goes high

0 = Comparator 2 is ignored

When COMOD<1:0> = 10(1)

C2EN has no effect

bit 5 C1EN: Comparator 1 Enable bit

When COMOD<1:0> = 00(1)

1 = PH1 is reset when C1OUT goes high

0 = PH 1 ignores Comparator 1

When COMOD<1:0> = X1(1)

1 = Complementary drive terminates when C1OUT goes high

0 = Comparator 1 is ignored

When COMOD<1:0> = 10(1)

C1EN has no effect

bit 4-0 PH<4:0>: PWM Phase bits

When COMOD<1:0> = 00(1)

00000 = PH1 st art s 1 pw m _clk p erio d a fter falli ng ed ge of SYNC pu ls e. A ll other PH1 delays are

expressed relative to this time.

00001 = PH1 is delayed by 1 pwm_clk pulse

••••• =• • •

11111 = PH1 is delayed by 31 pwm_clk pulses

When COMOD<1:0> = X1 or 1X(1)

00000 = Complemen tary drive st arts 1 pw m_clk period after falli ng edge of SYNC p ulse. All othe r

delays are expressed relative to this time.

00001 = Complementary drive start is delayed by 1 pwm_clk pulse

••••• =• • •

11111 = Comple m entary drive s tart is delayed by 31 pw m_c lk pulses

Note 1: See PWMCON1 register (Register 13-5).

PIC16F785/HV785

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

POL C2EN C1EN PH4 PH3 PH2 PH1 PH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 POL: PH2 Output Polarity bit

1 = PH2 Pin is active low

0 = PH2 Pin is active high

bit 6 C2EN: Comparator 2 Ena ble bit

When COMOD<1:0> = 00(1)

1 = PH2 is reset when C2OUT goes high

0 = PH2 ignores Comparator 2

When COMOD<1:0> = 1X or X1(1)

C2EN has no effect

bit 5 C1EN: Comparator 1 Ena ble bit

When COMOD<1:0> = 00(1)

1 = PH2 is reset when C1OUT goes high

0 = PH2 ignores Comparator 1

When COMOD<1:0> = 1X or X1(1)

C1EN has no effect

bit 4-0 PH<4:0>: PWM Phase bits

When COMOD<1:0> = 00(1)

00000 = PH2 start s 1 pwm_c lk period afte r falling edg e of SYNC puls e. All other PH2 d elays are

expressed relative to this time.

00001 = PH2 is delayed by 1 pwm_clk pulse

••••• =• • •

11111 = PH2 is delayed by 31 pwm_clk pulses

When COMOD<1:0> = 1X(1)

00000 = Com plem entary driv e term inates 1 pwm _clk peri od after falli ng ed ge of S YNC pu lse.

All other PH2 delays are expressed relative to this time.

00001 = Complementary dr ive termination is delayed by 1 pwm _clk pulse

••••• =• • •

11111 = Complementary drive termination is delayed by 31 pwm_clk pulses

When COMOD<1:0> = 01(1)

PH<4:0> has no effect.

Note 1: See PWMCON1 register (Register 13-5).

PIC16F785/HV785

FIGURE 13-2: TWO-PHASE PWM AUTO-SHUTDOWN AND SYNC TIMING

FIGURE 13-3: TWO-PHASE PWM START-UP TIMING

01 012 3 012 3 0

FOSC

SYNC

pwm_count

pwm_clk

SHUTDOWN

pha1

pha2

Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0

Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1

PWMP<1:0> = 0X01, PER <4:0> = 0X03

pwm_clk

012012

012

pwm_count 0

MASTER

SLAVE

012301

FOSC

SYNC

pwm_count

pwm_clk

PHnEN

PWMP<1:0> = 0X01, PER<4:0> = 0X03

pwm_clk

01201

pwm_count 3

MASTER

SLAVE

PIC16F785/HV785

13.7 Example Single Phase Application

Figure 13-4 shows an example of a single phase buck

voltage regulator application. The PWM output drives

Q1 with pulses to a lte rnat ely ch arge and disc harge L1.

C4 holds the charge from L1 during the inactive cycle

of the drive period. R4 and C3 form a ramp generator.

At the beginning of the PWM period, the PWM output

goes high causing the voltage on C3 to rise concur-

rently with the current in L1. When the voltage across

C3 reaches the threshold level present at the positive

input of Comparator 1, the comparator output changes

and terminates the drive output from the PWM to Q1.

When Q1 is not driven, the current path to L1 through

Q1 is interrupted, but since the current in L1 cannot

stop instantly, the current continues to flow through D2

as L1 discharges into C4. D1 quickly discharges C3 in

preparation of the next ramp cycle.

Resistor divider R5 and R6 scale the output voltage,

which is inverted and amplified by Op Amp 1, relative

to the refe rence voltage present at the non-inverting pin

of the op amp. R3, C5 and C2 form the inverting stabi-

lization gain feedback of the amplifier. The VR refer-

ence supplies a stable reference to the non-inverting

input of the op amp, which is tweaked by the voltage

source created by a secondary time based PWM

output of the CCP and R1 and C1.

Output regulation occurs by the following principle: If

the regula tor out put volt age is too low, then the volt age

to the non-inverting input of Comparator 1 will rise,

resulting in a higher threshold voltage and, conse-

quently, longer PWM dri ve pu lse s into Q1. If the outp ut

volt age is too high, then the voltage to the non-inverting

input of C omp arator 1 will fall, resu lting in s horter PWM

drive pulses into Q1.

FIGURE 13-4: EX AMPL E SING LE PHASE APPLICATION

VUNREG

OPA1

CCP

PIC16F785

FET

Driver

FOSC

R4 D1

TWO-Phase

PWM

PH1

PIC16F785/HV785

13.8 PWM Configuration

When configuring the Two-Phase PWM, care must be

taken to avoid active output levels from the PH1 and

PH2 pins before the PWM is fully configured. The

following sequence is suggested before the TRISC

are first configured:

• Output inactive (OFF) levels to the PORTC RC1/

AN5/C12IN1-/PH1 and RC4/C2OUT/PH2 pins.

• Clear TRISC bits 1 and 4 to configure the PH1

and PH2 pins as outputs.

• Configure the PWMCLK, PWMPH1, PWMPH2,

and PWMCON1 registers.

• Configure the PWMCON0 register.

EXAMPL E 13-1: PWM SE TU P EXA MP LE

;Example to configure PH1 as a free running PWM output using the SYNC output as the duty cycle

;termination feedback.

;This requires an external connection between the SYNC output and the comparator input.

;SYNC out = RB7 on pin 10

;C1 inverting input = RC2/AN6 on pin 14

;Configure PH1, PH2 and SYNC pins as outputs

;First, ensure output latches are low

BCF PORTC,1 ;PH1 low

BCF PORTC,4 ;PH2 low

BCF PORTB,7 ;SYNC low

;Configure the I/Os as outputs

BANKSEL TRISB

BCF TRISC,1 ;PH1 output

BCF TRISC,4 ;PH2 output

BCF TRISB,7 ;SYNC output

;PH1 shares its function with AN5

;Configure AN5 as digital I/O

BCF ANSEL0,5 ;AN5 is digital, all others default as analog

;Configure the PWM but don't enable PH1 or PH2 yet

BANKSEL PWMCLK

;PWM control setup

MOVLW B'00001100' ;auto shutdown off, no blanking, SYNC on, PH1 and PH2 off

MOVWF PWMCON0 ;see data sheet page 93

;PWM clock setup

MOVLW B'00111101' ;pwm_clk = Fosc, 30 clocks in PWM period

MOVWF PWMCLK ;see data sheet page 94

;PH1 setup

MOVLW B'00101111' ;non-inverted, terminate on C1, Start on clock 15

MOVWF PWMPH1 ;see data sheet page 95

;PH2 setup

MOVLW B'00110101' ;non-inverted, terminate on C1, Start on clock 21

MOVWF PWMPH2 ;see data sheet page 96

;Configure Comparator 1

MOVLW B'10011110' ;C1 on, internal, inverted, normal speed, +:C1VREF, -:AN6

MOVWF CM1CON0 ;see data sheet page 68

;Configure comparator voltage reference

BANKSEL VRCON

MOVLW B'10101100' ;C1VREN on, low range, CVREF= VDD/2

MOVWF VRCON ;see data sheet page 72

;Everything is setup at this point so now it is time to enable PH1

BANKSEL PWMCON0

BSF PWMCON0,PH1EN ;enable PH1

;Module is running autonomously at this point

PIC16F785/HV785

13.9 Complementary Output Mode

The Two-Phase PWM module may be configured to

operate in a Complementary Output mode where PH1

and PH2 are always 180 degrees out-of-phase (see

Figure 13-5). Three complementary modes are

availa ble and are se lected by the COMO D<1: 0> bits in

the PWMCON1 registe r (see Register 13-5). The differ-

ence between the modes is the method by which the

PH1 and PH2 outputs switch from the active to the

inactive state during the PWM period.

In Complementary mode, there are three methods by

which the duty cycle can be controlled. These modes

are selected with the COMOD<1:0> bits (see

is started when the pwm_count = PWMPH1<4:0> and

terminates on one of the following:

• Feedback through C1 or C2

• When the pwm_count equals PWMPH1<4:0>

• Combined feedback and pwm_count match

When COMOD<1:0> = 01, the duty cycle is controlled

only by feedback through comparator C1 or C2. In this

mode, the active drive cycle starts when pwm_count

equals PWMPH1<4: 0> and termi nates wh en compa ra-

tor C1’s output goes high (if enabled by

PWMPH1<5> = 1) or when comparator C2 output goes

high (if enabled by PWMPH1<6> = 1).

When COMOD<1:0> = 10, the duty cycle is controlled

only by the PWM Phase counter. In this mode, the

active drive cycle starts when the pwm_count equals

PWMPH1<4:0> and terminates when the pwm_count

equals PWMPH2<4:0>. For example, free running

50% duty cycle can be accomplished by setting

COMOD<1:0> = 10 and choosing appropriate values

for P WMPH1<4: 0> and PWMPH2<4:0>.

When COMOD<1:0> = 11, the duty cycle is controlled

by the phase counter or feedback through comparator

C1 or C2. For example, in this mode, the maximum

duty cycle is determined by the values of

PWMPH1<4:0> (duty cycle start) and PWMPH2<4:0>

(duty cycle end). The duty cycle can be terminated

earlier than the maximum by feedback through

comparator C1 or C2.

13.9.1 DEAD BAND CONTROL

The Complementary Output mode facilitates driving

series connected MOSFET drivers by providing dead

band drive timing between each phase output (see

Figure 13-6). Dead band times are selectable by the

CMDLY<4:0> bits of the PWMCON1 register. Delays

from 0 to 155 nanoseconds (typical) with a resolu tion of

5 nanoseconds (typical) are available.

13.9.2 OVERLAP CONTROL

Overla p timing c an be acco mplishe d by config uring the

Complementary mode for the desired output polarity

and overl ap time (as dead ti me) then swapping the out-

put connections and inverting the outputs. For exam-

ple, to configure a complementary drive for 55 ns of

overlap an d a n active-hi gh dri ve ou tput on PH1 an d a n

active-low drive output on PH2, set the PWM control

registers as follows:

• Connect PH1 driver to PH2 output

• Connect PH2 driver to PH1 output

• Initialize P ORTC<1> to 1 ( PH2 d river off)

• Initialize P ORTC<4> to 0 ( PH1 d river off)

• Set TRISC<1,4> to 0 for output

• Set PWMPH1<POL> to 1 (Inverted PH1)

• Set PWMPH2<POL> to 1 (Non-Inverted PH2)

• Set PWMCON1 for 55 ns delay and desired

termination (comparator, count or both)

• Set PWMCON0 desi red SYNC and auto-shut down

configuration and to enable PH1 an d PH2

13.9.3 SHUTDOWN IN COMPLEMENTARY

MODE

During shutdown the PH1 and PH2 complementary

outputs are forced to their inactive states (see

Figure 13-5). When shutdown ceases the PWM out-

puts revert to their start-up states for the first cycle

which is PH1 inactiv e (output undri ven) and PH2 active

(output driven).

PIC16F785/HV785

FIGURE 13-5: COMPLEM ENTARY OUTPUT PWM BLOCK DIAGRAM

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-5 COMOD<1:0>: Complementary Mode Select bits(1)

00 = Normal two-phase operation. Complementary mode is disabled.

01 = Complementary operation. Duty cycle is terminated by C1OUT or C2OUT.

10 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count.

11 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count or C1OUT or C2OUT.

bit 4-0 CMDLY<4:0>: Complementary Drive Dead Time bits (typical)

00000 =Delay = 0

00001 = Delay = 5 ns

00010 = Delay = 10 ns

••••• =• • •

11111 = Delay = 155 ns

Note 1: PWMCON 0<1:0> must be set to ‘11’ for Complementary mode operation.

Prescale

PWMPH1<C1EN>

PWMPH1<C2EN>

PWMPH2<4:0>

PWMPH2<POL>

PWMPH1<POL>

PWMPH1<4:0>

FOSC

C1OUT

C2OUT

PS<1:0>

pwm_clk

pha1

pha2

pwm_reset

Delay S

R(1)

10 delay S

R(1)

COMOD<1:0>

CMDLY<4:0>

RC1/AN5/C12IN1-/PH1

RC4/C2OUT/PH2

Phase

Counter

PER<4:0>

5pwm_count

PWMASE MASTER

Res

PH1EN

PH2EN

PASEN

RB7/SYNC

pwm_reset

Shutdown

Note 1: Reset dominant.

PIC16F785/HV785

FIGURE 13-6: COMPLEMENTARY OUTPUT PWM TIMING

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

othe r Resets

CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 0000 0000 0000 0000

CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 0000 0000 0000 0000

PWMCLK PWMASE PWMP1 PWMP0 PER4 PER3 PER2 PER1 PER0 0000 0000 0000 0000

PWMCON0 PRSEN PASEN BLANK2 BLANK1 SYNC1 SYNC0 PH2EN PH1EN 0000 0000 0000 0000

PWMCON1 — COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0 -000 0000 -000 0000

PWMPH1 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 0000 0000

PWMPH2 POL C2EN C1EN PH4 PH3 PH2 PH1 PH0 0000 0000 0000 0000

REFCON — — BGST VRBB VREN VROE CVROE —--00 000- --00 000-

VRCON C1VREN C2VREN VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data PWM

module.

01230112301

FOSC

SYNC

pwm_count

pwm_clk

C1OUT

pha1

pha2

Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BL AN Kx = X, COMOD<1: 0> = 0x01

PWMP<1:0> = 0X01, PER<4:0> = 0X03

Delay Delay

Shutdown

PIC16F785/HV785

14.0 DAT A EEPROM MEMORY

The EEPROM data memory is readable and writable

during norma l operation (full VDD range). This memo ry

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDAT

• EEADR

EEDAT holds the 8-bit da t a fo r read/ write , and EEADR

holds the address of the EEPROM location being

accessed. The PIC16F785/HV785 has 256 bytes of

data EEPROM with an address range from 0h to FFh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the n ew data (erase be fore write). The EEPROM

data memory is rated for high eras e/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip-to-chip. Please refer to AC Specifications in

Section 19.0 “Electrical Specifications” for exact

limits.

When the data memory is code-protected, the CPU

may continue to read and write the data EEPROM

memory . The device programmer can no longer access

the data EEPROM data and will read zeroes.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEDATn: Byte Value to Write to or Read From Data EEPROM bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits

PIC16F785/HV785

14.1 EECON1 and EECON2 Registers

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are non-

impleme nted and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of th e r ead or wr i t e ope r a tio n. T he in a bi l it y to cl ea r the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bi t is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal

operatio n. In these s ituations , following Reset, th e user

can check the WRERR bit, clear it and rewrite the loca-

tion. The EEDAT and EEADR registers are cleared by

a Reset. Therefore, the EEDAT and EEADR registers

will need to be re-initialized.

Interrupt flag EEIF bit of the PIR1 Register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

Note: The EECON1, EEDAT and EEADR

registers should not be modified during a

data EEPROM write (WR bit = 1).

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 IUnimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR reset)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a wr ite cycl e (The bit is cle ared by hardw are o nce wr ite is co mplet e. The WR b it ca n only

be set, not cleared, in software.)

0 = Write cycle to the data EEPROM is complete

bit 0 RD: Read Cont rol bit

1 = Initiates an EEPROM read (Read t akes one cycle. RD is cleared i n hardware. The RD bit c an only

be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

PIC16F785/HV785

14.2 Reading the EEPROM Dat a

Memory

To read a dat a memory location, the user must write the

address to the EEADR register and then set control bit

RD of the EECON 1 Register, as shown in Example 14-

1. The data is available, in the very next cycle, in the

EEDAT register. Therefore, it can be read in the next

instruction. EEDAT holds this value until another read,

or until it is written to by the user (during a write

operation).

EXAMPLE 14-1: DATA EEPROM READ

14.3 Writing to the EEPROM Data

Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 14-2.

EXAMPLE 14-2: DATA EEPROM WRITE

The wri te will not in itiate if the se quence in Ex ample 14-2

is not foll owe d ex ac tl y (w ri te 55 h to EECO N 2, writ e A Ah

to EECON2, th en set WR bi t) for each byte. It is str ongly

recommended that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating the EEPROM. The WREN bit is not cleared by

hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l

be inhibi ted from being s et u nle ss the W R EN bit is se t.

At the completion of the write cycle, the WR bit is

cleared in the hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit of the

PIR1 Register must be cleared by software.

14.4 Write Veri fy

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should b e verifie d (see Example 14-3) to the

desired value to be written.

EXAMPL E 14-3: WRITE VERIFY

14.4.1 USING THE DATA EEPROM

The dat a EEPROM is a hi gh-endu rance, byte a ddress-

able array that has been optimized for the storage of

frequently changing information (e.g., program

variables or other data that are updated often). When

variables in one section change frequently, while vari-

ables i n an other s ectio n do no t chang e, it is poss ible to

exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

total number of write cycles to a single byte (specifica-

tions D120 and D120A). If this is the case, then a

refresh of the array must be performed. For this reason,

variables that change infrequently (such as constants,

IDs, cali bration, etc.) should be stored in Flash program

memory.

14.5 Protect Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been buil t in. On power-u p, WREN is cleare d. Also, the

Power-up Timer (64 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit helps

prevent an accidental write during a brown-out, power

glitch and software malfunction.

BSF STATUS,RP0 ;Bank 1

BCF STATUS,RP1 ;

MOVLW CONFIG_ADDR ;

MOVWF EEADR ;Address to read

BSF EECON1,RD ;EE Read

MOVF EEDAT,W ;Move data to W

BSF STATUS,RP0 ;Bank 1

BCF STATUS,RP1 ;

BSF EECON1,WREN ;Enable write

BCF INTCON,GIE ;Disable INTs

BTFSC INTCON,GIE ;See AN-576

GOTO $-2 ;

MOVLW 55h ;Unlock write

MOVWF EECON2 ;

MOVLW AAh ;

MOVWF EECON2 ;

BSF EECON1,WR ;Start the write

BSF INTCON,GIE ;Enable INTs

Sequence

Required

BSF STATUS,RP0 ;Bank 1

BCF STATUS,RP1 ;

MOVF EEDAT,W ;EEDAT not changed

from previous write

BSF EECON1,RD ;YES, Read the

; value written

XORWF EEDAT,W ;

BTFSS STATUS,Z ;Is data the same

GOTO WRITE_ERR ;No, handle error

;Yes, continue

PIC16F785/HV785

14.6 Data EEPROM Operation During

Code-Protect

Data me mory can be co de-prot ected by program ming

the CPD bit in the Configuration Word (Register 15.2)

to ‘0’.

When the data memory is code-protected, the CPU is

able to read and write data to the data EEPROM. It is

recommended that the user code protect the program

memory when code protecting the data memory. This

prevents anyone from programming zeroes over the

existing code (w hich w ill execute as NOPs) to reach an

added routine, programmed in unused program mem-

ory, which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also hel p prev ent data memory code pr otec tion

from becom in g breac hed .

TABLE 14-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000

EECON2 EEPROM Control register 2 (not a physical register) ---- ---- ---- ----

EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon c ondition. Shaded cells are not used by

data EEPROM m od ule.

PIC16F785/HV785

15.0 SPECIAL FEATURES OF THE

CPU

The PIC1 6F785/HV785 has a host of fea tures intende d

to maximize system reliability, minimize cost through

elimination of external components, provide p ower sav-

ing features and offer code protection.

These features are:

• Reset:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Ti mer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator selection

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming™ (ICSP™)

The PIC16F785/HV785 has two timers that offer

necessary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

Reset until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a fixed

delay o f 64 ms (nominal) on power-up o nly , designed to

keep the part in Reset while the power supply stabi-

lizes. There is also circuitry to reset the device if a

brown-out occurs, which can use the Power-up Timer

to provide at least a 64 ms Reset. With these three

functions on-chip, most applications need no external

Reset circuitry.

The Sleep mode is de signe d to of fer a very low-c urrent

Power-down mode. The user can wake-up from Sleep

through an external Reset, Watchdog Timer Wake-up

or interrupt.

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost, while the LP crystal option saves

power. A set of configuration bits are used to select

various options (see Register 15.2).

15.1 Configurati on Bits

The configuration bits can be programmed (read as

‘0’), or left un programmed (read as ‘ 1’) to select various

device configurations as shown in Register 15.2.

These bits are mapped in program memory location

2007h.

Note: Address 2007h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/HV785

Memory Programming Specification”

(DS41237) fo r more in formatio n.

PIC16F785/HV785

U-0 U-0 U-0 U-0 R/P-0 R/P-0 R/P-1 R/P-1

— — — — FCMEN IESO BOREN1 BOREN0

bit 15 bit 8

R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend:

R = Rea da b l e bi t W = Writab l e b it U = Uni m pleme nt ed bit , re ad as ‘ 0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unkno wn

bit 13-12 FCMEN: Fail-Safe Clock Monitor Enabled bit(5)

1 = Fail-Saf e Cloc k Monitor is enabled

0 = Fail-Safe Clock Monitor is disabled

bit 10 IESO: Internal External Switchover bit

1 = Internal External Switchover mode is enabled

0 = Internal External Switchover mode is disabled

bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)

11 = BOR enabled

10 = BOR enabled during operation and disabled in Sleep

01 = BOR controlled by SBOREN bit (PCON<4>)

00 = BOR disabled

bit 7 CPD: Dat a Code Pr ot ectio n bi t(2), (3)

1 = Data memory code protection is disabled

0 = Data memory code protection is enabled

bit 6 CP: Code Protection bit(2)

1 = Program memory code protection is disabled

0 = Program memory code protection is enabled

bit 5 MCLRE: RA3/MCLR pin function select bit(4)

1 = RA3/MCLR pin function is MCLR

0 = RA3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 4 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit(5)

1 = WDT enabled

0 = WDT disable d and can be enabled by SWDTEN bit (WDTCO N<0>)

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN

110 = RCIO oscil lator: I/O func tion on RA4/AN3/T 1G/OSC2/CLK OUT pin, RC on RA5/T1CKI/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on

RA5/T1CKI/OSC1/CLKIN

100 = INTOSCIO oscillator: I/O function on RA4/AN3/T1G/ OSC2/CLKOUT pin, I/O function on

RA5/T1CKI/OSC1/CLKIN

011 = EC: I/O func tion on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T 1CKI/OSC1/CLKIN

010 = HS oscillator: High-speed crys tal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN(5)

001 = XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/ C LKI N(5)

000 = LP oscillator: Low-power crystal on RA4/AN3/T1G/OSC2/C LKOUT and RA5/T1CKI/OSC1/CLKIN(5)

Note 1: Enabling Brown-out Res et does not automa tic ally enable Power-up Timer.

2: Progr am memory bulk erase must be performed to turn off code protection.

3: The entire data EEPROM will be eras ed when the code protec tion is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

5: If the HS, XT, or LP oscillat or fails In Fail-safe mode the Watchdog time-out can occur only once after which it will be disabled

until the oscillator is restored.

PIC16F785/HV785

15.2 Reset

The PIC16F785/HV785 differentiates between various

kinds of Re set :

• Power-on Reset (POR)

• WDT Reset during normal operation

• WDT Reset during Sleep

•MCLR

Reset during normal operation

•MCLR Reset during S leep

• Brown-out Reset (BOR)

Some regi sters a re not af fected in any Rese t condi tion;

their st at us is un kn ow n o n POR a nd un ch ang ed in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on R eset

•MCLR

Reset

•MCLR

Reset du ring Sleep

•WDT Reset

• Brown-out Reset (BOR)

They are not affected by a WDT wake-up since this is

viewe d as the resumptio n of no rm al op eration. TO an d

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 15-2. These bits are

used in software to determine the nature of the Reset.

See Table 15-4 for a full description of Reset states of

all registers.

A simplif ied block diagra m of the On-Chip Rese t Circu it

is sh own i n Figure 15-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 19.0 “Electrical

Specifications” for pulse width specifications.

FIGURE 15-1: SI MPLI FIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

LFINTOSC

WDT

Time-out

Power- on Rese t

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out(1)

Reset SBOREN

BOREN

CLKI pin

Note 1: Refer to the Configuration Word register (Register 15.2).

PIC16F785/HV785

15.2.1 POWER-ON RESET

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. A minimum rise rate for VDD is re quired. Se e

Section 19.0 “Electrica l Specifica tions” for details. If

the BOR is enabled, the minimum rise rate specifica-

tion does not apply. The BOR circuitry will keep the

device in Reset until VDD reaches VBOR (see

Section 15.2.4 “Brown-Out Reset (BOR)”)

The POR ci rcu it, on thi s devic e, has a POR re-arm cir-

cuit. This circuit is designed to ensure a re-arm of the

POR circuit if VDD dro ps below a prese t re-armin g volt-

age (VPARM) for at least the minimum required time.

Once VDD is below the re- arming point f or the minimu m

required time, the POR Reset will reactivate and

remain in Reset until VDD returns to a value greater

than VPOR. At this point, a 1 μs (typical) delay will be ini-

tiated to allow VDD to continue to ramp to a voltage

safely above VPOR.

When the device starts normal operation (exits the

Reset condition), device operating parameters

(i.e., voltage, frequency, temperature, etc.) must be

met to ensure operation. If these conditions are not

met, the device must be held in Reset until the

operating conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

15.2.2 MASTER CLEAR (MCLR)

PIC16F785/HV785 has a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from earlier devices of this family.

Vo lta ges app lied to the pin th at exce ed it s s pecif icatio n

can resu lt in both MCL R Rese t s a nd e xc es sive c urre nt

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MC LR

pin no long er be tied direc tly to VDD. The use of an RC

network, as shown in Figure 15-1, is suggested.

FIGURE 15-2: REC OMME NDED MCLR

CIRCUIT

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word. When cleared,

MCLR is internally tied to VDD and an internal Weak

Pull-up is enabled for the MCLR pin. The VPP functi on

of the RA3/MCLR/VPP pin is not affected by selecting

the internal MCLR option.

15.2.3 POWER-UP TIMER (PWRT)

The P owe r-u p Timer pr ov ides a fi xed 64 ms (nomi nal )

time out on power-up only, from POR or Brown-out

Reset. The Power-up Ti mer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.4 “Internal Clock Mo des”. Th e ch ip is ke pt

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A config-

uration bit, PWRTE can disable (if ‘1’) or enable (if ‘0’)

the Power-up Timer. The Power-up Timer should be

enabled when Brown-out Reset is enabled, although it

is not required.

The Power-up Time Delay will vary from chip-to-chip

and vary due to:

•V

DD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 19.0

“Electrical Specifications”).

15.2.4 BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

W ord se lec t o ne of four BOR mod es . Two mode s h av e

been added to allow software or hardware control of

the BOR enable. When BOREN<1:0> = 01, the SBO-

REN bit of the PCON Register enables/disables the

BOR allowing it to be controlled in software. By select-

ing BORE N<1:0>, the BO R is automa tically d isabled in

Sleep to conserve power, and enabled on wake-up. In

this mode, the SBOREN bit is disabled. See

If VDD falls below VBOR for greater than parameter

(TBOR), see Section 19.0 “Electrical Specifica-

tions”, the Brown-out situation will reset the device.

This wi ll occur regardless of the VDD slew rate. A Reset

is not assured if VDD falls below VBOR for less than

parameter (TBOR).

On any Rese t (Power-on, Brown-out Reset, W atchdog,

etc.), the chip will r emain in Re set until VDD rises ab ove

VBOR (see F igur e 1 5-3) . The Po wer-u p Time r will now

be invoked, if enabled, and will keep the chip in Reset

an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-u p Timer will be re-initialized. Onc e VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

VDD

RA3/MCLR/VPP

1kΩ (or greater)

0.1 μF

(optional, not critical)

PIC16F785/HV785

Note: The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word.

PIC16F785/HV785

15.2.5 BOR CALIBRATION

The PIC16F785/HV785 stores the BOR calibration

values in fuses located in the Calibration Word (2008h).

The Calibration Word is not erased when using the

specified bulk erase sequence in the “PIC16F785/

HV785 Memory Programming Specification”

(DS4123 7) and thus , doe s not requi re repr ogramming.

FIGURE 15-3: BROWN-OUT SITUATIONS

Note: Address 2008h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/HV785

Memory Programming Specification”

(DS41237) f o r m ore in f o r m a t i o n .

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset 64 ms(1)

<64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F785/HV785

15.2.6 TIME-OUT SEQUENCE

On power- up, the t ime-out sequ ence is a s follows: first,

PWRT time out is invoked after POR has expired, then

OST is activated after the PWRT time out has expired.

The total time out will vary based on oscillator configu-

ration and PWRTE bit stat us. For exampl e, in EC mode

with PWR TE bit equal to ‘1’ (PWR T disabled), there will

be no time out at all. Figure 15-4, Figure 15-6 and

Figure 15-6 depict ti me-out sequences. The device can

execut e code from the INT OSC, whi le OST is active by

enablin g Two-S pee d Start-up or Fai l-Saf e M on itor (see

Section 3.6.2 “Two-Speed Start-up Sequence” and

Section 3.7 “Fail-Safe Clock Monitor”).

Since th e time ou ts oc cur from th e POR puls e, if MCLR

is kept low long en ough, the time out s will ex pire. The n

bringing MCLR high will begin execution immediately

(see Figure 15-6). This is useful for testing purposes or

to synchronize more than one PIC16F785/HV785

device operating in parallel.

Table 15-5 shows the Reset conditions for some

special registers, while Table 15-4 shows the Reset

conditions for all the registers.

15.2.7 POWER CONTROL (PCON)

The Power Cont rol register (add ress 8Eh) has two S t a-

tus bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00 in the Configuration Word).

Bit 1 is POR (Power-on Reset). It is ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

For more inf ormation, see Section 15.2.4 “Brow n-Out

Reset (BOR)”.

TABLE 15-1: TIME OUT IN VARIOUS SITUATIONS

TABLE 15-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Oscillator Configuration Power-up Brown-out Reset Wake-up from

Sleep

PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1

XT, HS, LP TPWRT +

1024•TOSC 1024•TOSC TPWRT +

1024•TOSC 1024•TOSC 1024•TOSC

RC, EC, INTOSC TPWRT —TPWRT ——

POR BOR TO PD Condition

0x11Power-on Reset

u011Brown-out Reset

uu0uWDT Reset

uu00WDT Wake-up

uuuuMCLR Reset during normal operation

uu10MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

PCON — — —SBOREN——PORBOR ---1 --qq ---1 --qq

STATUS IRP RP1 RP0 TO PD ZDC C0001 1xxx 0001 1xxx

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are

not used by BOR.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

PIC16F785/HV785

FIGURE 15-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

FIGURE 15-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

PIC16F785/HV785

TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS

WDT Reset

Brown-out Reset(1)

Wake-up from Sleep through interrupt

Wake-up from Sleep through WDT Time-out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h --x0 x000(6) --u0 u000(7) --uu uuuu

PORTB 06h xx00 ----(6) uu00 ----(7) uuuu ----

PORTC 07h 00xx 0000(6) 00uu uuuu(7) uuuu uuuu

PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2)

PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H 14h xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 15h --00 0000 --00 0000 --uu uuuu

WDTCON 18h ---0 1000 ---0 1000 ---u uuuu

ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh 0000 0000 0000 0000 uuuu uuuu

OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h --11 1111 --11 1111 --uu uuuu

TRISB 86h 1111 ---- 1111 ---- uuuu ----

TRISC 87h 1111 1111 1111 1111 uuuu uuuu

PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu

PCON 8Eh ---1 --0x ---u --uq (1,5) ---u --uu

OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu

OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu

ANSEL0 91h 1111 1111 1111 1111 uuuu uuuu

PR2 92h 1111 1111 1111 1111 1111 1111

ANSEL1 93h ---- 1111 ---- 1111 ---- uuuu

WPUA 95h --11 1111 --11 1111 --uu uuuu

IOCA 96h --00 0000 --00 0000 --uu uuuu

REFCON 98h --00 000- --00 000- --uu uuu-

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up) .

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 15-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Analog channels read 0 but data latches are unknown.

7: Analog channels read 0 but data latches are unchanged.

PIC16F785/HV785

VRCON 99h 000- 0000 000- 0000 uuu- uuuu

EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu

EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh ---- ---- ---- ---- ---- ----

ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON1 9Fh -000 ---- -000 ---- -uuu ----

PWMCON1 110h -000 0000 -000 0000 -uuu uuuu

PWMCON0 111h 0000 0000 0000 0000 uuuu uuuu

PWMCLK 112h 0000 0000 0000 0000 uuuu uuuu

PWMPH1 113h 0000 0000 0000 0000 uuuu uuuu

PWMPH2 114h 0000 0000 0000 0000 uuuu uuuu

CM1CON0 119h 0000 0000 0000 0000 uuuu uuuu

CM2CON0 11Ah 0000 0000 0000 0000 uuuu uuuu

CM2CON1 11Bh 00-- --10 00-- --10 uu-- --uu

OPA1CON 11Ch 0--- ---- 0--- ---- u--- ----

OPA2CON 11Dh 0--- ---- 0--- ---- u--- ----

TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

WDT Reset

Brown- out Reset(1)

Wake-up from Sleep through interrupt

Wake-up from Sleep through WDT Time-out

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up) .

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 15-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Analog channels read 0 but data latches are unknown.

7: Analog channels read 0 but data latches are unchanged.

PIC16F785/HV785

TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---1 --0x

MCLR Reset during normal operation 000h 000u uuuu ---u --uu

MCLR Reset during Sleep 000h 0001 0uuu ---u --uu

WDT Reset 000h 0000 uuuu ---u --uu

WDT Wake- up PC + 1 uuu0 0uuu ---u --uu

Brown-out Reset 000h 0001 1uuu ---1 --u0

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---u --uu

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the

interrupt v ector (0 004h) afte r execution of PC + 1.

PIC16F785/HV785

15.3 Interrupts

The PIC16F785/HV785 has 11 sources of interrupt:

• External Interrupt RA2/IN T

• TMR0 Overflow Interru pt

• PORTA Change Interrupt

• 2 Comparator Interrupts

• A/D Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt

The Interrup t Control register (INTCON) and Peripheral

Interrupt register (PIR1) record individual interrupt

requests in flag bits. The INTCON register also has

individual and global interrupt enable bits.

A Globa l Inte rrupt Ena ble b it, GI E of the INT CON Re g-

ister enables (if set) all unmasked interrupts, or dis-

ables (i f clear ed) a ll inte rrupt s. Indi vi dual in terrupt s ca n

be disabled through their corresponding enable bits in

INTCON register and PIE1 register. GIE is cleared on

Reset.

The Return from Interrupt instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which

re-enables unmasked inte rrupts.

The following interrupt flags are contained in the INT-

CON register:

• INT Pin Interrupt

• PORTA Change Interrupt

• TMR0 Overflow Interru pt

The peripheral interrupt flags are contained in the

special register PIR1. The corresponding interrupt

enable bit is contained in special register PIE1.

The following interrupt flags are contained in the PIR1

• EEPROM Data Write Interrupt

• A/D Interrupt

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt

• The return address is PUSHed onto the stack

• The PC is loaded with 0004h

For external interrupt events, such as the INT pin or

PORTA change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 15-8). The latency is the same for one or two-

cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

For additional information on Timer1, Timer2,

comparators, A/D, Data EEPROM or CCP modules,

refer to the respective peripheral section.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

PIC16F785/HV785

15.3.1 RA2/AN2/T0CKI/INT/C1OUT

INTERRUPT

External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin

is edge-triggered; either rising, if INTEDG bit of the

OPTION Register is set, or falling, if INTEDG bit is

clear. When a valid edge appears on the RA2/AN2/

T0CKI/INT/C1OUT pin, the INTF bit of the INTCON

Regis ter i s set. Th is interrupt can be dis ab led by cle ar-

ing the INTE control bit of the INTCON Register. The

INTF bit must be cleared in software in the Interrupt

Service Routine before re-enabling this interrupt. The

RA2/AN2/T0CKI/INT/C1OUT interrupt can wake-up

the proce ssor from Sleep if the INTE bit was set prio r to

going into Sleep. The status of the GIE bit decides

whether or not the processor branches to the interrupt

vector following wake-up (0004h). See Section 15.6

“Power-Down Mod e (Sleep )” for d etails on Sleep an d

Figure 15-10 for timing of wake-up from Sleep through

RA2/AN2/T0CKI/INT/C1OUT interrupt.

15.3.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF bit of the INTCON Register. The interrupt can

be enabled/disabled by setting/clearing T0IE bit of the

INTCON Register. See Section 5.0 “Timer0 Module”

for operation of the Tim er0 mo dul e.

15.3.3 PORTA INTERRUPT

An input change on PORTA change sets the RAIF of

the INTCO N Register bit. The interrupt c an be enable d/

disabl ed by setting/clearing the RAIE bit of the INTCON

through the IOCA register.

FIGURE 15-7: INTERRUP T LOGIC

Note: The ANSEL0 (91h), and ANSEL1 (93h)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 c ycle), then the RAIF int er-

rupt flag may not get set.

TMR1IF

TMR1IE

C1IF

C1IE

T0IF

T0IE

INTF

INTE

RAIF

RAIE

GIE

PEIE

Wake-up (If in Sleep mode)(1)

Inte rrup t to C PU

EEIE

EEIF

ADIF

ADIE

IOC-RA0

IOCA0

IOC-RA1

IOCA1

IOC-RA2

IOCA2

IOC-RA3

IOCA3

IOC-RA4

IOCA4

IOC-RA5

IOCA5

TMR2IF

TMR2IE

CCP1IF

CCP1IE

OSFIF

OSFIE

C2IF

C2IE

Note 1: Some peripherals depend upon the system clock for

operation. Since the system clock is suspended during Sleep, only

those peripherals which do not depend upon the system clock will wake

the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”.

PIC16F785/HV785

FIGURE 15-8: INT PIN INTERRUPT T IMING

TABLE 15-6: SUMMARY OF INTERRUPT REGISTERS

Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 B i t 1 Bit 0 Valu e on

POR, BOR Value on all

other Re s e ts

INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 0000

PIE1 EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not

used by the Interrupt module.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF Fl a g

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC + 1)

Inst (PC - 1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interru pt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycl e time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1) (2)

(3) (4)

(5)

(1)

PIC16F785/HV785

15.4 Context Saving During Interr upts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since the last 16 bytes of all banks are common in the

PIC16F785/HV785 (see Figure 2-2), temporary hold-

ing registers W_TEMP and STATUS_TEMP should be

placed in here. These 16 locations do not require

bankin g, therefore, making it e asier to save an d restore

context. The same code shown in Example 15-1 can

be used to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

EXAMPLE 15-1: SAVING STATUS AND W REGISTERS IN RAM

Note: The PIC16 F785/H V785 normal ly does not

require saving the PCLATH. However, if

computed GOTO’ s are u sed in th e ISR an d

the main code, the PCLATH must be

saved and restored in the ISR.

MOVWF W_TEMP ;Copy W to TEMP register

SWAPF STATUS,W ;Swap status to be saved into W (swap does not affect status)

CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

:(ISR) ;Insert user code here

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into Status register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F785/HV785

15.5 Watchdog Timer (WDT)

For PIC16F785/HV785, the WDT has been modified

from previous PIC16FXXX devices. The new WDT is

code and functionally compatible with previous

PIC16FXXX WDT m odules and adds a 16-bit presc aler

to the WDT. This allows the user to scale the value for

the WDT and TMR0 at the same time. In addition, the

WDT time out value can be extended to 268 seconds.

WDT is cleared under certain conditions described in

Table 15-7.

15.5.1 WDT OSCILLATO R

The WDT derives its time base from the 31 kHz LFIN-

TO SC. The LTS bit does not reflec t that the LFINT OSC

is enabled (OSCON<1>).

The value of WDTCON is ‘---0 1000’ on a ll Re sets.

This gives a nominal time base of 16 ms, which is

compatible with the time base generated with previous

PIC16FXXX microcon trol le r versions.

A new prescaler has been added to the path between

the INT RC and the m ultipl exers used t o select the pa th

for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTRC by 128 to 65536,

giving the time base us ed for the WDT a nominal range

of 1 ms to 268s.

15.5.2 WDT CONTROL

The WDTE bit is located in the Configuration Word.

When set, the WDT runs continuously.

When the WDTE bit i n the Configurati on Word register

is set, the SWDTEN bit of the WDTCON Register has

no effect. If WDTE is clear, then the SWDTEN bit can

be used to ena ble and disable th e WDT. Setting the b it

will enable it and clearing the bit will disable it.

The PSA and PS<2:0> bits of the OPTION Register

have the same function as in previous versions of the

PIC16FXXX family of microcontrollers. See

Section 5.0 “Timer0 Module” for more information.

FIGURE 15-9: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 15-7: WDT STATUS

Note: When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

bec ause the WD T Ri pple Cou nte r i s us ed

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

Conditions WDT

WDTE = 0

Cleared

CLRWDT command

OSC FAIL detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

31 kHz PSA

16-bit WDT Prescaler

From TMR0 Clock Source

PS<2:0>

PSA

WDT Time-out

TO T MR 0

WDTPS<3:0>

WDTE from Configuration Word

SWDTEN from WDTCON

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

Prescaler(1)

8-bit

PIC16F785/HV785

TABLE 15-8: SUMMARY OF WATCHDOG TIMER REGISTERS

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = reserved

1101 = reserved

1110 = reserved

1111 = reserved

bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)

1 = WDT is turned on

0 = WDT is turned off (Reset value)

Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE con-

figuration bit = 0, then it is possible to turn WDT on/off with this control bit.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on all

other

Resets

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 15.2 for operation of all Configuration Word bits.

PIC16F785/HV785

15.6 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running

•PD

bit in the STATUS register is cleared

•TO

bit is set

• Oscillator driver is turned off

• I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin and all unused

peripheral modul es s ho uld be disabl ed . D i gital I/O pins

that are high-impedance inputs should be pulled high,

or low, externally to avoid sw itching curre nts ca used by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribu tion from on-c hip pull-ups on PORTA should be

considered.

The MCLR pin must be at a logic high level.

15.6.1 WAKE-UP FROM SLEEP

The devi ce can wa ke-up from Sleep through one of th e

following events:

1. External Reset input on MCLR pin

2. Watchdog T imer W ake-up (if WDT was ena bled)

3. Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin,

PORTA change or a peripheral interrupt.

The firs t event wi ll ca use a de vice Res et. The two latter

events are considered a continuation of program exe-

cution. The T O an d PD bit s in the STATUS register ca n

be used to determine the cause of device Reset. The

PD bit, which is set on power-up, is cleared when Slee p

is invoked. TO bit is cleare d if W DT Wake-u p occurre d.

The follo wing periph eral interrupt s can wake the device

from Sleep:

• TMR1 interrupt; Timer1 must be operating as an

asynchronous counter.

• CCP Capture mode interrupt

• A/D conversion (when A/D clock source is RC)

• EEPROM write operation completion

• Comparator output changes state

• Interrupt-on-change

• External Interrupt from INT pin

Other peripherals cannot generate interrupts since,

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up thro ugh an interrupt eve nt, the co rres pon din g

interrupt enable bit (and PEIE bit where applicable)

must be set (enabled). Wake-up is regardless of the

state of the GIE bit. If th e GIE bit is clear (disa bled), the

device continues execution of the instruction after the

SLEEP instruction. If the GIE bit is set (enabled), the

device executes the instruc tion afte r the SLEEP instruc-

tion, then bra nches to the interru pt address (00 04h). In

cases where the execution of the instruction, following

SLEEP, is not desired, the user should place a NOP

after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

15.6.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (i.e., GIE bit of the

INTCON regi ster is cl ear) and any interrupt source has

both it s interrupt enable bit and interrupt flag bit set, one

of the fo llowing will o c cur:

• If the interrupt occurs before the execution of a

SLEEP instruction, the SLEEP instruction will

comple te as a NOP. Therefore, th e WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. The refore, the WDT and WDT pres caler

and pos tsc aler (if enable d) wi ll be c leared , the T O

bit will be set, and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruct ion completes. To

determine whether a SLEEP ins tructio n execut ed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

When global interrupts are disabled, a CLRWDT

instruction should be executed before a SLEEP

instruction to ensure that the WDT is cleared.

Note: It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

Note: If the g lobal interrup ts a re di sable d (GIE is

cleared ), but any interrup t source has bo th

it s interrupt enabl e bit and the corres pond-

ing interrupt flag bits set (including PEIE,

where applicable), the device will immedi-

ately wake-up from Sleep. The SLEEP

instruction is completely executed.

PIC16F785/HV785

FIGURE 15-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1)

15.7 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP™ for verifi cation purposes.

15.8 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are

readable and writable during Program/Verify. Only the

Least Significant 7 bits of the ID locations are used.

15.9 In-Circuit Serial Programming™

(ICSP™)

The PIC16F785/HV785 microcontrollers can be seri-

ally programmed while in the end application circuit.

This is simply done with five lines:

•Clock

•Data

•Power

•Ground

• Programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allow s the most recent firmw are, or a cus tom fi rmwar e,

to be programmed.

The device is placed into a Program/Verify mode by

holding the RA0 and RA1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH. See the “PIC16 F785/

HV785 Memory Programming Specification”

(DS41237) for more information. RA0 becomes the

programming data and RA1 becomes the programming

clock. Both RA0 and RA1 are Schmitt Trigger inputs in

this mode.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the “PIC16F785/HV785 Memory Pr ogr amm in g S peci -

fication” (DS41237).

A typical In-Circuit Serial Programming connection is

shown in Figure 15-11.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor

in Sleep

Interrupt Latency(3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC + 2

Note 1: XT, HS or LP Oscilla tor mode assume d.

2: TOST = 1024TOSC (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up

(see Section 3.6 “Two-Speed Clock Start-up Mode”).

3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h.

If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

Note: If the code protection is turned off, the

entire data EEPROM and Flash program

memory will be erased by performing a

bulk erase command. See the

“PIC16F785/HV785 Memory Program-

ming Specification” (DS41237) for more

information.

PIC16F785/HV785

FIGURE 15-11: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

15.10 In-Circuit Debugger

• In-circuit debuggin g requires clock, data and

MCLR pins. A special 28-pin PIC16F785-ICD

device is used with MPLAB® ICD 2 to provide

separate clock, data and MCLR pins so that no

pins are lost for these functions, leaving all 18 of

the PIC16F785/HV785 I/O pins available to the

user during debug operation.

• This special ICD device is mounted on the top of a

header and its signals are routed to the MPLAB

ICD 2 c onnec tor. On t he bot tom of the he ader i s a

20-pin socket that plugs into the user’s target via

the 20-pin stand-off connector.

• When the ICD pin on the PIC16F785-ICD device

is held low, the In-Circuit D ebugger functiona lity is

enabled. This function allows simple debugging

functions when used with MPLAB ICD 2. When

the microcontroller has this feature enabled, some

of the re so urces are no t availa ble for ge neral u se.

Table 15-9 shows which features are consumed

by the background debugger.

TABLE 15-9: DEBUGGER RESOURCES

For more information, see “MPLAB® ICD 2 In-Circuit

Debugger User’s Guide” (DS51331), available on

Micro chip’s we b site (www.microchip.c om).

FIGURE 15-12: 28-PIN ICD PINOUT

Resource Description

I/O pins ICDCLK, ICDDATA

Stack 1 level

Data RAM 65h-70h, F0h

Program Memory Address 0h mu st be NOP

700h-7FFh

External

Connector

Signals

To Normal

Connections

To Normal

Connections

VDD

VSS

MCLR/VPP/RA3

RA1

RA0

+5.0V

VPP

CLK

Data I/O

* * *

* Isolation devices (as required)

PIC16F785

28-Pin PDIP

PIC16F785/HV785-ICD

In-Circuit Debug Device

SHNTREG

ICDMCLR/VPP

VDD

RA5

RA4

RA3

ICDCLK

ICDDATA

Vss

RA0

RC6 RB4

RA1

RA2

RC5

RC4

RC3

RC0

RC1

RC2

NC NC

RC7

RB7

ICD

RB5

RB6

PIC16F785/HV785

16.0 VOLTAGE REGULATOR

The PIC16HV785 includes a permanent internal 5 volt

(nominal) shunt regulator in parallel with the VDD pin.

This elim inates the need for an external volt age regula-

tor in systems sourced by an unregulated supply. All

external devices connected directly to the VDD pin will

share the regulated supply voltage and contribute to

the total VDD supply current (ILOAD).

16.1 Regulator Operation

The regulator operates by maintaining a constant

voltage at the VDD pin by adjusting the regulator shunt

current in res ponse to variation s of the VDD supply load

and the unregulated supply voltage. The regulator

behaves like a fully compensated Zener diode. (See

Figure 16-1).

FIGURE 16-1: REGULATOR

An external current limiting resistor, RSER, located

betwee n the u nreg ulated supp ly, V UNREG, and the VDD

pin, drops the difference in voltage between VUNREG

and VDD. RSER must be between RMAX and RMIN as

defined by Equatio n 16-1.

EQUATION 16-1: RSER LIMITING RESISTOR

16.2 Regulator Precautions

The total VDD load curren t varia tion must be less than

46 mA so that it falls within the voltage regulator shunt

current dynamic range. If the load current rises above

the expected maximum, the regulator will be starved for

current and go out of regulation causing VDD to drop.

Since the regulator uses the band gap voltage as the

regu lated voltag e refe renc e, th e VR vo ltage r efer ence

is permanently enabled in the PIC16HV785 device.

(used on blank pages to make page count even)

VUNREG

RSER

VDD To other circuitry

PIC16HV785

Voltage

Regulator

RMAX = (VUMIN - VDD) • 1000

1.05 • (4 MA + ILOAD)

RMIN = (VUMIN - VDD) • 10 00

0.95 • (50 MA)

Where:

RMAX = maximum value of RSER (ohms)

RMIN = minimum value of RSER (ohms)

VUMIN = minimum value of VUNREG

VUMAX= maximum value of VUNREG

VDD = regulated voltage (5V nominal)

ILOAD = maximum expected load current in mA

including I/O pin currents and external

circuits connected to VDD.

1.05 = com pensa tion for +5 % tolera nce of RSER

0.95 = compensation for -5% tolerance of RSER

PIC16F785/HV785

17.0 INSTRUCTION SET SUMMARY

The PIC1 6F785/HV 785 instructio n set i s high ly ortho g-

onal and is comprised of three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the ins truc tio n. The format for e ach o f th e c ate go ries i s

presented in Figure 17-1, while the various opcode

fields are sum m ariz ed in Table 17-1.

Table 17-2 lists the instructions recognized by the

MPASMTM assembler.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zer o, t h e r esu lt is

placed in the W re gister . If ‘d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operatio n, whi le ‘f’ re pre sen t s t he ad dres s o f the file i n

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency o f 4 MHz, t his gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

change d as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies

a hexadecimal digit.

17.1 Read-Modify-Write Op erations

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (RMW)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is always performed, even if the instruction is a Write

command.

For example, a CLRF PORTA instruction will read

PORT A, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

result of clearing the condition that set the RAIF flag.

TABLE 17-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 17-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future products, do not use the OPTION

and TRIS instructions.

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral fie ld, constant data or label

xDon’t care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

PD Power-down bit

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

d = 1 for destination f

Bit-oriente d file register operations

13 10 9 7 6 0

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

k = 8-bit immediate value

13 11 10 0

k = 11-bit immediate value

General

CALL and GOTO instructions only

OPCODE d f (FILE #)

f = 7-bit file register address

OPCODE b (BIT #) f (FILE #)

OPCODE k (literal)

PIC16F785/HV785

TABLE 17-2: PIC16F785/HV785 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcod e Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

–

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that v alue present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

PIC16F785/HV785

17.2 Instructi on Descriptions

ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the W

ADDWF Add W and f

Syntax: [label] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (destination)

Status Affected: C, DC, Z

Desc ription: Add the contents o f the W regis ter

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W registe r . I f

‘d’ is ‘1’, the result is stored back

in register ‘f’.

ANDLW AND Literal with W

Syntax: [label] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

‘k’. The r esult is placed in the W

ANDWF AND W with f

Syntax: [label] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (destination)

St at us Af fe cte d: Z

Description: AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

BCF Bit Clear f

Syntax: [label] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

St at us Af fe cte d: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [label] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

St at us Af fe cte d: None

Description: Bit ‘b’ in register ‘f’ is set.

PIC16F785/HV785

BTFSC Bit Test f, Skip if Clear

Syntax: [label] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Desc ription: If bit ‘b’ in regis ter ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOP is exec uted instead , making

this a two-cycle instruction.

BTFSS Bit Test f, Skip if Set

Syntax: [label] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Desc ription: If bit ‘b’ in register ‘f’ is ‘0’, th e next

instructi on is exec uted .

If bit ‘b’ is ‘1’, then the n ext inst ruc-

tion is discarded and a NOP is

executed instead, making this a

two -cycle instruc tion.

CALL Call Subroutin e

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 204 7

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit immedi-

ate a ddress is loade d into P C bit s

<10:0>. The upper bits of the PC

are loaded from PCLATH. CALL

is a two-cycle instructi on.

CLRF Clear f

Syntax: [label] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

St at us Af fe cte d: Z

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

St at us Af fe cte d: Z

Description: W register is cleared. Zero bit (Z)

is se t.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

St at us Af fe cte d: T O , PD

Description: CLRWDT instruction resets the

W atchdog T imer . It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

PIC16F785/HV785

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in regis-

ter ‘f’.

DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

registe r. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decrem ented. If ‘d’ is ‘0’, th e result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next instruc-

tion is ex ecute d. If the resu lt is ‘0’,

then a NOP is executed instead,

making it a two- cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

St at us Af fe cte d: None

Description: GOTO is an unconditional branch.

The e leven-bit imme diate value i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a two-

cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination)

St at us Af fe cte d: Z

Description: The contents of register ‘f’ are

incremen ted. If ‘d’ is ‘0’, the res ult

is placed in the W register . If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination),

skip if result = 0

St at us Af fe cte d: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next in struc-

tion is executed. If the result is ‘0’,

a NOP is execu ted inst ead, maki ng

it a two-cycle instruction.

PIC16F785/HV785

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Descrip tion: The co ntents of the W register

are OR’ed with the ei ght-bit literal

‘k’. The result is placed in the W

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (destina tion)

Status Affected: Z

Description: Inclusive OR the W register with

placed in the W register. If ‘d’ is

‘1’, the result is placed bac k in

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The c ontents of register ‘f’ is

moved to a destination depen-

dent upon the sta tus of ‘d’. If ‘ d’ =

0, destination is W register. If ‘d’

= 1, the des tina tion is f ile register

‘f’ itself. ‘d’ = 1 is useful to test a

file register since status flag Z is

affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

St at us Af fe cte d: None

Encoding: 11 00xx kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded

into W register. The “don’t cares”

will assemble as 0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

St at us Af fe cte d: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

St at us Af fe cte d: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

PIC16F785/HV785

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS)

is loa ded in th e PC. In terrupts are

enabled by setting Global

Interrupt Enable bit, GIE of the

INTCON Register. This is a two-

cycle instruction.

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with

the eight-bit literal ‘k’. The pro-

gram cou nter is loaded from the

top of the stack (the return

address). This is a two-cycle

instruction.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Description: Return f rom subroutine. The stack

is POPed an d t he top o f th e s t a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

St at us Af fe cte d: C

Encoding: 00 1101 dfff ffff

Descr ipti on : The content s of regi ste r ‘f’ are

rotat ed one bi t to the lef t throu gh

the Carry Flag. If ‘d’ is ‘0’, the

result is p laced in th e W re giste r.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operati on: See description below

St at us Af fe cte d: C

Encoding: 00 1100 dfff ffff

Description: The contents of register ‘f’ are

rotated one bit to the right

through the Carry Flag. If ‘d’ is

‘0’, the result is placed in the W

placed back in registe r ‘f ’.

SLEEP Go into Standby mode

Syntax: [label] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

St at us Af fe cte d: T O, PD

Encoding: 00 0000 0110 0011

Description: The power-down Status bit, PD

is cleared. Time out Status bit,

TO is set. W atchdog T imer and

it s pres ca ler are cl eare d .

The processor is put into Sleep

mode with the oscillator

stopped.

PIC16F785/HV785

SUBLW Subtract W from Literal

Syntax: [label]SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected: C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

C = 1; result is pos iti ve or zero

C = 0; result is neg ati ve

SUBWF Subtract W from f

Syntax: [label] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected: C, DC, Z

Encoding: 00 0010 dfff ffff

Desc ript ion : Subtract (2’s c om ple me nt m eth od)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stor ed bac k in regi ste r ‘f’.

C = 1; result is positive or zero

C = 0; result is negative

SWAPF Swap Nibbles in f

Syntax: [ label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status

Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of

is ‘0’, the result is placed in W

placed in register ‘f’.

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: 5 ≤ f ≤ 6

Operation: (W) → TRIS register f;

St at us Af fe cte d: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for

code compatibility with the

PIC16C5X prod uc t s. Since TRIS

registers are readable and

writ abl e, the us er can dire ctl y

address them.

Words: 1

Cycles: 1

Example: To maintain upward compati-

bility with future PIC®

products, do not use this

instruction.

XORLW Exclusive OR Literal with W

Syntax: [label]XORLW k

Operands: 0 ≤ k ≤ 255

Operati on: (W) .XOR. k → (W)

St at us Af fe cte d: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed

in the W register.

PIC16F785/HV785

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status

Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’

is ‘0’, the result is stored in the

W register. If ‘d’ is ‘1’ t he result i s

stored back in register ‘f’.

PIC16F785/HV785

NOTES:

PIC16F785/HV785

18.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Programmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

18.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold sep ara tel y)

- I n-Ci rcuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensi ve on-l in e help

• Inte gration of select thir d party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your s ource files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using :

- Source file s (asse mbly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC16F785/HV785

18.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

18.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 and PIC24 families of microcon-

trollers and the dsPIC30 and dsPIC33 family of digital

signal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compil ers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

18.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and ex traction

18.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directi ve set

• Flexible macro language

• MPLAB IDE compatibility

18.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC16F785/HV785

18.7 MPLAB ICE 2000

High-Performance

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

18.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated D evelopment Environment (IDE),

included with each kit.

The MPLAB REAL ICE pro be is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or w ith the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB ID E, new devic es w ill be supported,

and new features will be added, suc h as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages ov er competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables .

18.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step -

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

18.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions an d

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC16F785/HV785

18.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated D evelopm ent Envir onment software m akes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

18.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash m emory microcon trollers. The PICkit 2 S tarter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler , and is desig ned to hel p get up to s peed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

18.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards includ e prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

PIC16F785/HV785

19.0 ELECTRICAL SPECIFICATIONS

Abso lut e Maximum Ratings(†)

Ambient temperature under bias.................................................................................................................-40 to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Vo lt a ge on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V

Vo lt a ge on MCLR with respect to Vss ........................................................................................................-0.3 to +13.5V

Voltage on RB6 open-drain pin with respect to Vss .....................................................................................-0.3 to +8.5V

Voltage on all other pins with respect to VSS .................................................................................-0.3V to (VDD + 0.3V)

Total power dissipation(1) (PDIP and SOIC).........................................................................................................800 mW

Total power dissipation(1) (SSOP)........................................................................................................................600 mW

Maximum curr ent out of VSS pin ...........................................................................................................................300 mA

Maximum curr ent into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)................................................................................................................ ±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTC (combined).................................................................200 mA

Maximum current sourced PORTA, PORTB, and PORTC (combined).................................................................200 mA

Note 1: Power diss ip ation is ca lcula ted as follo ws: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a s tress rating on ly and fu nctional ope ration of the device at th ose or any ot her conditi ons abov e those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a s eries resis tor of 50-100Ω s hould be used when a pplying a “low” lev el to the MC LR pin, rathe r than

pulling this pin d irect ly to VSS.

PIC16F785/HV785

FIGURE 19-1: PIC16F785/HV785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH,

-40°C

≤

+125°C(2)

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)(2)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is

after the postscaler.

3: The internal shunt regulator of the PIC16HV785 keeps VDD at or below 5.0V (nominal).

81612 2010

(3)

PIC16F785/HV785

19.1 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001

D001A

D001B

D001C

D001D

VDD Supply Voltage(2) 2.0

2.2

2.5

3.0

4.5

—

5.5

FOSC ≤ 4 MHz:

PIC16F785 with A/D off

PIC16F785 with A/D on, 0°C to +125°C

PIC16F785 with A/D on, -40°C to +125°C

4 MHz ≤ FOSC ≤ 10 MHz

10 MHz ≤ FOSC ≤ 20 MHz

D002 VDR RAM Data Retention

Voltage(1) 1.5* — — V Device in Sleep mode

D003 VPOR VDD voltage above which

the interna l POR releases —1.8— VSee Section 15.2.1 “Power -On Rese t”

for details.

D003A VPARM VDD voltage below which

the internal POR rearms —1.0— VSee Section 15.2.1 “Po wer-On Reset”

for details.

D004 SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05* — — V/ms See Section 1 5.2.1 “Power-On Reset”

for details.

D005 VBOR Brown-out Reset —2.1— V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C un less o therwise st a ted . The se p ara me ters are fo r des ig n gu idance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: Maximum supply voltage is VSHUNT for PIC16 HV785 device (see Table 19-14).

PIC16F785/HV785

19.2 DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD

D010 Supply Current (IDD)—1123μA2.0FOSC = 32 kHz

LP Oscillator mode

—1838 μA3.0

—3575 μA5.0

D011 — 140 240 μA2.0F

OSC = 1 MHz

XT Oscillator mode

— 220 380 μA3.0

— 380 550 μA5.0

D012 — 260 360 μA2.0F

OSC = 4 MHz

XT Oscillator mode

— 420 650 μA3.0

— 0.8 1.1 mA 5.0

D013 — 130 220 μA2.0F

OSC = 1 MHz

EC Oscillator mode

— 215 360 μA3.0

— 360 520 μA5.0

D014 — 220 340 μA2.0F

OSC = 4 MHz

EC Oscillator mode

— 375 550 μA3.0

—0.65 1 mA 5.0

D015 — 8 20 μA2.0F

OSC = 31 kHz

INTRC mode

—1640 μA3.0

—3165 μA5.0

D016 — 340 450 μA2.0F

OSC = 4 MHz

INTOSC mode

— 500 700 μA3.0

— 800 1200 μA5.0

D017 — 230 400 μA2.0F

OSC = 4 MHz

EXTRC mode

— 400 680 μA3.0

— 0.63 1.1 mA 5.0

D018 — 2.6 3.25 mA 4.5 FOSC = 20 MHz

HS Oscillator mode

— 2.8 3.35 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD curren t from th i s l imit. Ma x

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.

PIC16F785/HV785

D020 Power-down Base Current

(IPD)(4) — 0.15 1.2 μA 2.0 WDT, BOR, Comparators, V REF, T1OSC,

Op Amps and VR disabled

— 0.20 1.5 μA3.0

— 0.35 1.8 μA5.0

D021 — 1.7 3.0 μA 2.0 WDT Current(3)

—2 4 μA3.0

—3 7 μA5.0

D022 — 42 60 μA 3.0 BOR Current(3)

— 85 122 μA5.0

D023 — 362 465 μA 2.0 Comparator Current(3)

CxSP = 1

— 418 532 μA3.0

— 500 603 μA5.0

D023A — 96 125 μA 2.0 Comparator Current(3)

CxSP = 0

— 112 142 μA3.0

— 132 162 μA5.0

D024 — 39 47 μA2.0CV

REF Current(3)

Low Range

—5972 μA3.0

— 98 124 μA5.0

D024A — 30 36 μA2.0CV

REF Current(3)

High Range (VRR = 0)

—4555 μA3.0

—7595 μA5.0

D025 — 2.5 7.0 μA 2.0 T1 OSC Current(3)

—3.214 μA3.0

—4.832 μA5.0

D026 — 0.30 1.6 nA 3.0 A/D Current(3)

(not converting)

— 0.36 1.9 nA 5.0

D027 — 9 13 μA 2.0 VR Current(3)

—1014 μA3.0

—1115μA5.0

D028 — 202 370 μA 3.0 Op Amp C urrent (3)

— 217 418 μA5.0

19.2 DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current fr om thi s l im i t. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.

PIC16F785/HV785

19.3 DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD

D010E Supply Current (IDD)—1123μA2.0FOSC = 32 kHz

LP Oscillator mode

—1838 μA3.0

—3575 μA5.0

D011E — 140 240 μA2.0F

OSC = 1 MHz

XT Oscillator mode

— 220 380 μA3.0

— 380 550 μA5.0

D012E — 260 360 μA2.0F

OSC = 4 MHz

XT Oscillator mode

— 420 650 μA3.0

— 0.8 1.1 mA 5.0

D013E — 130 220 μA2.0F

OSC = 1 MHz

EC Oscillator mode

— 215 360 μA3.0

— 360 520 μA5.0

D014E — 220 340 μA2.0F

OSC = 4 MHz

EC Oscillator mode

— 375 550 μA3.0

— 0.65 1.0 mA 5.0

D015E — 8 20 μA2.0F

OSC = 31 kHz

INTRC mode

—1640 μA3.0

—3165 μA5.0

D016E — 340 450 μA2.0F

OSC = 4 MHz

INTOSC mode

— 500 700 μA3.0

— 800 1200 μA5.0

D017E — 230 400 μA2.0F

OSC = 4 MHz

EXTRC mode

— 400 680 μA3.0

— 0.63 1.1 mA 5.0

D018E — 2.6 3.25 mA 4.5 FOSC = 20 MHz

HS Oscillator mode

— 2.8 3.35 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD curren t from th i s l imit. Ma x

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode , wi th a ll I/O p in s in hi gh -im pe dan c e state a n d ti ed to V DD. When A/D is off, it w ill no t

consume any current other than leakage current. The power-down current spec includes any such leakage from the

A/D module.

PIC16F785/HV785

D020E Power-down Base Current

(IPD)(4) —0.15 9 μA 2.0 WDT, BOR, Comparators, V REF, T1OSC,

Op Amps and VR disabled

—0.2011 μA3.0

—0.3515 μA5.0

D021E — 1.7 17.5 μA 2.0 WDT Current(3)

—219μA3.0

—322μA5.0

D022E — 42 65 μA 3.0 BOR Current(3)

— 85 127 μA5.0

D023E — 362 476 μA 2.0 Comparator Current(3)

CxSP = 1

— 418 554 μA3.0

— 500 625 μA5.0

D023E — 96 130 μA 2.0 Comparator Current(3)

CxSP = 0

— 112 147 μA3.0

— 132 168 μA5.0

D024E — 39 47 μA2.0CV

REF Current(3)

Low Range

—5972 μA3.0

— 98 124 μA5.0

D024E — 30 36 μA2.0CV

REF Current(3)

High Range

—4555 μA3.0

—7595 μA5.0

D025E — 2.5 21 μA 2.0 T1 OSC Current(3)

—3.228 μA3.0

—4.845 μA5.0

D026E — 0.30 12 uA 3.0 A/D Current(3)

(not converting)

—0.3616 uA 5.0

D027E — 9 20 μA 3.0 VR Current(3)

—1026 μA3.0

—1130μA5.0

D028E — 202 417 μA 3.0 Op Amp C urrent (3)

— 217 468 μA5.0

19.3 DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

Param

No. Device Char ac ter is tics Min Typ† Max Unit s Conditions

VDD

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current fr om thi s l im i t. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode , wi th a ll I/O p in s in hi gh -im pe d anc e state a n d ti ed to V DD. When A/D is off, it w ill no t

consume any current other than leakage current. The power-down current spec includes any such leakage from the

A/D module.

PIC16F785/HV785

19.4 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E

(Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C ≤ TA ≤ +85°C for indu st rial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VIL Input Low Voltage

I/O por ts

D030 with TTL buffer VSS —0.8V4.5V ≤ VDD ≤ 5.5V

D030A VSS — 0.15 VDD V Otherwise

D031 with Schmitt Trigger buffer VSS —0.2 VDD V Entire range

D032 MCLR, OSC1 (RC mode)(1) VSS —0.2 VDD V

D033 O SC1 (XT and LP modes) VSS —0.3V

D033A OSC1 (HS mode) VSS —0.3 VDD V

VIH Input High Voltage

I/O por ts —

D040

D040A with TTL buffer 2.0

(0.25 VDD + 0.8) —

—VDD

VDD V

V4.5V ≤ VDD ≤ 5.5V

Otherwise

D041 with Schmitt Trigger buffer 0.8 VDD —VDD V Entire range

D042 MCLR 0.8 VDD —VDD V

D043 O SC1 (XT and LP modes) 1.6 — VDD V

D043A OSC1 (HS mode) 0. 7 VDD —VDD V

D043B OSC1 (RC mode) 0.9 VDD —VDD V(Note 1)

D070 IPUR PORTA Weak Pull-up Current 50* 250 400* μAVDD = 5.0V, VPIN = VSS

IIL Input Leakage Current(2)

D060 I/O ports — ±0.1±1μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

D060A Analog inputs — ±0.1±1μAV

SS ≤ VPIN ≤ VDD

D060B VREF —±0.1±1μAVSS ≤ VPIN ≤ VDD

D061 MCLR(3) —±0.1±5μAVSS ≤ VPIN ≤ VDD

D063 OSC1 — ±0.1±5μAVSS ≤ VPIN ≤ VDD, XT, HS a n d

LP osc configuration

VOL Output Low Voltage

D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V

D083 O SC2/CLKO UT (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

VOH Output High Voltage

D090 I/O ports V DD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V

D092 O SC2/CLKO UT (RC mode) VDD – 0 .7 — — V IOH = -1.3 m A, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

D193* VOD Open-Drain High Voltage — — 8.5 V RB6 pin

* These parameters are characterized but not tested.

† D ata in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 14.4.1 “Using the Data EEPROM” on page 105.

PIC16F785/HV785

Capacitive Loading Specs on Output Pins

D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101 CIO All I/O pins — — 50* pF

Data EEPROM M em o ry

D120 EDByte Enduran ce 100K 1M — E/W -40°C ≤ TA ≤ +85°C

D120A EDByte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECO N1 to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write cycle time — 5 6 ms

D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

D124 TREF Number of Total Erase/Write

Cycles before Refresh(4) 1M 10M — E/W -40°C ≤ TA ≤ +85°C

Program Fla s h Memory

D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C

D130A EPCell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VPEW VDD for Erase/Write 4.5 — 5.5 V

D133 TPEW Erase/Write cycle time — 2 2.5 ms

D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

19.4 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended)

(Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C ≤ TA ≤ +85°C for indu str ial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† D ata in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 14.4.1 “Using the Data EEPROM” on page 105.

PIC16F785/HV785

19.5 Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

FIGURE 19-2: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppe rcase lett ers and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

Pin Pin

RL=464Ω

CL= 50 pF for all pins

15 pF for OSC2 output

Load Cond ition 1 Load Condition 2

Legend:

PIC16F785/HV785

FIGURE 19-3: EXTERNAL CLOCK TIMING

TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) — 32.768 — kHz LP mode (com pl em entary input

only)

DC — 4 MHz XT mode

DC — 2 0 MHz HS mode

DC — 2 0 MHz EC mode

Osci lla tor Freq uen cy (1) — 32.768 — kHz LP Os c mo de

—4 —MHzINTOSC mode

DC — 4 M H z RC Osc mode

0.1 — 4 MHz XT Osc mode

1— 20MHzHS Osc mode

1TOSC External CLKIN Period(1) —0.3052 — μs LP mode (complem entary input

only)

50 — ∞ns H S Osc mo de

50 — ∞ns EC Osc mode

250 — ∞ns XT Osc mode

Oscillator Perio d(1) —0.3052 — μsLP Osc mode

—250 — nsINTOSC mode

250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mode

50 — 1,000 ns HS Osc mode

CY Instructi on Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC

3 TosL,

TosH External CLKIN (OSC1) High

External CLKIN Low 2* — — μsLP oscillator, TOSC L/H duty cycle

20* — — n s HS os ci lla tor, TOSC L/H d uty cycle

100 * — — ns XT oscil lat or, TOSC L/H duty cycle

4TosR,

TosF External CLKIN Rise

External CLKIN Fall — — 50* ns LP oscillator

— — 25* ns XT oscillator

— — 15* ns HS oscillator

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Instruction cycle p eriod (TCY) equals four times the input oscillator time base period. All specified values

are based on charac teri za tion data for that part ic ular oscillator typ e unde r st andard operating con di tions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’

values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle

time limit is ‘DC’ (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

3344

PIC16F785/HV785

FIGURE 19-4: CLKOUT AND I/O TIMING

TABLE 19-2: CLKOUT AND I/O TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10 TOSH2CKLOSC1↑ to CLKOUT↓ —75200ns(Note 1)

11 TOSH2CKHOSC1↑ to CLKOUT↑ —75200ns(Note 1)

12 TCKR CLKOUT rise time — 35 100 ns (Note 1)

13 TCKF CLKOUT fall time — 35 100 ns (Note 1)

14 TCKL2IOVCLKOUT↓ to Port out valid — — 20 ns (Note 1)

15 TIOV2CKH Port input valid before CLKOUT↑ TOSC + 200 ns — — ns (Note 1)

16 TCKH2IOI Port input hold after CLKOUT↑ 0 — — ns (Note 1)

17 TOSH2IOVOSC1↑ (Q1 cycle) to Port out valid — 50 150 * ns

——300ns

18 TOSH2IOIOSC1↑ (Q2 cycle) to Port input

invalid (I/O in hold time) 100 — — ns

19 TIOV2OSH Port input valid to OSC1↑

(I/O in setup time) 0——ns

20 TIOR Port output rise time — 10 40 ns

21 TIOF Port output fall time — 10 40 ns

22 TINP INT pin hi gh or low time 25 — — ns

23 TRBP PORTA interrupt-on-change high or

low time TCY ——ns

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

OSC1

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

PIC16F785/HV785

TABLE 19-3: PRECISION INTERNAL OSCILLATOR PARAMETERS

FIGURE 19-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

Param

No. Sym Characteristic Freq.

Tolerance Min Typ† Max Units Conditions

F10 FOSC Intern al Cali brat ed

INTOSC Frequency(1) ±1% 7.92 8.00 8.08 MHz VDD = 3.5V, 25°C

±2% 7.84 8.00 8.16 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85 °C

±5% 7.60 8.00 8.40 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

F14 TIOSCST Oscillator wake-up from

Sleep start-up time* — — 12 24 μsVDD = 2.0V, -40°C to +85°C

——714μsV

DD = 3.0V, -40°C to +85°C

——611μsVDD = 5.0V, -40°C to +85°C

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O Pins

PIC16F785/HV785

FIGURE 19-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS

TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2

11 —

18 —

24 μs

μsVDD = 5.0V, -40°C to +85° C

Extended temperature

31 TWDT Watchdog T im er Time- out Perio d

(No Prescaler) 10

10 17

17 25

30 ms

ms VDD = 5.0V, -40°C to +85°C

Extended temperature

32 TOST Oscill ati on St a rt-up Timer Perio d — 1024 TOSC ——TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28* 64 132* ms VDD = 5.0V, -40°C to +85° C

34 TIOZ I/O High-impedance f rom MCLR

Low or Watchdog Timer Reset ——2.0μs

35 VBOR Brown -out R ese t Vo lt a ge 2.025 — 2.175 V

36 TBOR Brown-out Reset Pulse Width 100* — — μsVDD ≤ VBOR (D005)

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

VBOR

Reset (due to BOR)

VDD

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

64 ms time-out(1)

Note 1: 64 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.

PIC16F785/HV785

FIGURE 19-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* TT0P T0CKI Period Greater of:

20 or TCY + 40

— — ns N = prescale

value (2, 4, ...,

256)

45* TT1H T1CKI High

Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Pr escaler 15 — — ns

Asynchronous 30 — — ns

46* TT1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Pr escaler 15 — — ns

Asynchronous 30 — — ns

47* TT1P T1CKI Input

Period Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale

value (1, 2, 4,

Asynchronous 60 — — ns

48 FT1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz

49 TCKEZTMR1 Delay from external clock edge to timer increment 2 TOSC*—7 TOSC*—

* These parameters are characterized but not tested.

† D ata in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

T0CKI

T1CKI

40 41

45 46

47 49

TMR0 o r

TMR1

PIC16F785/HV785

FIGURE 19-8: CAPTURE/ COM PARE/PWM TIMINGS (CCP)

TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

50* TCCL CCP1 input low time No Prescaler 0.5TCY +

20 ——ns

With Prescaler 20 — — ns

51* TCCH CCP1 input high time No Prescaler 0.5TCY +

20 ——ns

With Prescaler 20 — — ns

52* TCCP CCP1 input period 3TCY + 40

N— — ns N = prescale value

(1,4 or 16)

53* TCCR CCP1 output rise time — 25 50 ns

54* TCCF CCP1 output fall time — 25 45 ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note: Refer to Figure 19-2 for load conditions.

(Capture mode)

50 51

53 54

CCP1

(Compare or PWM mode)

CCP1

PIC16F785/HV785

TABLE 19-7: COMPARATOR SPECIFICATIONS

TABLE 19-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

TABLE 19-9: VOLTAGE REFERENCE (VR) SPECIFICATIONS

TABLE 19-10: VOLTAGE REFERENCE OUTPUT (VREF) BUFFER SPECIFICATIONS

Comparator Specifications Standard Operating Conditions (unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min Typ Max Units Comments

C01 VOS Input Offset Voltage — ±5±10 mV

C02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V

C03 ILC Input Leakage Current — — 200* nA

C04 CMRR Common Mode Rejection

Ratio +70* — — dB

C05 TRT Response Time(1) —

——

—20*

40* ns

ns Internal

Output to pin

* These parameters are characterized but not tested.

Note 1: Response ti me meas ured with on e comp arator inp ut at (VDD – 1.5)/2 , while the oth er input tran sitions from

VSS to VDD – 1.5V.

Comparator Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min Typ Max Units Comments

CV01 CVRES Resolution —

—VDD/24*

VDD/32 —

—LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

CV02 Absolute Accuracy —

——

—±1/4*

±1/2* LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

CV03 Unit Resistor Value (R) — 2K* — Ω

CV04 Sett ling Time(1) —— 10*μs

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.

VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Operating Voltage 3.0V ≤ VDD ≤ 5.5V

Param

No. Symbol Characteristics Min Typ Max Units Comments

VR01 VROUT VR voltage output 1.188

1.176

1.164

1.200

1.212

1.224

1.236

TA = 25°C

0°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

Volta ge Re feren ce Output Buffer

Specifications

Standard Operating Conditions (unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +125°C

Operating voltag e 3.0V ≤ VDD ≤ 5.5V

Param

No. Symbol Characteristics Min Typ Max Units Comments

VB01* CL External capacitor load — — 200 pF

* These parameters are characterized but not tested.

PIC16F785/HV785

TABLE 19-11: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS

TABLE 19-12: OPERATIONAL AMPLIFIER (OPA) MODULE AC SPECIFICATIONS

TABLE 19-13: TWO-PHASE PWM DEAD TIME DELAY SPECIFICATIONS

OPA DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50pF,

RL = 100k

Ope rati ng temperature -40°C ≤ TA ≤ +125°C

Param

No. Sym Characteristics Min Typ Max Units Comments

OPA01 VOS Input Offset Voltage —±5—mV

OPA02*

OPA03* IB

IOS

Input current and impedance

Input bi as current

Input offset bias current —

—±2*

±1* —

—nA

OPA04*

OPA05* VCM

CMR

Common Mode

Common mode input range

Common mode rejection VSS

65 —

70 VDD – 1.4

—V

dB VDD = 5.0V

VCM = VDD/2, Freq. = DC

OPA06A*

OPA06B* AOL

AOL

Open Loop Gain

DC Open loop gain

DC Open loop gain —

—90

60 —

—dB

dB No load

Standard load

OPA07*

OPA08*

Vout

Isc

Output

Out put voltage swing

Output short circuit current

VSS+100

—

VDD – 100

To VDD/2 (20 kΩ

connected to VDD,

20 k Ω + 20 pF to Vss)

OPA10 PSR Power Supply

Power supply rejection 80 — — dB

* These parameters are characterized but not tested.

OPA AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50 pF,

RL = 100k

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min Typ Max Units Comments

OPA11* GBWP Gain bandwidth product — 3 — MHz

OPA12* TON Turn on time — 10 15 μs

OPA13* ΘMPhase margin — 60 — deg

OPA14* SR Slew rate 2 — — V/μs

* These parameters are characterized but not tested.

Dead Time Delay Characteristics Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min Typ Max Units Comments

PW01* TDLY De ad Time Del ay 205 231 275 ns FOSC = 4 MHz,

maximum delay,

Complementary mode

* These parameters are characterized but not tested.

PIC16F785/HV785

TABLE 19-14: SHUNT REGULATOR SPECIFICATIONS (PIC16HV785 only)

TABLE 19-15: PIC16F785/HV785 A/D CONVERTER CHARACTERISTICS:

SHUNT REGULATOR CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No. Symbol Characteristics Min Typ Max Units Comments

SR01 VSHUNT Shunt Voltage 4.75 5 5.25 V

SR02 ISHUNT Shunt Current 4 — 50 mA

SR03* TSETTLE Settling Time — — 150 ns To 1% of final value

SR04* CLOAD Load Capacitance 0.01 — 10 μF Bypass capacitor on VDD

SR05* ΔISNT Regulator operating current — — 180 μA Includes band gap

reference current

* These parameters are characterized but not tested.

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 10 bits bit

A03 EIL Integral Error — — ±1LSbVREF = 5. 0V (extern al)

A04 EDL Differential Error — — ±1 LSb No missing codes to 10 bits

VREF = 5 .0V (external)

A06 EOFF Offset Error — — ±1LSbVREF = 5.0V (external)

A07 EGN Gain Error — — ±1LSbVREF = 5.0V (external)

A20

A20A VREF Reference Voltage 2.2(4)

1.0 ——

VDD + 0.3 VAbsolute minimum to ensure 10-bit

accuracy

A25 VAIN Analog Input

Voltage VSS —VREF(5) V

A30 ZAIN Recommended

Impedance of

Analog Voltage

Source

—— 10kΩ

A50 IREF VREF Input

Current*(3) —

—

150

μA

During VAIN acquisition.

Based on differential of VHOLD to

VAIN.

Transie nt during A /D conversion

cycle.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Total Absolute Error includes Integral, Differential, Offset and Gain Errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: VREF current is from external VREF or VDD pin, whichever is selected as reference input.

4: Only limited when VDD is at or below 2.5V. If VDD is above 2.5V, VREF is allow ed to go as low as 1.0V.

5: Analog input voltages are allowed up to VDD, however the conversion accuracy is limited to VSS to VREF.

PIC16F785/HV785

FIGURE 19-9: PIC16F785/HV785 A/D CONVERSION TIMING (NORMAL MODE)

TABLE 19-16: PIC16F785/HV785 A/D CONVE RSI ON REQUIREM ENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — μsTOSC-based, VREF ≥ 3.0V

3.0* — — μsT

OSC-based, VREF full range

130 TAD A/D Internal RC

Oscillator Period 3.0* 6.0 9. 0* μsADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0* 4.0 6.0* μsAt V

DD = 5.0V

131 TCNV C onvers ion Time (not

including

Acquisition Time)(1)

—11—TAD Set GO bit to new data in A/D result

132 TACQ Acquisition Time (Note 2)

11.5

—

μs

μs The minimum ti me is the ampl ifi er settl ing

time. This may be used i f the “new” inpu t

volta ge has not changed by more than 1

LSb (i.e., 4.1 mV @ 4.096V) from the last

sampled volt age (as stored o n CHOLD).

134 TGO Q4 to A/D Clock Start — TOSC/2 — — If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock starts. This allows the SLEEP

instruction to be executed.

* These parameters are characterized but not tested.

† D ata in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

no t te sted.

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Section 12.2 “A/D Acquisition Requirements” for minimum conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DAT A

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

987 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134 (TOSC/2)(1)

1 TCY

PIC16F785/HV785

FIGURE 19-10 : PI C16F78 5/HV 78 5 A/D CONVERSION TIMING (SLEEP MODE)

TABLE 19-17: PIC16F785/HV785 A/D CONVERSI ON REQUI REM ENTS (SLEE P MO DE)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Internal RC

Osci lla tor Perio d 3.0* 6.0 9.0* μsADCS<1:0> = 11 (RC mode)

At VDD = 2. 5V

2.0* 4.0 6.0* μsAt VDD = 5.0V

131 TCNV Conversion Time

(not including

Acquisition T ime)(1)

—11—T

132 TACQ Acquis iti on Tim e (Note 2)

11.5

—

μs

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

change d by more than 1 LSb (i.e .,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134 TGO Q4 to A/D Clock

Start —TOSC/2 + TCY — — If the A/D clo ck s ou r ce i s selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to b e

executed.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: ADRES register may be read on the following TCY cycle.

2: See Table 12-1 for minimum conditions.

131

130

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMP LING STOPPED

DONE

NEW_DATA

9 7 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This

allows the SLEEP instruction to be executed.

134

132

1 TCY

(TOSC/2 + TCY)(1)

1 TCY

PIC16F785/HV785

NOTES:

PIC16F785/HV785

20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents

(mean + 3σ) or (mean - 3σ) respectively , where σ is a standard deviation, over each temperature range.

FIGURE 20-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only . The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

3.0V

4.0V

5.0V

5.5V

2.0V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-case Te mp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

FIGURE 20-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

3.0V

4.0V

5.0V

2.0V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

IDD (mA)

5.5V

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-c ase Te mp) + 3σ

(-40°C to 125°C)

HS Mode

3.0V

3.5V

4.0V

4.5V

5.0V

5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4 MHz 10 MHz 16 MHz 20 MHz

FOSC

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

FIGURE 20-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE)

HS Mode

3.5V

4.0V

4.5V

5.0V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

4 MHz 10 MHz 16 MHz 20 MHz

FOSC

IDD (mA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -case Temp) + 3σ

(-40°C to 125°C)

3.0V

5.5V

100

200

300

400

500

600

700

800

900

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

PIC16F785/HV785

FIGURE 20-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)

FIGURE 20-7: IDD vs. VDD (LP MODE)

200

400

600

800

1,000

1,200

1,400

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-case Te mp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

Typical Typical

2.0 11

2.5 14.5

3.0 18

3.5 22.25

4.0 26.5

4.5 30.75

5.0 35

5.5 39.25

Max Maximum

2.0 23

2.5 30.5

30 38

Typical

Maximum

2 2.5 3 3.5 4 4.5 5 5.5

VDD (V)

IDD (uA)

Typical: Statistical Mean @25×C

Maximum: Mean (Wor st Case

T)+3

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-8: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)

FIGURE 20-9: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE)

100

200

300

400

500

600

700

800

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (μA)

1 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -case Temp) + 3σ

(-40°C to 125°C)

4 MHz

200

400

600

800

1,000

1,200

1,400

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

PIC16F785/HV785

FIGURE 20-10 : IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)

FIGURE 20-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)

LFINTOSC Mode, 31KHZ

Typical

Maximum

VDD (V)

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-c ase Tem p) + 3σ

(-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

2.0V

3.0V

4.0V

5.0V

5.5V

200

400

600

800

1,000

1,200

1,400

1,600

125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz

FOSC

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-12 : MAX IMU M IDD vs. FOSC OVER VDD (HFINTOSC MODE)

FIGURE 20-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

2.0V

3.0V

4.0V

5.0V

5.5V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz

FOSC

IDD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t - case Temp) + 3σ

(-40°C to 125°C)

Typ 25×C Max 85×C Max 125×C

2 0.150 1.20

9.00

2.5 0.175 1.285

10.000

3 0.200 1.50

11.00

3.5 0.238 1.483

11.800

4 0.275 1.585

12.600

4.5 0.313 1.688

13.400

5 0.350 1.79

14.20

5.5 0.388 1.893

(Sleep Mode all Periphreals Disabled)

0.0

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

2.02.53.03.54.04.55.05.5

(V)

(uA)

Typical: Statistical Mean @25

°C

PIC16F785/HV785

FIGURE 20-14 : MAX IMU M IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

FIGURE 20-15 : CO MPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)

Maximum

(Sleep Mode all Periphreals Disabled)

Max 125°C

Max 85°C

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

()

100

120

140

160

180

200

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Max

Typical

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-16 : CO MPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) CXSP=1

FIGURE 20-17 : BO R IPD vs. VDD OVER TEMP ER ATURE

Typical Max

2 362 4 6 0

Typical

Max

100

200

300

400

500

600

700

800

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25×C

Maximum: Mean (Wors t Case

Temp)+3

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

100

120

140

160

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Maximum

Typical

PIC16F785/HV785

FIGURE 20-18: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE

FIGURE 20-19: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Typical Max 85×C Max 125×C

21.700 3.000 4.5

2.51.850 3.500 4.75

32.000 4.000 5

3.52.250 4.750 6.25

42.500 5.500 7.5

4.52.750 6.250 8.75

53.000 7.000 10

5.53.250 7.750

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

0.0

2.0

4.0

6.0

8.0

10.0

12.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

PIC16F785/HV785

FIGURE 20-20 : CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)

FIGURE 20-21 : CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)

High Range

Typical

Max. 85°C

100

120

140

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Me an (Wors t-case Te mp) + 3σ

(-40°C to 125°C)

Typical

Max. 85°C

100

120

140

160

180

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (μA)

Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-22 : T 1OSC I PD vs. VDD OVER TEMPERATURE (32 kHz)

FIGURE 20-23 : VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

Typ 25×C Max 85×C Max 125×C

2 2.500 7.00 21.00

2.5 2.850 10.50 24.50

3 3.200 14.00 28.00

3.5 3.600 18.50 32.25

4 4.000 23.00 36.50

4.5 4.400 27.50 40.75

5 4.800 32.00 45.00

5.5 5.200 36.50

Max 85°C

Max 125°C

0.0

10.0

20.0

30.0

40.0

50.0

60.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (uA)

Typ 25°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

6.5 0.2518 0.3336 0.401 0.1503

7 0.2716 0.3609 0.4354 0.1622

7.5 0.2911 0.3884 0.4695 0.1743

8 0.3116 0.4166 0.5049 0.1862

8.5 0.3318 0.4453 0.5413 0.1984

9 0 3524 0 4744 0 5782 0 2107

(VDD = 3V, -40×C TO 125×C)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (m A)

VOL (V)

Max. 85°C

Max. 125°C

Typic a l 25°C

Min. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-24 : VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

FIGURE 20-25 : VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

IOL (m A)

VOL (V)

Typical: Statistical Mean @25×C

Maximum: Meas + 3 (-40×C to 125×C)

Typical: Statistical Mean @25°C

Maximum: Mean (Worst -case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

Typ. 25°C

Min. -40°C

Max. 125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (W ors t-case Tem p ) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-26 : VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

FIGURE 20-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

3.0

3.5

4.0

4.5

5.0

5.5

-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)

VOH (V)

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-case Tem p) + 3σ

(-40°C to 125°C)

(TTL Input, -40×C TO 125×C)

0.5

0.7

0.9

1.1

1.3

1.5

1.7

2.02.5 3.03.5 4.04.5 5.05.5

VDD (V)

VIN (V)

Typ. 25°C

Max. -40°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-c ase Tem p) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TE MP ER ATURE

FIGURE 20-29: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)

(ST Input, -40×C TO 125×C)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

VIH Max. 125°C

VIH Min. -40°C

VIL Min. 125°C

VIL Max. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Wors t-case Tem p) + 3σ

(-40°C to 125°C)

LFINTOSC 31Khz

5,000

10,000

15,000

20,000

25,000

30,000

35,000

40,000

45,000

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Frequency (Hz)

Max. -40°C

Typ. 25°C

Min. 85°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-30: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

FIGURE 20-31: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

25°C

85°C

125°C

-40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

85°C

25°C

-40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-32: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

FIGURE 20-33: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

-40C to +85C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

-40°C

85°C

25°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

-40C to +85C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Time (μs)

-40°C

25°C

85°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

PIC16F785/HV785

FIGURE 20-34: TYPICAL HFINTOSC FREQUE NCY CHANGE vs. VDD (25°C)

FIGURE 20-35: TYPICAL HFINTOSC FREQUE NCY CHANGE OVER DEVICE VDD (85°C)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change fr om Calibration (%)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change from Calibration (%)

PIC16F785/HV785

FIGURE 20-36: TYPICAL HFINTOSC FREQUE NCY CHANGE vs. VDD (125°C)

FIGURE 20-37: TYPICAL HFINTOSC FREQUE NCY CHANGE vs. VDD (-40°C)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change fr om Calibration (%)

-5

-4

-3

-2

-1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Change from Calibration (%)

PIC16F785/HV785

FIGURE 20-38: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V)

FIGURE 20-39: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V)

Typical VP6 Reference Voltage vs. Temperature (VDD=3V)

0.52

0.54

0.56

0.58

0.6

0.62

0.64

0.66

-40°C 25°C 85°C 125°C

Temperature (°C)

VP6 (V)

Min.

Max.

Typical

Typical VP6 Reference Voltage vs. Temperature (VDD=5V)

0.52

0.54

0.56

0.58

0.6

0.62

0.64

0.66

-40 °C 25 °C 85 °C 125 °C

Temperature (°C)

VP6 (V)

Max.

Typical

Min.

PIC16F785/HV785

FIGURE 20-40: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C)

FIGURE 20-41: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

100

Parts = 150

Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

PIC16F785/HV785

FIGURE 20-42: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C)

FIGURE 20-43: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

PIC16F785/HV785

FIGURE 20-44: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C)

FIGURE 20-45: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C)

Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

PIC16F785/HV785

FIGURE 20-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C)

FIGURE 20-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C)

Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

Voltage (V)

Number of Parts

Parts = 150

1.170

1.176

1.182

1.188

1.194

1.200

1.206

1.212

1.218

1.224

1.230

1.236

Voltage (V)

Number of Parts

Parts = 150

PIC16F785/HV785

21.0 PACKAGING INFORMATION

21.1 Package Marking Information

The following sections give the technical details of the packages.

20-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F785-I/P

0810017

20-Lead SOIC (.300”)

XXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F785

-E/SO 0810017

20-Lead SSOP

XXXXXXXXXXX

YYWWNNN

Example

PIC16F785

-I/SS

0810017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microc hip p art num ber cann ot be marked on one lin e, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*S t anda rd PIC® device markin g consists of Micro chip p art num ber, year code, week code , and tracea bility

code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

20-Lead QFN Example

XXXXXXX

YWWNNN

16F785

-I/ML

0810017

PIC16F785/HV785







  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 

&  1,

&&  < < 

##44!!   - 

1!&&   < <

"#&"#=#& . - - -

##4=#& .   >

: 9&  > - ?

&& 9  - 

9#4!!  >  

69#=#& )  ? 

9*9#=#& )  > 

: *+ 1 < < -

NOTE 1

123

  * ,1

PIC16F785/HV785

 ! ! "#$%& !'



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  1,

: 8&  < < ?

##44!!   < <

&#%%+   < -

: =#& . -1,

##4=#& . 1,

: 9&  >1,

,'%@&A   < 

3&9& 9  < 

3&& 9 .3

3& IB < >B

9#4!!   < --

9#=#& ) - < 

#%& DB < B

#%&1&&' EB < B

123

NOTE 1

  * ,1

PIC16F785/HV785

 ()* ! &% !



  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  ?1,

: 8&  < < 

##44!!  ?  >

&#%%   < <

: =#& .  > >

##4=#& .  - ?

: 9&  ?  

3&9& 9   

3&& 9 .3

9#4!!   < 

3& B B >B

9#=#& )  < ->

NOTE 1

  * ,1

PIC16F785/HV785

+,#*-./0/0%1+,





  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

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PIC16F785/HV785

&&255***''54

PIC16F785/HV785

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Updates throughout document.

Revision C

Revised part number to include “HV785”; Added PWM

Setup Example; Added Voltage Regulator secton.

Revision D

Revised VROUT min./max. limits in Table 19-9.

Revision E

Adding Characterization Data and small updates and

reformatting.

APPENDIX B: MIGRATING FROM

OTHER PIC®

DEVICES

This d iscusses some of the issues i n migrating from the

PIC16F684 PIC® device to the PIC16F785/HV785.

B.1 PIC16F684 to PIC16F78 5/HV785

TABLE B-1: FEATURE COMPARISON

Feature PIC16F684 PIC16F785

Max O perating

Speed 20 MHz 20 MHz

Max Program

Memory (Words) 2048 2048

SRAM (bytes) 128 128

A/D Resolution 10-bit 10-bit

Data EEPROM

(bytes) 256 256

Timers (8/16-bit) 2/1 2/1

Oscillator modes 8 8

Brown-out Reset Y Y

Internal Pull-ups RA0/1/2/4/5

MCLR RA0/1/2/3/4/5

MCLR

Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5

Comparator 2

CCP ECCP Y

Op Amps N 2

PWM N Two-Phase

Ultra Low-Power

Wake-up YN

Extended WDT Y Y

Software Control

Option of WDT/BOR YY

INT OSC Freq ue nci es 32 kHz -

8MHz 32 kHz -

8MHz

Clock Switc hin g Y Y

PIC16F785/HV785

NOTES:

PIC16F785/HV785

INDEX

A/D......................................................................................79

Acquisition Requirements .......................... ........... .... ..86

Analog Port Pins.........................................................80

Associ a te d Re gisters.......... ..................... ...................89

Block Diag ram............. ..................... ..................... ......79

Calculating Acquisition Time.......................................86

Channel Selection............................................... .... ....80

Configuration and Operation.......................................80

Configuring..................................................................85

Configuring Interrupt...................................................85

Conversi o n Clo ck............ ............... ..................... ........80

Effects of Reset...........................................................89

Internal Sampling Switch (Rss) Impedance... .............86

Operation During Sleep ..............................................88

Outpu t Fo r mat....... ........................... ..................... ......81

Reference Voltage (VREF)...........................................80

Source Impedance.................................................... ..86

Special Event Trigger..................................................89

Specifications..................................... .. .... .159, 160, 161

Starting a Conversion .................................................81

Using the ECCP Trigger .............................................89

Absolute Maximum Ratings..............................................141

AC Characteristics

Load Conditions.................... .. ....... .. .. .. .... .. .. ....... .. .. ..150

ADCON0 Register ...............................................................83

ADCON1 Register ...............................................................84

Analog-to-Digital Converter. See A/D

ANSEL Register....................................................93, 94, 101

ANSEL0 Register................................................................82

ANSEL1 Register................................................................82

Assembler

MPASM Assembler...................................................138

Block Diagrams

(CCP) Capture Mode Operation .................................58

A/D..............................................................................79

Analog Input Model.....................................................87

CCP PWM...................................................................60

Clock Source...............................................................23

Comparator 1............ .............. ..................... ...............64

Comparator 2............ .............. ..................... ...............66

Compare.....................................................................58

CVref...........................................................................71

Fail-Safe Clock Monitor (FSCM).................................31

In-Circuit Serial Programming Connections..............125

Inter rupt Logic............................ ..................... ..........118

On-Chip Rese t Circuit........... ......... .............. .............109

OPA Module.................. .. .. .... .. ..... .... .. .. .. .... .. ..... .... .. .. ..75

PIC16F785/HV785........................................................5

RA0 Pin .......................................................................38

RA1 Pin .......................................................................38

RA2 Pin .......................................................................39

RA3 Pin .......................................................................39

RA4 Pin .......................................................................40

RA5 Pin .......................................................................40

RB4 and RB5 Pins......................................................43

RB6 Pin .......................................................................43

RB7 Pin .......................................................................43

RC0 and RC1 Pins............................... .... .. .. ....... .. .... ..43

RC0, RC6 and RC7 Pins ............................................46

RC1 Pin.......................................................................46

RC2 and RC3 Pins........................ .. .. ....... .. .. .. .. .... .. .. .. 47

RC4 Pin...................................................................... 47

RC5 Pin...................................................................... 48

Resonator Operation.................................................. 25

Timer1 ........................................................................ 51

Timer2 ........................................................................ 56

TMR0/WDT Prescaler ................................................ 49

Two Phase PWM

Complementary Output Mode .......................... 101

Simpl ifie d Dia g ram .................... ......................... 92

Singl e Ph as e Exampl e ........... .. ..... .. ...... .. .. ...... .. . 98

VR Reference............................................................. 74

Watchdog Timer (WDT)............................................ 121

Brown-out Reset (BOR).................................................... 110

Associated Registers................................................ 112

Calibration ................................................................ 111

Specifications ........................................................... 154

Timing and Characteristics................................. .. .... 154

C Compilers

MPLAB C18.............................................................. 138

MPLAB C30.............................................................. 138

Capture Module. See Capture/Compare /PWM (CCP)

Capture/Compare/PWM ( CCP)...................... ........ ............ 57

Associated Registers.................................................. 62

Associated Registers w/ Capture/Compare/Timer1 ... 59

Capture Mode............................................................. 58

CCP1 Pin Configuration ............................................. 58

Compare Mode........................................................... 58

CCP1 Pin Configuration ..................................... 59

Software Interrupt Mode..................................... 59

Special Event Trigger and A/D Conversions...... 59

Timer1 Mode Selection....................................... 59

Prescaler .................................................................... 58

PWM Mode............. ..................... ........................... .... 60

Duty Cycle.......................................................... 61

Effects of Reset.................................................. 62

Example PWM Frequencies and Resolutions.... 61

Operation in Power Managed Modes................. 62

Operation with Fail-Safe Clock Monitor.............. 62

Setup for Operation............................................ 62

Setu p fo r PW M Ope ra t i o n ............ . ...... ...... .. ...... . 62

Specifications ........................................................... 156

Time r R e so u r ces ......... ..... ...... .......... ..... ...... ...... ...... ... 57

CCP. See Capture/Compare/PWM (CCP)

CCP1CON Regis te r.............. ............... ............... ................ 57

CCPR1H Register............................................................... 57

CCPR1L Register............................................................... 57

Clock Sources..................................................................... 23

CM1CON0.......................................................................... 65

CM2CON1.......................................................................... 68

Code Examples

Assign i n g Prescale r to Timer0.................................... 50

Assigning Prescaler to WDT....................................... 50

Changing Between Capture Prescalers ..................... 58

Data EEPROM Read................................................ 105

Data EEPROM Write................................................ 105

EEPROM Write Verify .............................................. 105

Indir ect Add ress i n g.. ...... ..... ...... ...... ...... ..... ...... ...... ..... 22

Initializing A/D............................................................. 85

Init i a li zi n g PORT A ....... ..... ...... ...... ...... ..... ...... ...... ...... . 35

Init i a li zi n g PORT B ....... ..... ...... ...... ...... ..... ...... ...... ...... . 42

Init i a li zi n g PORT C ... ...... ..... ...... ...... ......... ...... ...... ...... . 45

PIC16F785/HV785

Inter rupt Context Saving ... ..................... ...................120

Code Protection ................................................................124

Comparator Module ........... ....... .. .... .. .... .. ....... .... .. .... .. ....... ..63

Associ a te d Re g i sters................ ..................... .............74

C1 Output State Versus Input Conditions...................63

C2 Output State Versus Input Conditions...................66

Comparator Interrupts....... .............. ..................... .......69

Effects of Reset...........................................................69

Comparator Voltage Reference (CVREF)

Specifications............................................................157

Comparators

C2OUT as T1 Gate............................ ..................... ....52

Specifications............................................................157

Compare Module. See Capture/Compare/ PW M (CCP)

CONFIG Regi ster.................... .............. ..................... .......108

Configuration Bits..............................................................107

Customer Change Notification Service .............................201

Custome r Notification Ser vice.................... .............. .........201

Customer Support............................. ...... ........... ...... .... .....201

Data EEPRO M Memor y

Associ a te d Re g i sters................ ..................... ...........106

Code Protection ................................................103, 106

Data Memory.........................................................................9

DC and AC Characteristics

Graphs and Tables ...................................................163

DC Characteristics

Extended and Industrial............................................148

Industrial and Extended............................................143

Development Support .......................................................137

Device Overview...................................................................5

EEADR Register ...............................................................103

EECON1 Regist e r....................... ..................... .................104

EECON2 Regist e r....................... ..................... .................104

EEDAT Regi ster.................... ..................... .............. .........103

EEPROM Data Memory

Avoiding Spurious Write............................................105

Reading.....................................................................105

Write Verify ...............................................................105

Writing.......................................................................105

Effects of Reset

A/D module .............................................. .... .... .... .......89

Comparator module ................................. .. .... .. .. .........69

OPA module............. .. ....... .. .. .. .... .. .. ....... .. .. .... .. .. .. .......77

PWM mode..................... ..................... .......................62

Electrical Specifications ....................................................141

Errata ....................................................................................4

Fail-Safe Clock Monitor.......................................................31

Fail-Safe Condition Clearing.......................................32

Reset and Wake-up from Sleep..................................32

Firmware Instructions........................................................127

Fuses. See Configuration Bits

General Purpose Register File..............................................9

ID Locations......................................................................124

In-Circuit Debugger...........................................................125

In-Circuit Serial Programming (ICSP)...............................124

Indirect Addressing, INDF and FSR Registers....................22

Instruction Format............................................................. 127

Instr uctio n Se t....... ...... ..... ...... .. ...... ..... ...... ...... ...... ..... .. ..... 127

ADDLW..................................................................... 129

ADDWF..................................................................... 129

ANDLW..................................................................... 129

ANDWF..................................................................... 129

MOVF ....................................................................... 132

RRF .......................................................................... 133

SLEEP...................................................................... 133

SUBLW..................................................................... 134

SUBWF..................................................................... 134

SWAPF..................................................................... 134

TRIS ......................................................................... 134

XORLW .................................................................... 134

XORWF .................................................................... 135

BCF .......................................................................... 129

BSF........................................................................... 129

BTFSC...................................................................... 130

BTFSS...................................................................... 130

CALL......................................................................... 130

CLRF ........................................................................ 130

CLRW....................................................................... 130

CLRWDT .................................................................. 130

COMF....................................................................... 131

DECF........................................................................ 131

DECFSZ ................................................................... 131

GOTO ....................................................................... 131

INCF ......................................................................... 131

INCFSZ..................................................................... 131

IORLW...................................................................... 132

IORWF...................................................................... 132

MOVLW.................................................................... 132

MOVWF.................................................................... 132

NOP.......................................................................... 132

RETFIE..................................................................... 133

RETLW..................................................................... 133

RETURN................................................................... 133

RLF........................................................................... 133

Summary Ta b l e...... .............. ............................ ........ 128

INTCON Register................................................................ 17

Internal Oscillator Block

INTOSC

Specifications ................................................... 153

Internal Sampling Switch (Rss) Impedance........................ 86

Internet Address .. .................................. ........................... 201

Interrupts........................................................................... 117

(CCP) Compa re........ ..................... ..................... ........ 58

A/D.............................................................................. 85

Associated Registers................................................ 119

Comparator................................................................. 69

Context Saving.........................................................120

Data EEPRO M Mem ory Write..... ..................... ........104

Interrupt-on-Change ................................................... 37

Oscillato r Fail (OSF)..... ....................... ................. ...... 31

PORTA Interru pt-on-change..................................... 118

RA2/INT.................................................................... 118

TMR0........................................................................ 118

TMR1.......................................................................... 52

TMR2 to PR 2 M atch...... ...... .. ..... ...... ...... ...... . ...... . 55, 5 6

INTOSC Specifications..................................................... 153

IOCA (Interrupt-on-Change) ............................................... 37

IOCA Register........ ..................... ..................... ............... .... 37

Load Conditions................................................................ 150

PIC16F785/HV785

MCLR................................................................................110

Internal......................................................................110

..............................................................................................9

Data ..............................................................................9

Data EEPROM Mem o ry............. .............. .................103

Program........................................................................9

..................... .. .. .. .... .. .. .......201, 193, 138, 139, 137, 139, 138

OPA2CON Register........ .............. ..................... ............... ..76

OPCODE Fiel d Descr ip tions........... ............... ............... ....127

Operational Amplifier (OPA) Module

AC Specifications..............................................158, 159

Associ a te d Re g i sters................... ..................... ..........77

DC Specifications......................................................158

OPTION_R EG Re g i ster........ ............... ..................... ..........17

OSCCON Register..............................................................33

Oscillator

Associ a te d Re g i sters................... ..................... ..........34

Oscillator Specifications....................................................151

Oscillator Start-up Timer (OST)

Specifications............................................................154

Oscillator Switching

Fail-Safe Clock Monitor...............................................31

Two-Speed Clock Start-up..........................................30

OSCTUNE

Oscillator Tuning Register (Address 90h). ..................28

Packaging .........................................................................187

PCL and PCLATH...............................................................21

Stack...........................................................................21

PCON

Power Control Register (Address

8Eh) ....................................................................20

PCON Register.................................................................112

PICSTART Plus Development Programmer.....................140

PIE1 Register......................................................................18

Pin Diagram ......................................................................2, 3

Pinout Descriptions

PIC16F684....................................................................6

PIR1 Regi ster............. ..................... ..................... ...............19

PORTA................................................................................35

Additional Pin Functions .............................................36

Interrupt-on-change ............................................37

Weak Pull-up ......................................................36

Associ a te d Re g i sters................... ..................... ..........41

Pin Descriptions and Diagrams. ..................................38

RA0.............................................................................38

RA1.............................................................................38

RA2.............................................................................39

RA3.............................................................................39

RA4.............................................................................40

RA5.............................................................................40

Specifications............................................................152

PORTB................................................................................42

Associ a te d Re g i sters................... ..................... ..........44

Pin Descriptions and Diagrams. ..................................43

RB4.............................................................................43

RB5.............................................................................43

RB6.............................................................................43

RB7.............................................................................43

PORTC ...............................................................................45

Associ a te d Re g i sters............ ..................... ...........34, 48

Pin Descriptions and Diagrams .................................. 46

RC0 ............................................................................ 46

RC1 ............................................................................ 46

RC2 ............................................................................ 47

RC3 ............................................................................ 47

RC4 ............................................................................ 47

RC5 ............................................................................ 48

RC6 ............................................................................ 46

RC7 ............................................................................ 46

Specifications ........................................................... 152

Power-Down Mode (Sleep)............................................... 123

Power-up Timer (PWRT).................................................. 110

Specifications ........................................................... 154

Power-up Ti ming D e l a ys........ ..... ...... .. ...... ..... ...... ...... ...... . 112

Precisio n In ternal Oscilla to r Parameter s...................... .... 153

Prescaler

Shared WDT/Timer0................................................... 50

Switching Prescaler Assignment................................ 50

Program Memory.................................................................. 9

Map and Stack .............................................................. 9

Prog r a mming , D e v i ce In stru c ti o ns.... ...... ...... ..... .. ...... .. ..... 127

PWM. See Two Phase PWM

PWMCLK Register.............................................................. 94

PWMCON0 Register........................................................... 93

PWMCON1 Register......................................................... 101

PWMPH1 Register.............................................................. 95

PWMPH2 Register.............................................................. 96

Reader Response............................................................. 202

Read-Modify-Write Operations......................................... 127

REFCON (VR Control)........................................................ 73

INTCON INTERRUPT CONTROL REGISTER (AD-

DRESS

0Bh, 8Bh, 10Bh or 183h).................................... 17

IOCA (Interrupt-on-Change)....................................... 37

WPUA (Weak Pull-up PORTA)................................... 36

Registers

ADCON0 (A/D Control 0)............................................ 83

ADCON1 (A/D Control 1)............................................ 84

ANSEL (Analog Select)................................ 93, 94, 101

ANSEL0 (Analog Select 0)......................................... 82

ANSEL1 (Analog Select 1)......................................... 82

CCP1CON (CCP Operation) ...................................... 57

CCPR1H..................................................................... 57

CCPR1L ..................................................................... 57

CM1CON0 (C1 Control) ............................................. 65

CM1CON0 (C2 Control)

CM2CON0.......................................................... 67

CM2CON1 (C2 Control) ............................................. 68

CONFIG (Configuration Word)................................. 108

Data Memory Map...................................................... 10

EEADR (EEPR OM Add re ss)...... .. ...... .. ..... .. .. .. ...... .. . 103

EECON1 (EEPROM Control 1)........... ......... ............ 104

EECON2 (EEPROM Control 2)........... ......... ............ 104

EEDAT (EEPROM Data).......................................... 103

INTC ON (I n te r rupt Control) ...... ...... ...... ......... .......... ... 1 7

IOCA (Interrupt-on-Change PORTA).......................... 37

Op Amp 2 Contro l Register (OPA2C ON) ..... .............. 76

OPTION_REG

OPTION REGISTER .......................................... 16

OPTION_R EG (Option)................... ..................... ...... 17

OSCC ON (Osc il l a tor Con t r o l ). ...... ...... ..... .......... ...... ... 33

PCON (Power Control)............................................. 112

PIE1 (Peripheral Interrupt Enable 1) .......................... 18

PIC16F785/HV785

PIR1 (Peripheral Interrupt Register 1) ........................19

PORTA........................................................................35

PORTB........................................................................42

PORTC .......................................................................45

PWMCLK (PWM Clock Control) ... ......... .............. .......94

PWMCON0 (PWM Contro l 0 ) ...................... ...............93

PWMCON1 (PWM Contro l 1 ) ...................... .............101

PWMPH1 (PWM Phase 1 control)..............................95

PWMPH2 (PWM Phase 2 control)..............................96

REFCON (VR Control)................................................73

Reset Values...... ............... ........................... .............114

Reset Values (Special Registers).............................116

Special Function Registers ...........................................9

Special Register Summary .............................12, 13, 14

STATUS......................................................................15

Status..................................................................16, 109

T1CON (Timer1 Con tr o l)....... ....................... ........ .......53

T2CON (Timer2 Con tr o l)....... ....................... ........ .......55

TRISA (Tri-State PORTA)...........................................36

TRISB (Tri-State PORTB)...........................................42

TRISC (Tri -state PORTC)............................ ...............45

WDTCON (Watchdog Tim er Contro l)........................122

WPUA (Wea k Pull-up PORTA).............. .....................36

Resets...............................................................................109

Power-On Re set ...... ............... ..................... .............110

Revision History................................................................193

RRF Instruction............ ............... ............... .............. .........133

SLEEP

Instruction .................................................................133

Power-Down Mode ...................................................123

Wake-Up...................................................................123

Wake-Up Using Interrupts .........................................123

Softwa re Simulator ( MP L AB SIM).................... .................138

Special Event Trigger..........................................................89

Special Function Registers ...................................................9

Specifications....................................................................158

STATUS Regi ster....... ..................... ..................... ...............15

Statu s Reg i ster....... ..................... ..................... ...........16, 109

SUBLW Ins truction............. ............................ ...................134

SUBWF Instruction............................................................134

SWAPF Ins truction............. ..................... ..........................134

Time-out Sequence........................... .... ......... .... .... .... .......112

Timer0.................................................................................49

Associ a te d Re gisters.............. ..................... ...............50

External Clock.............................................................50

Interrupt.......................................................................49

Operation ....................................................................49

Prescaler.....................................................................50

Specifications............................................................155

Timer1.................................................................................51

Associ a te d Re gisters.............. ..................... ...............54

Asynchronous Counter Mode .....................................54

Reading and Writing ....... .. .. .. .. ....... .. .. .. .. .. .. ....... ..54

Interrupt.......................................................................52

Modes of Operations.......................................... .. .......52

Operation During Sleep ..............................................54

Oscillator.....................................................................54

Prescaler.....................................................................52

Specifications............................................................155

Timer1 Gate

Inve r t in g Gate.... .. ...... ...... ..... .......... ...... ..... ...... ... 52

Selectin g So u rce ....................... ..................... .... 52

TMR1H Register.........................................................51

TMR1L Register.......................................................... 51

Timer2................................................................................. 55

Associated Registers.................................................. 56

Operation.................................................................... 55

Postscaler................................................................... 55

PR2 Register .............................................................. 55

Prescaler .................................................................... 55

TMR2 Register............................................................55

TMR2 to PR2 Match Interrupt............................... 55, 56

Timing Diagrams

A/D Conver sion....... ..................... .............. ...............160

A/D Conversion (Sleep Mode).................................. 161

Brown-out Reset (BOR)............................................ 154

Brown-out Reset Situations...................................... 111

Capture/Compare/PWM ( CCP)...................... ........ .. 156

CLKOUT and I/O ...................................................... 152

External Clock...........................................................151

Fail-Safe Clock Monitor (FSCM)................................. 32

INT Pin Interrupt ....................................................... 119

Reset, WDT, OST and Power-up Timer................... 153

Time-out Sequence

Case 1.............................................................. 113

Case 2.............................................................. 113

Case 3.............................................................. 113

Timer0 and Timer1 External Clock........................... 155

Timer1 Incrementing Edge......................................... 52

Two Phase PWM

Complemen t a r y Outpu t .... ...... .......... ..... .......... . 102

Start-up............................................................... 97

Two Speed Start-up....................... .... .. .. .. .... ..... .. .... .. .. 31

Two-Phase PWM

Auto-Shutdown................................................... 97

Wake-up from Interrupt ............................................. 124

Timing Parameter Symbology .......................................... 150

TRIS Instr u ction................................... .............. ............... 134

TRISA Register................................................................... 36

TRISB Register................................................................... 42

TRISC Regist e r.... ..................... ............... ............... ............ 45

Two Phase PWM.................... .................................. .......... 91

Activating.................................................................... 91

Active Output Level .................................................... 92

Associated Registers................................................ 102

Auto-shutdown............................................................ 92

Clock Control (PWMCLK)........................................... 94

Control Register 0 (PWMCON0)................................. 93

Control Register 1 (PWMCON1)............................... 101

Master /Slave Operation..................... ............... ........ .. 91

Output Bla n king...................... ..................... ............... 91

Phase 1 Contro l (PWMPH1).............. ............... .......... 95

Phase 2 Contro l (PWMPH1).............. ............... .......... 96

PWM Duty Cycle... .............. ............... ............... .......... 91

PWM Frequency......................................................... 91

PWM Period..... ............................ ............................... 91

PWM Phase................................... ............................. 91

PWM Phase Reso lu tion..................... ........ ................. 91

Shutdown.................................................................... 92

Two-Phase PWM

Dead Time Delay...................................................... 158

Two-Speed Clock Start-up Mode........................................ 30

PIC16F785/HV785

Voltage Reference (VR)

Specifications............................................................157

Voltage Reference Output (VREF) BUFFER

Specifications............................................................157

Voltage References ................................... .. .... .. ......... .. .... ..70

Associ a te d Re g i sters................... ..................... ..........74

Configuring CVref .......................................................70

CVref (Comparator Reference)...................................70

CVref Accuracy...........................................................70

Fixed VR r ef e rence........................ ........................... ..73

VR Stabilization ...........................................................74

VREF. SEE A/D Reference Voltage

Wake-up Using Interrupts.................................................123

Watchdog Timer (WDT)............................. .... .... ......... .... ..121

Associ a te d Re g i sters................... ..................... ........122

Clock Source.............................................................121

Modes.......................................................................121

Period........................................................................121

Specifications............................................................154

WDTCON Registe r ......... .............. ..................... ...............122

WPUA (Wea k Pull-up PORTA)....... ....................................36

WPUA Regist e r.................................... ..................... ..........36

WWW Address..................................................................201

WWW, On-Line Support .......................................................4

XORLW Instruction...........................................................134

XORWF Instr u ction................. ..................... ............... ......135

PIC16F785/HV785

NOTES:

PIC16F785/HV785

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

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To register, access the Microchip web site at

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Users of Microchip products can receive assistance

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Customers should contact their distributor,

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support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical suppo rt is avail able throug h the we b site

at: http://support.microchip.com

PIC16F785/HV785

READER RESP ONSE

It is ou r intention to provide you w it h th e b es t documentation possible to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subject matter, and ways in whic h our doc umenta tion

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DS41249EPIC16F785/HV785

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

PIC16F785/HV785

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F785(1), PIC16HV785 (1), PIC16F 78 5 T (2),

PIC16HV785T(2);

VDD range 4.2V to 5.5V

PIC16F785(1), PIC16HV785(1), PIC16F785T(2),

PIC16HV785T(2);

VDD range 2.0V to 5.5V

Temperature

Range: I= -40°C to +85°C Industrial)

E= -40°C to +125°C Extended)

Package: ML = QFN

P=PDIP

SO = SOIC

SS = SSOP

Pattern: QTP, SQTP, Code or Special Requirements

(blank oth erwis e )

Examples:

a) PIC16F785 - E/SO 301 = Extended temp.,

SOIC package.

b) PIC16F785 - I/ML = Industrial temp., QFN

package.

Note 1: F = Standard Voltage Range

LF = Wide Vo ltage Range

2: T = in tape and reel PLCC, and TQFP

packages only.

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WORLDWIDE SALES AND SERVICE

01/02/08