XR16M580IB25 - Exar Corporation

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017

•

www.exar.com

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

SEPTEMBER 2008 REV. 1.0.0

GENERAL DESCRIPTION

The XR16M5801 (M580) is an enhanced Universal

Asynchronous Receiver and Transmitter (UART) with

16 bytes of transmit and receive FIFOs, selectable

transmit and receive FIFO trigger levels, automatic

hardware and software flow control, and data rates of

up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5

Mbps at 1.8V with 4X data sampling rate.

The Auto RS-485 Half-Duplex Direction control

feature simp lifies both the hardware and software for

half-duplex RS-485 applications. In addition, the

Multidrop mode with Auto Address detection

increases the performance by simplifying the

softwar e routines.

The Independent TX/RX Baud Rate Generator

feature allows the transmitter and receiver to operate

at different baud rates. Power consumption of the

M580 can be minimized by enabling the sleep mode

and PowerSave mode.

The M580 has a 16550 compatible register set that

provide users with operating status and control,

receiver error indications, and modem serial interface

controls. An internal loopback capability allows

onboard diagnostics. The M580 is available in 32-pin

QFN, 48-pin TQFP and 25-pin BGA packages. All

three packages offer both the 16 mode (Intel bus)

interface and the 68 mode (Motorola bus) interface

which allows easy integration with Motorola

processors.

OTE

1 Covered by U.S. Patent #5,649,122.

FEATURES

•

Pin-to-pin compatible with XR16L580 in 32-QFN

and 48-TQFP packages

•

Intel or Motorola Bus Interface select

•

16Mbps maximum data rate

•

Selectable TX/RX trigger levels

•

TX/RX FIFO Level Counters

•

Independent TX/RX Baud Rate Generator

•

Fractional Baud Rate Generator

•

Auto RTS/CTS Hardware Flow Control

•

Auto XON/XOFF Software Flow Control

•

Auto RS-485 Half-Duplex Direction Control

•

Multidrop mode w/ Auto Address Detect

•

Sleep Mode with Automatic Wake-up

•

PowerSave mode

•

Infrared (IrDA 1.0 and 1.1) mode

•

1.62V to 3.63V supply operation

•

Crystal oscillator or external clock input

APPLICATIONS

•

Personal Digital Assistants (PDA)

•

Cellular Phones/Data Devices

•

Battery-Operated Devices

•

Global Positioning Syst em (G PS)

•

Bluetooth

FIGURE 1. XR16M580 BLOCK DIAGRAM

VCC

XTAL1

XTAL2

C ry s ta l Osc /Buffer

TX, RX,

RTS#, CTS#,

DTR#, DSR#,

In te l or

Motorola

D a ta B us

Interface

UART

16 Byte RX FIFO

BRG

ENDEC

TX &

UART

Regs

A2:A0

PwrSave

16 Byte TX FIFO

RI#, CD#

RESET

(RESET#)

D7:D0

IO W# (R /W#)

CS#

IN T (IR Q#)

IOR#

GND

(1.62 to 3.63 V)

16/68#

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

FIGURE 2. PIN OUT ASSIGNMENT FOR 32-PIN QFN AND 48-PIN TQFP PACKAGES IN 16 AND 68 MODE

12345678

24 23 22 21 20 19 18 17

VCC

10 1

10 XTAL 1

XTAL 2

R/W#

GND

IOR#

PwrSave

GND

RI#

VCC

DSR#

CD#

XTAL

IOW

GND

IOR

PwrSave

16/68#

32- pin QF N in

Intel Bus Mode

RESET

RTS#

INT

DTR#

CTS#

RI#

VCC

DSR#

CD#

24 23 22 21 20 19 18 17

RESET#

RTS#

IRQ#

DTR#

CTS#

32-pin QF N in

Motorola Bus

Mode

12345678

CS#

16/68#

VCC

36 35 34 33 32 31 30 29 28 27 26 25

48-TQFP in

Motorola Bus Mode

1 2 3 4 5 6 7 8 9 10 11 12

36 35 34 33 32 31 30 29 28 27 26 25

48-TQFP in

Intel Bus Mode

VCC GND

1 2 3 4 5 6 7 8 9 10 11 12

RESET

DTR#

RTS#

INT

CTS#

DSR#

CD#

RI#

VCC

CS#

16/68# RESET#

DTR#

RTS#

IRQ#

CS#

16/68#

CTS#

DSR#

CD#

RI#

VCC

IOR#

GND

IOW#

XTAL2

XTAL1

PwrSave

IOR#

GND

R/W#

XTAL2

XTAL1

PwrSave

VCC

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

FIGURE 3. PIN OUT ASSIGNMENT FOR 25-PIN BGA PACKAGE

ORDERING INFORMATION

ART

UMBER

ACKAGE

PERATING

EMPERATURE

ANGE

EVICE

TATUS

XR16M580IL32 32-PinQFN -40°C to +85°C Active

XR16M580IM48 48-Lead TQFP -40°C to +85°C Active

XR16M580IB25 25-Pin BGA -40°C to +85°C Active

1 2 3 4 5

Transparent Top View

A1 Corner

CTS# RESET INT A1 A2

VCC 16/68# RTS# A0 IOR#

D0 D6 D7 PwrSave IOW#

D3 D1 TX CS# XTAL1

D4 D2 D5 RX GND

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

PIN DESCRIPTIONS

Pin Description

AME

32-QFN

#48-TQFP

PIN# 25-BGA

YPE

ESCRIPTION

DATA BUS INTERFACE

IAddress lines [2:0]. These 3 address lines select the internal regis-

ters in UART channel during a data bus transaction.

I/O Data bus lines [7:0] (bidirectional).

IOR# 14 19 B5 IWhen 16/68# pin is at logic 1, the Intel bus interface is selected and

this input becomes read strobe (active low). The falling edge insti-

gates an internal read cycle and retri eves the data byte from an

internal register pointed by the address lines [A2:A0], puts the data

byte on the data bus to allow the host processor to read it on the ris-

ing edge.

When 16/68# pin is at logic 0, the Motorola bus interface is selected

and this input should be connected to VCC.

IOW#

(R/W#) 12 16 C5 IWhen 16/68# pin is at logic 1, it selects Intel bus interface and this

input becomes write strobe (active low). The falling edge instigates

the internal write cycle and the rising edge transfers the data byte

on the data bus to an internal register pointed by the address lines.

When 16/68# pin is at logic 0, the Motorola bus interface is selected

and this input becomes read (logic 1) and write (logic 0) signal .

CS# 811 D4 IThis input is chip select (active low) to enable the devi ce.

INT

(IRQ#) 20 30 A3 O

(OD) When 16/68# pin is at logic 1 for Intel bus interface, this output

become the active high device interrupt output. The output state is

defined by the user through the software setting of MCR[3]. INT is

set to the active mode when MCR[3] is set to a logic 1. INT is set to

the three state mode when MCR[3] is set to a logic 0. See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output

becomes the active low device interrup t ou tput (open drain). An

external pull-up resistor is required for proper operation.

MODEM OR SERIAL I/O INTERFACE

TX 7 8 D3 OUART Transmit Data or infrared encoder data. Standard transmit

and receive interface is enabled when MCR[6] = 0. In this mode,

the TX signal will be a logic 1 during reset or idle (no data). Infrared

IrDA transmit and receive interface is enabled when MCR[6] = 1. In

the Infrared mode, the inactive state (no data) for the Infrared

encoder/decoder interface is a logic 0. If it is not used, leave it

unconnected.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

RX 6 7 E4 IUART Receive Data or infrared receive data. Normal receive data

input must idle at logic 1 condition. The infrared receiver idles at

logic 0. This input should be connected to VCC when not used.

RTS# 21 32 B3 OUART Request-to-Send (active low) or gene ral purpose output.

This output must be asserted prior to using auto RTS flow control,

see EFR[6], MCR[1] and IER[6].

CTS# 24 38 A1 IUART Clear-to-Send (active low) or general purpose input. It can

be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].

This input should be connected to VCC when not used.

DTR# 22 33 - O UART Data -Terminal-Ready (active low) or general purpose output.

DSR# 25 39 - I UART Data-Set-Ready (active low) or general purpose input. This

input should be connected to VCC when not used.

CD# 26 40 - I UART Carrier-Detect (active low) or general purpose input. This

input should be connected to VCC when not used.

RI# 27 41 - I UART Ring-Indicator (active low) or general purpose input. This

input should be connected to VCC when not used.

ANCILLARY SIGNALS

XTAL1 10 14 D5 ICrystal or external clock input.

XTAL2 11 15 - O Crystal or buffered clock output.

PwrSave 913 C4 IPower-Save (active high). This feature isolates the M580’s data bus

interface from the host preventing other bus activities that cause

higher power drain during slee p mode. See Sleep Mode with Auto

W ake-up and Power-Save Feature section for details. This pin does

not have an internal pull-down resistor. This input should be con-

nected to GND when not used.

16/68# 2 1 B2 IIntel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or

Intel Mode, the device will operate in the Intel bus type of interfa c e.

When 16/68# pin is at logic 0, 68 or Motorola mode, the device will

operate in the Moto rola bus type of interface. This pin does not

have an internal pull-up or pull-down resistor.

RESET

(RESET#) 23 35 A2 IWhen 16/68# pin is at logic 1 for Intel bus interface, this inp ut

becomes RESET (active high). When 16/68# pin is at logic 0 for

Motorola bus interface, this input becomes RESET# (active low).

A 40 ns minimum active pulse on this pin will reset th e internal reg-

isters and all outputs of the UART. The UART transmitter output will

be held at logic 1, the receiver input will be ignored and outputs are

reset during reset period (see UART Reset Conditions).

VCC 28 42 B1 Pwr 1.62V to 3.63V power supply.

GND 13 18 E5 Pwr Power supply common, ground.

GND Center

Pad - - Pwr The center pad on the backside of the QFN package is metallic and

should be connected to GND on the PCB. The thermal pad size on

the PCB should be the approximate size of this center pad and

should be solder mask defined. The solder mask opening should be

at least 0.0025" inwards from the edge of the PCB thermal pad.

Pin Description

AME

32-QFN

#48-TQFP

PIN# 25-BGA

YPE

ESCRIPTION

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

Pin type: I=Input, O=Ou tput, I/O= Input/ou t pu t, OD=Output Open Drain .

1.0 PRODUCT DESCRIPTION

The XR16M580 (M580) is a high performance single channel UART. The configuration registers set is 16550

UART compatible for control, status and data transfer. Additionally, the M580 channel has 16 bytes of transmit

and receive FIFOs, Automatic RTS/CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character

Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud

rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps. The XR16M580 can operate

from 1.62 to 3.63 volts. The M580 is fabricated with an advanced CMOS process.

Data Rate

The M580 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate. The device can

operate at 3. 3V with a 24 MHz cryst al on pins XTAL1 and XTAL2, or exter nal clock source of 32 MHz on XTAL1

pin. With a t ypical cr ystal of 14.7456 MHz and t hroug h a software option, the user can set t he prescaler b i t and

sampling rate for data rates of up to 3.68 Mbps.

Enhanced Features

The rich feature set of the M580 is available through the internal registers. Automatic hardware/software flow

control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder,

modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning

off (Xon) sof tware flo w control with any incoming (RX) character. The M580 includes ne w features such a s 9-bit

(Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX, fast IR mode

and fractional baud rate ge nerator.

NC 15, 16 5, 6, 9,

10, 12,

17, 20-

25, 29,

31, 34,

36, 37, 48

--No Connects.

Pin Description

AME

32-QFN

#48-TQFP

PIN# 25-BGA

YPE

ESCRIPTION

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The M580 data interface supports the Intel and motorola compatible types of CPUs. No

clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous

using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is

shown in Figure 4.

FIGURE 4. XR16M580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS

VCCVCC

UART_CS#

IOR#

IOW#

CS#

IOR#

IOW#

UART_INT INT

Intel Data Bus Interconnections

GND

UART_RESET RESET

16/68#

RI#

CD#

DSR#

CTS#

RTS#

DTR#

PwrSave

Serial Transceivers of

RS-232

RS-485

RS-422

Or In frare d

POWERSAVE

VCCVCC

UART_CS#

R/W#

D7 A0

CS#

IOR#

IOW#

UART_IRQ# INT

M otorola Data Bus Interconnections

GND

UART_RESET# RESET

RI#

CD#

DSR#

CTS#

RTS#

DTR#

16/68#

vcc

POWERSAVE PwrSave

Serial Transceivers of

RS-232

RS-485

RS-422

Or Infrared

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

2.2 Serial Interface

The M580 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical

connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422

transceivers, go to www.exar.com or send an e-mail to uarttechsupport@exar.com.

FIGURE 5. XR16M580 TYPICAL SERIAL INTERFACE CONNECTIONS

VCC

RS-485 Full-Duplex Serial Interface

GND

CD#

DSR#

CTS#

DTR#

RTS#

TX DI

UART

RS-485

Transceiver

Full-duplex

TX+

TX-

RX+

RX-

RI#

NC VCC

RE#

VCC

VCCVCC

RS-2 3 2 Full-Mo dem Ser ia l In te r fa c e

GND

RI#

CD#

DSR#

CTS#

RTS#

DTR#

TX T1IN

R1OUT

T2IN

T3IN

R2OUT

R3OUT

R4OUT

R5OUT

GND

UART

RS-232

Transceiver

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

FIGURE 6. XR16M580 TYPICAL SERIAL INTERFACE CONNECTIONS

VCC

RS-485 Half-Duplex Serial Interface

GND

CD#

DSR#

CTS#

DTR#

RTS#

TX DI

UART

RS-485

Transceiver

Half-duplex

RI#

NC VCC DE

RE#

VCCVCC

Infrared C onnection

GND

RI#

CD#

DSR#

CTS#

RTS#

DTR#

TX TXD

RXD

UART

Transceiver

VCC

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs to their default state (see

Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in

the device. Following a power-on reset or an external reset, the M580 is software compatible with previous

generation of UARTs, XR16L580 and ST16C550.

2.4 Internal Registers

The M580 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.

These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),

a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control

registers (MSR/ MCR), programmable dat a rate (clock) divisor registers (DLL/DL M/DLD), and a us er accessible

scratchpad register (SPR).

Beyond the gen eral 16C550 f eature s and ca pa bilities, t he M580 of fers enh anced featu re register s (EFR, Xon 1/

Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR and FC) that provide automatic RTS and CTS hardware flow control,

automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control, different

baud rate for TX and RX and fractional baud rate generator. All the register functions are discussed in full

detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 24.

2.5 INT Ouput

The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2

summarize the operating behavior for the transmitter and receiver. Also see Figure 22 through 25.

OTE

: The IRQ# pin requires a pull-up resistor for proper operation.

TABLE 1: INT PIN OPERATION FOR TRANSMITTER

FCR B

-0 = 0 (FIFO D

ISABLED

)FCR B

-0 = 1 (FIFO E

NABLED

)

INT Pin

(16/68# = 1) LOW = One byte in THR

HIGH = THR empty LOW = FIFO above trigger leve l

HIGH = FIFO below trigger level or FIFO empty

IRQ# Pin

(16/68# = 0) HIGH = One byte in THR

LOW = THR empty HIGH = FIFO above trigger level

LOW = FIFO below trigger level or FIFO empty

TABLE 2: INT PIN OPERATION FOR RECEIVER

FCR B

-0 = 0 (FIFO D

ISABLED

)FCR B

-0 = 1 (FIFO E

NABLED

)

INT Pin

(16/68# = 1) HIGH = One byte in RHR

LOW = RHR empty LOW = FIFO below trigger le vel

HIGH = FIFO above trigger level or RX Data Timeout

IRQ# Pin

(16/68# = 0) LOW = One byte in RHR

HIGH = RHR empty HIGH = FIFO below trigger level

LOW = FIFO above trigger level or RX Data Timeout

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.6 Crystal Oscillator or External Clock Input

The M580 includes an on-chip osc illator to produce a clock for the baud rate generators in the device when a

crystal is connected bet ween XTAL1 and XTAL2 as show below. The CPU dat a bus does not req uire t his clock

for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRGs) in the

UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For

programming details, see “Section 2.7, Programmable Baud Rate Generator with Fractional Divisor” on

page 12.

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown

in Figure 7. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate

generator for standard or custom rates. The BGA package has XTAL1 only, the external clock is required. For

further reading on oscillator circuit, see application note DAN108 on EXAR’s web site.

FIGURE 7. TYPICAL CRYSTAL CONNECTIONS

22-47pF C2

22-47pF

Y1 1.8432 M H z

24 MH z

0-120

(Optional)

500K - 1M

XTAL1 XTAL2

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

2.7 Programmable Baud Rate Generator with Fractional Divisor

The M580 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.

The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to

divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG

further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/

16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the

transmitter for data bit s hifting an d receiver for data sampling. For transmitter and receiver, the M580 provides

respective BRG divisors. The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL =

0x01, DLM = 0x0 0 an d DL D = 0 x0 0) up on re se t. Th eref or e, the BRG mu st be pr og ram me d du rin g initia liza tion

to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD

registers provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value

from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator

Registers DLL , DLM and DLD pr ovides the capability for select ing the operating data rate. Table 3 shows the

standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used

(MCR bit-7 = 1), the output dat a rate will be 4 times less than t hat shown in Table 3. At 8X sampling rate, these

data rates would double. And at 4X sampling rate, they would quadruple. Also, when using 8X sampling mode,

please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number.

When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the

following equation(s):

The closest divisor that is obtainable in the M580 can be calculated using the following formula:

In the formulas above, please note that:

TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.

ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.

A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.

2.7.1 Independent TX/RX BRG

The XR16M580 has t wo indepen dent se ts of TX and RX baud rate generat or. Please see the Figure 8. TX and

RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data

to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate

setting, please See ”Section 4.13, Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write” on

page 38..

Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’

Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’

ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where

DLM = TRUNC(Required Divisor) >> 8

DLL = TRUNC(Required Divisor) & 0xFF

DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

FIGURE 8. BAUD RATE GENERATOR

TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING

Required

Output Data

Rate

IVISOR

FOR

16x

Clock

(Decimal)

IVISOR

BTAINABLE

M580

DLM P

ROGRAM

ALUE

(HEX) DLL P

ROGRAM

ALUE

(HEX) DLD P

ROGRAM

ALUE

(HEX) D

ATA

RROR

ATE

(%)

400 3750 3750 EA6 0 0

2400 625 625 271 0 0

4800 312.5 312 8/16 138 8 0

9600 156.25 1 56 4/16 09C 4 0

10000 150 150 096 0 0

19200 78.125 78 2/16 04E 2 0

25000 60 60 03C 0 0

28800 52.0833 52 1/16 034 10.04

38400 39.0625 39 1/16 027 1 0

50000 30 30 01E 0 0

57600 26.0417 26 1/16 01A 10.08

75000 20 20 014 0 0

100000 15 15 0 F 0 0

115200 13.0208 13 0 D 0 0.16

153600 9.7656 9 12/16 0 9 C 0.16

200000 7.5 7 8/16 0 7 8 0

225000 6.6667 6 11/16 0 6 B 0.31

230400 6.5104 6 8/16 0 6 8 0.16

250000 66 0 6 0 0

300000 55 0 5 0 0

400000 3.75 3 12/16 0 3 C 0

460800 3.2552 3 4/16 0 3 4 0.16

500000 33 0 3 0 0

750000 22 0 2 0 0

921600 1.6276 1 10/16 0 1 A 0.16

1000000 1.5 1 8/16 0 1 8 0

XTAL1

XTAL2 /

(default)

16X or 8X or 4X

Sampling Rat e Clock

to Transmitter

Prescaler

Divide by 1

Prescaler

Divide by 4

MCR Bit 7=0

MCR Bit-7=1

Crystal

Osc

Buffer

DLL

DLM

DLD[5:0]

DLL

DLM

DLD[5:0]

16X or 8X or 4X

Sampling Rat e Clock

to Receiver

DLD[7]=0

DLD[7]=1

DLD[6]

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

2.8 Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X

internal clock. A bit time is 16/8/4 clock periods. The transmitter sends the start-bit followed by the number of

data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are

reported in the Line Status Register (LSR bit-5 and bit-6).

2.8.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.8.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byt e is transfe rred to TSR. THR flag ca n generate a tr an smit empty int errupt (I SR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

(THR)

Transmit Shift Register (TSR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

TXNOFIFO1

16X or 8X or 4X

Clock

( DLD[5:4] )

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.8.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is e mpty. The THR empty flag can gen erate a t ransmit empty int errupt (I SR bit-1) wh en th e

FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set

when TSR/FIFO becomes empty.

2.9 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It

verifies and validates every bit on the incoming characte r in the m iddle of each d ata bit. On th e falling edge of

a start or false start bit, an inter nal receiver co unter starts counting at the 1 6X/8X/4X c lock rate. After 8 cloc ks

(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is

sampled and if it is still a logic 0 it is validated . Eval uating t he st art bit in this manne r prevents the receiver from

assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same

manner to pr event f alse framin g. If there were any err or(s), they are r eported in the LSR r egister bits 2-4. Upon

unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are

immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data

ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data

delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4

word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR

interrupt is enab led by IER bit-0. See Figure 11 and Figure 12 below.

2.9.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be re ported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit Data Shift Register

(TSR)

Transmit

D ata B yte THR In ter ru p t (ISR b it-1 ) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Transmit

FIFO

16X or 8X or 4X Clock

(DLD[5:4])

Auto CTS Flow Control (CTS# pin)

Auto Softwar e Flow Control

Flow Control Characters

(Xoff1/2 and Xon1/2 R eg.)

TXFIFO1

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE

FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

Receive Data Shift

Receive

Da ta B y te

and Errors RH R Inte rrupt (ISR bit-2)

Receive Data

Holding Register

(RHR)

RXFIFO1

16X or 8X or 4X Clock

( DLD[5:4] )

Receive Data Characters

Da ta B it

Validation

Error

Tags in

LSR bits

4:2

Receive Data Shift

RXFIFO1

16X or 8X or 4X Clock

( DLD[5:4] )

Error Tags

(16-sets)

Error Tags in

LSR bits 4:2

Receive Data C haracters

D ata B it

Validation

Receive

D a ta F IF O

Receive

Data

Receive Data

B y te and E rr o r s

RH R Interrupt (ISR bit-2) program m ed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

RT S# de-asserts when data fills above the flow

control trig ger level to suspend remote transmitter.

Enable by EFR bit-6=1, M C R bit-1.

RT S # re - a s serts wh e n d ata fa lls b e lo w th e flow

contr o l tr ig g e r le v e l to restart re mote tra nsmitte r .

Enable by EFR bit-6=1, MCR bit-1.

16 bytes by 11-bit wide

FIFO

Trigger=8

Data f a lls to

D a ta fills to

Example

: - RX F IFO trigger level selected at 8 bytes

(See Note Below )

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.10 Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enab le d to fit sp ec ific ap plic atio n req uirem e nt (see Figure 13):

•

Enable auto RTS flow control using EFR bit-6.

•

The auto R TS function must be st arted by asserting R TS# output pin (MCR bit-1 to logic 1 af ter it is enabled).

If using the Auto RTS interrupt:

•

Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.11 Auto RTS Hysteresis

With the Auto R TS funct ion enab led, an interrup t is generat ed when the r eceive FIFO reaches th e selected RX

trigger level. The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches one trigger level

above the selected trigger level in the trigger table (Table 9). The RTS# pin will return LOW after the RX FIFO

is unloaded to one level below the selected trigger level. Under the above described conditions, the M580 will

continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS#

output pin is asserted LOW (RTS On).

2.12 Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 13):

•

Enable auto CTS flow control using EFR bit-7.

If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an

interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend

TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL

RIGGER

EVEL

INT P

CTIVATION

RTS# D

ASSERTED

IGH

)

HARACTERS

IFO

)RTS# A

SSERTED

)

HARACTERS

IFO

)

1 1 4 0

4 4 8 1

8 8 14 8

14 14 14 14

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after

the CTS# input is re-asserted (LOW), indicating more data may be sent.

FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is norma lly connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unlo aded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

RTSA# CTSB#

RXA TXB Transmitter

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

Auto CTS

Monitor

RTSA#

TXB

RXA FIFO

CTSB#

Remote UART

UARTB

Local UART

UARTA

ON OFF ON

Suspend Restart

RTS High

Threshold

Data Starts

ON OFF ON

Assert RTS# to Begin

Transmission

Receive

Data RTS Low

Threshold

Receiver FIFO

Trigger Reached

Auto RTS

Trigger Level

Transmitter

Auto CTS

Monitor

RTSB#CTSA#

RXBTXA

INTA

(RXA FIFO

Interrupt)

RX FIFO

Trigger Level

RX FIFO

Trigger Level

RTSCTS1

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.13 Auto Xon/Xoff (Software) Flow Control

When software flow control is enabled (See Table 15), the M580 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the M580 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the M580 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the M580 will resume operation

and clear the fl ags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user

can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/

Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters

are selected, the M580 compares two consecutive receive characters with two software flow control 8-bit

values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow

control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or

FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the M580 automatically

sends an Xoff message (when enabled) via the serial TX output to the remote modem. The M580 sends the

Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)

after the receive FIFO crosses the selected trigger level. To clear this condition, the M580 will transmit the

programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the selected

trigger level. Table 5 below explains this.

* Af ter the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);

for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

2.14 Special Char acter Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this chara cter (Xof f 2) is de te cted, it will be placed in the FIFO along wit h normal

incoming RX data.

The M580 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the

Internal Register Table shows Xon, Xo ff Registers with eight bits of character information, the actual number of

bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff

Registers corresponds with the LSB bit for the receive character.

2.15 Normal Multidrop Mode

Normal multidrop mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR[5] = 0 (Special Character

Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received

(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR

TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

RX T

RIGGER

EVEL

INT P

CTIVATION

OFF

HARACTER

(

) S

ENT

(

CHARACTERS

FIFO

HARACTER

(

) S

ENT

(

CHARACTERS

FIFO

)

1 1 1* 0

4 4 4* 1

8 8 8* 4

14 14 14* 8

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the

receiver if the address matches its slave address, otherwise, it does not enable the receiver.

If the receiver has been enabled, th e receiver will receive the subsequent data. If an address byte is received,

it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave

address, it does not have to do anything. If the address does not match its slave address, then the receiver

should be disabled.

2.15.1 Auto Address Detection

Auto address detection mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The

desired slave address will need to be writ ten into the XOFF2 regist er. The receiver will try to detect an address

byte that m atches the porgr ammed character in the XOFF2 register. If the received byte is a data byte or an

address byte that does not match the programmed character in the XOFF2 register, the receiver will discard

these data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be

automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with

the parity bit (in p lace of the parity error bit). T he receiver also generates an LSR interrupt. The receiver will

then receive the subsequent data. If another address byte is received and this address does not match the

programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is

ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity

bit in the parity error bit.

2.16 Infrared Mode

The M580 UAR T include s the infr ared en coder an d deco der co mp atible to the I rDA (Infr ared Data Association)

version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a

3/16 of a bit wide

HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1

standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit

data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED,

hence reduces the power consumption. See

Figure 14

below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the

infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to

be compatible to the IrDA 1.1 standard, MSR bit-7 will also need to be set to a ’1’ when EFR bit-4 is set to ’1’.

Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 14.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.

Each time it senses a light pulse, it returns a logic 1 to the data bit stream.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.17 Sleep Mode with Auto Wake-Up and Power-Save feat ure

The M580 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save

feature is included to reduce its power consumption when the chip is not actively used.

2.17.1 Sleep mode

All of these conditions must be satisfied for the M580 to enter sle ep mode:

■

no interrupts pending (ISR bit-0 = 1)

■

sleep mode is enabled (IER bit-4 = 1)

■

modem inputs are not toggling (MSR bits 0-3 = 0)

■

RX input pin is idling HIGH in normal mode or LOW in infrared mode

■

divisor is non-zero

■

TX and RX FIFOs are empty

The M580 stops its crystal oscillator to conserve powe r in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The M580 resumes normal operation by any of the following:

■

a receive data start bit transition (HIGH to LOW)

■

a data byte is loaded to the transmitter, THR or FIFO

■

a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the M580 is awakened by any one of the above conditions, it will return to the sleep mode automatically after

all interrupting conditions have been serviced and cleared. If the M580 is awakened by the modem inputs, a

read to the MSR is required to reset the modem inputs. In any case, the s leep mode will not be entered while

FIGURE 14. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data B its

Start

Stop

0000 0

11 111

Bit Time

1/16 Clock Delay

IRdecoder-1

RX Data

Receive

IR Pu ls e

(RX pin)

Character

Data Bits

Start

Stop

0000 0

11 111

TX Data

Transmit

IR Pulse

(TX Pin) Bit Time 1/2 Bit Tim e

3/16 or 1/4 Bit Time

IrEncoder-1

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

an interrup t is pen ding from any ch annel. Th e M58 0 will stay in the s leep m ode of operation until it is disabled

by setting IER bit-4 to a logic 0.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the

first few receive characters may be lost. Also, make sure the RX pin is idling HIGH or “marking” condition

during sleep mode. This may not occu r when the external interface transceivers (RS-232, RS-485 or another

type) are also put to sleep mo de an d cann ot maintain the “marking” condition. To avoid this, the system design

engineer can use a 47k ohm pull-up resistor on each of the RX input.

2.17.2 Power-Save Feature

If the address lines, da ta bus lines, IOW# , IOR #, CS# and modem input lines remain steady when the M580 is

in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical

Characteristics on page 43. If the input lines are floating or are toggling while the M580 is in sleep mode, the

current can be up to 100 ti mes mo re. If not using the Power-Sa ve featur e, an exte rnal buffer would be required

to keep the address and data bus lines from toggling or floating to achieve the low current. But if the Power-

Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by

internally isolating the addres s, data and control signals (see Figure 1 on page 1) from other bus act ivities th at

could cause wasteful p ower dr ain. The M5 80 ent ers Powe r-Save mo de when this pin is connected to VCC and

the M580 is in sleep mode (see Sleep Mode section above).

Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:

■

a receive data start bit transition (HIGH to LOW) at the RX input or

■

a change of logic state on the modem or general purpose serial input CTS#, DSR#, CD#, RI#

The M580 will return to the Power-Save mode automatically af ter a r ead to the MSR (to reset the modem input

CTS#) and all interrupting conditions have been serviced and cleared. The M580 will stay in the Power-Save

mode of operatio n unt il it is disabled by setting IER bit- 4 t o a logic 0 and/ or t he Power- Save pin is conne cted t o

GND.

2.17.3 Wake-up Interrupt

The M580 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The

default status of wake up interrupt is disabled. Please See ”Section 4.5, FIFO Control Register (FCR) -

Write-Only” on page 30.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

2.18 Internal Loopback

The M580 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode

is enabled by setting MCR register bit-4 to logic 1. All regular UAR T funct ions operate norm ally.

Figure 15 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,

DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else

upon exiting the loopback test the UART may detect and report a false “break” signal.

FIGURE 15. INTERNAL LOOPBACK

Modem / General Purpose Control Logic

Internal Data Bus Lines and Control Signals

RTS#

MCR bit-4=1

VCC

Transmit Shift Register

(THR/FIFO)

Receive Shift Register

(RHR/FIFO)

CTS#

DTR#

DSR#

RI#

CD#

OP1#

RTS#

CTS#

DTR#

DSR#

RI#

CD#

VCC

OP2#

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

3.0 UART INTERNAL REGISTERS

The complete register set for the M580 is shown in Table 6 and Table 7.

TABLE 6: UART INTERNAL REGISTERS

A2 A1 A0

DDRESSES

EGISTER

EAD

RITE

OMMENTS

16C550 C

OMPATIBLE

EGISTERS

0 0 0 DREV - Device Revision Read-only LCR[7] = 1, LCR ≠ 0xBF,

DLL = 0x00, DLM = 0x00

0 0 1 DVID - Device Identification Register Read-only

0 0 0 DLL - Divisor LSB Register Read/Write LCR[7] = 1, LCR ≠ 0xBF

See DLD[7: 6]

0 0 1 DLM - Divisor MSB Register Read/Write

0 1 0 DLD - Divisor Fractional Register Read/Write LCR[7] = 1, LCR ≠ 0xBF,

EFR[4] = 1

0 0 0 RHR - Receive Holding Register

THR - Transmit Holding Register Read-only

Write-only LCR[7] = 0

0 0 1 IER - Interrupt Enable Register Read/Write

0 1 0 ISR - Interrupt S tatus Register

FCR - FIFO Control Register Read-only

Write-only LCR[7] = 0 if EFR[4] = 1

LCR ≠ 0xBF if EFR[4] = 0

0 1 1 LCR - Line Control Register Read/Write

1 0 0 MCR - Modem Control Register Read/Write

LCR ≠ 0xBF1 0 1 LSR - Line Status Register Read-only

1 1 0 MSR - Modem Status Register Read-only

1 1 0 MSR - Modem Status Register Write-only LCR ≠ 0xBF

EFR[4] = 1

1 1 1 SPR - Scratch Pad Register Read/Write LCR ≠ 0xBF, FCTR[6] = 0

1 1 1 EMSR - Enhanced Mode Select Register Write-only LCR ≠ 0xBF, FCTR[6] = 1

1 1 1 FC - RX/TX FIFO Level Counter Register Read-only

NHANCED

EGISTERS

0 0 0 FC - RX/TX FIFO Level Counter Register Read-only

LCR = 0xBF

0 0 1 FCTR - Feature Control Register Read/Write

0 1 0 EFR - Enhanced Function Reg Read/Write

1 0 0 Xon-1 - Xon Character 1 Read/Write

1 0 1 Xon-2 - Xon Character 2 Read/Write

1 1 0 Xoff-1 - Xoff Character 1 Read/Write

1 1 1 Xoff-2 - Xoff Character 2 Read/Write

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

TABLE 7: INTERNAL REGISTERS DESCRIPTION.

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1

DDRESS

A2-A0 R

AME

EAD

RITE

-7 B

-6 B

-5 B

-4 B

-3 B

-2 B

-1 B

-0 C

OMMENT

16C550 Compatible Registers

0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

LCR[7] = 0

0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 0 1 IER RD/WR 0/ 0/ 0/ 0/ Modem

Stat. Int.

Enable

RX Line

Stat.

Int.

Enable

Empty

Int

Enable

Data

Int.

Enable

CTS#

Int.

Enable

RTS#

Int.

Enable

Xoff Int.

Enable Sleep

Mode

Enable

0 1 0 ISR RD FIFOs

Enabled FIFOs

Enabled 0/ 0/ INT

Source

Bit-3

INT

Source

Bit-2

INT

Source

Bit-1

INT

Source

Bit-0 LCR[7] = 0

if EFR[4]=1

LCR≠0xBF

if EFR[4]=0

RTS

CTS

Interrupt

Xoff

Interrupt

0 1 0 FCR WR RX FIFO

Trigger RX FIFO

Trigger TX FIFO

Trigger Wake up

Int Enable TX

FIFO

Reset

FIFO

Reset

FIFOs

Enable

0 1 1 LCR RD/WR Divisor

Enable Set TX

Break Set

Parity Even

Parity Parity

Enable Stop

Bits Word

Length

Bit-1

Word

Length

Bit-0

1 0 0 MCR RD/WR 0/ 0/ 0/ Internal

Lopback

Enable

INT Out-

put

Enable

(OP2#)

OP1# RTS#

Output

Control

DTR#

Output

Control

LCR≠0xBF

BRG

Pres-

caler

IR Mode

ENable XonAny

1 0 1 LSR RD RX FIFO

Global

Error

THR &

TSR

Empty

THR

Empty RX Break RX Fram-

ing Error RX

Parity

Error

Over-

run

Error

Data

Ready

1 1 0 MSR RD CD#

Input RI#

Input DSR#

Input CTS#

Input Delta

CD# Delta

RI# Delta

DSR# Delta

CTS#

WR Fast IR Enable

9-bit

mode

Disable

RX Disable

TX 0 0 0 0

1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR≠0xBF

FCTR[6]=0

1 1 1 EMSR WR Xoff

interrupt

mode

select

LSR

interrupt

mode

select

0 0 Invert

RTS i n

RS485

mode

Send

imme-

diate

FIFO

count

control

bit-1

FIFO

count

control

bit-0 LCR≠0xBF

FCTR[6]=1

1 1 1 FC RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 15.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 14.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

Baud Rate Generator Divisor

0 0 0 DREV RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1

LCR≠0xBF

DLL= 0x00

DLM= 0x00

0 0 1 DVID RD 0 0 0 0 0 0 0 1

0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1

LCR≠0xBF

DLD[7:6]

0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

0 1 0 DLD RD/WR BRG

select Enable

Indepen-

dent

BRG

4X Mode 8X Mode Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1

LCR≠0xBF

EFR[4] = 1

Enhanced Registers

0 0 0 FC RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

LCR=0

0 0 1 FCTR RD/WR RX/TX

select Swap

SCR 0 0 RS485

interrupt

mode

invert

RX IR 0 0

0 1 0 EFR RD/WR Auto

CTS#

Enable

Auto

RTS#

Enable

Special

Char

Select

Enable

IER [7:4],

ISR [5:4],

FCR[5:3],

MCR[7:5],

DLD

Soft-

ware

Flow

Cntl

Bit-3

Soft-

ware

Flow

Cntl

Bit-2

Soft-

ware

Flow

Cntl

Bit-1

Soft-

ware

Flow

Cntl

Bit-0

1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

TABLE 7: INTERNAL REGISTERS DESCRIPTION.

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1

DDRESS

A2-A0 R

AME

EAD

RITE

-7 B

-6 B

-5 B

-4 B

-3 B

-2 B

-1 B

-0 C

OMMENT

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.3.1 IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enab led, th e RHR int errupt s

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the selected trig-

ger level. It will be cleared when the FIFO drops below the selected trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive dat a re ady bit ( LSR BIT-0) is set as soon as a character is t ransf err ed f rom th e shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M580 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR

RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive dat a ready int erru pt will be issued when RHR ha s a data character in the non-FIFO mode

or when

the receive FIFO has reached the selected trigger level in the FIFO mode.

Logic 0 = Disable the receive data ready interrupt (default).

Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the selected trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

Logic 0 = Disable Transmit Ready interrupt (default).

Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an

overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error. However,

when EMSR bit-6 changes to 1 (default is 0), LSR bit 2-4 generate an interrupt when the character is received

in the RX FIFO. See “Section 4.12, Enhanced Mode Select Register (EMSR) - Write-only” on page 37.

•

Logic 0 = Disable the receiver line status interrupt (default).

•

Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

•

Logic 0 = Disable the modem status register interrupt (default).

•

Logic 1 = Enable the modem status register interrupt.

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

IER[4]: Sleep Mode Enable (requires EFR[4] = 1)

•

Logic 0 = Disable Sleep Mode (default).

•

Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)

•

Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)

•

Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for

details.

IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)

•

Logic 0 = Disable the RTS# interrupt (default).

•

Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from LOW to HIGH (if enabled by EFR bit-6).

IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)

•

Logic 0 = Disable the CTS# interrupt (default).

•

Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

LOW to HIGH (if enable d by EFR bit-7) .

4.4 Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR ) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table , Table 8, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1 Interrupt Generation:

•

LSR is by any of the LSR bits 1, 2, 3 and 4.

•

RXRDY is by RX trigger level.

•

RXRDY Time-out is by a 4-char plus 12 bits delay timer.

•

TXRDY is by TX trigger level or TX FIFO empty.

•

MSR is by any of the MSR bits 0, 1, 2 and 3.

•

Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.

•

CTS# is when the r emote transmitter t oggles the input pin (from LOW to HIGH) dur ing auto CTS flow cont rol.

•

RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

•

Wakeup interrupt is genera ted when the M580 wakes up from the sleep mode.

4.4.2 Interrupt Clearing:

•

LSR interrupt is cleared by a read to the LSR register.

•

RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

•

RXRDY Time-out interrupt is cleared by reading RHR.

•

TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

•

MSR interrupt is cleared by a read to the MSR register.

•

Xon or Xoff interrupt is cleared by a read to the ISR register. See EMSR[7].

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

•

Special character interrupt is cleared by a read to ISR register or after next character is received. See

EMSR[7].

•

RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

•

Wakeup interrupt is cleared by a read to ISR register.

]

ISR[0]: Interrupt Status

•

Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine .

•

Logic 1 = No interrupt pending (default condition) .

ISR[3:1]: Interrupt Status

These bit s indi cate the so urce for a pendin g interr upt at int errupt priori ty leve ls (See Int errupt Source Table 8).

ISR[4]: Interrupt Status (requires EFR bit-4 = 1)

This bit is enabled wh en EFR bit-4 is set to a logic 1. IS R bit-4 indicates that the receiver detected a data mat ch

of the Xoff, Xon or special character(s).

ISR[5]: Interrupt Status (requires EFR bit-4 = 1)

ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

TABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL

RIORITY

ISR R

EGISTER

TATUS

ITS

OURCE

INTERRUPT

EVEL

-5 B

-4 B

-3 B

-2 B

-1 B

-0

1 0 0 0 1 1 0 LSR (Receiver Line Status Register)

2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)

3 0 0 0 1 0 0 RXRDY (Received Data Ready)

4 0 0 0 0 1 0 TXRDY (Transmit Ready)

5 0 0 0 0 0 0 MSR (Modem Status Register)

6 0 1 0 0 0 0 RXRDY (Received Xon, Xoff or Special character)

7 1 0 0 0 0 0 CTS#, RTS# change of state

- 0 0 0 0 0 1 None (default) or Wakeup interrupt

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.5 FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

enable the wake up interrupt. They are defined as follows:

FCR[0]: TX and RX FIFO Enable

•

Logic 0 = Disable the transm it and receive FIFO (default).

•

Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

•

Logic 0 = No receive

FIFO

reset (default)

•

Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

•

Logic 0 = No transmit FIFO reset (default).

•

Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)

•

Logic 0 = Disable the wake up interrupt (default) .

•

Logic 1 = Enable the wake up interrupt.

Please refer to “Section 2.17.3, Wake-up Interrupt” on page 22.

FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the

FIFO did not get filled over the trigger level on last re-load. Table 9

below shows the selections. Note that the

receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to

both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

These 2 bits are used to set the trigger level for the receive FIFO. The UAR T will issue a receive interrupt when

the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.

Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last

applies to both the RX and TX side.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.6 Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 10 for parity selection summary below.

•

Logic 0 = No parity.

•

Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION

FCR B

-7 FCR B

-6 FCR B

-5 FCR

BIT

-4 R

ECEIVE

RIGGER

EVEL

RANSMIT

RIGGER

EVEL

OMPATIBILITY

11(default)

1(default)

16L580

BIT-1 BIT-0 W

ORD

LENGTH

0 0 5 (default)

0 1 6

1 0 7

1 1 8

BIT-2 W

ORD

LENGTH

TOP

BIT

LENGTH

TIME

(

))

05,6,7,8 1 (default)

1 5 1-1/2

16,7,8 2

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

•

Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

•

Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

•

LCR BIT-5 = logic 0, parity is not forced (default).

•

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive

data.

•

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive

data.

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

•

Logic 0 = No TX break condition. (default)

•

Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM/DLD) enable.

•

Logic 0 = Data registers are select ed . (d ef au lt)

•

Logic 1 = Divisor latch registers are selected.

4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

•

Logic 0 = Force DTR# output HIGH (default).

•

Logic 1 = Force DTR# output LOW.

TABLE 10: PARITY SELECTION

LCR B

-5 LCR B

-4 LCR B

-3 P

ARITY

SELECTION

X X 0 No parity

0 0 1 Odd parity

0 1 1 Even parity

1 0 1 Force parity to mark, HIGH

1 1 1 Forced parity to space, LOW

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by

EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.

•

Logic 0 = Force R TS# output HIGH (default).

•

Logic 1 = Force RTS# output LOW. It is required to start Auto RTS Flow Control.

MCR[2]: Reserved

OP1# is not available as an output pin on the M580. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

MCR[3]: INT Output Enable

Enable or disable INT outputs to become active or in three-state. This bit is also used to control the OP2#

signal during internal loopback mode.

•

Logic 0 = INT output disabled (three state) in the 16 mode (default). During internal loopback mode, OP2# is

HIGH.

•

Logic 1 = INT output enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.

MCR[4]: Internal Loopback Enable

•

Logic 0 = Disable loopback mode (default).

•

Logic 1 = Enable local loopback mode, see loopback section and Figure 15.

MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)

•

Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

•

Logic 1 = Enable Xon-Any fun ct ion . In th is mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and

the M580 is programmed to use the Xon/Xoff flow control.

MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)

•

Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)

•

Logic 1 = Enable infrared IrDA re ce ive and tr ansm it inp uts/outputs. The TX/RX ou tp ut / inpu t ar e ro ut ed t o the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output

will be LOW during idle data conditions.

MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)

•

Logic 0 = Divide by one. The input cl ock from the cr ysta l or external clock is fed dir ectly to the Programmabl e

Baud Rate Generator without further modification, i.e., divide by one (default).

•

Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

TABLE 11: INT OUTPUT MODES

MCR

-3 INT O

UTPUT

16 M

ODE

0Three-State

1Active

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.8 Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART a nd the host. If IER bit- 2 is enabled, LSR

bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an

error is in the RHR.

LSR[0]: Receive Data Ready Indicator

•

Logic 0 = No data in receive holding register or FIFO (default).

•

Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Flag

•

Logic 0 = No overrun error (default).

•

Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive s hift register is not transf erred into

the FIFO, ther ef or e th e da ta in the FIFO is not co rr up te d by the er ro r.

LSR[2]: Receive Data Parity Error Tag

•

Logic 0 = No parity error (default).

•

Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Tag

•

Logic 0 = No framing error (default).

•

Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

LSR[4]: Receive Break Tag

•

Logic 0 = No break condition (default).

•

Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame tim e). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX

input return s to the idle condition, “mark” or HIGH.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indi cator. The THR bit is set to a logic 1 when the last dat a byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrent ly with the data loading to th e transmit hold ing register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

•

Logic 0 = No FIFO error (default).

•

Logic 1 = A global indicato r for the sum of all er ror bits in the RX FIFO. At least one pari ty error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.9 Mode m Status Regist er (MSR) - Rea d On ly

This register provides the current state of the modem interface input signals. Lower four bits of this register are

used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem

changes state. These bits may be used for general purpose inputs when they are not used with modem

signals. Reading the higher four bits shows the status of the modem signals.

MSR[0]: Delta CTS# Input Flag

•

Logic 0 = No change on CTS# input (default).

•

Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

•

Logic 0 = No change on DSR# input (default).

•

Logic 1 = The DSR# in put has ch anged state since the last time it was monitor ed. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

•

Logic 0 = No change on RI# input (default).

•

Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

•

Logic 0 = No change on CD# input (default).

•

Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto

CTS (EFR bit-7). Auto CTS Flow Control allows starting and stopping of local data transmissions based on the

modem CTS# signal. A HIGH on the CTS# p in will stop UAR T tran smitter as soon as the cur rent charact er has

finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of

the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The

CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complemen t of th e DSR# input. In the loopb ack mode, t his bit is equival en t to th e DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the mo dem interf ace is

not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopbac k mode this bit is equivalent to bit-2 in the

MCR register. Th e RI# inpu t ma y be use d as a gen er al pu rpo s e inpu t whe n th e mo de m interfa ce is not us ed .

MSR[7]: CD Input Status

Normally this bit is the comp lement of the CD# input. In th e loopback mode this bit is equivalent to bit-3 in the

MCR register. Th e CD# inpu t ma y be use d as a gen er al pu rpose input when the mo de m inte rfa ce is not us ed .

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.10 Modem Status Register (MSR) - Write Only

This register provides the advanced features of XR16M580. Lower four bits of this register are reserved.

Writing to the higher four bits enables additional functions.

MSR[3:0]: Reserved

MSR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)

•

Logic 0 = Enable Transmitter (default).

•

Logic 1 = Disable Transmitter.

MSR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)

•

Logic 0 = Enable Receiver (default).

•

Logic 1 = Disable Receiver.

MSR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)

For the 9-bit mode information, See ”Section 2. 15, Normal Multidrop Mode” on page 19.

•

Logic 0 = Normal 8-bit mode (default).

•

Logic 1 = Enable 9-bit or Multidrop mode.

MSR[7]: Enable/Disable fast IR mode (Requires EFR[4] = 1)

The M580 supports the new fast IR transmission with data rate up to 1.152 Mbps.

•

Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).

•

Logic 1 = IrDA version 1.1, 1 /4 pulse ratio, d ata rat e up to 1.152 Mbp s. For m ore IR mode informatio n, please

See ”Section 2. 16 , In fra red Mo de ” on page 20.

4.11 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off- on cycle.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.12 Enhanced Mode Select Register (EMSR) - Write-only

This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.

EMSR[1:0]: Receive/Transmit FIFO Level Count

When Scratchpad Swap (FCTR[6]) is asser ted, EMSR bits 1-0 controls wh at mode the FIFO L evel Counter is

operating in.

During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been

asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO

Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and

so on and so forth.

EMSR[2]: Send TX Immediat ely

•

Logic 0 = Do not send TX immediately (default).

•

Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the

TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only

1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If

more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.

EMSR[3]: Invert RTS in RS485 mode

•

Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).

•

Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.

EMSR[5:4]: Reserved

EMSR[6]: LSR Interrupt Mode

•

Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character

with the error is in the RHR.

•

Logic 1 = LSR Int errupt Immed iate. LSR bit s 2 , 3, and 4 will g enerat e an inte rrupt as soon a s the cha racter is

received into the FIFO.

EMSR[7]: Xoff/Special character Interrupt Mode Select

This bit selects how the Xoff and Special character interrupt is clear ed . The XON interr up t can on ly be cleare d

by reading the IS R register.

•

Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.

Special character interrupt is cleared by either reading ISR register or when next character is received.

(default).

•

Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.

TABLE 12: SCRATCHPAD SWAP SELECTION

FCTR[6] EMSR[1] EMSR[0] Scratchpad is

0 X X Scratchpad

1 X 0 RX FIFO Level Counter Mode

1 0 1 TX FIFO Level Counter Mode

1 1 1 Alternate RX/TX FIFO Counter Mode

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.13 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write

These registers make-up the value of the baud rate divisor. The M580 has different DLL, DLM and DLD for

transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with

different rate. The M580 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling

frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit

divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be

enabled via EFR bit-4 before it can be accessed. See Table 13 below and See ”Section 2.7, Programmable

Baud Rate Generator with Fractional Divisor” on page 12.

DLD[5:4]: Sampling Rate Select

These bit s se lect the d at a sampl ing r ate. By de fault, t he dat a sampling rate is 16X. Th e maximum dat a ra te will

double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.

DLD[6]: Independent BRG enable

•

Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).

•

Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting

which baud rate generator to configure.

DLD[7]: BRG select

When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DL D[5 :0] will be for t he Transmit

Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator

used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and

DLD[5:0]. .

TABLE 13: SAMPLING RATE SELECT

DLD[5] DLD[4] S

AMPLING

ATE

0 0 16X

0 1 8X

1 X 4X

TABLE 14: BRG SELECT

DLD[7] DLD[6] BRG

0 0 Transmitter and Receiver uses same BRG.

Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.

0 1 Transmitter and Receiver uses different BRGs.

Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.

1 1 Transmitter and Receiver uses different BRGs.

Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.

1 0 Transmitter and Receiver uses same BRG.

Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.14 RX/TX FIFO Level Count Register (FC) - Read-Only

This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also

accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad

FC[7:0]: RX/TX FIFO Level Count

Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter

FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting

or receiving data.

4.15 Feature Control Register (FCTR) - Read/ Write

FCTR[1:0]: Reserved

FCTR[2]: IrDa RX Inversion

•

Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).

•

Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).

FCTR[3]: Auto RS-485 Direction Control

•

Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register

becomes empty and transmit shift register is shifting data out .

•

Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its

output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.

Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The

RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,

RTS# behavior can be inverted by setting EMSR[3] = 1.

FCTR[5:4]: Reserved

FCTR[6]: Scratchpad Swap

•

Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.

•

Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of

characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced

Mode Select Register is selected when it is written into.

FCTR[7]: Programmable Trigger Register Select

•

Logic 0 = Register FC selected for RX.

•

Logic 1 = Register FC selected for TX.

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.16 Enhanced Feature Register (EFR) - Read/Write

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff 1 and Xof f2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

EFR[4]: Enhanced Function Bits Enable

Enhanced function cont r ol bit . This b i t en ables I ER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, and DLD

to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.

This feature pre vent s le gacy software from altering or overwriting the enhance d fun ctions on ce set. Normally, it

is recommended to leave it enabled, logic 1.

•

Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-

7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 3-5,

and MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).

•

Logic 1 = Enables the EFR[3:0] register bits to be modified by the user.

TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS

EFR

BIT

-3

ONT

-3 EFR

BIT

-2

ONT

-2 EFR

BIT

-1

ONT

-1 EFR

BIT

-0

ONT

-0 T

RANSMIT

AND

ECEIVE

OFTWARE

LOW

ONTROL

0 0 0 0 No TX and RX flow control (default and reset)

0 0 X X No transmit flow control

1 0 X X Transmit Xon1, Xoff1

0 1 X X Transmit Xon2, Xoff2

1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 No receive flow control

X X 1 0 Receiver compares Xon1, Xoff1

X X 0 1 Receiver compares Xon2, Xoff2

1 0 1 1 Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0 1 1 1 Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0 0 1 1 No transmit flo w control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

EFR[5]: Special Character Detect Enable

•

Logic 0 = Special Character Detect Disabled (default).

•

Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an in terrup t will be genera ted wh en the re ceive FIF O is filled to the select ed tri gger level and R TS de-

asserts HIGH at the ne xt upper trigger level/hysteresis level. RTS# will retur n LOW when FIFO dat a falls be low

the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the auto RTS

can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.

•

Logic 0 = Automatic RTS flow control is disabled (default).

•

Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

•

Logic 0 = Automatic CTS flow control is disabled (default).

•

Logic 1 = En able Automa tic CTS flow control. Data trans mission stops when CT S# input de -asserts to logic

1. Data transmission resumes when CTS# returns to a logic 0.

4.17 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These reg isters are used as th e programmable software f low control characte rs xoff1, xoff2, xon1, an d xon2.

For more det a ils, se e Table 5. The xoff 2 is also used as aut o addres s dete ct register when the aut o 9-bit mod e

enabled. See ”Section 2.15.1, Auto Address Detection” on page 20.

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

TABLE 16: UART RESET CONDITIONS

REGISTERS RESET STATE

DLM, DLL

(Both TX and RX) DLM = 0x00 and DLL = 0x01. Only resets to these val-

ues during a power up. They do not reset when the

Reset Pin is asserted.

DLD Bits 7-0 = 0x00

RHR Bits 7- 0 = 0xXX

THR Bits 7-0 = 0xXX

IER Bits 7- 0 = 0x0 0

FCR Bits 7-0 = 0x00

ISR Bits 7- 0 = 0x0 1

LCR Bits 7-0 = 0x00

MCR Bits 7- 0 = 0x0 0

LSR Bits 7- 0 = 0x6 0

MSR Bits 7-0 =0xX0 (Read-only)

Bits 7-4 = 0000 (Write-only)

SPR Bits 7- 0 = 0xF F

EMSR Bits 7- 0 = 0x0 0

FC Bits 7- 0 = 0x0 0

FCTR Bits 7 - 0 = 0x0 0

EFR Bits 7- 0 = 0x0 0

XON1 Bits 7- 0 = 0x0 0

XON2 Bits 7- 0 = 0x0 0

XOFF1 Bits 7- 0 = 0x0 0

XOFF2 Bits 7- 0 = 0x0 0

I/O SIGNALS RESET STATE

TX HIGH

RTS# HIGH

DTR# HIGH

INT

(16 Mode) Three-State Condition

IRQ#

(68 Mode) HIGH

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

Test 1: The followin g inputs remain steady at VCC or GND state to minimize Sl eep current: A0-A2, D0-D7, IOR#, IOW#,

CS#. Also, RX input must idle at HIGH while asleep.

For Power-Save, the U ART internally isolates all of these inputs (except the modem inputs, 16/68# and Reset pins) there -

fore eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWER-SAVE FEATURE” ON

ABSOLUTE MAXIMUM RATINGS

Power Supply Range 3.6 Volt s

Voltage at Any Pin GND-0.3 V to 3.6 V

Operating Temperature -40

to +85

Storage Temperature -65

to +150

Package Dissipation 500 mW

TYPICAL PACKAGE THERMAL RESISTANCE DATA

(MARGIN OF ERROR: ± 15%)

Thermal Resistance (32-QFN) theta-ja = 28

C/W, theta-jc = 10.5

C/W

Thermal Resistance (48-TQFP) theta-ja = 49

C/W, theta-jc = 10

C/W

Thermal Resistance (25-BGA) theta-ja = 166

C/W, theta-jc = 98.2

C/W

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA = -40

TO +85

C, VCC IS 1.62 TO 3.63V

YMBOL

ARAMETER

IMITS

1.8V

IMITS

2.5V

IMITS

3.3V

NITS

ONDITIONS

ILCK

Clock Input Low Level -0.3 0.3 -0.3 0.4 -0.3 0.6 V

IHCK

Clock Input High Level 1.4 VCC 2.0 VCC 2.4 VCC V

Input Low Voltage -0.3 0.2 -0.3 0.5 -0.3 0.7 V

Input High Voltage 1.4 VCC 1.8 VCC 2.0 VCC V

Output Low Voltage

0.4 0.4 0.4 V

= 6 mA

= 4 mA

= 1.5 mA

Output High Voltage

1.4 1.8 2.0 V

= -4 mA

= -2 mA

= -200 uA

Input Low Leakage Current ±15 ±15 ±15 uA

Input High Leakage Current ±15 ±15 ±15 uA

Input Pin Capacitance 555pF

Power Supply Current 1.5 22.5 mA Ext Clk = 5MHz

SLEEP/

PWRSV

Sleep / Power Save Current

(16 and 68 modes) 3 6 15 uA See Test 1

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

PAGE 22. To achieve minimu m power drain, the voltage at an y of the in puts of the M580M580 should NOT be lowe r than

its VCC supply.

AC ELECTRICAL CHARACTERISTICS

TA = -40

TO +85

C, VCC IS 1.62 TO 3.6V, 70 PF LOAD WHERE APPLICABLE

YMBOL

ARAMETER

IMITS

1.8V ± 10%

IMITS

2.5V ± 10%

IMITS

3.3V ± 10%

NIT

XTAL1 UART Crystal Frequency 24 24 24 MHz

ECLK External Clock Frequency 30 50 64 MHz

ECLK

External Clock Time Period 15 9 7 ns

Address Setup Time (16 Mode) 000ns

Address Hold Time (16 Mode) 000ns

Chip Select Width (16 Mode) 90 60 35 ns

IOR# Strobe Width (16 Mode) 90 60 35 ns

Read Cycle Delay (16 Mode) 90 60 35 ns

RDV

Data Access Time (16 Mode) 85 55 30 ns

Data Disable Time (16 Mode) 25 10 5ns

IOW# Strobe Width (16 Mode) 90 60 35 ns

Write Cycle Delay (16 Mode) 90 60 35 ns

Data Setup Time (16 Mode) 30 15 10 ns

Data Hold Time (16 Mode) 333ns

ADS

Address Setup (68 Mode) 500ns

ADH

Address Hold (68 Mode) 000ns

RWS

R/W# Setup to CS# (68 Mode) 000ns

RDA

Data Access Time (68 mode) 85 55 30 ns

RDH

Data Disable Time (68 mode) 15 15 15 ns

WDS

Write Data Setup (68 mode) 15 10 10 ns

WDH

Write Data Hold (68 Mode) 333ns

RWH

CS# De-asserted to R/W# De-

asserted (68 Mode) 333ns

CSL

CS# Strobe Width (68 Mode) 90 60 35 ns

CSD

CS# Cycle Delay (68 Mode) 90 60 35 ns

WDO

Delay From IOW# To Output 50 50 50 ns

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

MOD

Delay To Set Interrupt From MODEM

Input 50 50 50 ns

RSI

Delay To Reset Interrupt From IOR# 50 50 50 ns

SSI

Delay From Stop To Set In terrupt 1 1 1 Bclk

RRI

Delay From IOR# To Reset Interrupt 45 45 45 ns

Delay From Start To Interrupt 45 45 45 ns

INT

Delay From Initial INT Reset To

Transmit Start 824 824 824 Bclk

WRI

Delay From IOW# To Reset Interrupt 45 45 45 ns

SSR

Delay From Stop To Set RXRDY# 1 1 1 Bclk

Delay From IOR# To Rese t RXRDY# 45 45 45 ns

Delay From IOW# To Set TXRDY# 45 45 45 ns

SRT

Delay From Center of Start To Reset

TXRDY# 8 8 8 Bclk

RST

Reset Pulse Width 40 40 40 ns

Bclk Baud Clock 16X or 8X or 4X of data rate Hz

FIGURE 16. CLOCK TIMING

AC ELECTRICAL CHARACTERISTICS

TA = -40

TO +85

C, VCC IS 1.62 TO 3.6V, 70 PF LOAD WHERE APPLICABLE

YMBOL

ARAMETER

IMITS

1.8V ± 10%

IMITS

2.5V ± 10%

IMITS

3.3V ± 10%

NIT

OSC

CLK

EXTERNAL

CLOCK

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

FIGURE 17. MODEM INPUT/OUTPUT TIMING

FIGURE 18. 16 MODE (INTEL) DATA BUS READ TIMING

IOW #

IOW

RTS#

DTR#

CD#

CTS#

DSR#

INT

IOR#

RI#

WDO

MOD

RSI

MOD

Active

C hange of state C hange of state

Active Active Active

C hange of state C hange of state

C hange of state

Active Active

RDV

Valid Address Valid Address

Valid Data Valid D ata

A0-A2

CS#

IOR#

D0-D7

RDTm

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

FIGURE 19. 16 MODE (INTEL) DATA BUS WRITE TIMING

FIGURE 20. 68 MODE (MOTOROLA) DATA BUS READ TIMING

16Write

TAS

TDH

TAH

TWR

TDS

TDY

TDH

TDS

TAH

TAS TCS

Valid Address Valid Address

V a lid D a ta V a lid D a ta

A0-A2

CS#

IOW#

D0-D7

TCS

TWR

68Read

ADS

RDH

ADH

CSL

RDA

CSD

RWS

Valid Address Valid Address

Valid Data

A0-A2

CS#

R/W#

D0-D7

RWH

V alid Data

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

FIGURE 21. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]

68Write

ADS

ADH

CSL

WDS

CSD

RWS

Valid Address Valid Address

V a lid Da ta

A0-A2

CS#

R/W#

D0-D7

RWH

V a lid Da ta

WDH

RXRDY#

IOR#

INT

D0:D7

Start

Bit D0:D7

Stop

Bit D0:D7

SSR

1 Byte

in RHR

Active

Data

Ready

Active

Data

Ready

Active

Data

Ready

1 Byte

in RHR 1 Byte

in RHR

SSR

RXNFM

SSR

(Reading data

out of RHR)

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]

FIGURE 24. RECEIVE READY & INTERRUPT TIMING [FIFO MODE]

TXRDY#

IOW#

INT*

D0:D7

Start

Bit D0:D7

Stop

Bit D0:D7

TXNonFIFO

WRI

SRT

*INT is cleared when the ISR is read or when data is loaded into the THR.

ISR is read ISR is readISR is read

(Loading data

into THR)

(Unloading)

IER[1]

enabled

RXRDY#

IOR#

INT

D0:D7

SSR

RXINTDMA#

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RX FIFO drops

below RX

Trigger L evel

FIFO

Empties

First Byte is

Received in

RX FIFO

D0:D7

Start

Bit

Stop

Bit

RRI

SSI

(Reading data out

of RX FIFO)

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE]

TXRDY#

IOW#

INT*

TXDMA#

D0:D7

Start

Bit Stop

Bit

WRI

(Unloading)

(Loading d ata

into FIFO)

Last Data Byte

Transmitted

TX FIFO fills up

to trigger level TX FIFO drops

below trigger level

Data in

TX FIFO

Empty

SRT

TX FIFO

Empty

ISR is read

IER[1]

enabled

ISR is read

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9

)

Note: The control dimension is in millimeter.

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A0.031 0.039 0.80 1.00

A1 0.000 0.002 0.00 0.05

A3 0.006 0.010 0.15 0.25

D0.193 0.201 4.90 5.10

D2 0.138 0.150 3.50 3.80

b0.007 0.012 0.18 0.30

e0.0197 BSC 0.50 BSC

L0.012 0.020 0.35 0.45

k0.008 -0.20 -

Note: the actual center pad

is metallic and the size (D 2)

is device-dependent with a

typical tolerance of 0.3mm

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1

)

Note: The control dimension is the millimeter column

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A0.039 0.047 1.00 1.20

A1 0.002 0.006 0.05 0.15

A2 0.037 0.041 0.95 1.05

B0.007 0.011 0.17 0.27

C0.004 0.008 0.09 0.20

D0.346 0.362 8.80 9.20

D1 0.272 0.280 6.90 7.10

e0.020 BSC 0.50 BSC

L0.018 0.030 0.45 0.75

a0× 7× 0× 7×

36 25

Seating

Plane

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

PACKAGE DIMENSIONS (25 PIN BGA - 3 X 3 X 0.8

)

Note: The control dimension is the millimeter column

INCHES MILLIMETERS

SYMBOL MIN MAX MIN MAX

A0.028 0.031 0.70 0.80

A1 0.005 0.007 0.13 0.19

A2 0.022 0.024 0.57 0.61

D0.114 0.122 2.90 3.10

D1 0.079 BSC 2.00 BSC

b0.008 0.012 0.20 0.30

e0.020 BSC 0.50 BSC

A1 corner

13245

AA2

(A1 corner feature is mfger option)

Plane

Seating

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuit s described he rein, conveys n o license unde r any p atent o r other ri ght, and makes no represent ati on that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user ’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Prod ucts are not authorized for u se in such a pp lica tions u nless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected un de r the circumstances.

Datasheet Septembe r 2008.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

REVISION HISTORY

ATE

EVISION

ESCRIPTION

September 2008 Rev 1.0.0 Final Datasheet.

XR16M580

REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

GENERAL DESCRIPTION................................................................................................ 1

FEATURES................................................................................................................................................... . 1

APPLICATIONS ............................................................................................................................................. . 1

IGURE

1. XR16M580 B

LOCK

IAGRAM

.......................................................................................................................................... 1

IGURE

2. P

SSIGNMENT

32-

QFN

AND

48-

TQFP P

ACKAGES

AND

68 M

ODE

............................................. 2

IGURE

3. P

SSIGNMENT

25-

BGA P

ACKAGE

........................................................................................................... 3

ORDERING INFORMATION............................................................................................................................... 3

PIN DESCRIPTIONS ........................................................................................................ 4

1.0 PRODUCT DESCRIPTION .................................................................................................................. ... . 6

2.0 FUNCTIONAL DESCR IPTIO NS ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...... ... .... ... ... ... . 7

2.1 CPU INTERFACE ................................................................................................................................................ 7

IGURE

4. XR16M580 T

YPICAL

NTEL

OTOROLA

ATA

NTERCONNECTIONS

............................................................................ 7

2.2 SERIAL INTERFACE........................................................................................................................................... 8

IGURE

5. XR16M580 T

YPICAL

ERIAL

NTERFACE

ONNECTIONS

................................................................................................... 8

IGURE

6. XR16M580 T

YPICAL

ERIAL

NTERFACE

ONNECTIONS

................................................................................................... 9

2.3 DEVICE RESET................................................................................................................................................. 10

2.4 INTERNAL REGISTERS.................................................................................................................................... 10

2.5 INT OUPUT........................................................................................................................................................ 10

ABLE

1: INT P

PERATION

FOR

RANSMITTER

..................................................................................... ...................................... 10

ABLE

2: INT P

PERATION

FOR

ECEIVER

................................................................................................................................ 10

2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 11

IGURE

7. T

YPICAL

RYSTAL

ONNECTIONS

.................................................................................................................................. 11

2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 12

2.7.1 INDEPENDENT TX/RX BRG........................................................... .............................................................................. 12

IGURE

8. B

AUD

ATE

ENERATOR

............................................................................................................................................... 13

ABLE

3: T

YPICAL

DATA

RATES

WITH

24 MH

CRYSTAL

EXTERNAL

CLOCK

16X S

AMPLING

................................................... 13

2.8 TRANSMITTER.................................................................................................................................................. 14

2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 14

2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................... 14

IGURE

9. T

RANSMITTER

PERATION

NON

-FIFO M

ODE

.............................................................................................................. 14

2.8.3 TRANSMITTER OPERATION IN FIFO MODE............................................................................................................. 15

IGURE

10. T

RANSMITTER

PERATION

FIFO

AND

LOW

ONTROL

ODE

................................................................................... 15

2.9 RECEIVER......................................................................................................................................................... 15

2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 15

IGURE

11. R

ECEIVER

PERATION

NON

-FIFO M

ODE

.................................................................................................................. 16

IGURE

12. R

ECEIVER

PERATION

FIFO

AND

UTO

RTS F

LOW

ONTROL

ODE

....................................................................... 16

2.10 AUTO RTS (HARDWARE) FLOW CONTROL................................................................................................ 17

2.11 AUTO RTS HYSTERESIS ............................................................................................................................... 17

ABLE

4: A

UTO

RTS (H

ARDWARE

) F

LOW

ONTROL

....................................................................................................... ................. 17

2.12 AUTO CTS FLOW CONTROL......................................................................................................................... 17

IGURE

13. A

UTO

RTS

AND

CTS F

LOW

ONTROL

PERATION

....................................................................................................... 18

2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 19

ABLE

5: A

UTO

OFF

OFTWARE

) F

LOW

ONTROL

............................................................................................................... 19

2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 19

2.15 NORMAL MULTIDROP MODE........................................................................................................................ 19

2.15.1 AUTO ADDRESS DETECTION .................................................................................................................................. 20

2.16 INFRARED MODE........................................................................................................................................... 20

IGURE

14. I

NFRARED

RANSMIT

ATA

NCODING

AND

ECEIVE

ATA

ECODING

.......................................................................... 21

2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWER-SAVE FEATURE...................................................... 21

2.17.1 SLEEP MODE ............................................................................................................................................................. 21

2.17.2 POWER-SAVE FEATURE .......................................................................................................................................... 22

2.17.3 WAKE-UP INTERRUPT ........................................... ................................................................................................... 22

2.18 INTERNAL LOOPBACK................................................................................................................................. 23

IGURE

15. I

NTERNAL

OOPBACK

................................................................................................................................................... 23

3.0 UART INTERNAL REGISTERS.... ......................................................................................................... 24

ABLE

6: UART INTERNAL REGISTERS ........................................................................ .......................................................... 24

ABLE

7: INTERNAL REGISTERS DESCRIPTION. S

HADED

BITS

ARE

ENABLED

WHEN

EFR B

-4=1 ......................................... 25

4.0 INTERNAL REGISTER DESCRIPTIONS.............................................................................................. 26

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY.................................................................................. 26

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY............................................................................... 26

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 27

XR16M580

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.0

4.3.2 IER VERSUS RECEIVE/TRANSMIT FI FO POLLED MODE OPERATION.................................................................. 27

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28

4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28

4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28

ABLE

8: I

NTERRUPT

OURCE

AND

RIORITY

EVEL

....................................................................................................................... 29

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 30

ABLE

9: T

RANSMIT

AND

ECEIVE

FIFO T

RIGGER

ABLE

AND

EVEL

ELECTION

............................................................................ 31

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31

ABLE

10: P

ARITY

SELECTION

........................................................................................................................................................ 32

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUT S CONTROL - READ/WRITE.. 32

ABLE

11: INT O

UTPUT

ODES

..................................................................................................................................................... 33

4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 34

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 35

4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 36

4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36

4.12 ENHANCED MODE SELECT REGISTER (EMSR) - WRITE-ONLY............................................................... 37

ABLE

12: S

CRATCHPAD

WAP

ELECTION

.................................................................................................................................... 37

4.13 BAUD RATE GENERATOR REGISTERS (DLL, DL M AND DLD) - READ/WRITE ....................................... 38

ABLE

13: S

AMPLING

ATE

ELECT

............................................................................................................................................... 38

ABLE

14: BRG S

ELECT

................................................................................................................................................................ 38

4.14 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 39

4.15 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE............................................................................ 39

4.16 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 40

ABLE

15: S

OFTWARE

LOW

ONTROL

UNCTIONS

........................................................................................................................ 40

4.17 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE................... 41

ABLE

16: UART RESET CONDITIONS ...................................................................................................................................... 42

ABSOLUTE MAXIMUM RATINGS.................................................................................. 43

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 43

ELECTRICAL CHARACTERISTICS............................................................................... 43

DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 43

AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 44

TA = -40O TO +85OC, VCC IS 1.62 TO 3.6V, 70 PF LOAD WHERE APPLICABLE ............................................. 44

IGURE

16. C

LOCK

IMING

............................................................................................................................................................. 45

IGURE

17. M

ODEM

NPUT

UTPUT

IMING

.................................................................................................................................... 46

IGURE

18. 16 M

ODE

NTEL

) D

ATA

EAD

IMING

................................................................................................................... 46

IGURE

19. 16 M

ODE

NTEL

) D

ATA

RITE

IMING

.................................................................................................................. 47

IGURE

20. 68 M

ODE

OTOROLA

) D

ATA

EAD

IMING

.......................................................................................................... 47

IGURE

22. R

ECEIVE

EADY

& I

NTERRUPT

IMING

-FIFO M

ODE

]............................................................................................ 48

IGURE

21. 68 M

ODE

OTOROLA

) D

ATA

RITE

IMING

......................................................................................................... 48

IGURE

23. T

RANSMIT

EADY

& I

NTERRUPT

IMING

-FIFO M

ODE

].......................................................................................... 49

IGURE

24. R

ECEIVE

EADY

& I

NTERRUPT

IMING

[FIFO M

ODE

].................................................................................................... 49

IGURE

25. T

RANSMIT

EADY

& I

NTERRUPT

IMING

[FIFO M

ODE

].................................................................................................. 50

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9

).............................................. 51

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1

)............................................... 52

PACKAGE DIMENSIONS (25 PIN BGA - 3 X 3 X 0.8

).............................................. 53

REVISION HISTORY...................................................................................................................................... 54