@ LG Semicon. Co., LTD. Description Features The GM71C4400D/DL is the new generation _ 1,048,576 Words x 4 Bit Organization dynamic RAM organized 1,048,576 x 4 bit. | * Fast Page Mode Capability GM71C4400D/DL has realized higher density, higher * Single Power Supply (5V + 10%) performance and various functions by utilizing + Fast Access Time & Cycle Time advanced CMOS process technology. The (Unit: ns) GM71C4400D/DL offers Fast Page Mode as a high speed access Mode. Multiplexed address inputs frac | teac | tec | tre permit the GM71C4400D/DL to be packaged in a GM71C4400D/DL-60 | 60 15 | 110 | 40 standard 300mil 20pin plastic SOJ, and standard 300mil 20pin plastic TSOP II. The package size provides high system bit densities and is compatible GM71C4400D/DL-80 | 80 20 | 150 | 50 with widely available automated testing and insertion equipment. System oriented features include single + Low Power power supply of 5V+10% tolerance, direct Active : 440/385/358mW (MAX) interfacing capability with high performance logic Standby : 5.5mW (CMOS level : MAX) families such as Schottky TTL. 0.55mW (L-series) *RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-series) * Battery Back Up Operation (L-series) GM71C4400D/DL-70 | 70 20 130 45 Pin Configuration 20 (26) SOJ 20 (26) TSOP II S I 2 alls PIFIFIE See2re Blololmics REVERSE TYPE (Top View) (Top View) MB 4028757 GOOS43S Sol mm@ LG Semicon. Co., LTD. Pin Description Pin Function Pin Function A0-A9 Address Inputs WE Read/Write Enable A0-A9 Refresh Address Inputs OE Output Enable Y/O1-I/04 Data Input/Data Output Vee Power (+5V) RAS Row Address Strobe Ves Ground CAS Column Address Strobe Ordering Information Type No. Access Time Package CercuRDIDLT on 20 2006 GM71C4400DJ/DLJ-80 sons GM71C4400DT/DLT-60 60ns 300 Mil, 20 (26) Pin GM71C4400DT/DLT-70 70ns Plastic TSOP II GM71C4400DT/DLT-80 Ons (Normal Type) GM71C4400DR/DLR-60 60ns 300 Mil, 20 (26) Pin GM71C4400DR/DLR-70 70ns Plastic TSOP Il GM71C4400DR/DLR-80 Ons (Reverse Type) Absolute Maximum Ratings* Symbol Parameter Rating Unit Ta Ambient Temperature under Bias 0~70 c Tsto Storage Temperature (Plastic) -55 ~ 125 c Vin/Vour Voltage on any Pin Relative to Vss -10~7.0 Vv Vec Voltage on Vec Relative to Vss -10~7.0 Vv Iour Short Circuit Output Current 50 mA Pp Power Dissipation 1.0 Ww *Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Recommended DC Operating Conditions (Ta = 0 ~ 70) Symbol Parameter Min Typ Max Unit Vcc Supply Voltage 4.5 5.0 5.5 Vv Vin Input High Voltage 2.4 - 6.5 Vv Vu Input Low Voltage -1.0 - 0.8 Vv ME 4028757 OOOS43Sb 448_@ LG Semicon. Co., LTD. DC Electrical Characteristics (Vcc = 5V+10%, Ta=0~70) Symbol Parameter Min | Max] Unit} Note Vou Output Level Output "H" Level Voltage (lour = -5mA) 24 | Veo} Vv Vor Output Level 0 04 Vv Output "L" Level Voltage (lour= 4,2mA) . Tec Operating Current 60ns - 80 Average Power Supply Operating Current (RAS, CAS, Address Cyoling: tac = trc min) 70ns * 70 mA 1,2 80ns - 65 Teco Standby Current (TTL) Power Supply Standby Current - 2 nA (RAS, CAS= Vax, Dour = High-Z) Ices RAS-Only Refresh Current 60ns - 80 Avi P Supply Current RAS-Only Refresh Mode 7oms| - | 70 | wa | 2 (RAS Cycling, CAS = Vin, tac = tac min) 80ns . 65 Too Fast Page Mode Current 60ns - 20 Average Power Supply Current Fast Page Mode 7ons| - | 70 | wA | 1,3 (RAS = Vit, CAS, Address Cycling: tec = tec min) 80ne . 65 Ices Standby Current (CMOS) - 1 mA 5 Power Supply Standby Current (RAS, CAS =Vcc-0.2V, Dour=High-Z) - 100 uA 4,5 Toes CAS-before-RAS Refresh Current 60ns - 80 (tac = tac min) 70ns - 10 wA 80ns - 65 Icer Battery Back Up Current (Standby with CBR Refresh) _ . 300 | wa | 4,5 (tko=125us, tras S lus, WE=Vin, CAS=Vin, OE, Address and Dn= Vii orVi, , Dout=High-Z) Icce Standby Current RAS = Vii CAS = Vit . 5 mA 1 Dour = Enable lig) Input Leakage Current Any Input (OVS Viv-S7V) 10 | 10] HA Toa) Output Leakage Current 10 10 yA {Dour is Disabled, 0V < VourS7V) Note: 1. Icc depends on output load condition when the device is selected. Icc{max) is specified at the output open condition. 2. Address can be changed once or less while RAS = Vu. 3. Address can be changed once or less while CAS = Vin. 4. L Series. 5. Vee-0.2V S Vir S6.5V, 0V SV. S0.2V. Me 4028757 0005437 384@tc Semicon. Co., LTD. Capacitance (Vcc = SV10%, Ta=25'C) Symbol Parameter Min Max Unit Note Cn Input Capacitance (Address) - 5 ed 1 Cr Input Capacitance (Clocks) - 7 +o 1 Cro Data Input,Output Capacitance (Data-In,Out} - 7 iF 1,2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = Vii to disable Dour. AC Characteristics (Vcc = 5V+10%, Ta=0~70C, Notes 1, 14, 15, 16) Test Conditions Input rise and fall times: Sas Input, output timing reference levels: 0.8V, 2.4V Output load : 2 TTL gate + Cz (100nF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) GM71C4400 | GM71C4400 | GM7104400 Symbol Parameter -DDL-60__ DDL 70 __} DDL-8)__| Unit | Note Min | Max] Min | Max! Min | Max tac Random Read or Write Cycle Time 110} - | 130] - | 150] - ns ter RAS Precharge Time 40} - | Sof - | co] - ns tras RAS Pulse Width 60 |10,000] 70 }10,000} 80 }10,000| ns tcas CAS Pulse Width 15 }10,000] 20 |10,000} 20 |10,000] ans taser Row Address Set-up Time O71 - Oo; - Oo; - nS tran Row Address Hold Time 10} - 10] - 10] - nS tasc Column Address Set-up Time oO] - oO] - 0] - hs tcan Column Address Hold Time 1S] - 1s} - I5ft - BS tren RAS to CAS Delay Time 20] 45 | 20] so | 20] 60 | ns 8 trap RAS to Column Address Delay Time 15} 30 | 15] 35 | 15] 40 | as 9 tesu RAS Hold Time is} - | 20] - | 20] - | as tesu CAS Hold Time 60} - | 707 - | go] - ns torr CAS to RAS Precharge Time 10} - | 10] - | to] - | aos tovp OE to Dw Delay Time 1s} - | 20] - | 20] - ns tozo OE Delay Time from Da Of - oO; - oO; - ns tozc CAS Set-up Time from Dm oO; - oO}; - Oj] - t Rise ant Fall) 3} so| 3] 50 | 3] so] om | 7 teer Refresh Period (1024 Cycles) - 16 - 16 - 16 |] ms Refresh Period (1024 Cycles) - }128] - | 128] - | 128] ms | Lseries M@ 4028757 0005438 210_@ LG Semicon. Co., LTD. Read Cycle GM71C4400 | GM7104400 | GM71C4400 Symbol Parameter DDI pon DIDI-80 Unit | Note Min | Max] Min | Max] Min | Max trac Access Time from RAS - 60 - 70 - 80 ns 2,3,17 teac Access Time from CAS - 15 - 20 - 20 ns 3, 4, 13,17 taa Access Time from Address - 30 - 35 - 40 ns 8 7 toac Access Time from OE - | 15] - | 20] - | 20] os | 3,17 tres Read Command Setup Time 0 - 0 - 0 - ns tren Read Command Hold Time to CAS 0 - 0 - 0 - ns 18 tern Read Command Hold Time to RAS 0 - 0 - 0 - ns 18 traL Column Address to RAS Lead Time 30 - 35 - 40 - ns torri Output Buffer Turn-off Time 0] 15 0] 20 0} 20] ms 6 torr? Output Buffer Turn-off Time from OF 07; 15] Of] 20] Of} 20] aos 6 tepp CAS to Dw Delay Time I] - | 20] - | 207 - ns toze OE Pulse width 15} - | 20] - | 20] - ns Write Cycle GM71C4400 | GM7104400 | GM7104400 Symbol Parameter pps DDL? PPIs Unit | Note Min | Max] Min | Max} Min | Max twes Write Command Setup Time O;} - 0 : 0 - ns 10 twen Write Command Hold Time 15 - 15 - 15 - ns twr Write Command Pulse Width 10 - 10 - 10 - nS trwe Write Command to RAS Lead Time 15 - 20 - 20 - ns tew. Write Command to CAS Lead Time 15 - 20 - 20 - ns tos Data-in Setup Time 0 - 0 : 0 - ns 11 tou Data-in Hold Time 15 - 15 - 15 - ns 11 mm 4024757 0005439 157@ LG Semicon. Co., LTD. Read- Modify-Write Cycle GM7104400 | GM71C4400 | GM71C4400 Symbol Parameter DDS DDLA70 DELS Unit | Note Min | Max] Min |] Max] Min | Max trwe Read-Modify-Write Cycle Time 150} - | 180] - | 200] - ns trwp RAS to WE Delay Time go} - | 95] - | 105] - | 28 10 tewo | CAS to WE Delay Time 35} - | 45] - | 45] - | aos 10 tawp Column Address to WE Delay Time soi - | 6o| - | 65] - | as 10 torn OE Hold Time from WE 1s} - | 20} - | 207 - | as Refresh Cycle GM71C4400 | GM71C4400 | GM71C4400 Symbol Parameter Dai | DOL _| DpL-#__| Unit | Note Min | Max | Min | Max| Min | Max tesr CAS Set-up Time (CAS-before-RAS Refresh Cycle) 107 - | w]Y - | oO} - | os tcnr CAS Hold Time (CAS-before-RAS Refresh Cycle) 1] - 7 1] - | 10] - | os trec RAS Precharge to CAS Hold Time io] - | 10] - | 10] - | os teen CAS Precharge Time in Normal Mode 10 : 10 - 10 - ns Fast Page Mode Cycle GM71C4400 | GM71C4400 | GM71C4400 Symbol Parameter _DDL-60__1 DDL70__| DDL-80_| Unit | Note Min | Max] Min | Max] Min | Max tec Fast Page Mode Cycle Time 40; - | 45] - | 50] - ns tcp Fast Page Mode CAS Precharge Time CO 10] - 10} - ns trasp Fast Page Mode RAS Pulse Width - [100,000] - [100,000] ~ | 100,000] ns 12 tacr Access Time from CAS Precharge - | 35] - | 40] - | 45 | ns [333,07 truce | RAS Hold Time from CAS Precharge 35] - | 40] - | 45] - | os terw Fast Page Mode Read-Modify-Write Cycle | 55 | - | 65] - | 70] - ns CAS Precharge to WE Delay Time tecm Fest Page Mode Read-Modify-Write Cycle 80 . 95 | - | wol - ns 10 me 4028757 DOOS44O 575 Me@ LG Semicon. Co., LTD. Test Mode Cycle GM71C4400 | GM7104400 | GM71C4400 Symbol Parameter Dpt-s0 pp Bpr-80 Unit | Note Min | Max] Min | Max} Min | Max tws Test Mode WE Setup Time Oo] - 0 - 0 - ns twi Test Mode WE Hold Time 10] - | of - | 10] - | os Counter Test Cycle GM71C4400 | GM71C4400 | GM71C4400 Symbol Parameter = DDL poe Unit | Note Min | Max] Min | Max] Min | Max terr Ode Time in Counter Test 4o| - 40 . | 40 . ns Notes: 1. AC Measurements assume tr = 5ns. 2. Assumes that trco Strcp(max) and trap Strap(max). If tcp or tran is greater than the maximum recommended value shown in this table, trac exceeds the value shown. 3. Measured with a load circuit equivalent to 2TTL loads and 100pF. 4. Assumes that trcp = tecp(max) and trap <trap(max). 5 . Assumes that trcp Strcn(max) and tran = trap(max). 6. torr(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. transition times are measured between Vin and Vin. - Vin(min) and Vit(max) are reference levels for measuring timing of input signals. Also, - Operation with the trcp(max) limit insures that trac(max) can be met, trcp(max) is specified as a reference point only; if trcp is greater than the specified trcp(max) limit, then access time is controlled exclusively by tcac. . Operation with the tran(max) limit insures that trac(max) can be met, trap(max) is specified as a reference point only; if trap is greater than the specified tran(max) limit, then access time is controlled exclusively by taa. WM 4028757 0005441 405@ LG Semicon. Co., LTD. 10. 11. 12. 13. 14. 15. 16. 17. twes, trwp, tcwp tcew and tawn are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs =twcs(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if trwp=tawp{min), tewo=tewo(min), tawp = tawn(min) and tcrw=tcew(min), the cycle is a read- modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or a read modify write cycle. trasp defines RAS pulse width in fast page mode cycles. Access time is determined by the longer of tas or tcac or tacr. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or "CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. In delayed write or read-modify-write cycles, OF must disable output buffer prior to applying data to the device. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - CAO. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of two test bits do not accord, the condition of the output data is low level. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS-before-RAS refresh cycle. In a test mode read cycle, the value of trac, taa, tcac, toac and tacr is delayed for 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. MM 4028757 OOOS44e 74, me@ LG Semicon. Co., LTD. Timing Waveforms tec > Le tras - ter RAS K "x tesa el i tore le trep ele tesy tr s-le lg_{cAs____ CAS y g_fRAD___ gt fay 2 8 tran 9tAsc tcan ADDRESS ROW t COLUMN XXX Y XN x ) xs x RON O YN OK CX trey tres : trcw 1 vs ta RRR High-Z f Dout sh Dour - trac A torr2 toze RRR High-Z XXXKXKRKY PM RRR ORS aX XS OS tozo toac ; topp . RRR EKKO SEER oF RY Ue XY RK RXX ae! Se WK x BK FIGURE 1. READ CYCLE M 4028757 0005443 bahle tre | tras tre _ TY RAS N Kk tesy tr ~s}1e = trcp tcrp CAS ADDRESS RKC twes twcn LA AA AAAAAAAAA LASVLA ISR AAARAAASLAS mK IKK KIRIN) FE RE ERK i t tos B tou D C O) De KKK KKK KKK High-Z*** Dout + et : Don't oare ** OE : Don't care *** twos 2 twcs (min) FIGURE 2. EARLY WRITE CYCLE Me 402875? OOOS444y S14 \OADDRESS DIN Dout XXX XK XK xXXXX SII 6505000 RXR tozo LALA AAS OCR KARKM XK A? OKKRXKK trwi twp FORK K KR KKKKKKKX DRS KIKI II RRO) +a/ INVALID OUTPUT torr KNX KKK KKK KKK) eK) 0.054" KKK * Re : Don't care ** Invalid Dour comes out, when OE is low level. FIGURE 3. DELAYED WRITE CYCLE we 4028757 COOS44S 450 \\_@ LG Semicon. Co., LTD. ADDRESS Din Dout tr tawc le tras oXKK A KKK WY OY teas LR KKK KIN OX KK terp KRY XXX? XX WYK QOL Re XXX YY) QOOQKY XXX OXOKXK KKXK XK) O () KKK XK) FLAS SVASLS ALISA ORI XX MXXA i XM * Re : Don't care FIGURE 4. READ MODIFY WRITE CYCLE Mm 40ea757 OOOS4Y46 357 Me la@ LG Semicon. Co., LTD. tre [has _ tap "| RAS tr tcrp a CAS () () is KKK KKKKK KK) OOOOKOOCICKIOK IOI IID APPRESS ORK ERK High-Z Dovut * OE,WE : Don't care FIGURE 5. RAS ONLY REFRESH CYCLE ** Refresh address : AO~A9 RAS CAS APP BESS ORK IKK III IKI torr High-Z Dout my atiD iy ay TY ry | * RXXXX : Don't care KAAKA ** WE: Vin FIGURE 6. CAS BEFORE RAS REFRESH CYCLE MM 4028757 OO05447? 223_@ LG Semicon. Co., LTD. tre trc L tre RAS Cas ADDRESS RRR HRN WE Dout Fars .Valaval, i . Dm OREN RK HighzZ | R LDELALLLA tcpp topp TKK KKK KKK RRR) FIGURE 7. HIDDEN REFRESH CYCLE ME 4028757 COOS44a 167 \4tran al MN N tern tacn | treu tozc tepp teop Fr i g : torr: is AXK v OOK * : " XXX Don't care FIGURE 8 FAST PAGE MODE READ CYCLE Me 4026757? OOOS449 OTb Meaa CAS ADDRESS az OXxxKXxK XK KX) XxxKK KX PRR IIS aalatee High-Z Dovut FIGURE 9. FAST PAGE MODE EARLY WRITE CYCLE M@ 40286757 GCOOS4SO 816 Mm \Le@tc Semicon. Co., LTD. ADDRESS Din trasp tre h. | tr tee tcp tcrr >| tesy ot I< tec . tasx tecp teas tcas lg__tcas_ trap taser | tasc . tasc a fasc L tray tcan tean AKA A ROW COLUMN 1 COLUMN 2 cotumnn J XS ORE KE a a PENNS N tew. tcw. tew. > tres tres tres fe noel twe twe twe tos tos tos tox tox H Dwi Div 2 DaN High-Z topp a torn -b| + RRR : Don't care FIGURE 10. FAST PAGE MODE DELAYED WRITE CYCLE Me 402875? OOOS4S1 754 "]_@ LG Semicon. Co., LTD. tRASP trije M. tec ter tee tcrp = CAS fran tace tasc tran tcaR tase i tasc " cS () xKXKX) Y= q (xX) L~XX XX KX ee IY OM PRR PRR PRR icy tres Ltt Me a twr tres Oy tace ty eo tox Z| xX xX XxX x] D KRY 2; trac tpzo foac tor toac Dow {ex toFr2 | tom tpz0 ; topp > YXXX \/ i C BERK Y c / Me 402875? OO0545e 910 FIGURE 11. FAST PAGE MODE READ MODIFY WRITE CYCLE WS@tc Semicon. Co., LTD. Set Cycle*** Test Mode Cyole Reset Cycle*,*** RAS CAS aN =e RD * CBR or RAS-only refresh ot : Don't care *** Address, DIN, OE: Don't oare FIGURE 12. TEST MODE CYCLE Le ter RAS v sere Y ,.. XY tws __ KKK KKXK KKK KKK KKK KKK KIKI IKK U7 YF KORO REXXAR KR KRKN APPRESS RRR RK torr High-Z DoutT INVALID Dour * RRR : Don't oare FIGURE 13. TEST MODE SET CYCLE \ ME 4028757 0005453 527 a@ LG Semicon. Co., LTD. Test Mode Reset Cycle trc ter tras tr, RAS _ tnec tcsr tere, tear - tr TRA os " Ry tws we OX COO DORA ICN SKY KR KKK KER RN KKK KKK KKK IK KKK KKK KK KKK KKK KKK HK NHK KKK MORES KIRIN OFF] Dour INVALID High-Z Dour RG on FIGURE 14. CAS BEFORE RAS REFRESH CYCLE < tec ter RAS CAS XK XX XXX V4 ~X) [now KKK KKK KKK KK KKKKKKK xX) APRESS RY, BO PREG I 5 High-Z Dout NOOOLK| * O XXX) ** Refresh Address : A0-A9 (AX0-AX9) 4** WE : Don't care : Don't care FIGURE 15. RAS ONLY REFRESH CYCLE MB 402875? OOOS4S4 4b3 aDtec Is tras trp y Ras N teal trs le ' H torr teas XM KX KK KKK K KKK) () xXx) (xX X xxx APPRESS RRR RICO KKK tern tw tres eT tex | WE PPPOE RF RR WE x) KY tozc > tcpp XXKKXKXKYKXK xXx \/ xX3 High-Z DI OSG _ \/ KOK KXKKKK KKKKYRKKK KKK KKK KY) FE RRR RARE AROS . > High-Z I Dour Dour * RRR : Don't care FIGURE 16. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (READ) MB 4028757? OOOS4SS 3TT aAS tean KKK KKK III KKK KKK KIKI KN APPRESS RRR RK ROK COLUMN RIK twa twen KKK KKM XXXXX \/ XXX WE KKK KKK KY Nellore YX XXX XXXXKKY XK XKKX) + KKXXKK XX KKK) PRIS OH KR BE R000) IUCR POKER III IIE f\ High-Z * ou : Don't care FIGURE 17. CAS BEFORE RAS REFRESH COUNTER CHECK CYCLE (WRITE) M8 4024757 O0054S6b 236 AX_@ LG Semicon. Co., LTD. Package Dimension Unit: Inches (mm) 20 (26) SOJ 0.025(0.63) MIN 0.039(1.00) MAX | f Ooo Orr LE a Sb octo20 0.661(16.80) MIN 0.08501 Le 661(16.80) 0.103(2.61) MAX 275(6.99) MAX 0.330(8.38) MIN 0.340(8.64) MAX 0.305(7.75) MAX 0 0.669(17.00) MAX 0.128(3.25) MIN , 0.148(3.76) MAX 0.050(1.2 rl __ ,.0.026(0.66) MIN TYP 0.036(0.91) MAX 0.015(0.38) MIN 0.021(0. 53) MAX 20 (26) TSOP (TYPE. 11) NOOO HnnonM OO OnOnnn 6 ale WUUULU UOUOUO UYUUUL UWOUOO NORMAL TYPE REVERSE TYPE 0.355(9.02) MIN 0.371(9.42) MAX o-8* 0.012(0.30) MIN 0.028(0.70) MAX 0.667(16.94) MIN 2 i" 0.683(17.34) MAX F 0.041(1.03) MIN : 0,048(1.23) MAX 18 012(0. .O50(1. 0.001(0.03) MIN 0.020(0.50) MAX TYP 18 ~8 0.009(0.23) MAX 0.009(0.22) MAX AD Me 402675? 000545? 172