REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3307
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
High Accuracy anyCAP™
100 mA Low Dropout Linear Regulator
FUNCTIONAL BLOCK DIAGRAM
THERMAL
PROTECTION
DRIVER G
M
CC
IN
ADP3307
OUT
R1
R2
NR
GND
Q1
ERR
SD
BANDGAP
REF
Q2
V
OUT
= +3.3V
V
IN
+
–
ADP3307-3.3
NR
OUT
ERR
ON
OFF
SD GND
R1
330kV
IN
E
OUT
C2
0.47mF
C1
0.47mF
Figure 1. Typical Application Circuit
FEATURES
0.8% Accuracy Over Line and Load Regulations @ +258C
Ultralow Dropout Voltage: 120 mV Typical @ 100 mA
Requires only CO = 0.47 mF for Stability
anyCAP = Stable with All Types of Output Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Dropout Detector
Low Shutdown Current: 1 mA
3.0 V to 12 V Supply Range
–208C to +858C Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23-6 (RT-6) Package
Excellent Line and Load Regulations
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulator
Bar Code Scanners
Camcorders, Cameras
GENERAL DESCRIPTION
The ADP3307 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3307 stands
out from the conventional LDOs with a novel architecture and
an enhanced process. Its patented design requires only a 0.47 µF
output capacitor for stability. This device is stable with any type
of capacitor regardless of its ESR (Equivalent Series Resistance)
value, including ceramic types (MLCC) for space restricted
applications. The ADP3307 achieves exceptional accuracy of
±0.8% at room temperature and ±1.4% overall accuracy over
temperature, line and load regulations. The dropout voltage of
the ADP3307 is only 120 mV (typical) at 100 mA.
The ADP3307 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 100 mA.
It features an error flag that signals when the device is about to
lose regulation or when the short circuit or thermal overload
protection is activated. Other features include shutdown and
optional noise reduction capabilities. The ADP330x anyCAP
LDO family offers a wide range of output voltages and output
current levels from 50 mA to 300 mA:
ADP3300 (50 mA, SOT-6)
ADP3307 (100 mA, SOT)
ADP3301 (100 mA, SO-8)
ADP3302 (100 mA, Dual Output)
ADP3303 (200 mA)
ADP3306 (300 mA)
anyCAP is a trademark of Analog Devices, Inc.
–2– REV. 0
ADP3307–SPECIFICATIONS
(@ TA = –208C to +858C, VIN = 7 V, CIN = 0.47 mF, COUT = 0.47 mF, unless
otherwise noted)1 The following specifications apply to all voltage options.
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE ACCURACY V
OUT
V
IN
= V
OUTNOM
+ 0.3 V to 12 V
I
L
= 0.1 mA to 100 mA
T
A
= +25°C –0.8 +0.8 %
V
IN
= V
OUTNOM
+ 0.3 V to 12 V
I
L
= 0.1 mA to 100 mA –1.4 +1.4 %
LINE REGULATION V
IN
= V
OUTNOM
+ 0.3 V to 12 V
T
A
= +25°C 0.02 mV/V
LOAD REGULATION I
L
= 0.1 mA to 100 mA
T
A
= +25°C 0.06 mV/mA
GROUND CURRENT I
GND
I
L
= 100 mA 0.76 2.0 mA
I
L
= 0.1 mA 0.19 0.3 mA
GROUND CURRENT IN DROPOUT I
GND
V
IN
= 2.5 V
I
L
= 0.1 mA 0.6 1.2 mA
DROPOUT VOLTAGE V
DROP
V
OUT
= 98% of V
OUTNOM
I
L
= 100 mA 0.126 0.22 V
I
L
= 10 mA 0.025 0.07 V
I
L
= 1 mA 0.004 0.015 V
SHUTDOWN THRESHOLD V
THSD
ON 2.0 0.75 V
OFF 0.75 0.3 V
SHUTDOWN PIN INPUT CURRENT I
SDIN
0 < V
SD
, < 5 V 1 µA
5 < V
SD
≤ 12 V @ V
IN
= 12 V 22 µA
GROUND CURRENT IN SHUTDOWN I
Q
V
SD
= 0 V, V
IN
= 12 V
MODE T
A
= +25°C 0.005 1 µA
V
SD
= 0 V, V
IN
= 12 V
T
A
= +85°C 0.01 3 µA
OUTPUT CURRENT IN SHUTDOWN I
OSD
T
A
= +25°C @ V
IN
= 12 V 2 µA
MODE T
A
= +85°C @ V
IN
= 12 V 4 µA
ERROR PIN OUTPUT LEAKAGE I
EL
V
EO
= 5 V 13 µA
ERROR PIN OUTPUT
“LOW” VOLTAGE V
EOL
I
SINK
= 400 µA 0.12 0.3 V
PEAK LOAD CURRENT I
LDPK
V
IN
= V
OUTNOM
+ 1 V 170 mA
OUTPUT NOISE @ 3.3 V OUTPUT V
NOISE
f = 10 Hz–100 kHz
C
NR
= 0 100 µV
rms
C
NR
= 10 nF, C
L
= 10 µF30µV rms
NOTES
1
Ambient temperature of +85 °C corresponds to a junction temperature of 125°C under typical full load test conditions.
Specifications subject to change without notice.
∆V
O
∆V
IN
∆V
O
∆I
L
ADP3307
–3–REV. 0
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Error Flag Output Voltage . . . . . . . . . . . . . . . –0.3 V to +16 V
Noise Bypass Pin Voltage . . . . . . . . . . . . . . . . –0.3 V to +5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . .Internally Limited
Operating Ambient Temperature Range . . . –55°C to +125°C
Operating Junction Temperature Range . . . –55°C to +125°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 s) . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Output Package Marking
Model Voltage Option Code
ADP3307ART-2.7 2.7 V RT-6 LTC
ADP3307ART-3 3.0 V RT-6 LUC
ADP3307ART-3.2 3.2 V RT-6 LVC
ADP3307ART-3.3 3.3 V RT-6 LWC
Contact the factory for the availability of other output voltage options.
Other Members of anyCAP Family
1
Output Package
Model Current Options
2
Comments
ADP3300 50 mA SOT-23-6 High Accuracy
ADP3301 100 mA SO-8 High Accuracy
ADP3302 100 mA SO-8 Dual Output
ADP3303 200 mA SO-8 High Accuracy
ADP3306 300 mA SO-8, TSSOP-14 High Accuracy,
High Current
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline, SOT-23 = Surface Mount, TSSOP = Thin Shrink Small
Outline.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3307 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin Name Function
1 GND Ground Pin.
2 NR Noise Reduction Pin. Used for further reduc-
tion of the output noise. (See text for details.)
No connection if not used.
3SD Active Low Shutdown Pin. Connect to ground
to disable the regulator output. When shut-
down is not used, this pin should be con-
nected to the input pin.
4 OUT Output of the Regulator, fixed 2.7 V, 3.0 V ,
3.2 V or 3.3 V output voltage. Bypass to
ground with a 0.47 µF or larger capacitor.
5 IN Regulator Input.
6ERR Open Collector Output that goes low to indi-
cate that the output is about to go out of
regulation.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
GND
NR
SD
ERR
IN
OUT
ADP3307
WARNING!
ESD SENSITIVE DEVICE
ADP3307
–4– REV. 0
INPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
3.202
3.198
3.195
3.3 4 145678910111213
3.201
3.200
3.197
3.196
3.199
V
OUT
= 3.2V
I
L
= 0mA
I
L
= 10mA
I
L
= 100mA
I
L
= 50mA
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
OUTPUT LOAD – mA
GROUND CURRENT – mA
900
750
150 0 25 100
50 75
600
450
300
IL = 0 TO 100mA
Figure 5. Ground Current vs. Load
Current
OUTPUT LOAD – mA
INPUT/OUTPUT VOLTAGE – mV
120
96
00 25 10050 75
72
48
24
Figure 8. Dropout Voltage vs.
Output Current
–Typical Performance Characteristics
OUTPUT LOAD – mA
OUTPUT VOLTAGE – Volts
3.202
3.1950 10 100
20 30 40 50 60 70 80 90
3.201
3.200
3.199
3.198
3.197
3.196
V
OUT
= 3.2V
V
IN
= 7V
Figure 3. Output Voltage vs. Load
Current Up to 100 mA
0.2
–0.4
–45 –25 135–5 15 35 75 95 11555
0.1
0.0
–0.1
–0.2
–0.3
I
L
= 50mA
I
L
= 0
I
L
= 100mA
TEMPERATURE – 8C
OUTPUT VOLTAGE – %
Figure 6. Output Voltage Variation %
vs. Temperature
5
4
001 0
234321
3
2
1
V
OUT
= 3.2V
R
L
= 32V
INPUT/OUTPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Figure 9. Power-Up/Power-Down
INPUT VOLTAGE – Volts
GROUND CURRENT – mA
800
640
00 1.2 12.02.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8
480
320
160
V
OUT
= 3.2V
I
L
= 0
Figure 4. Quiescent Current vs. Sup-
ply Voltage—3.2 V (Both Outputs)
TEMPERATURE – 8C
GROUND CURRENT – mA
1000
800
0
–25 –5 135
15 35 55 75 95 115
600
400
200
Figure 7. Quiescent Current vs.
Temperature
TIME – ms
INPUT/OUTPUT VOLTAGE – Volts
8.0
5.0
00 20 200
40 60 80 100 120 140 160 180
7.0
6.0
3.0
1.0
4.0
2.0 VSD = VIN
CL = 0.47mF
RL = 32V
VOUT = 3.2V
VIN
VOUT
Figure 10. Power-Up Overshoot
ADP3307
–5–REV. 0
VOLTS
3.220
3.190
0 40 400
80 120 160 200 240 280 320 360
3.210
3.200
7.0
3.180
7.5
V
OUT
= 3.2V
R
L
= 32V
C
L
= 0.47mF
V
IN
TIME – ms
Figure 11. Line Transient Response
3.220
3.210
0 100 500
200 300 400
3.190
3.180
100
10
3.200
VOLTSmA
TIME – ms
V
OUT
= 3.2V
C
L
= 4.7mF
Figure 14. Load Transient
VOLTS
4
3
010 50
20 30 40
1
0
3
0
2
TIME – ms
VSD
CL = 0.47mF
VOUT = 3.2V
RL = 32V
3.2V
Figure 17. Turn Off
TIME – ms
VOLTS
3.220
3.190
0 20 200
40 60 80 100 120 140 160 180
3.210
3.200
7.0
3.180
7.5
V
OUT
= 3.2V
R
L
= 3.2kV
C
L
= 0.47mF
V
IN
Figure 12. Line Transient Response
V
OUT
= 3.2V
mA
300
200
01 5234
0
4
2
0
100
VOLTS
V
OUT
I
OUT
TIME – sec
0.5 4.51.5 2.5 3.5
Figure 15. Short Circuit Current
FREQUENCY – Hz
RIPPLE REJECTION – dB
10 100 10M1k 10k 1M
0
–10
–100
–20
–30
–40
–50
–60
–70
100k
a. 0.47mF, R
L
= 33kV
b. 0.47mF, R
L
= 33V
c. 10mF, R
L
= 33kV
d. 10mF, R
L
= 33V
V
OUT
= 3.3V
d
c
b
a
–80
–90
db
c
a
Figure 18. Power Supply Ripple
Rejection
3.220
3.210
0 100 500
200 300 400
3.190
3.180
100
10
3.200
VOLTSmA
TIME –
m
s
VOUT = 3.2V
CL = 0.47mF
Figure 13. Load Transient
VOLTS
4
3
0
0 20 10040 60 80
2
1
0
3V
SD
C
L
= 0.47mFV
OUT
3.2V
C
L
= 4.7mF
V
OUT
= 3.2V
R
L
= 32V
3V
TIME – ms
Figure 16. Turn On
10
1
0.01
100 1k 100k10k
0.1
FREQUENCY – Hz
VOLTAGE NOISE SPECTRAL DENSITY – mV Hz
VOUT = 5V, CL = 0.47mF
IL = 1mA, CNR = 0
VOUT = 2.7– 5.0V, CL = 4.7mF
IL = 1mA, CNR = 10nF
VOUT = 2.7– 5.0V, CL = 0.47mF
IL = 1mA, CNR = 10nF
VOUT = 3.3V, CL = 0.47mF
IL = 1mA, CNR = 0
0.47mF BYPASS
PIN 5 TO PIN 1
Figure 19. Output Noise Density
ADP3307
–6– REV. 0
THEORY OF OPERATION
The ADP3307 anyCAP
LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
PTAT
V
OS
G
M
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3307
COMPENSATION
CAPACITOR ATTENUATION
(V
BANDGAP
/V
OUT
)R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
R
LOAD
C
LOAD
(a)
GND
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset volt-
age” that is repeatable and very well controlled. The gained up
temperature proportional offset voltage is combined with the
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the trade-off of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consist-
ing of R3 and R4, the values are chosen to produce a tempera-
ture stable output.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR val-
ues for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value, required to keep conventional LDOs
stable, changes depending on load and temperature. These
ESR limitations make designing with conventional LDOs more
difficult because of their unclear specifications and the depen-
dence of ESR over temperature.
This is no longer true with the ADP3307 anyCAP LDO. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. The innovative design allows the
circuit to be stable with just a small 0.47 µF capacitor on the
output. Additional advantages of the design scheme include
superior line noise rejection and very high regulator gain that
lead to excellent line and load regulation. An impressive ±1.4%
accuracy is guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard solu-
tions that give warning after the output has lost regulation, the
ADP3307 provides improved system performance by enabling
the ERR pin to give warning before the device loses regulation.
As the chip’s temperature rises above 165°C, the circuit acti-
vates a soft thermal shutdown, indicated by a signal low on the
ERR pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main di-
vider network (a) is made available at the noise reduction (NR)
pin which can be bypassed with a small capacitor (10 nF–100 nF).
APPLICATION INFORMATION
Capacitor Selection: anyCAP
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3307 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. There is an upper
limit on the size of the output capacitor. The ADP3307 is stable
with extremely low ESR capacitors (ESR ≈ 0), such as multi-
layer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not re-
quired; however, for applications where the input source is high
impedance or far from the input pins, a bypass capacitor is
recommended. Connecting a 0.47 µF capacitor from the input
to ground reduces the circuit’s sensitivity to PC board layout. If
a bigger output capacitor is used, the input capacitor should be
1 µF minimum.
Noise Reduction
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
10 nF–100 nF range provide the best performance. As the noise
reduction capacitor increases the high frequency loop-gain of
the regulator, the circuit requires a larger output capacitor if it is
used. The recommended value is 4.7 µF, as shown in Figure 21.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node should be
carefully done to avoid noise pick up from external sources. The
pad connected to this pin should be as small as possible. Long
PC board traces are not recommended.
ADP3307
–7–REV. 0
V
OUT
= 3.3V
V
IN
+
C1
1mF
ADP3307-3.3
NR
OUT
ERR
ON
OFF
SD GND
330k
IN
E
OUT
C2
4.7mF
+
R1
C
NR
10nF
Figure 21. Noise Reduction Circuit
Thermal Overload Protection
The ADP3307 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C. Un-
der extreme conditions (i.e., high ambient temperature and
power dissipation), where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
has dropped to a safe level. Output current is restored when the
die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 125°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
P
D
= (V
IN
– V
OUT
) I
LOAD
+ (V
IN
) I
GND
Where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are input and output voltages respectively.
Assuming I
LOAD
= 100 mA, I
GND
= 2 mA, V
IN
= 5.5 V and
V
OUT
= 3.3 V, device power dissipation is:
P
D
= (5.5 – 3.3) 0.1 + 5.5 × 2 mA = 0.231 W
∆T = T
J
– T
A
= P
D
× θ
JA
= 0.231 × 165 = 38°C
With a maximum junction temperature of 125°C, this yields a
maximum ambient temperature of ~72°C.
Printed Circuit Board Layout Consideration
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
The following general guidelines will be helpful when designing
a board layout:
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and wider traces.
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
3. Do not use solder mask or silkscreen on the heat dissipating
traces because it will increase the junction-to-ambient ther-
mal resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to a TTL low level or tying it to ground will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1 µA.
Error Flag Dropout Detector
The ADP3307 will maintain its output voltage over a wide
range of load, input voltage and temperature conditions. If the
output is about to lose regulation, for example, by reducing the
supply voltage below the combined regulated output and drop-
out voltages, the ERR pin will be activated. The ERR output is
an open collector that will be driven low.
Once set, the ERRor flag’s hysteresis will keep the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
APPLICATIONS CIRCUITS
Crossover Switch
The circuit in Figure 22 shows that two ADP3307s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide of the data sheet.
ADP3307-2.7
ADP3307-3.3
+
OUTIN
SD
GND
+
IN OUT
SD GND
C1
1.0mFC2
0.47mF
V
OUT
= 2.7V/3.3V
V
IN
= 4V TO 12V
OUTPUT SELECT
4V
0V
Figure 22. Crossover Switch
Higher Output Current
The ADP3307 can source up to 100 mA without any heatsink
or pass transistor. If higher current is needed, an appropriate
pass transistor can be used, as in Figure 23, to increase the
output current to 1 A.
ADP3307-3.3
OUT
IN
SD
GND
+
V
IN
= 4V TO 8V MJE253* V
OUT
= 3.3V@1A
C1
47mF
C2
10mF
*AAVID531002 HEAT SINK IS USED
ERR
R1
50V
Figure 23. High Output Current Linear Regulator
ADP3307
–8– REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3234–8–12/97
PRINTED IN U.S.A.
+
V
IN
= 2.5V TO 3.5V C1
100mF
10V
L1
6.8mHD1
1N5817
C2
100mF
10V
I
LIM
V
IN
SW1
SW2GND FB
ADP3000-ADJ
R1
120VR2
30.1kV
1%
Q1
2N3906
ADP3307-3.3
IN OUT
GND
SD
R3
124kV
1%
R4
274kV
Q2
2N3906
C3
2.2mF
3.3V@100mA
Figure 24. Constant Dropout Post Regulator
6-Lead Plastic Surface Mount
(RT-6)
0.122 (3.10)
0.106 (2.70)
PIN 1
0.071 (1.80)
0.059 (1.50) 0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1 3
4 5 6
2
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
10°
0°
0.020 (0.50)
0.010 (0.25)
0.059 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
Constant Dropout Post Regulator
The circuit in Figure 24 provides high precision with low drop-
out for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
dropout voltage, which limits the power dissipation of the LDO
to 30 mW. The ADP3000 used in this circuit is a switching
regulator in the step-up configuration.
