The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.6
For the informat ion for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
8-bit Microcontrollers
New 8FX MB95630H Series
MB95F632H/F632K/F633H/F633K/F634H/F634K/F636H/F636K
■DESCRIPTION
The MB95630H Series is a series of gener al-purpose , single-chip micr ocontrollers. In a ddition to a compact
instruction set, the microcontrollers of this series contain a variety of periphera l functions.
■FEATURES
•F
2MC-8FX CPU core
Instruction set optimized fo r controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F2MC is the abbrevia tion of FUJITSU Flexible Microcontroller.
•Clock
• Selectable main clock source
- Main os cillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
- External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
- Ma i n CR clock (4 MHz ±2%)
- Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz ±2% when the PLL multiplication rate is 2.
- The main CR PLL clock frequency becomes 10 MHz ±2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz ±2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz ±2% when the PLL multiplication rate is 4.
• Selectable subclock source
- Suboscillation clock (32.768 kHz)
- External clock (32.768 kHz)
- Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
•Timer
• 8/16-bit composite timer × 2 channels
• 8/16-bit PPG × 3 channels
• 16-bit PPG timer × 1 channel (can work independently or together with the multi-pulse generator)
• 16-bit reload timer × 1 channel (can work independently or together with the multi-pulse generator)
• Time-base timer × 1 channel
• Watch prescaler × 1 channel (Continued)
DS702–00009–3v0-E
MB95630H Series
2DS702–00009–3v0-E
(Continued)
•UART/SIO × 1 channel
• Full duplex double buffer
• Capable of clock asynchronous (U ART) serial data tr ansfer and cloc k synchronous (SIO) serial data tr ans-
fer
•I
2C bus interface × 1 chan nel
Built-in w ake-up function
• Multi-pulse generator (MPG) (for DC motor control) × 1 channel
• 16-bit reload timer × 1 channel
• 16-bit PPG timer × 1 channel
• Wave form sequencer (including a 16-bit timer equipped with a buffer and a compare clear function)
•LIN-UART
• Full duplex double buffer
• Capable of clock asynchronous serial data transfer and clock synchronous serial data transfer
• External interrupt × 10 channels
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumpt ion (standby) modes
• 8/10-bit A/D converter × 8 channels
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
There are four standby modes as follows:
• Stop mode
• Sleep mode
•Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal standby mode and deep standby mode.
• I/O port
• MB95F632H/F633H/F634H/F636H (number of I/O po rts: 28)
- General-purpose I/O ports (CMOS I/O) : 25
- General-purpose I/O ports (N-ch open drain) : 3
• MB95F632K/F633K/F634K/F636K (number of I/O ports: 29)
- General-purpose I/O ports (CMOS I/O) : 25
- General-purpose I/O ports (N-ch open drain) : 4
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/soft ware watchdog time r
• Built-in ha rdware watchdog timer
• Built-in software watchdog timer
• Power-on reset
A pow er-on reset is generated when the power is swit ched on.
• Low-voltag e detection reset circuit (only available on MB95F632K/F633K/F634K/F636K)
Built-in lo w-voltag e detection function (The comb ination of detection v oltage and relea se voltage can be se-
lected from four options.)
•Comparator
• Clock sup ervisor counter
Built-in clock supervisor co unter
• Dual operatio n Flash memory
The prog ram/erase operation and th e r ead op er a tio n can be executed in d iffer en t b anks ( upp er ba nk/lower
bank) simultaneously.
• Flash memory security function
Protects the content of the Flash memory.
MB95630H Series
DS702–00009–3v0-E 3
■PRODUCT LINE-UP
(Continued)
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
Type Flash memory product
Clock
supervisor
counter It supervises the main clock oscillation and the subclock oscillation.
Flash memory
capacity 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte
RAM capacity 256 bytes 512 bytes 1024 byt es1024 bytes 256 bytes 512 bytes 1024 bytes 1024 bytes
Power-on reset Yes
Low-voltage
detection reset No Yes
Reset input Dedicated Selected through software
CPU functions
• Number of basic instructions : 136
• Instruction bit length : 8 bits
• Instruction length : 1 to 3 byt es
• Data bit length : 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz)
General-
purpose I/O
• I/O port : 28
• CMOS I/O : 25
• N-ch open drain : 3
• I/O port : 29
•CMOS I/O :25
• N-ch open drain : 4
Time-base timerInterval time: 0.256 ms to 8.3 s (e xternal clock frequency = 4 MHz)
Hardware/
software
watchdog timer
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
• The sub-CR clock can be used as the source clock of the software watchdog timer.
Wild register It can be used to replace 3 bytes of data.
LIN-UART
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
• Both cloc k synchronous serial data tr ansfer and clock asynch ronous serial data tran sfer are
enabled.
• The LIN function can be used as a LIN master or a LIN slave.
8/10-bit
A/D converter 8 channels
8-bit or 10-bit resolution can be selected.
8/16-bit
composite tim er
2 channels
• The timer can be configure d as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel” .
• It has the f ollowing functions: in terva l ti mer function, PWC function, PWM function and inpu t
capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
External
interrupt
10 channels
• Interrupt by edge detection (The rising edge, f alling edge, and both edges can be selected.)
• It can be used to wake up the device from different standby modes.
On-chip debug • 1-wire serial control
• It supports serial writing (asynchronous mode).
MB95630H Series
4DS702–00009–3v0-E
(Continued)
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
UART/SIO
1 channel
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial
data transfer are enabled.
I2C bus
interface
1 channel
• Master/slave transmission and reception
• It has the following functions: bus error function, arbitration function, transfer direction de-
tection function, wake-up function, and functions of generating and detecting repeated
START conditions.
8/16-bit PPG 3 channels
• Each channel can be used as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
• The counter operating clock can be selected from eight clock sources.
16-bit PPG
timer
1 channel
• PWM mode and one-shot mode are ava ilable to use.
• The counter operating clock can be selected from eight clock sources.
• It supports external trigger start.
• It can work independently or together with the multi-pulse generator.
16-bit reload
timer
1 channel
• Two clock modes and two counter operating modes are available to use.
• It can output square wave.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Two counter operating modes: reload mode and one-shot mode
• It can work independently or together with the multi-pulse generator.
Multi-pulse
generator (for
DC motor
control)
• 16-bit PPG timer: 1 channel
• 16-bit reload ti mer operations: toggle output, one-shot output
• Event counter: 1 channel
• Wavefor m sequencer (including a 16-bit timer equipped with a buffer and a compare clear
function)
Watch prescalerEight di fferent time intervals can be selected.
Comparato r 1 channel
Flash memory
• It supports automatic programming (Embedded Algorithm), and program/erase/erase-
suspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embe dded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles 1000 10000 100000
Data retention time 20 years 10 years 5 years
MB95630H Series
DS702–00009–3v0-E 5
(Continued)
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
Standby mode
There are four standby modes as follows:
• Stop mode
• Sleep mode
•Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal stan dby mode and deep
standby mode.
Package FPT-32P-M30
DIP-32P-M06
LCC-32P-M19
MB95630H Series
6DS702–00009–3v0-E
■PACKAGES AND CORRESPONDING PRODUCTS
Ο: Available
Part number
Package
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
FPT-32P-M30 ΟΟΟΟΟΟΟΟ
DIP-32P-M06 ΟΟΟΟΟΟΟΟ
LCC-32P-M19 ΟΟΟΟΟΟΟΟ
MB95630H Series
DS702–00009–3v0-E 7
■DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of Flash memory pro-
gram/erase.
F or details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
•Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSION”.
• Operating voltage
The operating v oltage varies, depending on whether the on-chip debug function is used or not.
For details of operating voltage, see “■ ELECTRICAL CHARA CTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
For details of the connection method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING
CONNECTION” in “New 8FX MB95630H Series Hardware Manual”.
MB95630H Series
8DS702–00009–3v0-E
■PIN ASSIGNMENT
(Continued)
Vss
PF1/X1
PF0/X0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(T OP VIEW)
LQFP32
FPT-32P-M30
32
31
30
29
28
27
26
25
24
23
22
21 P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
20
19
18
17
1
2
3
4
5
6
7
8
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
P60/INT08/SDA/DTTI
9
10
11
12
P00/INT00/AN00/CMP0_P
P01/INT01/AN01/CMP0_N
P02/INT02/AN02/SCK
13
14
15
P03/INT03/AN03/SOT 16
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
PF2/RST
PF0/X0
PF1/X1
Vss
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(T OP VIEW)
SH-DIP32
DIP-32P-M06
32
31
30
29
28
27
26
25
24
23
22
21 P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01/CMP0_N
P00/INT00/AN00/CMP0_P
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
13
14
15
P60/INT08/SDA/DTTI 16
MB95630H Series
DS702–00009–3v0-E 9
(Continued)
Vss
PF1/X1
PF0/X0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(T OP VIEW)
QFN32
LCC-32P-M19
32
31
30
29
28
27
26
25
24
23
22
21 P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
20
19
18
17
1
2
3
4
5
6
7
8
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
P60/INT08/SDA/DTTI
9
10
11
12
P00/INT00/AN00/CMP0_P
P01/INT01/AN01/CMP0_N
P02/INT02/AN02/SCK
13
14
15
P03/INT03/AN03/SOT 16
MB95630H Series
10 DS702–00009–3v0-E
■PIN FUNCTIONS
(Continued)
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
15
PG2
C
General-pur pose I/O por t
Hysteresis CMOS — Ο
X1A Subclock I/O oscillation pin
SNI2 Trigger input pin for the position
detection function of the MPG
waveform sequencer
26
PG1
C
General-pur pose I/O por t
Hysteresis CMOS — Ο
X0A Subclock input oscillation pin
SNI1 Trigger input pin for the position
detection function of the MPG
waveform sequencer
37V
CC — P ower supply pin — — — —
48C—
Decoupling capacitor connection
pin ————
59
P67
D
General-pur pose I/O por t
High-current pin
Hysteresis CMOS — Ο
PPG21 8/16-bit PPG ch. 2 output pin
TRG1 16-bit PPG timer ch. 1 trigger
input pin
OPT5 MPG waveform sequencer
output pin
610
P66
D
General-pur pose I/O por t
High-current pin
Hysteresis CMOS — Ο
PPG20 8/16-bit PPG ch. 2 output pin
PPG1 16-bit PPG timer ch. 1 output pin
OPT4 MPG waveform sequencer
output pin
711
P65
D
General-pur pose I/O por t
High-current pin Hysteresis CMOS — ΟPPG11 8/16-bit PPG ch. 1 output pin
OPT3 MPG waveform sequencer
output pin
812
P64
D
General-pur pose I/O por t
High-current pin
Hysteresis CMOS — Ο
EC1 8/16-bit comp osite timer ch. 1
clock input pin
PPG10 8/16-bit PPG ch. 1 output pin
OPT2 MPG waveform sequencer
output pin
MB95630H Series
DS702–00009–3v0-E 11
(Continued)
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
913
P63
D
General-pur pose I/O por t
High-current pin
Hysteresis CMOS — Ο
TO11 8/16-bit composite timer ch. 1
output pin
PPG01 8/16-bit PPG ch. 0 output pin
OPT1 MPG waveform sequencer
output pin
10 14
P62
D
General-pur pose I/O por t
High-current pin
Hysteresis CMOS — Ο
TO10 8/16-bit composite timer ch. 1
output pin
PPG00 8/16-bit PPG ch. 0 output pin
OPT0 MPG waveform sequencer
output pin
11 15
P61
I
General-pur pose I/O por t
CMOS CMOS Ο—
INT09 External interrupt input pin
SCL I2C bus interface ch. 0 clock I/O
pin
TI1 16-bit reload timer ch. 1 input pin
12 16
P60
I
General-pur pose I/O por t
CMOS CMOS Ο—
INT08 External interrupt input pin
SDA I2C bus interface ch. 0 data I/O
pin
DTTI MPG waveform sequencer input
pin
13 17
P00
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT00 External interrupt input pin
AN00 8/10-bit A/D converter analog
input pin
CMP0_P Comparator non-inverting analog
input (positive input) pin
14 18
P01
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT01 External interrupt input pin
AN01 8/10-bit A/D converter analog
input pin
CMP0_N Comparator inverting an alog
input (negat ive input) pin
15 19
P02
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT02 External interrupt input pin
AN02 8/10-bit A/D converter analog
input pin
SCK LIN-UART clock I/O pin
MB95630H Series
12 DS702–00009–3v0-E
(Continued)
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
16 20
P03
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT03 External interrupt input pin
AN03 8/10-bit A/D converter analog
input pin
SOT LIN-UART data output pin
17 21
P04
F
General-pur pose I/O por t
CMOS/
analog CMOS — Ο
INT04 External interrupt input pin
AN04 8/10-bit A/D converter analog
input pin
SIN LIN-UART data input pin
EC0 8/16-bit comp osite timer ch. 0
clock input pin
18 22
P05
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT05 External interrupt input pin
AN05 8/10-bit A/D converter analog
input pin
TO00 8/16-bit composite timer ch. 0
output pin
19 23
P06
E
General-pur pose I/O por t
Hysteresis/
analog CMOS — Ο
INT06 External interrupt input pin
AN06 8/10-bit A/D converter analog
input pin
TO01 8/16-bit composite timer ch. 0
output pin
20 24
P07
E
General-pur pose I/O por t Hysteresis/
analog CMOS — Ο
INT07 External interrupt input pin
AN07 8/10-bit A/D converter analog
input pin
21 25 P10 GGeneral-purpose I/O port Hysteresis CMOS — ΟPPG10 8/16-bit PPG ch. 1 output pin
CMP0_O Comparator digital output pin
22 26 P11 GGeneral-purpose I/O port Hysteresis CMOS — Ο
PPG11 8/16-bit PPG ch. 1 output pin
23 27
P12
H
General-pur pose I/O por t
Hysteresis CMOS Ο—
DBG DBG input pin
EC0 8/16-bit comp osite timer ch. 0
clock input pin
24 28 P13 GGeneral-purpose I/O port Hysteresis CMOS — Ο
PPG00 8/16-bit PPG ch. 0 output pin
MB95630H Series
DS702–00009–3v0-E 13
(Continued)
Ο: Available
*1:FPT-32P-M30
*2:LCC-32P-M19
*3:DIP-32P-M06
*4:For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
*5:N-ch open drain
*6:Pull-up
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
25 29 P14 GGeneral-purpose I/O port Hysteresis CMOS — ΟUCK0 UART/SIO ch. 0 clock I/O pin
PPG01 8/16-bit PPG ch. 0 output pin
26 30 P15 GGeneral-purpose I/O port Hysteresis CMOS — ΟUO0 UART/SIO ch. 0 data outpu t pin
PPG20 8/16-bit PPG ch. 2 output pin
27 31 P16 JGeneral-purpose I/O port CMOS CMOS — ΟUI0 UART/SIO ch . 0 data input pin
PPG21 8/16-bit PPG ch. 2 output pin
28 32
P17
G
General-pur pose I/O por t
Hysteresis CMOS — Ο
TO1 16-bit reload timer ch. 1 output
pin
SNI0 Trigger input pin for the position
detection function of the MPG
waveform sequencer
29 1
PF2
A
General-pur pose I/O por t
Hysteresis CMOS Ο—
RST
Reset pin
Dedicated reset pin on
MB95F632H/F633H/F634H/
F636H
30 2 PF0 BGeneral-purpose I/O port Hysteresis CMOS — —
X0 Main cloc k input oscillation pin
31 3 PF1 BGeneral-purpose I/O port Hysteresis CMOS — —
X1 Main clock I/O oscillation pin
32 4 VSS — Power supply pin (GND) — — — —
MB95630H Series
14 DS702–00009–3v0-E
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A• N-ch open drain output
• Hysteresis input
• Reset output
B• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
C• Oscillation circuit
• Low-speed side
Feedback resistance:
approx. 5 MΩ
• CMOS output
• Hysteresis input
• Pull-up control
N-ch Reset output / Digital output
Reset input / Hysteresis input
Standby control / Port select
Clock input
Port select
Digital output
Digital output
Standby control
Hysteresis input
Digital output
Digital output
Standby control
Hysteresis input
Port select
X1
X0
N-ch
P-ch
N-ch
P-ch
Clock input
X1A
X0A
Standby control / Port select
N-ch
P-ch
Port select
Digital output
Digital output
Standby control
Hysteresis input
N-ch
Digital outputDigital output
Digital output
Standby control
Hysteresis input
P-ch
RPull-up control
Port select
P-ch
RPull-up control
MB95630H Series
DS702–00009–3v0-E 15
(Continued)
Type Circuit Remarks
D• CMOS output
• Hysteresis input
• Pull-up control
• High current output
E• CMOS output
• Hysteresis input
• Pull-up control
• Analog input
F• CMOS output
• CMOS input
• Pull-up control
• Analog input
G• CMOS output
• Hysteresis input
• Pull-up control
H• N-ch open drain output
• Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Analog input
A/D control
Standby control
CMOS input
N-ch
Standby control
Hysteresis input
Digital output
MB95630H Series
16 DS702–00009–3v0-E
(Continued)
Type Circuit Remarks
I• N-ch open drain output
• CMOS input
J• CMOS output
• CMOS input
• Pull-up control
N-ch Digital output
Standby control
CMOS input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Standby control
CMOS input
MB95630H Series
DS702–00009–3v0-E 17
■HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected
by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page
describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability
from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment u sing semiconductor devices.
• Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain est ablished limits, called ab so lute maximum ratings. Do not exceed these r ating s.
• Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales repre-
sentative beforehand.
• Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor de vices to power
supply and input/o utput functions.
(1) Preventing Over-Voltage and Ove r-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deteri-
oration within the device , and in extreme cases leads to permanent damage of the de vice. Try to pre vent
such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting o f output pins to supply pi ns or other output pins, or connecti on to large capacitance can cause
large current flows. Such conditions if present for e xtended periods of time can damage the device.
Therefore, a void this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such
pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Code: DS00-00004-2E
MB95630H Series
18 DS702–00009–3v0-E
• Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high v oltages, internal parasitic PNPN junctions (called th yristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply
pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
• Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
• Fail-Safe Design
Any semicondu ctor devices ha ve inherent ly a certain rate of f ailure . You must protect against injury, damage
or loss from such f ailures b y incorporating saf ety design measures into y our facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating condition s.
• Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (com-
puters , off ice a utomation and ot her offi ce equipment , indust rial, commun ications , and measur ement equ ip-
ment, personal or household devices, etc.).
CA UTION: Customers considering the use of our products in special applications where f ailure or abnormal
operation m ay directly aff ect human lives or cause physica l injury or property damage, or where e xtreme ly
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor re-
peaters, vehicle operating controls, medical devices f or life support, etc.) are requested to consult with sales
representatives before such use. The company will not be responsible for damages arising from such use
without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR’s recommended conditions.
For detailed information about mou nt conditions, contact your sales representative.
• Lead Insertion Type
Mounting of lead inser tion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involv es processes for inserting leads into through-holes on the board
and using the flow solder ing (wave soldering) method of applying liquid solder. In this case, the soldering
process usually causes leads to be subj ected to thermal stress in excess of t he absolute rating s f or storage
temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting
conditions.
If soc k et mount ing is used, dif f eren ces in surf a ce treatm ent of the so c ket contacts and I C lead surfaces can
lead to contact deterioration after long periods. F or this reason it is recommended that the surface treatment
of soc ket contacts and IC leads be verified before mounting.
MB95630H Series
DS702–00009–3v0-E 19
• Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily def ormed or bent. The use of packages with higher pin counts and narrow er pin pitch results
in increased susceptibility to open connections caused by deformed pins , or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised
to mount packages in accordance with FUJITSU SEMICONDUCTOR r anking of recommended conditions .
• Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted usin g Sn- Pb eu te ct ic
soldering, junction strength may be reduced under some conditions of use.
• Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins , e xposure to natural en vironmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To
prev ent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store produc ts in loca tio n s whe re tem pe ratur e ch an g es are slig ht.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5 °C and 30 °C.
When you open Dry Pack age that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moisture-
resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are e xposed to corrosive gases or high levels of dust.
• Baking
P ackag es that hav e absorbed moist ure may be de-moisturized b y baking (heat drying). F ollow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125 °C/24 h
• Static Electricity
Because semiconductor devices are par ticularly susceptible to damage by static electricity, you must take
the following precautio ns:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity b y the use of rings or bracelets conn ected to g roun d thro ugh high re sis-
tance (on the level of 1 MΩ).
W earing of conduct ive clothing and shoes , use of conductiv e floor mats and other measures to minimize
shock loa ds is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the u se of styrofoam or other highly stat ic-prone ma terials f or st or age of completed b oard assem-
blies.
MB95630H Series
20 DS702–00009–3v0-E
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-stat ic measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely
affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to
protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTI ON : Plastic molded devices are flamm a ble, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental
conditions should consult wit h sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
MB95630H Series
DS702–00009–3v0-E 21
■NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed t he maximum voltage rating.
In a CMOS IC, if a volt a ge h ighe r t ha n VCC or a voltage lower than V SS is applie d to a n input /out pu t pin t hat
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of powe r supply vo ltage mentioned in “1. Ab solute Maximu m Ratings” of “■ ELECTRICAL CHARA C-
TERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, po wer supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when po wer supply voltage fluctuates r apidl y even tho ugh the fluctuat ion is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress v oltage fluctuation so that the fluctuation in VCC ripple (p-p v alue)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the tran-
sient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power sup-
ply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■PIN CONNECTION
• Treatment of unused pins
If an un used input pi n is left unconnect ed, a component ma y be permanently damaged due to malfun ctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an un-
used input/output pin to the outp ut sta te and le a ve it unconnected, or set it to the input st ate and trea t it the
same as an unused input pin. If there is an unused output pin, leav e it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an in-
crease in the g round le v el, and conf orm to the total ou tput current st andard, alw ays co nnect the VCC pin and
the VSS pin to the power supply and ground outside the device. In addition, connect the current supply
source to the VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
•DBG pin
Connect the DBG pin to an external pull-up resistor of 2 kΩ or above.
After po wer-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin becomes a communication pin in debu g mode. Since the actual pull-up resistance depends
on the tool used and the inter connection length, ref er to the tool document when select ing a pull-up resistor .
•RST
pin
Connect the RST pin to an external pull-up resistor of 2 kΩ or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnec-
tion length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin
when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the
PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the
general-purpose I/O function can be selected by the RSTEN bit in the SYSC register.
MB95630H Series
22 DS702–00009–3v0-E
•C pin
Use a ceramic capa citor or a capacitor wit h equivalent frequency charact eristics. Th e deco upling capacit or
for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection
to a decouplin g ca pa cito r CS, see the diagram below. To prevent the device from unintentionally entering a
mode to which the device is not set to tr ansit du e to noise , minimiz e the dist ance betw een t he C pin and CS
and the distance between CS and the VSS pin when designing the layout of a printed circuit board.
• Note on serial communication
In serial communication, r eception of wrong data ma y occur due to noise or other ca uses. Theref ore, design
a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take
measures such as adding a checksum to the end of data in order to detect errors. If an err or is detected,
retransmit the data.
C
Cs
DBG
RST
• DBG/RST/C pins connection diagram
MB95630H Series
DS702–00009–3v0-E 23
■BLOCK DIAGRAM
Reset with LVD Dual operation Flash with
security function
(36/20/12/8 Kbyte)
F
2
MC-8FX CPU
RAM (1024/512/256 bytes)
Oscillator
circuit CR oscillator
Clock control
On-chip debug
Wild register
External interrupt
Interrupt controller
LIN-UART
Internal bus
8/16-bit composite timer ch. 0
8/10-bit A/D converter
16-bit reload timer
MPG
16-bit PPG timer
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
Waveform sequencer
UART/SIO
I
2
C bus interface ch. 0
8/16-bit PPG ch. 0
8/16-bit PPG ch. 2
Port Port
PF2
*1
/RST
*2
PF1/X1
*2
PF0/X0
*2
(PG2/X1A
*2
)
(PG1/X0A
*2
)
P02/INT02 to P07/INT07
External interrupt
P00/INT00, P01/INT01,
P60/INT08, P61/INT09
C
(P02/SCK)
(P03/SOT)
(P04/SIN)
(P14/UCK0)
(P15/UO0)
(P16/UI0)
(P62
*3
/PPG00), P13/PPG00
(P63
*3
/PPG01), P14/PPG01
(P66
*3
/PPG20), P15/PPG20
(P67
*3
/PPG21), P16/PPG21
(P60
*1
/SDA)
(P61
*1
/SCL)
(P12
*1
/DBG)
(P05/TO00)
(P06/TO01)
P12/EC0, (P04/EC0)
(P00/AN00 to P07/AN07)
(P62
*3
/TO10)
(P63
*3
/TO11)
(P64
*3
/EC1)
Comparator (P00/CMP0_P)
(P01/CMP0_N)
(P10/CMP0_O)
(P61/TI1)
(P17/TO1)
P62
*3
/OPT0 to P67
*3
/OPT5
P17/SNI0, PG1/SNI1, PG2/SNI2
(P60/DTTI)
(P61/TI1)
(P67
*3
/TRG1)
(P66
*3
/PPG1)
P10/PPG10, (P64
*3
/PPG10)
P11/PPG11, (P65
*3
/PPG11)
Vcc
Vss
*1:
*2:
*3:
P12, P60, P61 and PF2 are N-ch open drain pins.
Software select
P62 to P67 are high-current pins.
Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.
MB95630H Series
24 DS702–00009–3v0-E
■CPU CORE
• Memory space
The memory space of the MB95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended
I/O area, a data area, and a program area. The memory space includes areas intended f or specific purposes
such as general-purpose registers and a vector table. The memory maps of the MB95630H Series are
shown below.
• Memory maps
MB95F633H/F633K MB95F634H/F634KMB95F632H/F632K
I/O area
Access prohibited
RAM 256 bytes
Registers
Access prohibited
Extended I/O area
Access prohibited
Flash memory 4 Kbyte
Flash memory 4 Kbyte
0x0000
0x0080
0x0090
0x0100
0x0190
0x0F80
0x1000
0x2000
0xF000
0xFFFF
I/O area
Access prohibited
0x0000
0x0080
0x0090
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
0x0100
0x0200
0x0290
Registers
0x0100
0x0200
Access prohibited
Extended I/O area
Flash memory 4 Kbyte
0x0F80
0x1000
0x2000 Flash memory 4 Kbyte
0x1000
0x2000
Flash memory 4 Kbyte
Extended I/O area
0x0F80
0x1000
Access prohibited
RAM 512 bytes
Access prohibited
Flash memory 8 Kbyte
0xE000
0xFFFF
Access prohibited
0x8000
0x2000
Access prohibited
0xC000
RAM 1024 bytes
Flash memory 16 Kbyte
0x0490
0xFFFF
MB95F636H/F636K
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
0x0100
0x0200
Extended I/O area
0x0F80
Access prohibited
RAM 1024 bytes
Flash memory 32 Kbyte
0x0490
0xFFFF
MB95630H Series
DS702–00009–3v0-E 25
■MEMORY SPACE
The memory space of the MB95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended
I/O area, a data area, and a program area. The memory space includes areas f or specific applications such
as general-purpose registers and a vector table.
• I/O area (addresses: 0x0000 to 0x007F)
• This area contains the control registers and data reg isters for built-in peripheral functions.
• As the I/O area for ms par t of the memor y s pace, it can be accessed in the sa me way as the memor y. It
can also be accessed at high-speed by using direct addressing instructions.
• Extended I/O area (addresses: 0x0F80 to 0x0FFF)
• This area contains the control registers and data reg isters for built-in peripheral functions.
• As the extended I/O area forms par t of the memory space, it can be accessed in the same way as the
memory.
• Data area
• Static RAM is incorporated in the data area as the internal data area.
• The internal RAM size varies according to product.
• The RAM area from 0x0090 to 0x00FF can be accessed at high-speed b y using direct add ressing instruc-
tions.
• In MB95F636H/F63 6K, th e ar ea fro m 0x00 90 to 0x0 47F is an extended direct addressing area. It ca n be
accessed at high-spee d by direct addressing instructions with a direct bank pointer set.
• In MB95F634H/F63 4K, th e ar ea fro m 0x00 90 to 0x0 47F is an extended direct addressing area. It ca n be
accessed at high-spee d by direct addressing instructions with a direct bank pointer set.
• In MB95F633H/F63 3K, th e ar ea fro m 0x00 90 to 0x0 28F is an extended direct addressing area. It ca n be
accessed at high-spee d by direct addressing instructions with a direct bank pointer set.
• In MB95F632H/F63 2K, th e ar ea fro m 0x00 90 to 0x0 18F is an extended direct addressing area. It ca n be
accessed at high-spee d by direct addressing instructions with a direct bank pointer set.
• In MB95F633H/F633K/F634H/F634K/F636H/F636K, the area from 0x0100 to 0x01FF can be used as a
general-purpose register area.
• In MB95F632H/F63 2K, the area from 0x0100 to 0x018F can be used as a ge neral-purpose register a rea.
• Program area
• The Flash memory is incorporated in the program area as the internal program area.
• The Flash memory size varies according to product.
• The area from 0xFFC0 to 0xFFFF is used as the vector table.
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.
MB95630H Series
26 DS702–00009–3v0-E
• Memory space map
Direct addressing area
Extended direct addressing area
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
(General-purpose register area)
0x0100
0x0200
0x047F
Vector table area
Extended I/O area
0x0F80
0x0FFF
0x1000
Access prohibited
Program area
Data area
0x048F
0x0490
0xFFFF
0xFFC0
MB95630H Series
DS702–00009–3v0-E 27
■AREAS FOR SPECIFIC APPLICATIONS
The general-purpose register ar ea and vector table area are used for the specific applications.
• General-purpose register area (Addresses: 0x0100 to 0x01FF*1)
• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general-purpose registers, general-purpose register addressing enables high-
speed access with short instructions.
• Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to
“CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95630H Series
Hardware Manual”.
• Vector table area (Addresses: 0xF FC0 to 0xFFFF)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
• The top of the Flash memory area is allocated to the vector table area. The start address of a service
routine is set to an address in the vector table in the form of data.
“■ INTERR UPT SOURCE TABLE” lists the vector table addresses corresponding to vector call instructions,
interrupts, and resets.
For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction
■Special Instr u ction ● CALLV #vct” in “New 8FX MB95630H Series Hardware Manual”.
• Direct bank pointer and access area
*1:Due to the memory size limit, the available access area is up to “0x018F” in MB95F632H/F632K.
*2:Due to the memory size limit, the available access area is up to “0x028F” in MB95F633H/F633K.
Direct bank pointer (DP[2:0]) Operand-sp ecified dir Access area
0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F
0b000 (Ini tial value) 0x0090 to 0x00FF 0x0090 to 0x 00FF
0b001
0x0080 to 0x00FF
0x0100 to 0x017F
0b010 0x0180 to 0x01FF*1
0b011 0x0200 to 0x027F
0b100 0x0280 to 0x02FF*2
0b101 0x0300 to 0x037F
0b110 0x0380 to 0x03FF
0b111 0x0400 to 0x047F
MB95630H Series
28 DS702–00009–3v0-E
■I/O MAP
(Continued)
Address Register
abbreviation Register name R/W Initial value
0x0000 PDR0 Port 0 data register R/W 0b00000000
0x0001 DDR0 Port 0 direction register R/W 0b00000000
0x0002 PDR1 Port 1 data register R/W 0b00000000
0x0003 DDR1 Port 1 direction register R/W 0b00000000
0x0004 — (Disabled) — —
0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111
0x0006 PLLC PLL control register R/W 0b000X0000
0x0007 SYCC System clock control register R/W 0bXXX11011
0x0008 STBC Standby control register R/W 0b00000000
0x0009 RSRR Reset source register R/W 0b000XXXXX
0x000A TBTC Time-base timer control register R/W 0b00000000
0x000B WPCR Watch prescaler control register R/W 0b00000000
0x000C WDTC Watchdog timer control register R/W 0b00XX0000
0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011
0x000E STBC2 Standby control register 2 R/W 0b00000000
0x000F
to
0x0015 — (Disabled) — —
0x0016 PDR6 Port 6 data register R/W 0b00000000
0x0017 DDR6 Port 6 direction register R/W 0b00000000
0x0018
to
0x0027 — (Disabled) — —
0x0028 PDRF Port F data register R/W 0b00000000
0x0029 DDRF Port F direction register R/W 0b00000000
0x002A PDRG Port G data register R/W 0b00000000
0x002B DDRG Port G direction register R/W 0b00000000
0x002C PUL0 Port 0 pull-up register R/W 0b00000000
0x002D PUL1 Port 1 pull-up register R/W 0b00000000
0x002E
to
0x0032 — (Disabled) — —
0x0033 PUL6 Port 6 pull-up register R/W 0b00000000
0x0034 — (Disabled) — —
0x0035 PULG Port G pull-up register R/W 0b00000000
0x0036 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000
0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000
0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000
0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000
MB95630H Series
DS702–00009–3v0-E 29
(Continued)
Address Register
abbreviation Register name R/W Initial value
0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000
0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000
0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000
0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000
0x003E PC21 8/16-bit PPG timer 21 control register R/W 0b00000000
0x003F PC20 8/16-bit PPG timer 20 control register R/W 0b00000000
0x0040 TMCSRH1 16-bit reload timer control status register (upper) R/W 0b00000000
0x0041 TMCSRL1 16-bit reload timer control status register (lower) R/W 0b00000000
0x0042 CMR0C Comparator control register R/W 0b00000101
0x0043 — (Disabled) — —
0x0044 PCNTH1 16-bit PPG stat us control register (upper) R/W 0b00000000
0x0045 PCNTL1 16-bit PPG status control register (lower) R/W 0b00000000
0x0046,
0x0047 — (Disabled) — —
0x0048 EIC00 Exter nal interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000
0x0049 EIC10 Exter nal interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000
0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000
0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000
0x004C EIC01 External interrupt circuit control register ch. 8/ch. 9 R/W 0b00000000
0x004D — (Disabled) — —
0x004E LVDR LVD reset voltage selection ID register R/W 0b00000000
0x004F — (Disabled) — —
0x0050 SCR LIN-UART serial control register R/W 0b00000000
0x0051 SMR LIN-UART serial mode register R/W 0b00000000
0x0052 SSR L IN- UART serial status register R/W 0 b0 0 001 00 0
0x0053 RDR LIN-UART receive data register R/W 0b00000000
TDR LIN-UART transmit data register
0x0054 ESCR LIN-UART extended status control register R/W 0b00000100
0x0055 ECCR LIN-UART extended communication control register R/W 0b000000XX
0x0056 SMC10 UART/SIO serial mode control register 1 R/W 0b00000000
0x0057 SMC20 UART/SIO serial mode control register 2 R/W 0b00100000
0x0058 SSR0 UART/SIO serial stat us and data register R/W 0b00000001
0x0059 TDR0 UART/SIO serial output data register R/W 0b00000000
0x005A RDR0 UART/SIO serial input data register R 0b000 00000
0x005B
to
0x005F — (Disabled) — —
0x0060 IBCR00 I2C bus control register 0 ch. 0 R/W 0b00000000
0x0061 IBCR10 I2C bus control register 1 ch. 0 R/W 0b00000000
0x0062 IBSR0 I2C bus status register ch. 0 R/W 0b00000000
0x0063 IDDR0 I2C data register ch. 0 R/W 0b00000000
MB95630H Series
30 DS702–00009–3v0-E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0x0064 IAAR0 I2C address register ch. 0 R/W 0b00000000
0x0065 ICCR0 I2C clock control register ch. 0 R/W 0b00000000
0x0066 OPCUR 16-bit MPG output control register (upper) R/W 0b00000000
0x0067 OPCLR 16-bit MPG output control register (lower) R/W 0b00000000
0x0068 IPCUR 16-bit MPG input control register (upper) R/W 0b00000000
0x0069 IPCLR 16-bit MPG input control register (lower) R/W 0b00000000
0x006A NCCR 16-bit MPG noise cancellatio n control register R/W 0b00000000
0x006B TCSR 16-bit MPG timer control status register R/W 0b00000000
0x006C ADC1 8/10-bit A/D converter control register 1 R/W 0b00000000
0x006D ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000
0x006E ADDH 8/ 10-bit A/D converter data register (upper) R/W 0b00000000
0x006F ADDL 8/10-bit A/D converter data register (lower) R/W 0b00000000
0x0070 — (Disabled) — —
0x0071 FSR2 Flash memory status register 2 R/W 0b00000000
0x0072 FSR Flash memory status register R/W 0b000X0000
0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000
0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX
0x0075 FSR4 Flash memory status register 4 R/W 0b00000000
0x0076 WREN Wild register address compare enable register R/W 0b00000000
0x0077 WROR Wild register data test setting register R/W 0b00000000
0x0078 — Mirror of register bank pointer (RP) and direct bank
pointer (DP) ——
0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111
0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111
0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111
0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111
0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111
0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111
0x007F — (Disabled) — —
0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000
0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000
0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000
0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000
0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000
0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000
0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000
0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000
0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000
0x0F89
to
0x0F91 — (Disabled) — —
MB95630H Series
DS702–00009–3v0-E 31
(Continued)
Address Register
abbreviation Register name R/W Initial value
0x0F92 T01CR0 8/16-bit composite timer 01 stat us control register 0 R/W 0b00000000
0x0F93 T00CR0 8/16-bit composite timer 00 stat us control register 0 R/W 0b00000000
0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000
0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000
0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode cont rol
register R/W 0b00000000
0x0F97 T11CR0 8/16-bit composite timer 11 stat us control register 0 R/W 0b00000000
0x0F98 T10CR0 8/16-bit composite timer 10 stat us control register 0 R/W 0b00000000
0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000
0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000
0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control
register R/W 0b00000000
0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111
0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111
0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111
0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111
0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111
0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111
0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111
0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111
0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000
0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000
0x0FA6 PPS21 8/16-bit PPG21 cycle setting buffer register R/W 0b11111111
0x0FA7 PPS20 8/16-bit PPG20 cycle setting buffer register R/W 0b11111111
0x0FA8 TMRH1 16-bit reload timer timer register (upper) R/W 0b00000000
TMRLRH1 16-bit reload timer reload register (upper )
0x0FA9 TMRL1 16-bit reload timer timer register (lower) R/W 0b00000000
TMRLRL1 16-bit reload timer reload register (lower)
0x0FAA PDS21 8/16-bit PPG21 duty setting buffer register R/W 0b11111111
0x0FAB PDS20 8/16-bit PPG20 duty setting buffer register R/W 0b11111111
0x0FAC
to
0x0FAF — (Disabled) — —
0x0FB0 PDCRH1 16-bit PPG downcounter register (upper) R 0b00000000
0x0FB1 PDCRL1 16-bit PPG downcounter register (lower) R 0b00000000
0x0FB2 PCSRH1 16-bit PPG cycle setting buffer register (upper) R/W 0b11111111
0x0FB3 PCSRL1 16-bit PPG cycle setting buffer register (lower) R/W 0b11111111
0x0FB4 PDUTH1 16-bit PPG duty setting buffer register (upper) R/W 0b11111111
0x0FB5 PDUTL1 16-bit PPG duty setting buffer register (lower) R/W 0b11111111
0x0FB6
to
0x0FBB — (Disabled) — —
MB95630H Series
32 DS702–00009–3v0-E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0x0FBC BGR1 LIN-UART baud rate generator register 1 R/W 0b00000000
0x0FBD BGR0 LIN-UART baud rate generator register 0 R/W 0b00000000
0x0FBE PSSR0 UART/SIO dedicated baud rate generator prescaler
select register R/W 0b00000000
0x0FBF BRSR0 UA RT/SIO dedicated baud rate generator baud rate
setting register R/W 0b00000000
0x0FC0
to
0x0FC2 — (Disabled) — —
0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000
0x0FC4 OPDBRH0 16-bit MPG output data buffer register (upper) ch. 0 R/W 0b00000000
0x0FC5 OPDBRL0 16-bit MPG output data buffer register (lower) ch. 0 R/W 0b00000000
0x0FC6 OPDBRH1 16-bit MPG output data buffer register (upper) ch. 1 R/W 0b00000000
0x0FC7 OPDBRL1 16-bit MPG output data buffer register (lower) ch. 1 R/W 0b00000000
0x0FC8 OPDBRH2 16-bit MPG output data buffer register (upper) ch. 2 R/W 0b00000000
0x0FC9 OPDBRL2 16-bit MPG output data buffer register (lower) ch. 2 R/W 0b00000000
0x0FCA OPDBRH3 16-bit MPG output data buffer register (upper) ch. 3 R/W 0b00000000
0x0FCB OPDBRL3 16-bit MPG output data buffer register (lower) ch. 3 R/W 0b00000000
0x0FCC OPDBRH4 16-bit MPG output data buffer register (upper) ch. 4 R/W 0b00000000
0x0FCD OPDBRL4 16-bit MPG output data buffer reg ister (lower) ch. 4 R/W 0b00000000
0x0FCE OPDBRH5 16-bit MPG output data buffer register (upper) ch. 5 R/W 0b00000000
0x0FCF OPDBRL5 16-bit MPG output data buffer register (lower) ch. 5 R/W 0b00000000
0x0FD0 OPDBRH6 16-bit MPG output data buffer register (upper) ch. 6 R/W 0b00000000
0x0FD1 OPDBRL6 16-bit MPG output data buffer register (lower) ch. 6 R/W 0b00000000
0x0FD2 OPDBRH7 16-bit MPG output data buffer register (upper) ch. 7 R/W 0b00000000
0x0FD3 OPDBRL7 16-bit MPG output data buffer register (lower) ch. 7 R/W 0b00000000
0x0FD4 OPDBRH8 16-bit MPG output data buffer register (upper) ch. 8 R/W 0b00000000
0x0FD5 OPDBRL8 16-bit MPG output data buffer register (lower) ch. 8 R/W 0b00000000
0x0FD6 OPDBRH9 16-bit MPG output data buffer register (upper) ch. 9 R/W 0b00000000
0x0FD7 OPDBRL9 16-bit MPG output data buffer register (lower) ch. 9 R/W 0b00000000
0x0FD8 OPDBRHA 16-bit MPG output data buffer reg ister (upper) ch. A R/W 0b00000000
0x0FD9 OPDBRLA 16-bit MPG output data buffer register (lower) ch. A R/W 0b00000000
0x0FDA OPDBRHB 16-bit MPG output data buffer register (upper) ch. B R/W 0b00000000
0x0FDB OPDBRLB 16-bit MPG ou tput data buffer register (lower) ch. B R/W 0b00000000
0x0FDC OPDUR 16-bit MPG output data register (upper) R 0b0000XXXX
0x0FDD OPDLR 16-bit MPG output data register (lower) R 0bXXXXXXXX
0x0FDE CPCUR 16-bit MPG compare clear register (upper) R/W 0bXXXXXXXX
0x0FDF CPCLR 16-bit MPG compare clear register (lower) R/W 0bXXXXXXXX
0x0FE0,
0x0FE1 — (Disabled) — —
MB95630H Series
DS702–00009–3v0-E 33
(Continued)
• R/W access symbols
• Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
Address Register
abbreviation Register name R/W Initial value
0x0FE2 TMBUR 16-bit MPG timer buffer register (upper) R 0bXXXXXXXX
0x0FE3 TMBLR 16-bit MPG timer buffer register (lower) R 0bXXXXXXXX
0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX
0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX
0x0FE6 — (Disabled) — —
0x0FE7 CRTDA Main CR clock temp erature dependent adjustment
register R/W 0b000XXXXX
0x0FE8 SYSC System configuration register R/W 0b11000011
0x0FE9 CMCR Clock monitoring control register R/W 0b00000000
0x0FEA CMDR Clock monitoring data register R 0b00000000
0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX
0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX
0x0FED,
0x0FEE — (Disabled) — —
0x0FEF WICR Interrupt pin selection circuit control register R/W 0b01000000
0x0FF0
to
0x0FFF — (Disabled) — —
R/W : Readable/Writable
R : Read only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
MB95630H Series
34 DS702–00009–3v0-E
■I/O POR T S
• List of port registers
R/W : Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the
read-modify-write (RMW) type of instruction.)
Register name Read/Write Initial value
Port 0 data register PDR0 R, RM/W 0b00000000
Port 0 direction register DDR0 R/W 0b00000000
Port 1 data register PDR1 R, RM/W 0b0000 0000
Port 1 direction register DDR1 R/W 0b00000000
Port 6 data register PDR6 R, RM/W 0b0000 0000
Port 6 direction register DDR6 R/W 0b00000000
Port F data register PDRF R, RM/W 0b00000000
Port F direction register DDRF R/W 0b00000000
Port G data register PDRG R, RM/W 0b00000000
Port G direction register DDRG R/W 0b00000000
Port 0 pull-up register PUL0 R/W 0b000000 00
Port 1 pull-up register PUL1 R/W 0b000000 00
Port 6 pull-up register PUL6 R/W 0b000000 00
Port G pull-up register PULG R/W 0b00000000
A/D input disable register (lower) AIDRL R/W 0b00000000
MB95630H Series
DS702–00009–3v0-E 35
1. Port 0
Por t 0 is a general-purpose I/O por t. This section focuses on its functions as a general-purpose I/O por t. For
details of peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware
Manual”.
(1) Port 0 configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 directio n re gister (DDR0)
• Port 0 pull-up register (PUL0)
• A/D input disable register (lower) (AIDRL)
(2) Block diagrams of port 0
• P00/INT00/AN00/CMP0_P pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT00)
• 8/10-bit A/D converter analog input pin (AN00)
• Comparator non-inverting analog input (positive input) pin (CMP0_P)
• P01/INT01/AN01/CMP0_N p in
This pin has the following peripheral functions:
• External interrupt circuit input pin (INT01)
• 8/10-bit A/D converter analog input pin (AN01)
• Comparator inverting analog input (negative input) pin (CMP0_N)
• Block diagram of P00/INT00/AN00/ CMP0_P and P01/INT01/AN01/CMP0_N
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
Internal bus
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Comparator analog input
Comparator analog input disable
Peripheral function input
Peripheral function input enable
(INT00 and INT01)
A/D analog input
Hysteresis
Pull-up
MB95630H Series
36 DS702–00009–3v0-E
• P02/INT02/AN02/SCK pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT02)
• 8/10-bit A/D converter analog input pin (AN02)
• LIN-UART clock I/O pin (SCK)
• P03/INT03/AN03/SOT pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT03)
• 8/10-bit A/D converter analog input pin (AN03)
• LIN-UART dat a output pin (SOT)
• P05/INT05/AN05/TO00 pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT05)
• 8/10-bit A/D converter analog input pin (AN05)
• 8/16-bit composite timer ch. 0 output pin (TO00)
• P06/INT06/AN06/TO01 pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT06)
• 8/10-bit A/D converter analog input pin (AN06)
• 8/16-bit composite timer ch. 0 output pin (TO01)
• Block diagram of P02/INT02/AN02/SCK, P03/INT03/AN03/SOT, P05/INT05/AN05/TO00 and
P06/INT06/AN06/TO01
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
(INT02, INT03, INT05 and INT06)
Peripheral function output enable
Peripheral function output
A/D analog input
HysteresisPull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 37
• P04/INT04/AN04/SIN/EC0 pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT04)
• 8/10-bit A/D converter analog input pin (AN04)
• LIN-UART data input pin (SIN)
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
• Block diagram of P04/INT04/AN04/SIN/EC0
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable (INT04) A/D analog input
CMOSPull-up
Internal bus
MB95630H Series
38 DS702–00009–3v0-E
• P07/INT07/AN07 pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT07)
• 8/10-bit A/D converter analog input pin (AN07)
• Block diagram of P07/INT07/AN07
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable (INT07) A/D analog input
Hysteresis
Pull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 39
(3) Port 0 registers
• Port 0 register functions
• Correspondence between registers and pins for port 0
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR0 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR0 va lue is “1”. As output port, outputs “H” level.
DDR0 0 Port input enabled
1 Port output enabled
PUL0 0 Pull-up disabled
1 Pull-up enabled
AIDRL 0 Analog input enabled
1 Port input enabled
Correspondence between related register bits and pins
Pin name P07 P06 P05 P04 P03 P02 P01 P00
PDR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR0
PUL0
AIDRL
MB95630H Series
40 DS702–00009–3v0-E
(4) Port 0 operations
• Operation as an outpu t po rt
• A pin becomes an output port if the bit in the DDR0 register correspondin g to that pin is set to “1”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
• If data is written to the PDR0 register , the v alue is stored in the output latch and is output to the pin set as
an output port as it is.
• Reading the PDR0 register returns the PDR0 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the
A/D input disable register (lower) (AIDRL) to “1”.
• If data is written to the PDR0 regist er, the v alue is stored in the o utput latch b ut is not out put to the pin se t
as an input port.
• Reading the PDR0 re gister returns the pin v alue. Ho wev er , if the read -modify-write (RMW) type of instruc-
tion is used to read th e PDR0 register, the PDR0 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the
output enable bit of a peripheral function corresponding to that pin.
• The pin v alue can be read f rom the PDR0 register e v en if the peripheral function o utput is enabl ed. There-
fore, the output value of a peripheral function can be read by the read operation on the PDR0 register.
However, if the read- modify- write (RMW) type of instruction is used to read the PDR0 registe r, the PDR0
register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an inp ut port, set the bit in the DDR0 register corresponding to the input pin of a peripheral
function to “0”.
• When using a pin shared with the analog input function as anot her peripheral functio n input pin, configure
it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”.
• Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that
pin as its input p in. However, if t he r ead-mo dif y-write (RMW) type of instruction is used t o re ad t he PDR0
register, the PDR0 register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin
shared with analog inpu t, its port input is disabled because the AIDRL register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits
to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless
of the DDR0 register value. The input of that pin is loc ked to “L” le v el and block ed in order to pre vent leaks
due to input open. Howe v er , if the interrupt input is enabled f or the external interrupt (INT00 to INT07), the
input is enabled and not blocked.
• If the pin state setting bit is “0”, the state of the por t I/O or that of the peripheral function I/O remains un-
changed and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR0 reg ist er bit corr espond ing t o the anal og input pin to “0” an d the bit cor resp ond ing
to that pin in the AIDRL register to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addi-
tion, set the corresponding bit in the PUL0 register to “0” .
MB95630H Series
DS702–00009–3v0-E 41
• Operation as an external interrupt input pin
• Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• The pin value is always input to the extern al interrup t circuit. When using a pin for a function o ther than
the interrupt, disable the external interrupt function corresponding to that pin.
• Operation of the pull-up register
Setting the bit in the PUL 0 register to “1” makes the pull-up resisto r be inte rnally connected to the pin. When
the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.
• Operation as a comparator input pin (only for P00 and P01)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of th e value of th e PDR0 register and that of the DDR0 register , if the compar ator analog input
enable bit in the comparator control register (CMR0C:VCID) is set to “0”, the comparator input function is
enabled.
• To disable the comparator inp ut function, set the VCID bit to “1”.
• For details of the comparator, refer to “CHAPTER 27 COMPARATOR” in “New 8FX MB95630H Series
Hardware Manual”.
MB95630H Series
42 DS702–00009–3v0-E
2. Port 1
Por t 1 is a general-purpose I/O por t. This section focuses on its functions as a general-purpose I/O por t. For
details of peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware
Manual”.
(1) Port 1 configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 directio n re gister (DDR1)
• Port 1 pull-up register (PUL1)
(2) Block diagrams of port 1
• P10/PPG1 0/C MP0_O pin
This pin has the following peripheral funct ions:
• 8/16-bit PPG ch. 1 output pin (PPG10)
• Comparator digital output pin (CMP0_O)
• P11/PPG11 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• P13/PPG00 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG00)
• P15/UO0/PPG20 pin
This pin has the following peripheral funct ions:
• UART/SIO ch. 0 data output pin (UO0)
• 8/16-bit PPG ch. 2 output pin (PPG20)
• Block diagram of P10/PPG10/CMP0_O, P11/PPG11, P13/PPG00 and P15/UO0/PPG20
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function output
HysteresisPull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 43
• P12/DBG/EC0 pin
This pin has the following peripheral funct ions:
• DBG input pin (DBG)
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
• Block diagram of P12/DBG/EC0
• P14/UCK0/PPG01 pin
This pin has the following peripheral funct ions:
• UART/SIO ch. 0 clock I/O pin (UCK0)
• 8/16-bit PPG ch. 0 output pin (PPG01)
• Block diagram of P14/UCK0/PPG01
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
DDR1
0
1
Stop mode, watch mode (SPL = 1)
OD
Hysteresis
Internal bus
Peripheral function input
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
HysteresisPull-up
Internal bus
MB95630H Series
44 DS702–00009–3v0-E
• P16/UI0/PPG21 pin
This pin has the following peripheral funct ions:
• UART/SIO ch. 0 data input pin (UI0)
• 8/16-bit PPG ch. 2 output pin (PPG21)
• Block diagram of P16/UI0/PPG21
• P17/TO1/SNI0 pin
This pin has the following peripheral functions:
• 16-bit reload timer ch. 1 output pin (TO1)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI0)
• Block diagram of P17/TO1/SNI0
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
CMOS
Pull-up
Internal bus
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function input
Peripheral function output
HysteresisPull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 45
(3) Port 1 registers
• Port 1 register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 1
*: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12
is not affected b y the setting of bit2 in the PUL1 register.
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR1 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.*
DDR1 0 Port input enabled
1 Port output enabled
PUL1 0 Pull-up disabled
1 Pull-up enabled
Correspondence between related register bits and pins
Pin name P17 P16 P15 P14 P13 P12 P11 P10
PDR1 bit7 bit6 bit5 bit4 bit3 bit2* bit1 bit0DDR1
PUL1
MB95630H Series
46 DS702–00009–3v0-E
(4) Port 1 operations
• Operation as an outpu t po rt
• A pin becomes an output port if the bit in the DDR1 register correspondin g to that pin is set to “1”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
• If data is written to the PDR1 register , the v alue is stored in the output latch and is output to the pin set as
an output port as it is.
• Reading the PDR1 register returns the PDR1 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• If data is written to the PDR1 regist er, the v alue is stored in the o utput latch b ut is not out put to the pin se t
as an input port.
• Reading the PDR1 re gister returns the pin v alue. Ho wev er , if the read -modify-write (RMW) type of instruc-
tion is used to read th e PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the
output enable bit of a peripheral function corresponding to that pin.
• The pin v alue can be read f rom the PDR1 register e v en if the peripheral function o utput is enabl ed. There-
fore, the output value of a peripheral function can be read by the read operation on the PDR1 register.
However, if the read- modify- write (RMW) type of instruction is used to read the PDR1 registe r, the PDR1
register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an inp ut port, set the bit in the DDR1 register corresponding to the input pin of a peripheral
function to “0”.
• Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that
pin as its input p in. However, if t he r ead-mo dif y-write (RMW) type of instruction is used t o re ad t he PDR1
register, the PDR1 register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits
to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless
of the DDR1 register value. The input of that pin is loc ked to “L” le v el and block ed in order to pre vent leaks
due to input open. However, if the interrupt input of P14/UCK0 and P16/UI0 is enabled by the external
interrupt control regist er ch. 0 (EIC00) of the e xternal interrupt circuit and the interrupt pin selection circui t
control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the por t I/O or that of the peripheral function I/O remains un-
changed and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL 1 register to “1” makes the pull-up resisto r be inte rnally connected to the pin. When
the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register.
MB95630H Series
DS702–00009–3v0-E 47
3. Port 6
Por t 6 is a general-purpose I/O por t. This section focuses on its functions as a general-purpose I/O por t. For
details of peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware
Manual”.
(1) Port 6 configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 directio n re gister (DDR6)
• Port 6 pull-up register (PUL6)
(2) Block diagrams of port 6
• P60/INT08/SDA/DTTI pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT08)
•I
2C bus inte rface ch. 0 data I/O pin (SDA)
• MPG waveform sequencer input pin (DTTI)
• P61/INT09/SCL/TI1 pin
This pin has the following peripheral funct ions:
• External interrupt circuit input pin (INT09)
•I
2C bus inte rface ch. 0 clock I/O pin (SCL)
• 16-bit reload timer ch. 1 input pin (TI1)
• Block diagram of P60/INT08/SDA/DTTI and P61/INT09/SCL/TI1
PDR6
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
DDR6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
(INT08 and INT09)
Peripheral function output enable
Peripheral function output
CMOS
Pin
OD
Internal bus
MB95630H Series
48 DS702–00009–3v0-E
• P62/T O10/PPG00/OPT0 pin
This pin has the following peripheral funct ions:
• 8/16-bit composite timer ch. 1 output pin (TO10)
• 8/16-bit PPG ch. 0 output pin (PPG00)
• MPG waveform sequencer output pin (OPT0)
• P63/T O11/PPG01/OPT1 pin
This pin has the following peripheral funct ions:
• 8/16-bit composite timer ch. 1 output pin (TO11)
• 8/16-bit PPG ch. 0 output pin (PPG01)
• MPG waveform sequencer output pin (OPT1)
• P65/PPG11/OPT3 pin
This pin has the following peripheral funct ions:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• MPG waveform sequencer output pin (OPT3)
• P66/PPG20/PPG1/OPT4 pin
This pin has the following peripheral funct ions:
• 8/16-bit PPG ch. 2 output pin (PPG20)
• 16-bit PPG timer ch. 1 outp ut pin (PPG1)
• MPG waveform sequencer output pin (OPT4)
• Block diagram of P62/TO10/PPG00/OPT0, P63/TO 11/PPG01/OPT1, P65/PPG11/OPT3 and
P66/PPG20/PPG1/OPT4
PDR6 Pin
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
PUL6 read
PUL6 write
DDR6
PUL6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function output
HysteresisPull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 49
• P64/EC1/PPG10/OPT2 pin
This pin has the following peripheral funct ions:
• 8/16-bit composite timer ch. 1 clock input pin (EC1)
• 8/16-bit PPG ch. 1 output pin (PPG10)
• MPG waveform sequencer output pin (OPT2)
• P67/PPG21/TRG1/OPT5 pin
This pin has the following peripheral funct ions:
• 8/16-bit PPG ch. 2 output pin (PPG21)
• 16-bit PPG timer ch. 1 trigger input pin (TRG1)
• MPG waveform sequencer output pin (OPT5)
• Block diagram of P64/EC1/PPG10/OPT2 and P67/PPG21/TRG1/OPT5
PDR6 Pin
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
PUL6 read
PUL6 write
DDR6
PUL6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
HysteresisPull-up
Internal bus
MB95630H Series
50 DS702–00009–3v0-E
(3) Port 6 registers
• Port 6 register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 6
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR6 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level.*
DDR6 0 Port input enabled
1 Port output enabled
PUL6 0 Pull-up disabled
1 Pull-up enabled
Correspondence between related register bits and pins
Pin name P67 P66 P65 P64 P63 P62 P61 P60
PDR6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR6
PUL6 --
MB95630H Series
DS702–00009–3v0-E 51
(4) Port 6 operations
• Operation as an outpu t po rt
• A pin becomes an output port if the bit in the DDR6 register correspondin g to that pin is set to “1”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.
• If data is written to the PDR6 register , the v alue is stored in the output latch and is output to the pin set as
an output port as it is.
• Reading the PDR6 register returns the PDR6 register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• If data is written to the PDR6 regist er, the v alue is stored in the o utput latch b ut is not out put to the pin se t
as an input port.
• Reading the PDR6 re gister returns the pin v alue. Ho wev er , if the read -modify-write (RMW) type of instruc-
tion is used to read th e PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the
output enable bit of a peripheral function corresponding to that pin.
• The pin v alue can be read f rom the PDR6 register e v en if the peripheral function o utput is enabl ed. There-
fore, the output value of a peripheral function can be read by the read operation on the PDR6 register.
However, if the read- modify- write (RMW) type of instruction is used to read the PDR6 registe r, the PDR6
register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an inp ut port, set the bit in the DDR6 register corresponding to the input pin of a peripheral
function to “0”.
• Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that
pin as its input p in. However, if t he r ead-mo dif y-write (RMW) type of instruction is used t o re ad t he PDR6
register, the PDR6 register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits
to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless
of the DDR6 register value. The input of that pin is loc ked to “L” le v el and block ed in order to pre vent leaks
due to input open . Ho w ever, if the int errupt input from t he external int errupt (INT08, INT09) is enabled, or
if the interrupt input of P6 4/EC1 and P67/TRG1 is e na bled by the external in te rrupt control re gis ter c h. 0
(EIC00) of the e xternal interrupt circuit and the interrupt pin selection circuit control registe r (WICR) of the
interrupt pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the por t I/O or that of the peripheral function I/O remains un-
changed and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL 6 register to “1” makes the pull-up resisto r be inte rnally connected to the pin. When
the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.
MB95630H Series
52 DS702–00009–3v0-E
4. Port F
Por t F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For
details of peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware
Manual”.
(1) Port F configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
(2) Block diagrams of port F
• PF0/X0 pin
This pin has the following peripheral function:
• Main clock input oscillation pin (X0)
• PF1/X1 pin
This pin has the following peripheral function:
• Main clock I/O oscillation pin (X1)
• Block diagram of PF0/X0 and PF1/X1
PDRF Pin
PDRF read
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF write
DDRF
0
1
Stop mode, watch mode (SPL = 1)
Internal bus
Hysteresis
MB95630H Series
DS702–00009–3v0-E 53
•PF2/RST pin
This pin has the following peripheral function:
• Reset pin (RST)
• Block diagram of PF2/RST
PDRF
PDRF read
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF write
DDRF
0
1
1
0
Stop mode, watch mode (SPL = 1)
Reset input
Reset input enable
Reset output enable
Reset output
Pin
OD
Internal bus
Hysteresis
MB95630H Series
54 DS702–00009–3v0-E
(3) Port F registers
• Port F register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port F
*: PF2/RST is the dedicated reset pin on MB95F632H/F633H/F634H/F636H.
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDRF 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.*
DDRF 0 Port input enabled
1 Port output enabled
Correspondence between related register bits and pins
Pin name - - - - - PF2* PF1 PF0
PDRF - - - - - bit2 bit1 bit0
DDRF
MB95630H Series
DS702–00009–3v0-E 55
(4) Port F operations
• Operation as an outpu t po rt
• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
• If data is written to the PDRF reg ister, the v alue is stored in th e output latch and is output to the p in set as
an output port as it is.
• Reading the PDRF register returns the PDRF register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• If data is written to the PDRF register, the v a lue is stored in t he output lat ch b ut is not out put to the pin set
as an input port.
• Reading the PDRF reg ister returns the pin value . Howe ver , if the read-modify-write (RMW) type of inst ruc-
tion is used to read th e PDRF register, the PDRF register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits
to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless
of the DDRF registe r v alue. The input of that pin is loc k ed to “L” le v el and b loc k ed in order to pre v ent le aks
due to input open.
• If the pin state setting bit is “0”, the state of the por t I/O or that of the peripheral function I/O remains un-
changed and the output level is maintained.
MB95630H Series
56 DS702–00009–3v0-E
5. Port G
Port G is a general-pur pose I/O por t. This section focuses on its functions as a general-purpose I/O por t. For
details of peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware
Manual”.
(1) Port G configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data reg iste r (PDR G )
• Port G directio n re gister (DDRG)
• Port G pull-up register (PULG)
(2) Block diagram of port G
• PG1/X0A/SNI1 pin
This pin has the following peripheral funct ions:
• Subclock input oscillation pin (X0A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI1)
• PG2/X1A/SNI2 pin
This pin has the following peripheral funct ions:
• Subclock I/O oscillation pin (X1A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI2)
• Block diagram of PG1/X0A/SNI1 and PG2/X1A/SNI2
PDRG Pin
PDRG read
PDRG write
Executing bit manipulation instruction
DDRG read
DDRG write
PULG read
PULG write
DDRG
PULG
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Hysteresis
Pull-up
Internal bus
MB95630H Series
DS702–00009–3v0-E 57
(3) Port G registe rs
• Port G register functions
• Correspondence between registers and pins for port G
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDRG 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level.
DDRG 0 Port input enabled
1 Port output enabled
PULG 0 Pull-up disabled
1 Pull-up enabled
Correspondence between related register bits and pins
Pin name - - - - - PG2 PG1 -
PDRG -----bit2bit1-DDRG
PULG
MB95630H Series
58 DS702–00009–3v0-E
(4) Port G operations
• Operation as an outpu t po rt
• A pin becomes an output port if the bit in the DDRG register correspondin g to that pin is set to “1”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
• If data is writ ten to the PDRG regi ster, the value is stored in the output latch and is output to the pin set
as an output port as it is.
• Reading the PDRG register returns the PDRG register value.
• Operation as an input port
• A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, d isable the output of such peripheral functions.
• If data is written to t he PDRG register, the v alue is stored in the output latch b ut is not o utput to the pin set
as an input port.
• Reading the PDRG register returns the pin v alue. Howev er , if the read-modify-write (RMW) type of instruc-
tion is used to read the PDRG register, the PDRG register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDRG regist er corresponding to the input p in of a peripheral
function to “0”.
• Reading the PDRG r egister re turns the pi n value, regardless of whether the p eripheral function uses that
pin as its input pin. Ho we v er, if the read- modify-write (RMW) type of instruction is used to read the PDRG
register, the PDRG register value is returned.
• Operation at reset
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits
to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless
of the DDRG re gister v alue. The inp ut of that pin is lock ed to “L” le v el and b lock ed in order to pre vent le aks
due to input open.
• If the pin state setting bit is “0”, the state of the por t I/O or that of the peripheral function I/O remains un-
changed and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When
the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register.
MB95630H Series
DS702–00009–3v0-E 59
■INTERRUPT SOURCE TABLE
Interrupt source Interrupt
request
number
Vector table
address Interrupt level
setting register Priority order of
interrupt sources
of the same level
(occurring
simultaneously)
Upper Lower Register Bit
External interrupt ch. 0 IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] High
Low
External interrupt ch. 4
External interrupt ch. 1 IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0]
External interrupt ch. 5
External interrupt ch. 2 IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0]
External interrupt ch. 6
External interrupt ch. 3 IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0]
External interrupt ch. 7
UART/SIO ch . 0 IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0]
MPG (DTTI)
8/16-bit composite timer ch. 0
(lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0]
8/16-bit composite timer ch. 0
(upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0]
LIN-UAR T (reception) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0]
LIN-UART (transmission) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0]
8/16-bit PPG ch. 1 (lower) IRQ09 0xFFE8 0xFFE9 I LR2 L09 [1:0]
8/16-bit PPG ch. 1 (upper) IRQ10 0xFFE6 0xFFE7 I LR2 L10 [1:0]
8/16-bit PPG ch. 2 (upper) IRQ11 0xFFE4 0xFFE5 I LR2 L11 [1:0]
8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 I LR3 L12 [1:0]
8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 I LR3 L13 [1:0]
8/16-bit composite timer ch. 1
(upper) IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0]
8/16-bit PPG ch. 2 (lower) IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0]
16-bit reload timer ch. 1 IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0]MPG (write timing/compare clear)
I2C bus interface
16-bit PPG timer ch. 1 IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0]
MPG (position detection/ compare
interrupt)
8/10-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0]
Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0]
Watc h prescaler IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0]
Comparator
External interrupt ch. 8 IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0]
External interrupt ch. 9
8/16-bit composite timer ch. 1
(lower) IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0]
Flash memory IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0]
MB95630H Series
60 DS702–00009–3v0-E
■PIN STATES IN EACH MODE
(Continued)
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
PF0/X0
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4I/O port*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PF1/X1
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4I/O port*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PG1/X0A/
SNI1
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4/
peripheral func-
tion I/O
I/O port*4/
peripheral func-
tion I/O
- Previous state
kept
- Input
blocked*2*4
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PG2/X1A/
SNI2
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4/
peripheral
function I/O
I/O port*4/
peripheral
function I/O
- Previous state
kept
- Input
blocked*2*4
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PF2/RST I/O port Reset input Reset input Reset input Reset input Reset input Reset input*3
P60/INT08/
SDA/DTTI
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P61/INT09/
SCL/TI1
P62/TO10/
PPG00/
OPT0 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P63/TO11/
PPG01/
OPT1
MB95630H Series
DS702–00009–3v0-E 61
(Continued)
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P64/EC1/
PPG10/
OPT2
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P65/PPG11/
OPT3 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P66/PPG1/
PPG20/
OPT4
P67/TRG1/
PPG21/
OPT5
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P10/PPG10/
CMP0_O I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P11/PPG11
P12/DBG/
EC0
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P13/PPG00 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
MB95630H Series
62 DS702–00009–3v0-E
(Continued)
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P14/UCK0/
PPG01
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P15/UO0/
PPG20
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P16/UI0/
PPG21
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P17/TO1/
SNI0
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P00/INT00/
AN00/
CMP0_P
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
blocked*2
P01/INT01/
AN01/
CMP0_N
P02/INT02/
AN02/SCK
P03/INT03/
AN03/SOT
MB95630H Series
DS702–00009–3v0-E 63
(Continued)
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1:“Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or
pull-down operation has to be perfor med in order to prevent leaks due to exter nal input. If a pin is used as
an output port, its pin state is the same as that of other ports.
*2:“Input blocked” means direct input gate operation from the pin is disabled.
*3:The PF2/RST pin stays at the state shown when configured as a reset pin.
*4:The pin stays at the state shown when configured as a general-purpose I/O port.
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P04/INT04/
AN04/SIN/
EC0
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the exter nal
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z(However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
blocked*2
P05/INT05/
AN05/TO00
P06/INT06/
AN06/TO01
P07/INT07/
AN07
MB95630H Series
64 DS702–00009–3v0-E
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1VCC VSS − 0.3 VSS + 6V
Input voltage*1VIVSS − 0.3 VSS + 6V*2
Output voltage*1VOVSS − 0.3 VSS + 6V*2
Maximum clamp current ICLAMP −2+2 mA Applicable to specific pins*3
Total maximum clamp
current Σ|ICLAMP| — 20 mA Applicable to specific pins*3
“L” level maximum
output current IOL —15mA
“L” level average current
IOLAV1
—
4
mA
Other than P62 to P67
Average output current =
operat ing current × operating ratio (1 pin)
IOLAV2 12 P62 to P67
Average output current =
operat ing current × operating ratio (1 pin)
“L” level total maximum
output current ΣIOL — 100 mA
“L” level total average
output current ΣIOLAV —37mA
Total average output current =
operat ing current × operating ratio
(Total number of pins)
“H” level maximu m
output current IOH —−15 mA
“H” le vel a ver age current
IOHAV1
—
−4
mA
Other than P62 to P67
Average output current =
operat ing current × operating ratio (1 pin)
IOHAV2 −8P62 to P67
Average output current =
operat ing current × operating ratio (1 pin)
“H” level total maximu m
output current ΣIOH —−100 mA
“H” level total average
output current ΣIOHAV —−47 mA Total average output current =
operat ing current × operating ratio
(Total number of pins)
Power consumption Pd— 320 mW
Operating temperature TA−40 +85 °C
Storage temperature Tstg −55 +150 °C
MB95630H Series
DS702–00009–3v0-E 65
(Continued)
*1:These parameters are based on the condition that VSS is 0.0 V.
*2:V1 and V0 must not exceed VCC + 0.3 V. V1 must not exceed the rated voltage. However, if the maximum
current to /from an inpu t is limited by means of an external c omponent, th e ICLAMP rating is used instea d of
the VI rating.
*3:Specif ic pins: P00 to P07, P10, P11, P13 to P17, P62 to P67, PF0, PF1, PG1, PG2
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High V oltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High V oltage) signal and the microcontroller before applying the HV (High V oltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High V oltage) signa l is input when the microcontro ller power supply is off ( not fixe d at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Vo ltage) input pin unconnected.
• Example of a recommended circuit:
W ARNING: Semiconductor de vices may be permanently damaged b y application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
HV(High V oltage) input (0 V to 16 V)
Protective diode
VCC
N-ch
P-ch
R
Limiting
resistor
• Input/Output equivalent circuit
MB95630H Series
66 DS702–00009–3v0-E
2. Recommended Operat ing Conditions (VSS = 0.0 V)
*1:The minim um po w er supp ly v olta ge becomes 2 .88 V when a product wit h the lo w-v olt age detect ion reset is
used or when the on-chip debu g mode is used.
*2:Use a cera mic capa citor or a capacitor wit h equivalent frequency charact eristics. Th e deco upling capacit or
for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection
to a decoupling ca pacitor CS, see the diag ram belo w . To prev en t the de vice from unintent ionally entering an
unknown mod e due to noise, minimiz e the distance betw een the C pin and C S and the distance bet ween CS
and the VSS pin when designing the la yout of a printed circuit board.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could res ult in device failu re .
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand .
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage VCC 2.4*15.5 VIn normal operation
2.3 5.5 Hold condition in stop mode
Decoupling capacitor CS0.022 1 µF *2
Operating temperature TA− 40 +85 °COther than on-chip debug mode
+5+35 On-chip debug mode
C
Cs
DBG
*
RST
• DBG / RST / C pins connection diagram
*: Connect the DBG pin to an e xternal pull-up resistor of 2 k Ω or abov e. After power-on, ensure that the
DBG pin does not st a y at “L” le ve l until the reset out put is released. The DBG pi n becomes a comm u-
nication pin in deb ug mode. Since the actual pull-up resistance dep ends on the too l used an d the in-
terconnection length, refer to the tool document wh en selecting a pull-up resistor.
MB95630H Series
DS702–00009–3v0-E 67
3. DC Characteri st ic s (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
input
voltage
VIHI P04, P16, P60,
P61 — 0.7 VCC —VCC + 0.3 V CMOS input level
VIHS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
— 0.8 VCC —VCC + 0.3 V Hysteresis input
VIHM PF2 — 0.8 VCC —VCC + 0.3 V Hysteresis input
“L” level
input
voltage
VILI P04, P16, P60,
P61 —V
SS − 0.3 — 0.3 VCC V CMOS input level
VILS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
—V
SS − 0.3 — 0.2 VCC V Hysteresis input
VILM PF2 — VSS − 0.3 — 0.2 VCC V Hysteresis input
Open-drain
output
application
voltage
VDP12, P60, P61,
PF2 —V
SS − 0.3 — Vss + 5.5 V
“H” level
output
voltage
VOH1
Output pins
other than P12,
P62 to P67,
PF2
IOH = −4 mA VCC − 0.5 — — V
VOH2 P62 to P67 IOH = −8 mA VCC − 0.5 — — V
“L” level
output
voltage
VOL1 Output pins
other than P62
to P67 IOL = 4 mA — — 0.4 V
VOL2 P62 to P67 IOL = 12 mA — — 0.4 V
Input leak
current (Hi-Z
output leak
current)
ILI All input
pins 0.0 V < VI < VCC −5—+5µA
When the internal
pull-up resistor is
disabled
Internal
pull-up
resistor RPULL
P00 to P07,
P10, P11,
P13 to P17,
P62 to P67,
PG1, PG2
VI = 0 V 25 50 100 kΩWhen the internal
pull-up resistor is
enabled
Input
capacitance CIN Other than VCC
and VSS f = 1 MHz — 5 15 pF
MB95630H Series
68 DS702–00009–3v0-E
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ*1Max*2
Power
supply
current*3
ICC
VCC
(External clock
operation)
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
—3.65.8mA
Except during
Flash memory
programming and
erasing
—7.513.8mA
During Flash
memory
programming and
erasing
— 4.1 9.1 mA At A/D conversion
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—1.3 3mA
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
— 49 145 µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—1015µA
In deep standby
mode
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
— 7 13 µA In deep standby
mode
ICCMPLL
VCC
FMCRPLL = 16 MHz
FMP = 16 MHz
Main CR PLL clock
mode
(multiplied by 4)
TA = +25°C
—4.76.8mA
ICCMCR
FCRH = 4 MHz
FMP = 4 MHz
Main CR clock
mode
—1.14.6mA
ICCSCR Sub-CR clock mode
(divided by 2)
TA = +25°C — 58.1 230 µA
ICCTS VCC
(External clock
operation)
FCH = 32 MHz
Time-base timer
mode
TA = +25°C
— 345 395 µA In deep standby
mode
ICCH Substop mode
TA = +25°C —610µA
In deep standby
mode
MB95630H Series
DS702–00009–3v0-E 69
(Continued) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85°C)
*1:VCC = 5.0 V, TA = +25°C
*2:VCC = 5.5 V, TA = +85°C (unless otherwise specified)
*3:• The power supply current is determined by the external clock. When the low-voltage detection circuit is
selected, the po wer supply curren t is the sum of adding t he current consump tion of the low-v oltage det ec-
tion circuit (ILVD) to one of the v alue s fro m ICC to ICCH. In addition, whe n both the low-voltage det ection op-
tion and the CR oscillator are selected, the power supply current is the sum of adding up the current
consumption of th e low-v oltage detection cir cuit (ILVD), the current consumption of the CR oscillators (ICRH,
ICRL) and a specified value . In on-chip debug mode, the CR oscillator (ICRH) and t he low-v oltag e detect ion
circuit are always in operation, and current consumption therefore increases accordingly.
• See “4. AC Characteristics (1) Clock Timing” for FCH, FCL, FCRH and FMCRPLL.
• See “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
• The power supply current value in standby mode is measured in deep standby mode. The current con-
sumption in normal standby is highe r than tha t in deep st an dby mode. The power supp ly curre nt value in
normal standby can be found by adding the current consumption difference between normal standby
mode and deep standby mode (INSTBY) to the power supply current value in deep standby mode. For de-
tails of normal standby and deep standby mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New
8FX MB95630H Series Hardware Manual”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ*1Max*2
Power
supply
current*3
IV
VCC
Current
consumption of the
comparator — 60 160 µA
ILVD
Current
consumption of the
low-voltage
detection circuit
—4 7µA
ICRH Current
consumption of the
main CR oscillator — 240 320 µA
ICRL
Current
consumption of the
sub-CR oscillator
oscillating at
100 kHz
—720µA
INSTBY
Current
consumption
difference between
normal standby
mode and deep
standby mode
TA = +25°C
—2030µA
MB95630H Series
70 DS702–00009–3v0-E
4. AC Characteristics
(1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock
frequency
FCH
X0, X1 — 1 — 16.25 MHz When the main oscillation
circuit is used
X0 X1: open 1 — 12 MHz When the main external clock
is used
X0, X1 * 1 — 32.5 MHz
FCRH ——
3.92 4 4.08 MHz Operating conditions
• The main CR clock is used.
•0°C ≤ TA ≤ +70°C
3.844.2MHz
Operating conditions
• The main CR clock is used.
•− 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
FMCRPLL ——
7.84 8 8.16 MHz Operating conditions
• PLL multiplication rate: 2
•0°C ≤ TA ≤ +70°C
7.688.4MHz
Operating conditions
• PLL multiplication rate: 2
•− 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
9.8 10 10.2 MHz Operating condi tions
• PLL multiplication rate: 2.5
•0°C ≤ TA ≤ +70°C
9.5 10 10.5 MHz
Operating conditions
• PLL multiplication rate: 2.5
•− 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
11.76 12 12.24 MHz Operating conditions
• PLL multiplication rate: 3
•0°C ≤ TA ≤ +70°C
11.4 12 12.6 MHz
Operating conditions
• PLL multiplication rate: 3
•− 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
15.68 16 16.32 MHz Operating conditions
• PLL multiplication rate: 4
•0°C ≤ TA ≤ +70°C
15.2 16 16.8 MHz
Operating conditions
• PLL multiplication rate: 4
•− 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
FCL X0A, X1A — — 32.768 — kHz When the suboscillation
circuit is used
— 32.768 — kHz When the sub-exter n al clock
is used
FCRL — — 50 100 150 kHz When the sub-CR clock is
used
MB95630H Series
DS702–00009–3v0-E 71
(Continued) (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock cycle
time tHCYL
X0, X1 ⎯61.5 ⎯1000 ns When the main oscillation
circuit is used
X0 X1: open 83.4 ⎯1000 ns When an external clock is
used
X0, X1 * 30.8 ⎯1000 ns
tLCYL X0A, X1A ⎯⎯30.5 ⎯µs When the subclock is used
Input clock
pulse width tWH1, tWL1 X0 X1: open 33.4 ⎯⎯ns When an exter nal clock is
used, the duty ratio should
range between 40% and 60%.
X0, X1 * 12.4 ⎯⎯ns
tWH2, tWL2 X0A ⎯—15.2⎯µs
Input clock
rising time and
falling time tCR, tCF
X0, X0A X1: open — ⎯5ns
When an exter nal clock is
used
X0, X1,
X0A, X1A *——5ns
CR oscillation
start ti me
tCRHWK ————50µs
When the main CR clock is
used
tCRLWK ————30µs
When the sub-CR clock is
used
PLL oscillation
start ti me tMCRPLLWK ————100µs
When the main CR PLL cloc k
is used
MB95630H Series
72 DS702–00009–3v0-E
X0, X1 0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
tWH1 tWL1
0.2 VCC
tHCYL
tCR tCF
• Input waveform generated when an external clock (main clock) is used
When a crystal oscillator or
a ceramic oscillator is used When an external clock
is used
X0 X1 X0 X1
FCH FCH
When an external clock is used
(X1 is open)
X0 X1
Open
FCH
• Figure of main clock input port external connection
X0A 0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
tWH2 tWL2
0.2 VCC
tLCYL
tCR tCF
• Input waveform generated when an external clock (subclock) is used
When a crystal oscillator or
a ceramic oscillator is used When an external clock
is used
X0A X1A X0A X1A
Open
F
CL
F
CL
• Figure of subclock input port external connection
tCRHWK 1/FCRH
Main CR clock
Oscillation startsOscillation stabilizes
• Input waveform generated when an internal clock (main CR clock) is used
MB95630H Series
DS702–00009–3v0-E 73
tCRLWK 1/FCRL
Sub-CR clock
Oscillation startsOscillation stabilizes
• Input waveform generated when an internal clock (sub-CR clock) is used
tMCRPLLWK 1/FMCRPLL
Main CR PLL clock
Oscillation startsOscillation stabilizes
• Input waveform generated when an internal clock (main CR PLL clock) is use d
MB95630H Series
74 DS702–00009–3v0-E
(2) Source Clock/Machin e Clock (VCC = 5.0 V±10%, V SS = 0.0 V, TA = −40°C to +85°C)
*1:This is the clock before it is divided according to the division ratio set by the machine clock division ratio
select bits (SYCC: DIV[1:0]) . Th is sour ce clock is divided to b ecom e a ma chine clock according to the d ivi-
sion ratio set b y the machine clock division ratio sel ect bits (SYCC:DIV[1:0]). In addition, a source clock can
be selected from the following.
• Main clock divided by 2
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2:This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Parameter Symbol Pin
name Value Unit Remarks
Min Typ Max
Source clock
cycle time*1tSCLK —
61.5 — 2000 ns When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5 — 250 ns When th e main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, no division
—61—µs
When the suboscillation clock is used
FCL = 32.768 kHz, divided by 2
—20—µs
When the sub-CR clock is used
FCL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.5 — 16.25 MHz When the main oscillation clock is used
— 4 — MHz When the main CR clock is used
FSPL
— 16.384 — kHz When the suboscillation clock is used
— 50 — kHz When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Machine clock
cycle time*2
(minimum
instruction
ex ecution time)
tMCLK —
61.5 — 32000 ns When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250 — 4000 ns When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 16
61 — 976.5 µs When the suboscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20 — 320 µs When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
Machine clock
frequency
FMP
—
0.031 — 16.25 MHz When the main oscillation clock is used
0.25 — 16 MHz When the main CR clock is used
FMPL
1.024 — 16.384 kHz When the suboscillation clock is used
3.125 — 50 kHz When the sub-CR clock is used
FCRL = 100 kHz
MB95630H Series
DS702–00009–3v0-E 75
FCH
(Main oscillation clock) Divided by 2
Divided by 2
Divided by 2
FMCRPLL
(Main CR PLL clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
FCRL
(Sub-CR clock)
SCLK
(Source clock) MCLK
(Machine clock)
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
Clock mode select bits
(SYCC:SCS[2:0])
Division circuit
×
×
×
×
1
1/4
1/8
1/16
• Schematic diagram of the clock generation block
Operating voltage (V)
A/D converter operation range
5.5
5.0
4.0
3.5
3.0
2.7
2.4
16 kHz 3 MHz 10 MHz 16.25 MHz
Source clock frequency (F
SP
/F
SPL
)
• Operating volta ge - Operating frequency (TA = −40°C to +85°C)
MB95630H Series
76 DS702–00009–3v0-E
(3) External Reset (VCC = 5.0 V±10%, V SS = 0.0 V, TA = −40°C to +85°C)
*: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Value Unit Remarks
Min Max
RST “L” level
pulse width tRSTL 2 tMCLK*⎯ns
0.2 VCC
RST0.2 VCC
tRSTL
MB95630H Series
DS702–00009–3v0-E 77
(4) Power-on Reset (VSS = 0.0 V, TA = −40°C to +85°C)
Note: A sudden change of pow er supp ly v oltage ma y acti vat e the po wer-on reset function. When changing t he
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
Parameter Symbol Condition Value Unit Remarks
Min Max
Power supply rising time tR⎯⎯50 ms
Power supply cutoff time tOFF ⎯1⎯ms Wait time until power-on
0.2 V0.2 V
tOFF
tR
2.5 V
0.2 V
V
CC
V
CC
2.3 V
V
SS
Hold condition in stop mode
Set the slope of rising to
a value below 30 mV/ms.
MB95630H Series
78 DS702–00009–3v0-E
(5) Peripheral Input Timing (VCC = 5.0 V±10%, V SS = 0.0 V, TA = −40°C to +85°C)
*: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Value Unit
Min Max
Peripheral input “H” pulse width tILIH INT00 to INT09, EC0, EC1, TI1,
TRG1 2 tMCLK*⎯ns
Peripheral input “L” pulse width tIHIL 2 tMCLK*⎯ns
INT00 to INT09,
EC0, EC1, TI1,
TRG1
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tILIH tIHIL
MB95630H Series
DS702–00009–3v0-E 79
(6) LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, V SS = 0.0 V, TA = −40°C to +85°C)
*1:There is a fu nctio n used to choose wheth er the sa mplin g of re ce ption data is per formed at a rising edge or
a falling edge of the serial clock.
*2:The ser ial clock delay function is a function used to delay the output signal of the serial clock for half the
clock.
*3:See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK Internal clock
operation output pin:
CL = 80 pF + 1 TTL
5 tMCLK*3—ns
SCK↓ → SOT delay time tSLOVI SCK, SOT −50 +50 ns
Valid SIN → SCK↑tIVSHI SCK, SIN tMCLK*3 + 80 — ns
SCK↑ → valid SIN hold time tSHIXI SCK, SIN 0 — ns
Serial clock “L” pu lse width tSLSH SCK
Exter nal clock
operation output pin:
CL = 80 pF + 1 TTL
3 tMCLK*3−tR—ns
Serial clock “H” pulse width t SHSL SCK tMCLK*3 + 10 — ns
SCK↓ → SOT delay time tSLOVE SCK, SOT — 2 tMCLK*3 + 60 ns
Valid SIN → SCK↑tIVSHE SCK, SIN 30 — ns
SCK↑ → valid SIN hold time tSHIXE SCK, SIN tMCLK*3 + 30 — ns
SCK f alling time tFSCK — 10 ns
SCK rising time tRSCK — 10 ns
MB95630H Series
80 DS702–00009–3v0-E
0.2 VCC 0.2 VCC
0.8 VCC
t
SLOVI
tIVSHI tSHIXI
0.8 VCC
0.2 VCC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
• Internal shift clock mode
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
tSLOVE
t
IVSHE
t
SHIXE
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN 0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SLSH
t
SHSL
t
R
0.8 V
CC
t
F
• External shift clock mode
MB95630H Series
DS702–00009–3v0-E 81
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*1:There is a fu nctio n used to choose wheth er the sa mplin g of re ce ption data is per formed at a rising edge or
a falling edge of the serial clock.
*2:The ser ial clock delay function is a function used to delay the output signal of the serial clock for half the
clock.
*3:See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK Internal clock
operation output pin:
CL = 80 pF + 1 TTL
5 tMCLK*3—ns
SCK↑ → SOT delay time tSHOVI SCK, SOT −50 +50 ns
Valid SIN → SCK↓tIVSLI SCK, SIN tMCLK*3 + 80 — ns
SCK↓→ valid SIN hold time tSLIXI SCK, SIN 0 — n s
Serial clock “H” pulse width t SHSL SCK
Exter nal clock
operation output pin:
CL = 80 pF + 1 TTL
3 tMCLK*3 − tR—ns
Serial clock “L” pu lse width tSLSH SCK tMCLK*3 + 10 — ns
SCK↑ → SOT delay time tSHOVE SCK, SOT — 2 tMCLK*3 + 60 ns
Valid SIN → SCK↓tIVSLE SCK, SIN 30 — ns
SCK↓→ valid SIN hold time tSLIXE SCK, SIN tMCLK*3 + 30 — ns
SCK f alling time tFSCK — 10 ns
SCK rising time tRSCK — 10 ns
MB95630H Series
82 DS702–00009–3v0-E
0.2 VCC
0.8 VCC
0.8 VCC
t
SHOVI
tIVSLI tSLIXI
0.8 VCC
0.2 VCC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
• Internal shift clock mode
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
tSHOVE
t
IVSLE
t
SLIXE
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN 0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SHSL
t
SLSH
t
F
0.8 V
CC
t
R
• External shift clock mode
MB95630H Series
DS702–00009–3v0-E 83
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is en abled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*1:There is a fu nctio n used to choose wheth er the sa mplin g of re ce ption data is per formed at a rising edge or
a falling edge of the serial clock.
*2:The ser ial clock delay function is a function used to delay the output signal of the serial clock for half the
clock.
*3:See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
5 tMCLK*3—ns
SCK↑ → SOT delay time tSHOVI SCK, SOT −50 +50 ns
Valid SIN → SCK↓tIVSLI SCK, SIN tMCLK*3 + 80 — ns
SCK↓→ valid SIN hold time tSLIXI SCK, SIN 0 — n s
SOT → SCK↓delay time tSOVLI SCK, SOT 3tMCLK*3 − 70 — ns
0.8 VCC
0.2 VCC 0.2 VCC
tSHOVI
tSOVLI
tIVSLI tSLIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
MB95630H Series
84 DS702–00009–3v0-E
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*1:There is a fu nctio n used to choose wheth er the sa mplin g of re ce ption data is per formed at a rising edge or
a falling edge of the serial clock.
*2:The ser ial clock delay function is a function used to delay the output signal of the serial clock for half the
clock.
*3:See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
5 tMCLK*3—ns
SCK↓ → SOT delay time tSLOVI SCK, SOT −50 +50 ns
Valid SIN → SCK↑tIVSHI SCK, SIN tMCLK*3 + 80 — ns
SCK↑ → valid SIN hold time tSHIXI SCK, SIN 0 — ns
SOT → SCK↑delay time tSOVHI SCK, SOT 3tMCLK*3 − 70 — ns
0.2 VCC
0.8 VCC 0.8 VCC
tSLOVI
tSOVHI
tIVSHI tSHIXI
0.8 VCC
0.2 VCC
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
MB95630H Series
DS702–00009–3v0-E 85
(7) Low-voltage Detection (VSS = 0.0 V, TA = −40°C to +85°C)
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID
register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to
“CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT” in “New 8FX MB95630H Series Hardware
Manual”.
Parameter Symbol Value Unit Remarks
Min Typ Max
Release voltage* VDL+
2.52 2.7 2.88
V At power supply rise
2.61 2.8 2.99
2.89 3.1 3.31
3.08 3.3 3.52
Detection voltage* VDL−
2.43 2.6 2.77
V At power supply fall
2.52 2.7 2.88
2.80 3 3.20
2.99 3.2 3.41
Hysteresis width VHYS ——100mV
Power supply start
voltage Voff ——2.3V
Power supply end
voltage Von 4.9 — — V
Power supply voltage
change time
(at power supply rise) tr650 — — µs Slope of pow er supply that the reset
release signal generates within the
rati ng (VDL+)
Power supply voltage
change time
(at power supply fall) tf650 — — µs Slope of power supply that the reset
detection signal gener at es with in th e
rati ng (VDL-)
Reset release delay
time td1 ——30µs
Reset detection delay
time td2 ——30µs
LVD reset threshold
voltage transition
stabilization time tstb 10 — — µs
MB95630H Series
86 DS702–00009–3v0-E
VHYS
td2 td1
tr
tf
VCC
Von
Voff
VDL+
VDL-
time
time
Internal reset signal
MB95630H Series
DS702–00009–3v0-E 87
(8) I2C Bus Interface Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*1:R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA
lines.
*2:The maximum tHD;DAT in the Standard-mode is a pplicable only when t he time during which the de vice is hold-
ing the SCL signal at “L” (tLOW) does not extend.
*3:A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the co ndition
of tSU;DAT ≥ 250 ns is fulfilled.
Parameter Symbol Pin name Condition
Value
Unit
Standard-
mode Fast-mode
MinMaxMinMax
SCL clock fr equency fSCL SCL
R = 1.7 kΩ,
C = 50 pF*1
01000400kHz
(Repeated) START condition hold
time
SDA ↓ → SCL ↓tHD;STA SCL, SDA 4.0 — 0.6 — µs
SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs
SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs
(Repeated) START condition setup
time
SCL ↑ → SDA ↓tSU;STA SCL, SDA 4.7 — 0.6 — µs
Data hold time
SCL ↓ → SDA ↓↑ tHD;DAT SCL, SDA 0 3.45*2 00.9
*3 µs
Data setup time
SDA ↓↑ → SCL ↑tSU;DAT SCL, SDA 0.25 — 0.1 — µs
STOP condition setup time
SCL ↑ → SDA ↑tSU;STO SCL, SDA 4 — 0.6 — µs
Bus free time bet ween STOP
condition and START condition tBUF SCL, SDA 4.7 — 1.3 — µs
SDA
SCL
t
WAKEUP
t
HD;STA
t
SU;DAT
f
SCL
t
HD;STA
t
SU;STA
t
LOW
t
HD;DAT
t
HIGH
t
SU;STO
t
BUF
MB95630H Series
88 DS702–00009–3v0-E
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
(Continued)
Parameter Symbol Pin
name Condition Value*2Unit Remarks
Min Max
SCL clock “L ”
width tLOW SCL
R = 1.7 kΩ,
C = 50 pF*1
(2 + nm/2)tMCLK − 20 — ns Master mode
SCL clock
“H” width tHIGH SCL (nm/2)tMCLK − 20 (nm/2)t MCLK + 20 ns Master mode
START
condition
hold time tHD;STA SCL,
SDA (-1 + nm/2) tMCLK − 20 (-1 + nm)tMCLK + 20 ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value is
applied.
STOP
condition
setup time tSU;STO SCL,
SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode
START
condition
setup time tSU;STA SCL,
SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode
Bus free time
between
STOP
condition
and START
condition
tBUF SCL,
SDA (2 nm + 4) tMCLK − 20 — ns
Data hold
time tHD;DAT SCL,
SDA 3 t MCLK − 20 — ns Mast er mode
Data setup
time tSU;DAT SCL,
SDA (-2 + nm/2) tMCLK − 20(-1 + nm/2) tMCLK + 20 ns
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
applied to the first
bit of continuous
data. Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL (nm/2) tMCLK − 20 (1 + nm/2) tMCLK + 20 ns
The minimum
value is applied
to the interrupt at
the ninth SCL↓.
The maximum
value is applied
to the interrupt at
the eighth SCL↓.
SCL clock “L ”
width tLOW SCL 4 tMCLK − 20 — ns At reception
SCL clock
“H” width tHIGH SCL 4 tMCLK − 20 — ns At reception
MB95630H Series
DS702–00009–3v0-E 89
(Continued) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*1:R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA
lines.
*2:• See “(2) Source Clock/Machine Clock” for tMCLK.
• m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0).
• n represents th e CS[2 :0 ] bits in the I2C clock control register ch. 0 (ICCR0).
• The actual timin g of the I2C b us interf ace is determined by the v alues of m and n set b y the machine cloc k
(tMCLK) and the CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz.
The usab le fr equen cie s of t he m achine clo ck are determined by the settings of m and n as sho wn below.
(m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK ≤ 10 MHz
(m, n) = (8, 22) : 0.9 MHz < tMCLK ≤ 16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clo ck) < 16.25 MHz.
The usab le fr equen cie s of t he m achine clo ck are determined by the settings of m and n as sho wn below.
(m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK ≤ 10 MHz
(m, n) = (5, 8) : 3.3 MHz < tMCLK ≤ 16.25 MHz
Parameter Symbol Pin
name Condition Value*2Unit Remarks
Min Max
START condition
detection tHD;STA SCL,
SDA
R = 1.7 kΩ,
C = 50 pF*1
2 tMCLK − 20 — ns
No ST ART condition
is detected when 1
tMCLK is used at
reception.
STOP condition
detection tSU;STO SCL,
SDA 2 tMCLK − 20 — ns
No STOP condition
is detected when 1
tMCLK is used at
reception.
RESTART
condition detection
condition tSU;STA SCL,
SDA 2 tMCLK − 20 — ns
No RESTART
condition is
detected when 1
tMCLK is used at
reception.
Bus free time tBUF SCL,
SDA 2 tMCLK − 20 — ns At reception
Data hold time tHD;DAT SCL,
SDA 2 tMCLK − 20 — ns At slave
transmission mode
Data setup time tSU;DAT SCL,
SDA tLOW − 3 tMCLK − 20 — ns At slave
transmission mode
Data hold time tHD;DAT SCL,
SDA 0 — ns At reception
Data setup time tSU;DAT SCL,
SDA tMCLK − 20 — ns At reception
SDA↓ → SCL↑
(with wakeup
function in use) tWAKEUP SCL,
SDA
Oscillation
stabilization wait time
+2 tMCLK − 20 —ns
MB95630H Series
90 DS702–00009–3v0-E
(9) UART/SIO, Serial I/O Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
*: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC UCK0
Internal clock operation
4 tMCLK*— ns
UCK ↓ → UO time tSLOV UCK0, UO0 −190 +190 ns
Valid UI → UCK ↑tIVSH UCK0, UI0 2 tMCLK*— ns
UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK*— ns
Serial clock “H” pulse width tSHSL UCK0
External clock operation
4 tMCLK*— ns
Serial clock “L” pulse width tSLSH UCK0 4 tMCLK*— ns
UCK ↓ → UO time tSLOV UCK0, UO0 — 190 ns
Valid UI → UCK ↑tIVSH UCK0, UI0 2 tMCLK*— ns
UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK*— ns
0.2 V
CC
0.2 V
CC
0.8 V
CC
t
SLOV
t
IVSH
t
SHIX
0.8 V
CC
0.2 V
CC
UCK0
UO0
UI0 0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SCYC
• Internal shift clock mode
t
SLOV
t
IVSH
t
SHIX
0.8 V
CC
0.2 V
CC
UCK0
UO0
UI0 0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
t
SLSH
t
SHSL
• External shift clock mode
MB95630H Series
DS702–00009–3v0-E 91
(10) MPG Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTIWH,
tTIWL SNI0 to SNI2,
DTTI —4 t
MCLK —ns
0.8 VCC
SNI0 to SNI2, DTTI 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
MB95630H Series
92 DS702–00009–3v0-E
(11) Comparator Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Pin name Value Unit Remarks
Min Typ Max
Voltage range CMP0_P,
CMP0_N 0—V
CC − 1.3 V
Offset voltage CMP0_P,
CMP0_N −15 — +15 mV
Delay time CMP0_O — 650 1200 ns Overdr ive 5 mV
— 140 420 ns Overdr ive 50 mV
Power down delay CMP0_O — — 1200 ns Power down recovery
PD: 1 → 0
Power up
stabilization time CMP0_O — — 1200 ns Output stabilization time at power up
MB95630H Series
DS702–00009–3v0-E 93
5. A/D Converter
(1) A/D Converter Electrical Characteristics (VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Resolution
—
— — 10 bit
Total error −3—+3LSB
Linearity error −2.5 — +2.5 LSB
Diff erential linearity
error −1.9 — +1.9 LSB
Zero transition
voltage V0T VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB V
Full-scale transition
voltage VFST VCC − 4.5 LSB VCC − 2 LSB VCC + 0.5 LSB V
Compare time — 3 — 10 µs 2.7 V ≤ VCC ≤ 5.5 V
Sampling time — 0.941 — ∞µs
2.7 V ≤ VCC ≤ 5.5 V,
with external
impedance < 3. 3 kΩ
and external
capacitance = 10 pF
Analog input current IAIN −0.3 — +0.3 µA
Analog input voltage VAIN VSS —VCC V
MB95630H Series
94 DS702–00009–3v0-E
(2) Notes on Using A/D Converter
• External impedance of analog input and its sampling time
The A/D con verter of the MB9563 0H Series has a samp le and hold cir cui t. I f t he external impe dance is t oo
high to k eep sufficient sampling time, th e analog voltage char ged to the capacitor of the internal sample and
hold circuit is insu fficient, adv ersely aff ecting A/D con version pre cision. Theref ore, to sa tisfy the A/D con ver-
sion precision standard, considering the relationship between the external impedance and minimum sam-
pling time, either adjust the register value and operating frequency or decrease the external impedance so
that the samplin g time is longer than th e minimum value. In addition , if sufficient sampling tim e cannot be
secured, connect a capacitor of about 0.1 µF to the analog input pin.
• A/D conversion error
As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
Note: The values are reference values.
4.5 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.5 V 1.45 kΩ (Max)
2.7 kΩ (Max) 14.89 pF (Max)
VCC R C
14.89 pF (Max)
ComparatorAnalog input
During sampling: ON
RC
• Analog input equivalent circuit
[External impedance = 0 kΩ to 100 kΩ]
External impedance [kΩ]
Minimum sampling time [μs]
0246810 12 14 16 1820
100
80
60
40
20
0
[External impedance = 0 kΩ to 20 kΩ]
External impedance [kΩ]
Minimum sampling time [μs]
0 0.5 1 1.5 2 2.5 33.5 4 4.5
20
15
10
5
0
Note: External capacitance = 10 pF
• Relationship between external impedance and minimum sampling t ime
MB95630H Series
DS702–00009–3v0-E 95
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates ho w much an act ual conversion v alue deviates from the straight line connecting the zero transi-
tion point ( “000000000 0” ← → “0000000001”) of a device to the full- scale tr ansition po int (“1111111 111” ←
→ “1111111110”) of the same device.
• Differential linear error (unit: LSB)
It indicate s how m uch the input v oltage requir ed to change t he output co de b y 1 LSB de viates f rom an ideal
value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
(Continued)
VFST
Ideal I/O characteristics
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Digital output
Digital output
2 LSB
V0T
1 LSB
0.5 LSB
Total error
Analog inputAnalog input
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Actual conversion
characteristic
Ideal characteristic
Actual conversion
characteristic
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from 0x(N − 1) to 0xN
{1
LSB
×
(N
−
1)
+
0.5
LSB}
VNT
Total error of digital output N VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSBLSB=
VCC − VSS
1024 V1 LSB =
VSS VCC VSS VCC
MB95630H Series
96 DS702–00009–3v0-E
(Continued)
Zero transition error
Linearity error
Full-scale transition error
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Digital output
Differential linearity error of digital output N V(N+1)T − VNT
1 LSB− 1=
Linearity error of digital output N VNT − {1 LSB × N + V0T}
1 LSB
=
Digital output
Analog input
0x001
0x002
0x3FC
0x3FD
0x003
0x3FE
0x3FF
0x004
Actual conversion
characteristic
Actual conversion
characteristic
V0T (measurement value)
Actual conversion
characteristic
Actual conversion
characteristic
VFST
(measurement
value)
VSS VCC
VSS VCC VSS VCC
VSS VCC
Analog input
Digital output
Analog input
Ideal characteristic
{1 LSB × N + V0T}
Actual conversion
characteristic
Ideal
characteristic
Actual conversion
characteristic
V0T (measurement value)
VFST
(measurement
value)
VNT
Differential linearity error
0x(N−2)
0x(N−1)
0xN
0x(N+1)
Digital output
Analog input
Actual conversion
characteristic
Ideal characteristic
VNT
Actual conversion
characteristic V(N+1)T
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from 0x(N − 1) to 0xN
V0T (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC − 2 LSB [V]
Ideal
characteristic
MB95630H Series
DS702–00009–3v0-E 97
6. Flash Memory Program/Erase Charact eristics
*1:VCC = 5.5 V, TA = +25°C, 0 cycle
*2:VCC = 2.4 V, TA = +85°C, 100000 cycles
*3:These values were converted from the result of a technology reliability assessment. (These values were
converted from the result of a high temperature accelerated test using the Arrhenius equation with the av-
erage temperature being +85°C.)
Parameter Value Unit Remarks
Min Typ Max
Sector erase time
(2 Kbyte sector) —0.3*
11.6*2s Th e time of writing “0x0 0” prior to er asure is e xclude d.
Sector erase time
(32 Kbyte sector) —0.6*
13.1*2s Th e time of writing “0x0 0” prior to er asure is e xclude d.
Byte writing time — 17 272 µs System-level overhead is excluded.
Program/erase cycle 100000 — — cycle
P ower supply voltage
at program/erase 2.4 — 5.5 V
Flash memory data
retention time
20*3——
year
Average TA = +85°C
Number of program/erase cycles: 1000 or below
10*3—— Average TA = +85°C
Number of program/erase cycles: 1001 to 10000
inclusive
5*3—— Averag e TA = +85°C
Number of program/erase cycles: 10001 or above
MB95630H Series
98 DS702–00009–3v0-E
■SAMPLE CHARACTERISTICS
• Power supply current temperature char acteristics
(Continued)
0
5
10
15
1234567
I
CC
[mA]
V
CC
[V]
F
MP
= 16 MHz
F
MP
= 10 MHz
F
MP
= 8 MHz
F
MP
= 4 MHz
F
MP
= 2 MHz
ICC − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operat ing
0
5
10
15
−50 0 +50 +100 +150
I
CC
[mA]
T
A
[°C]
F
MP
= 16 MHz
F
MP
= 10 MHz
F
MP
= 8 MHz
F
MP
= 4 MHz
F
MP
= 2 MHz
0
2
1
3
4
5
6
1234567
ICCS[mA]
VCC[V]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
2
1
3
4
5
6
−50 0 −50 +100 +150
I
CCS
[mA]
T
A
[°C]
F
MP
= 16 MHz
F
MP
= 10 MHz
F
MP
= 8 MHz
F
MP
= 4 MHz
F
MP
= 2 MHz
0
20
80
60
40
140
120
100
1234567
ICCL[μA]
VCC[V]
0
20
80
60
40
140
120
100
−50 0 +50 +100 +150
ICCL[μA]
TA[°C]
ICC − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divid ed by 2)
Main clock mode with the external clock operating
ICCS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divid ed by 2)
Main sleep mode with the external clock operating
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
MB95630H Series
DS702–00009–3v0-E 99
(Continued)
0
2
8
6
4
20
18
16
14
12
10
−50 0+50 +100 +150
ICCT[μA]
TA[°C]
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
0
10
20
30
−50 0+50 +100 +150
ICCLS[μA]
TA[°C]
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
0
10
20
30
1234567
ICCLS[μA]
VCC[V]
0
2
8
6
4
20
18
16
14
12
10
1234567
ICCT[μA]
VCC[V]
0
200
100
300
400
500
600
1234567
I
CCTS
[μA]
V
CC
[V]
F
MP
= 16 MHz
F
MP
= 10 MHz
F
MP
= 8 MHz
F
MP
= 4 MHz
F
MP
= 2 MHz
0
200
100
300
400
500
600
−50 0+50 +100 +150
ICCTS[μA]
TA[°C]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
ICCT − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
ICCTS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICCTS − TA
VCC = 5.5 V, FMP = 2, 4, 8, 10, 16 MHz (divid ed by 2)
Time-base timer mode with the external clock
operating
MB95630H Series
100 DS702–00009–3v0-E
(Continued)
0
8
4
12
16
20
−50 0+50 +100 +150
ICCH[μA]
TA[°C]
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the e xternal clock stopping
0
8
4
12
16
20
1234567
ICCH[μA]
VCC[V]
0
8
6
4
2
10
1234567
I
CCMCR
[mA]
V
CC
[V]
0
8
6
4
2
10
−50 0+50 +100 +150
I
CCMCR
[mA]
T
A
[°C]
0
8
6
4
2
10
1234567
I
CCMPLL
[mA]
V
CC
[V]
0
8
6
4
2
10
−50 0+50 +100 +150
I
CCMPLL
[mA]
T
A
[°C]
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
ICCMCR − VCC
TA = +25°C, FMP = 4 MHz (no division)
Main CR clock mode
ICCMCR − TA
VCC = 5.5 V, FMP = 4 MHz (no division)
Main CR clock mode
ICCMPLL − VCC
TA = +25°C, FMP = 16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
ICCMPLL − TA
VCC = 5.5 V, FMP = 16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
MB95630H Series
DS702–00009–3v0-E 101
(Continued)
0
150
100
50
200
−50 0+50 +100 +150
ICCSCR[μA]
TA[°C]
ICCSCR − TA
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Sub-CR clock mode
0
150
100
50
200
1234567
ICCSCR[μA]
VCC[V]
ICCSCR − VCC
TA = +25°C, FMPL = 50 kHz (divided by 2)
Sub-CR clock mode
MB95630H Series
102 DS702–00009–3v0-E
• Input voltage characteristics
0
1
2
4
5
234567
V
IHI
/V
ILI
[V]
V
CC
[V]
3
V
IHI
V
ILI
0
1
2
4
5
234567
V
IHS
/V
ILS
[V]
V
CC
[V]
3
V
IHS
V
ILS
VIHI − VCC and VILI − VCC
TA = +25°CVIHS − VCC and VILS − VCC
TA = +25°C
0
1
2
4
5
234567
V
IHM
/V
ILM
[V]
V
CC
[V]
3
V
IHM
V
ILM
VIHM − VCC and VILM − VCC
TA = +25°C
MB95630H Series
DS702–00009–3v0-E 103
• Output voltage characteristics
0.0
0.2
0.4
0.8
1.4
1.2
1.0
0−2−1−3−5−7−9−4−6−8−10 −11 −12 −13−14 −15
VCC − VOH2[V]
IOH[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
(VCC − VOH2) − IOH
TA = +25°C
VOL1 − IOL
TA = +25°C
0.0
0.2
0.4
0.8
1.4
1.2
1.0
0−2−1−3−5−7−9−4−6−8−10 −11 −12 −13−14 −15
VCC − VOH1[V]
IOH[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
(VCC − VOH1) − IOH
TA = +25°C
0.0
0.2
0.4
0.8
1.0
021357946810 11 12 1314 15
VOL2[V]
IOL[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL2 − IOL
TA = +25°C
0.0
0.2
0.4
0.8
1.4
1.2
1.0
021357946810 11 12 1314 15
VOL1[V]
IOL[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
MB95630H Series
104 DS702–00009–3v0-E
• Pull-up characteristics
0
50
100
150
200
123456
RPULL[kΩ]
VCC[V]
RPULL − VCC
TA = +25°C
MB95630H Series
DS702–00009–3v0-E 105
■MASK OPTIONS
No. Part number
MB95F632H
MB95F633H
MB95F634H
MB95F636H
MB95F632K
MB95F633K
MB95F634K
MB95F636K
Selectable/Fixed Fixed
1 Low-voltage detectio n reset Without low-voltage detection
reset With low-voltage detection reset
2 Reset With dedicated reset input Without dedicated reset input
MB95630H Series
106 DS702–00009–3v0-E
■ORDERING INFORMATION
Part number Package
MB95F632HPMC-G-SNE2
MB95F632KPMC-G-SNE2
MB95F633HPMC-G-SNE2
MB95F633KPMC-G-SNE2
MB95F634HPMC-G-SNE2
MB95F634KPMC-G-SNE2
MB95F636HPMC-G-SNE2
MB95F636KPMC-G-SNE2
32-pin plastic LQFP
(FPT-32P-M30)
MB95F632HP-G-SH-SNE2
MB95F632KP-G-SH-SNE2
MB95F633HP-G-SH-SNE2
MB95F633KP-G-SH-SNE2
MB95F634HP-G-SH-SNE2
MB95F634KP-G-SH-SNE2
MB95F636HP-G-SH-SNE2
MB95F636KP-G-SH-SNE2
32-pin plastic SH-DIP
(DIP-32P-M06)
MB95F632HWQN-G-SNE1
MB95F632KWQN-G-SNE1
MB95F633HWQN-G-SNE1
MB95F633KWQN-G-SNE1
MB95F634HWQN-G-SNE1
MB95F634KWQN-G-SNE1
MB95F636HWQN-G-SNE1
MB95F636KWQN-G-SNE1
32-pin plastic QFN
(LCC-32P-M19)
MB95630H Series
DS702–00009–3v0-E 107
■PACKAGE DIMENSION
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
32-pin plastic LQFP Lead pitch 0.80 mm
Package width ×
package length 7.00 mm × 7.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.60 mm MAX
32-pin plastic LQFP
(FPT-32P-M30)
(FPT-32P-M30)
C
7.00±0.10(.276±.004)SQ
0.80(.031)
"A"
0.10(.004)
9.00±0.20(.354±.008)SQ
18
1724
9
16
25
32
INDEX
0~7°
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.05
(.004±.002)
Details of "A" part
0.10(.004)
*
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
0.20(.008)M
0.35+0.08
–0.03
+.003
–.001
.014
0.13+0.05
–0.00
+.002
–.000
.005
(.063) MAX
1.60 MAX (Mounting height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB95630H Series
108 DS702–00009–3v0-E
(Continued)
32-pin plastic SDIP Lead pitch 1.778 mm
Low space 10.16 mm
Sealing method
Plastic mold
32-pin plastic SDIP
(DIP-32P-M06)
(DIP-32P-M06)
C
2003-2010 FUJITSUSEMICONDUCTOR LIMITED D32018S-c-1-3
(.350±.010)
*8.89±0.25
1.778(.070)
1.27(.050) 10.16(.400)
INDEX
*28.00
1.102
+0.20
–
0.30
–
.012
+.008
4.70
.185
+0.70
–
0.20
–
.008
+.028
3.30
.130
+0.20
–
0.30
–
.012
+.008
MAX.
1.02
.040
–
0.20
–
.008
+.012
+0.30
MIN.
0.51(.020)
0~15°
M
0.25(.010)
.019
0.48
+0.08
+.003
–
.005
–
0.12
0.27
.011–
.003
–
0.07
+.001
+0.03
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
MB95630H Series
DS702–00009–3v0-E 109
(Continued)
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
32-pin plastic QFN Lead pitch 0.50 mm
Package width ×
package length 5.00 mm × 5.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.06 g
32-pin plastic QFN
(LCC-32P-M19)
(LCC-32P-M19)
(.010 )
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
(.197±.004)
5.00±0.10
5.00±0.10
(.197±.004)
(3-R0.20)
((3-R.008))
0.50(.020) 1PIN CORNER
(C0.30(C.012))
0.75±0.05
(0.20(.008))
INDEX AREA
0.40±0.05
(.016±.002)
+0.03
–0.02
–.001
+.001
0.02
(.001 )
(.138±.004)
3.50±0.10
3.50±0.10
(.138±.004)
(TYP)
(.030±.002)
+0.05
–0.07
–.003
+.002
0.25
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB95630H Series
110 DS702–00009–3v0-E
■MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page Section Details
22 ■PIN CONNECTION
•C pin Corrected the following statement.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decouplin g cap a cito r for the VCC pin must have a
capacitance equal to or larger than the capacitance of C S.
66 ■ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions Corrected the following statement in remark *2.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decouplin g cap a cito r for the VCC pin must have a
capacitance equal to or larger than the capacitance of C S.
71 4. AC Characteristics
(1) Clock Timing Corrected the pin names of the parameter “Input clock
rising time and falling time”.
X0 → X0, X0A
X0, X1 → X0, X1, X0A, X1A
MB95630H Series
DS702–00009–3v0-E 111
MEMO
MB95630H Series
FUJITSU SEMICONDUCTOR LIMITED
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