Class-D Audio Power Amplifier AD1990/AD1992/AD1994/AD1996 Preliminary Technical Data GENERAL DESCRIPTION Integrated Stereo Modulator & Power Stage 0.005% THD+N 101.5dB Dynamic Range PSRR > 65 dB RDS-ON < 0.3 (per transistor) Efficiency > 80% @ 5W/6 EMI Optimized Modulator On-Off-Mute Pop Noise Suppression Short Circuit Protection Over-Temperature Protection Low Cost DMOS Process The AD199x is a two channel Bridge Tied Load (BTL) switching audio power amplifier with integrated modulator. The modulator accepts a 1Vrms input signal (maximum power) and generates a switching waveform to drive speakers directly. One of the two modulators can control both output stages providing twice the current for single-channel applications. A digital, microcontroller-compatible interface provides control of reset, mute and PGA gain as well as output signals for thermal and over-current error conditions. The output stage can operate from supply voltages ranging from 8V to 20V. The analog modulator and digital logic operate from a 5V supply. APPLICATIONS AD1990: 5Wx2 (10Wx1) AD1992: 10Wx2 (20Wx1) AD1994: 25Wx2 (50Wx1) AD1996: 40Wx2 (80Wx1) 63 32 31 NFR+ AINR AINL PGA0 NFL+ NFL62 PGA1 Flat Panel Televisions Automotive Amplifiers PC Audio Systems Mini Components 60 50 53 NFR- FEATURES 51 LEFT CHANNEL RIGHT CHANNEL 7,8 PVDD2 PVDD 4,5,6 41,42 PVDD2 DRIVER HIGH SIDE 43,44,45 DRIVER LOW SIDE PGND2 46,47,48 PVDD2 39,40 OUTL+ OUTR+ 1,2,3 PGND1 9,10 PVDD1 11,12,13 DRIVER HIGH SIDE 14,15,16 DRIVER LOW SIDE LEVEL SHIFT + DEAD TIME CONTROL MODULATOR PGA PGA MODULATOR LEVEL SHIFT + DEAD TIME CONTROL PGND2 PVDD2 DRIVER HIGH SIDE 36,37,38 DRIVER LOW SIDE 33,34,35 OUTL- OUTR- PGND1 PGND1 O1 55 REF_FILT 57 O1 O2 PGND2 PGND2 O2 VOLTAGE REFERENCE AVDD 56 AGND 24,25 DVDD TEMPERATURE SENSE & OVER-CURRENT PROTECTION OSCILLATOR MODE CONTROL LOGIC MUTE/ POP CONTROL 23,26 DGND 22 21 20 DCTRL2 49 DCTRL1 17 DCTRL0 18 ERR2 19 MONO 29 ERR1 30 ERR0 28 CLKO MUTE CLKI RST/PW DN 27 Figure 1. Block Diagram Rev. PrA - 1/20/05 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved. AD199x Preliminary Technical Data TABLE OF CONTENTS General Description ........................................................................ 1 Functional Description.................................................................. 10 AD199x--Specifications.................................................................. 3 Device Architecture ................................................................... 10 test conditions unless otherwise noted...................................... 3 Amplifier Gain............................................................................ 10 Absolute Maximum Ratings............................................................ 6 System Design............................................................................. 11 Pin Configurations And Functional Descriptions ....................... 7 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 8 ESD Caution................................................................................ 14 Rev. PrA - 1/20/05 | Page 2 of 16 Preliminary Technical Data AD199x AD199X--SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages AVDD DVDD PVDDX Ambient Temperature Load Impedance Clock Frequency Measurement Bandwidth 5V 5V 12 V 25 C 6 11.2896 MHz 20 Hz to 20 KHz Table 1. Performance of both channels is identical Parameter OUTPUT POWER (PO) AD1990 Min AD1994 AD1996 Efficiency RON per High Side Transistor per Low Side Transistor Maximum Current Through OUTx Thermal Warning Active Thermal Shutdown Active Overcurrent Shutdown Active Nominal Input Level Modulation Factor PERFORMANCE SPECIFICATIONS Total Harmonic Distortion (THD+N) Units W W W W W W W W % 0.3 0.2 4 135 150 4 1.0 90 0.005 0.007 0.01 0.02 102 102 -100 Signal/Noise Ratio (SNR) Dynamic Range (DNR) Crosstalk DC SPECIFICATIONS Input Impedance Output DC Offset Voltage Max 4 5 8 10 16 25 25 40 84 AD1992 Power supply rejection (PSRR) Typ A C C A VRMS % % % % % dB dB dB dB dB 60 45 20 10 Rev. PrA - 1/20/05 | Page 3 of 16 k mV Test Conditions/Comments RL = 6, PVDD = 20 V, 1 kHz (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) @ <0.01% THD+N @ 10% THD+N (FTC) fIN =1 kHz, PO = 5 W, RL = 6 @1A @1A Die temperature Die temperature PGA gain = 0 dB PGA = 0 dB, PO = 5 W PGA = 6 dB, PO = 5 W PGA = 12 dB, PO = 5 W PGA = 18 dB, PO = 5 W -60 dB Input Measured channel input = 0 VRMS, other channel = 1 kHz at 5W 20 Hz - 1 kHz 20 Hz - 20 kHz AINL and AINR analog inputs AD199x Parameter POWER SUPPLIES Supply Voltage AVDD Supply Voltage DVDD Supply Voltage PVDDX Powerdown Current AVDD DVDD PVDDX Mute Current AVDD DVDD PVDD Quiesent Current AVDD DVDD PVDDX Operating Current AVDD DVDD PVDD DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current on Digital Inputs Preliminary Technical Data Min Typ Max Units 4.5 4.5 6.5 5 5 8-20 5.5 5.5 22.5 V V V Test Conditions/Comments RST/PDN held low 0.1 0.1 19 0.5 0.5 25 A A A MUTE held low 19 2.7 1.5 mA mA mA 20 5.2 3.2 mA mA mA 22 5.8 mA mA A Inputs Grounded, Non-Overlap Time = TBD VIN = 1VRMS, PO = 5 W 4 2.0 DVDD 0.8 DVDD-0.8 0.4 10 V V V V A Rev. PrA - 1/20/05 | Page 4 of 16 per FET @ 2 mA @ 2 mA Preliminary Technical Data AD199x Table 2 DIGITAL TIMING (Guaranteed over -40C to +85C, AVDD = DVDD = 5.0V 10%, PVDDX =12V 10%, Non Overlap Time tNOL = Shortest, See Table 6: Non-Overlap Time Settings) Parameter tPDRP tMPDL tMUTEDLY Min 500 Typ Max Units ns s sec 5 1 Comments RST/PDN minimum low pulsewidth MUTE asserted to output initial response RST/PDN high to MUTE high delay OUTL+/ O UTR+ OUTL-/ OUTRtNOL t NOL Figure 2. Output Timing MUTE t PST t PST OUTX tMPDL t MPDL Figure 3. Mute Timing RESET MUTE t MUTEDLY Figure 4. Reset to Mute Delay Rev. PrA - 1/20/05 | Page 5 of 16 AD199x Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 3. AD199x Absolute Maximum Ratings1 2 Including any induced voltage due to inductive load PGND1 1 53 MONO 54 NFR+ 55 NC 56 NFR- 57 NC 58 AINR 59 AGND 60 REF_FILT 61 AV DD 62 NC 63 AINL NC 64 NC NFL- 260C 215C 220C NFL+ JC Thermal Impedance (LFCSP) JC Thermal Impedance (PSOP) Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Rating -0.3 V to +6.5 V -0.3 V to +30.0 V2 -0.3 V to +0.3 V -0.5 V to +0.5 V AGND to AVDD -40C to +85C -65C to +150C 150C 3C/W 1C/W AGND Parameter AVDD, DVDD to AGND, DGND PVDDX to PGND AGND to DGND to PGND AVDD, to DVDD Audio Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature 1 52 51 50 49 * 48 PGND2 PIN 1 IDENTIFIER PGND1 2 47 PGND2 PGND1 3 46 PGND2 OUTL+ 4 45 OUTR+ OUTL+ 5 44 OUTR+ OUTL+ 6 43 OUTR+ PV DD1 7 PV DD1 8 PV DD1 9 42 PV DD2 AD1990/92/94 TOP VIEW (Not to Scale) 41 PV DD2 40 PV DD2 PV DD1 10 39 PV DD2 OUTL- 11 38 OUTR- OUTL- 12 37 OUTR- OUTL- 13 36 OUTR- PGND1 14 35 PGND2 PGND1 15 34 PGND2 PGND1 16 33 PGND2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ERR2 ERR1 ERR0 DCTRL2 DCTRL1 DCTRL0 DGND DV DD DV DD DGND CLKI CLKO MUTE RST/PDN PGA1 PGA0 1990-0002 Figure 5. 64 Lead LFCSP Package Rev. PrA - 1/20/05 | Page 6 of 16 Preliminary Technical Data AD199x PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 4. Pin Function Descriptions LFCSP Pin No. 1,2,3 4,5,6 7,8,9,10 11,12,13 14,15,16 17 18 19 20 21 22 23,26 24,25 27 28 29 30 31 32 33,34,35 36,37,38 39,40,41,42 43,44,45 46,47,48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PSOP Pin No. 3 2 1,36 35 34 33 32 31 29,30 28 27 26 25 24 23 22 21 20 18,19 17 16 15 14 13 12 11 10 9 8 4 7 6 5 Name PGND1 OUTL+ PVDD1 OUTLPGND1 ERR2 ERR1 ERR0 DCTRL2 DCTRL1 DCTRL0 DGND DVDD CLKI CLKO MUTE RST/PDN PGA1 PGA0 PGND2 OUTRPVDD2 OUTR+ PGND2 AGND NFR+ NFRNC AINR NC REF_FILT AGND AVDD NC NC AINL NC NFLNFL+ MONO In/Out O O O O O I I I I O I I I I O O I I I O I I I I Description Negative power supply for high power transistors A2 and B2 Output of high power transistor pair, left channel positive polarity Positive power supply for high power transistors, left channel high-side Output of high power transistor pair, left channel negative polarity Negative power supply for high power transistors, left channel low-side Active low thermal shutdown error output Active low thermal warning error output Active low overcurrent error output Non-overlap time setting MSB Non-overlap time setting Non-overlap time setting LSB Negative power supply for low power digital circuitry Positive power supply for low power digital circuitry Clock input for 256 x fS audio modulator clock Inverted version of CLKI for use with external crystal oscillator Active low mute input Active low reset/power-down input Programmable gain amplifier (PGA) gain MSB Programmable gain amplifier (PGA) gain LSB Negative power supply for right channel high power transistors Output of high power transistor pair, right channel negative polarity Positive power supply for right channel high power transistors Output of high power transistor pair, right channel positive polarity Negative power supply for right channel high power transistors Negative power supply for low power analog circuitry Right channel negative feedback - positive input Right channel negative feedback - negative input Not Connected. This pin is not used and should be left floating Analog input for right channel Not Connected. This pin is not used and should be left floating Filter pin for bandgap reference - should be bypassed to AGND Negative power supply for low power analog circuitry Positive power supply for low power analog circuitry Not Connected. This pin is not used and should be left floating Not Connected. This pin is not used and should be left floating Analog input for left channel Not Connected. This pin is not used and should be left floating Left channel negative feedback - negative input Left channel negative feedback - positive input Mono mode (drive left and right output transistors from same modulator) Rev. PrA - 1/20/05 | Page 7 of 16 AD199x Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS +0 POWER = 100mW RL = 6 -20 Power (dB, relative to 7.75 Vrms = 10W) Power (dB, relative to 7.75 Vrms = 10W) 0 -40 -60 -80 -100 -120 -140 -160 POWER = 5W R L = 6 -20 -40 -60 -80 -100 -120 -140 -160 0 2 4 6 8 10 12 14 16 18 0 20 2 4 6 Frequency (Hz) Figure 6. 1KHz, 100mW into a 6 Load 12 14 16 18 20 0 POWER = 1W RL = 6 -20 -20 -40 -40 -60 -60 MAGNITUDE - dB -80 -100 POWER = 1W RL = 6 -80 -100 -120 -120 -140 TPC-0005 Power (dB, relative to 7.75 Vrms = 10W) 10 Figure 8. 1KHz, 5W into a 6 Load 0 -160 0 8 FRE QUENC Y ( KH z) -140 2 4 6 8 10 12 14 Frequency (KHz) 16 18 20 -160 0 2 4 6 8 10 12 14 FREQUENCY - KHz Figure 7. 1KHz, 1W into a 6 Load Figure 9. 7KHz, 1W into a 6 Load Rev. PrA - 1/20/05 | Page 8 of 16 16 18 20 Preliminary Technical Data AD199x 100 0 90 -20 POWER = 1W RL = 6 80 70 -60 Efficiency (%) MAGNITUDE - dB -40 -80 -100 60 50 40 30 -120 20 -160 TPC-0006 0 2 4 6 8 10 12 14 16 18 10 TPC0003 -140 0 20 0 1 2 FREQUENCY - KHz 4 5 Figure 13. Efficiency vs Power Figure 10. 10KHz, 1W into a 6 Load 0 -20 -30 -20 -40 POWER = 1W RL = 6 MAGNITUDE - dB -40 MAGNITUDE - dB 3 Watts Per Channel -60 -80 -100 -50 -60 -70 -80 -90 -120 -160 0 2 4 6 8 10 12 14 16 18 -110 -120 20 20 FREQUENCY - KHz 0 T PVDD = 12V RL = 6 AMPLIFIER GAIN (AV) = 2.7 POWER = (VRMS x AV x 2)2/RL -50 -60 fIN = 10KHz fIN = 1KHz -80 -90 fIN = 100Hz -100 TPC-0004 THD+N (dB) -40 -70 -110 -120 0 0.2 0.2W 0.4/ 0.78W 100 200 500 1K 2K 5K 10K Figure 14. THD+N vs Distortion, 1W into a 6 Load -10 -30 50 FREQUENCY - Hz Figure 11. 19KHz, 1W into a 6 Load -20 TPC-0008 TPC-0007 -100 -140 0.6/ 1.75W 0.8/ 3W 1.0/ 5W 1.2/ 7W VRMS (V) Figure 12. THD+N vs Input Signal/Power Output Rev. PrA - 1/20/05 | Page 9 of 16 20K AD199x Preliminary Technical Data FUNCTIONAL DESCRIPTION DEVICE ARCHITECTURE The AD199x is an audio quality, switching amplifier with an integrated sigma-delta modulator. The power stage of the AD199x is arranged internally as four transistor pairs, which are used as two H-bridge outputs to provide stereo amplification. The transistor pairs are driven by the output of the modulator. A user selectable non-overlap time is provided between the switching of the high side transistor and low side transistor to ensure that both transistors are never on at the same time. The AD199x implements turn on pop suppression to eliminates any pops or clicks following a reset or un-mute. Analog Input Section The analog input section uses an internal amplifier to bias the input signal to the reference level. A DC blocking capacitor should be connected as shown in Figure 15 to remove any external DC bias contained in the input signal 1.25V 0V + driving the OUTx pin. The nature of the inductors is to keep current flowing. For example the OUTx pin may approach and pass the PGND level to achieve this. When the voltage at the OUTx pin is 0.7V below PGND the parasitic diode associated with the low-side transistor will become forward biased and turn on. When the high-side transistor turns on the voltage at OUTx will rise to PVDD and will reverse bias the parasitic diode. However, by its nature the parasitic diode has a long reverse recovery time and current will continue to flow through it to PGND thus causing the entire circuit to draw more current than necessary. The addition of the schottky diodes prevents this happening. When the OUTx pin goes more than 0.3V below PGND the schottky diode becomes forward biased. When the high-side transistor turns on the schottky diode becomes reverse biased. The reverse recovery time of the schottky diode is significantly faster than the parasitic diode so far less current is wasted. A similar effect happens when the inductor induces a current which drives the OUTx pin above PVDD. Figure 16 shows how the external components of a system are connected to the pins of the AD199x to form the Hbridge configuration. AMPLIFIER GAIN AINL/ AINR Selecting the Modulator Gain 71046-0007 Figure 15. Normal Operation The Sigma-Delta Modulator Detailed description pending on patents pending, as well as announcements, conference proceedings and other scheduled public disclosures. The AD199x modulator can be thought of as a switching analog amplifier with a voltage gain controlled by two external resistors forming a resistor divider between the OUTxx pins and PGND. The centre of the resistor divider is connected to the appropriate feedback pin NFx. Selecting the gain along with the PVDD Voltage will determine how much power can be delivered to a load for a fixed input signal. The gain of the modulator is controlled by the values of R1 and R2 (see Figure 16) according to the equation below. Selecting Stereo or Mono Mode Gain = (R1 + R2)/R2 Driving the H-Bridge Each channel of the switching amplifier is controlled by a 4 transistor H-bridge to give a differential output stage. The outputs of the H-bridges, OUTR+, OUTR-, OUTL+ and OUTL- will switch between PVDD and PGND as determined by the sigma delta modulator. The power supply that is used to drive the power stage of the AD199x should be typically in the range of +8 V to +20 V and should be capable of supplying enough current to drive the load. This power supply is connected across the PVDD and PGND pins. The feedback pins, NFR+, NFR-, NFL+ and NFL-, are used to supply negative feedback to the modulator. The pins are connected to the outputs of the H-bridge via a resister divider network as shown in Figure 16. See the section on Selecting the Modulator Gain for more information. The gain should be selected such that a 1Vrms input signal doesn't cause the modulator to generate an output signal which has a peak to peak value greater than 90% of PVDD. Selecting a gain that meets this criteria will ensure that the modulator remains in a stable operating condition. PVDD PVDD EXTERNAL COMPONENTS D3 OUTx- OUTx+ D4 PGND PGND NFx- NFx+ External schottky diodes can be used to reduce power loss during the non-overlap time when neither of the high-side or low-side transistors is on. During this time neither transistor is Rev. PrA - 1/20/05 | Page 10 of 16 71046-0004 Figure 16. H-Bridge Configuration Preliminary Technical Data AD199x Programmable Gain Amplifier (PGA) high as required. The AD199x incorporates a single-ended to differential converter for each channel in the analog front-end section. Both single-ended to differential converters feature a programmable gain amplifier with four different gain settings. The gain is set using the pins PGA1 and PGA0 as shown in Table 5. The PGA1 and PGA0 pins are continuously monitored allow the gain to be changed at any time. On/Off/Mute Pop Noise Suppression The AD199x features pop suppression which is activated when the part is reset or taken out of mute. The pop suppression is achieved by pulsing the power outputs to bring the outputs of the LC filter from 0V to mid-scale in a controlled fashion. This feature eliminates unwanted transients on both the outputs and the high voltage power supply. Table 5. PGA Gain Settings Thermal Protection The AD199x features thermal protection. When the die temperature exceeds approximately 135C the Thermal Warning Error output (ERR1) is asserted. If the die temperature exceeds approximately 150C the Thermal Shutdown Error output (ERR2) is asserted. If this occurs, the part shuts down to prevent damage to the part. When the die temperature drops below approximately 120C both error outputs are negated and the part returns to normal operation. PGA1 0 0 1 1 PGA0 0 1 0 1 PGA Gain (dB) 0 6 12 18 SYSTEM DESIGN Clocking The AD199x has two clock pins, CLKI and CLKO which are used to configure the clocking scheme for the device. The AD199x should be driven by a clock which is 256 x fS where fS is the desired sampling rate. If a crystal is to be used as the clock source it should be connected across the CLKI and CLKO pins as shown in Figure 17. Crystal Connection The values and type of capacitors used will be determined by the crystal manufacturer. A square-wave clock source may be connected directly to the CLKI pin. The logic levels of the square wave should be compatible with those defined in the Digital I/O section of the specifications page. 47 22pF CLKO XTAL CLKI 22pF Figure 17. Crystal Connection Output Transistor Non-Overlap Time Ipsum lorum... Power-up Considerations Careful power-up is necessary when using the AD199x to ensure correct operation and avoid possible latch-up issues. The AD199x should be powered-up with RST/PDN and MUTE held low until all the power supplies have stabilized. Once the supplies have stabilized the AD199x can be brought out of reset by bringing RST/PDN high and then MUTE can be brought Over-current Protection The AD199x features over current or short circuit protection. If the current through any power transistors exceeds 4A the part goes into mute and the Over-current error output (ERR0) is asserted. This is a latched error and does not clear automatically. To clear the error condition and restore normal operation, the part must be either reset, or MUTE must be asserted and negated. Application Considerations Good board layout and decoupling are vital for correct operation of the AD199x. Due to the fact that the part switches high currents there is the potential for large PVDD bounce each time a transistor transitions. This can cause unpredictable operation of the part. To avoid this potential problem, close chip decoupling is essential. It is also recommended that the decoupling capacitors are placed on the same side of the board as the AD199x, and connected directly to the PVDD and PGND pins. By placing the decoupling capacitors on the other side of the board and decoupling through vias the effectiveness of the decoupling is reduced. This is because vias have inductive properties and therefore prevent very fast discharge of the decoupling capacitors. Best operation is achieved with at least one decoupling capacitor on each side of the AD199x, or optionally two capacitors per side can be used to further reduce the series resistance of the capacitor. If these decoupling recommendations cannot be followed and decoupling through vias is the only option, the vias should be made as large as possible to increase surface area, thereby reducing inductance and resistance. Rev. PrA - 1/20/05 | Page 11 of 16 AD199x Preliminary Technical Data DVDD PVDD + 0.1F 47F 0.1F 100F AVDD PVDD + 0.1F 47F PVDD1 PVDD2 DVDD AVDD + 100F 0.1F 100F PVDD L AINL OUTL+ C R1 NFL+ + 100F R2 AINR R2 NFLPVDD R1 OUTLL C AD1990 REF_FILT PVDD + 47F 100nF L OUTR+ C R1 NFR+ R2 MUTE R2 RST/PDN NFRPVDD R1 OUTRL ERR2 ERR0 DGND CLKO AGND CLKI 1990-0005 ERR1 OVERCURRENT PGND2 THERMAL WARNING R1 = 1K47 R2 = 523 L = 18H C = 1F PGND1 THERMAL SHUTDOWN Figure 18. Typical Stereo Mode Application Circuit Rev. PrA - 1/20/05 | Page 12 of 16 C Preliminary Technical Data AD199x DVDD PVDD + 0.1F 47F 0.1F 100F AVDD PVDD + 0.1F 47F PVDD1 DVDD AVDD + 100F PVDD2 100F 0.1F PVDD L AINL OUTL+ C R1 NFL+ R2 AINR R2 NFLPVDD R1 OUTLL AD1990 REF_FILT + 47F 100nF OUTR+ NFR+ MUTE RST/PDN NFR- DVDD ST/MO ERR1 OVERCURRENT ERR0 DGND CLKO AGND CLKI 1990-0007 ERR2 THERMAL WARNING PGND2 THERMAL SHUTDOWN PGND1 OUTR- Figure 19. Mono Mode Circuit Rev. PrA - 1/20/05 | Page 13 of 16 C AD199x Preliminary Technical Data OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 8.75 BSC SQ TOP VIEW 1 4.85 4.70 SQ* 4.55 BOTTOM VIEW 0.45 0.40 0.35 12 uMAX 64 49 48 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.25 0.18 33 32 1 17 6 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION Figure 20. 64-Lead Frame Chip Scale Package (LFCSP) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 6. Ordering Guide Products AD1990ACPZ AD1992ACPZ AD1994ACPZ AD1996ACPZ Package Temperature -40C to +85C -40C to +85C -40C to +85C -40C to +85C Power Rating 5W per channel 10W per channel 25W per channel 40W per channel Package Description Package Outline Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Power Small Outline Package CP-64 CP-64 CP-64 PSOP-36 Rev. PrA - 1/20/05 | Page 14 of 16 Preliminary Technical Data AD199x NOTES Rev. PrA - 1/20/05 | Page 15 of 16 AD199x Preliminary Technical Data NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR05380-0-1/05(PrA) Rev. PrA - 1/20/05 | Page 16 of 16