GALVANTECH, INC. ASYNCHRONOUS SRAM GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM 32K x 8 SRAM +5V SUPPLY, SINGLE CHIP ENABLE TRADITIONAL PINOUT FEATURES GENERAL DESCRIPTION * * * The GVT7232A8 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers one chip enable (CE#) along with output enable (OE#) for this organization. The chip is enabled when CE# is LOW. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. * * * * Fast access times: 7, 8, and 10ns Fast OE# access times: 4 and 5ns Single +5V +10% power supply (+5% power supply for 7ns and 8ns speed grade) Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs High-performance, low-power consumption, CMOS double-poly, double-metal process OPTIONS * * * MARKING Timing 7ns access 8ns access 10ns access -7 -8 -10 Packages 28-pin SOJ (300 mil) 28-pin TSOP SJ TS Temperature Commercial Industrial None I PIN ASSIGNMENT 28-Pin SOJ 28-Pin TSOP (0C to 70C) (-40C to 85C) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com Rev. 7/98 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC WE# A13 A8 A9 A11 OE# A10 CE# DQ8 DQ7 DQ6 DQ5 DQ4 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. FUNCTIONAL BLOCK DIAGRAM VCC VSS A0 MEMORY ARRAY 256 ROWS X 128 X 8 COLUMNS I/O CONTROL ADDRESS BUFFER ROW DECODER DQ1 DQ8 CE# WE# OE# A14 COLUMN DECODER POWER DOWN TRUTH TABLE MODE CE# WE# OE# DQ POWER L L L H H L H X L X H X Q D HIGH-Z HIGH-Z ACTIVE ACTIVE ACTIVE STANDBY READ WRITE OUTPUT DISABLE STANDBY PIN DESCRIPTIONS Pin Numbers SYMBOL TYPE 10, 9, 8, 7, 6, 5, 4, 3, 25, 24, 21, 23, 2, 26, 1 A0-A14 Input Addresses Inputs: These inputs determine which cell is addressed. 27 WE# Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. 20 CE# Input Chip Enable: This input is used to enable the device. When CE# is LOW, the chip is selected. When either CE# is HIGH, the chip is disabled and automatically goes into standby power mode. 22 OE# Input Output Enable: This active LOW input enables the output drivers. 11, 12, 13, 15, 16, 17, 18, 19 DQ1-DQ8 Input/ Output 28 VCC Supply Power Supply: 5V +10% 14 VSS Supply Ground July 7, 1998 Rev. 7/98 DESCRIPTION SRAM Data I/O: Data inputs and data outputs 2 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (All Temperature Ranges; VCC = 5V +10% unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) voltage VIH 2.2 VCC+1 V 1, 2 Input Low (Logic 0) Voltage VIl -0.5 0.8 V 1, 2 Input Leakage Current 0V < VIN < VCC ILI -5 5 uA Output Leakage Current Output(s) disabled, 0V < VOUT < VCC ILO -5 5 uA Output High Voltage IOH = -4.0mA VOH 2.4 Output Low Voltage IOL = 8.0mA VOL Supply Voltage VCC DESCRIPTION CONDITIONS Power Supply Current: Operating 4.5 V 1 0.4 V 1 5.5 V 1 SYM TYP -7* -8* -10 Device selected; CE# < VIL; VCC =MAX; f=fMAX; outputs open Icc 60 195 170 145 mA 3, 14 TTL Standby CE# >VIH; VCC = MAX; f=fMAX ISB1 20 57 45 41 mA 14 CMOS Standby CE# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 ISB2 0.75 5 5 5 mA 14 UNITS NOTES *NOTE: VCC = 5V + 5% for these speed grades. CAPACITANCE DESCRIPTION CONDITIONS Input Capacitance TA = 25oC; f = 1 MHz VCC = 5V Input/Output Capacitance (DQ) July 7, 1998 Rev. 7/98 SYMBOL MAX UNITS NOTES CI 6 pF 4 CI/O 8 pF 4 3 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. AC ELECTRICAL CHARACTERISTICS (Note 5) (All Temperature Ranges; VCC = 5V DESCRIPTION +10% for -10 speed grade, VCC = 5V +5% for -7 & -8 speed grades)) - 7* SYM MIN READ cycle time tRC 7 Address access time tAA - 8* MAX MIN - 10 MAX MIN MAX UNITS NOTES READ Cycle Chip Enable access time 8 10 7 tACE 8 7 8 tOH 3 3 3 Chip Enable to output in Low-Z tLZCE 3 3 3 Chip disable to output in High-Z tHZCE Output hold from address change Output Enable access time 5 tAOE Output Enable to output in Low-Z tLZOE Output Enable to output in High-Z tHZOE Chip Enable to power-up time tPU Chip disable to power-down time tPD 5 4 0 5 0 ns 10 ns ns ns 4, 7 5 ns 4, 6, 7 5 ns 0 4 0 ns 10 5 0 ns 5 0 7 8 10 ns 4, 6 ns 4 ns 4 WRITE Cycle WRITE cycle time tWC 7 8 10 ns Chip Enable to end of write tCW 5 6 7 ns Address valid to end of write, with OE# HIGH tAW 5 6 7 ns ns Address setup time tAS 0 0 0 Address hold from end of write tAH 0 0 0 ns WRITE pulse width tWP2 7 8 10 ns WRITE pulse width, with OE# HIGH tWP1 5 6 7 ns Data setup time tDS 5 5 5 ns Data hold time tDH 0 0 0 ns Write disable to output in Low-Z tLZWE 3 3 3 Write Enable to output in High-Z tHZWE 5 5 5 ns 4, 7 ns 4, 6, 7 *NOTE: VCC = 5V + 5% for these speed grades. July 7, 1998 Rev. 7/98 4 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. OUTPUT LOADS AC TEST CONDITIONS Q Input pulse levels 0V to 3.0V Input rise and fall times 1.5ns Input timing reference levels 1.5V Output reference levels 1.5V Output load Z0 = 50 50 30 pF Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT See Figures 1 and 2 +5V 480 Q 255 5 pF Fig. 2 OUTPUT LOAD EQUIVALENT NOTES 8. WE# is HIGH for READ cycle. 1. All voltages referenced to VSS (GND). 9. 2. Overshoot: Undershoot: Device is continuously selected. Chip enable and output enables are held in their active state. VIH +7.0V for t tRC /2. VIL -2.0V for t tRC /2 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. July 7, 1998 Rev. 7/98 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 5V, 25oC and 20ns cycle time. 5 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V VCC CE# t V 4.5V DR CDR tRC VIH VIL READ CYCLE NO. 1(8, 9) t RC ADDR VALID t AA t OH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2(7, 8, 10, 12) tRC CE# tAOE tLZOE OE# tHZCE tACE tHZOE tLZCE Q HIGH Z DATA VALID DON'T CARE UNDEFINED July 7, 1998 Rev. 7/98 6 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW)) tWC ADDR tAW t tAH CW CE# tWP2 tAS WE# tDS D tDH DATA VALID tHZWE tLZWE Q HIGH Z WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH) tWC ADDR tAW tAH t CW CE# t tAS WP1 WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE UNDEFINED July 7, 1998 Rev. 7/98 7 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled) t WC ADDR tAW t tAH t AS CW CE# tWP1 WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE July 7, 1998 Rev. 7/98 8 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM GALVANTECH, INC. Package Dimensions 28-pin 300 Mil Plastic SOJ (SJ) .730 (18.54) .697 (17.70) .305 (7.75) .292 (7.42) PIN #1 INDEX .347 (8.81) .327 (8.31) .140 (3.54) .120 (3.04) .050 (1.27) TYP .095 (2.41) .080 (2.03) SEATING PLANE .020 (0.51) .014 (0.36) .275 (6.99) .260 (6.60) .025 (0.63) MIN Note: All dimensions in inches (millimeters) MAX MIN or typical, min where noted. 28-pin Plastic TSOP (TS) .536 (13.60) .520 (13.20) .011 (0.27) .006 (0.15) .022 (0.55) TYP .319 (8.10) .311 (7.90) .047 (1.20) MAX .468 (11.90) .460 (11.70) .008 (0.20) .002 (0.05) Note: All dimensions in inches (millimeters) July 7, 1998 Rev. 7/98 MAX MIN or typical, max where noted. 9 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. GVT7232A8 TRADITIONAL PINOUT 32K X 8 SRAM Ordering Information GVT 7232A8 XX - XX X Galvantech Prefix Temperature (Blank = Commercial I = Industrial) Speed (7 = 7ns, 8= 8ns 10 = 10ns) Package (SJ= 300 mil SOJ, TS= TSOP) Part Number July 7, 1998 Rev. 7/98 10 Galvantech, Inc. reserves the right to change products or specifications without notice.