ASYNCHRONOUS
SRAM 32K x 8 SRAM
+5V SUPPLY, SINGLE CHIP ENABLE
TRADITIONAL PINOUT
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
Galvantech, Inc. reserves the right to change
products or specifications without notice.
Rev. 7/98
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699Web Site http://www.galvantech.com
FEATURES
•Fast access times: 7, 8, and 10ns
•Fast OE# access times: 4 and 5ns
•Single +5V +10% power supply (+5% power supply for
7ns and 8ns speed grade)
•Fully static -- no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•High-performance, low-power consumption, CMOS
double-poly, double-metal process
OPTIONSMARKING
•Timing
7ns access -7
8ns access -8
10ns access -10
•Packages
28-pin SOJ (300 mil) SJ
28-pin TSOP TS
•Temperature
Commercial None (0°C to 70°C)
Industrial I (-40°C to 85°C)
GENERAL DESCRIPTION
The GVT7232A8 is organized as a 32,768 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
Static design eliminates the need for external clocks or
timing strobes. For increased system flexibility and
eliminating bus contention problems, this device offers one
chip enable (CE#) along with output enable (OE#) for this
organization.
The chip is enabled when CE# is LOW. With chip being
enabled, writing to this device is accomplished when write
enable (WE#) is LOW and reading is accomplished when
(OE#) go LOW with (WE#) remaining HIGH. The device
offers a low power standby mode when chip is not selected.
This allows system designers to meet low standby power
requirements.
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
10
11
12
13
14
16
15
VCC
WE#
CE#
DQ8
DQ7
DQ6
DQ5
DQ4
A13
A8
A9
A11
OE#
A10
A14
A12
A1
A0
DQ1
DQ2
DQ3
VSS
A7
A6
A5
A4
A3
A2
PIN ASSIGNMENT
28-Pin SOJ
28-Pin TSOP
July 7, 19982Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
PIN DESCRIPTIONS
MODECE#WE#OE#DQPOWER
READLHLQACTIVE
WRITEL L XDACTIVE
OUTPUT DISABLELH H HIGH-ZACTIVE
STANDBYHX X HIGH-ZSTANDBY
Pin NumbersSYMBOLTYPEDESCRIPTION
10, 9, 8, 7, 6, 5, 4,
3, 25, 24, 21, 23,
2, 26, 1
A0-A14InputAddresses Inputs: These inputs determine which cell is addressed.
27 WE#InputWrite Enable: This input determines if the cycle is a READ or WRITE cycle. WE#
is LOW for a WRITE cycle and HIGH for a READ cycle.
20 CE#InputChip Enable: This input is used to enable the device. When CE# is LOW, the
chip is selected. When either CE# is HIGH, the chip is disabled and
automatically goes into standby power mode.
22 OE#InputOutput Enable: This active LOW input enables the output drivers.
11, 12, 13, 15,
16, 17, 18, 19DQ1-DQ8Input/
OutputSRAM Data I/O: Data inputs and data outputs
28 VCCSupplyPower Supply: 5V +10%
14 VSS SupplyGround
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
256 ROWS X 128 X 8
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A14
A0
VCC
VSS
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55oC to +125o
Junction Temperature .....................................................+125o
Power Dissipation ...........................................................1.2W
Short Circuit Output Current .......................................50mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
July 7, 19983Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 5V +10% unless otherwise noted)
*NOTE: VCC = 5V + 5% for these speed grades.
CAPACITANCE
DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES
Input High (Logic 1) voltageVIH2.2VCC+1V1, 2
Input Low (Logic 0) VoltageVIl-0.50.8V1, 2
Input Leakage Current0V < VIN < VCCILI-5 5 uA
Output Leakage CurrentOutput(s) disabled,
0V < VOUT < VCCILO-5 5 uA
Output High VoltageIOH = -4.0mA VOH2.4V1
Output Low VoltageIOL = 8.0mA VOL0.4V1
Supply VoltageVCC4.55.5V1
DESCRIPTIONCONDITIONS SYMTYP-7*-8*-10UNITSNOTES
Power Supply
Current: OperatingDevice selected; CE# < VIL; VCC =MAX;
f=fMAX; outputs openIcc60195170145mA3, 14
TTL StandbyCE# >VIH; VCC = MAX; f=fMAXISB120574541mA14
CMOS StandbyCE# >VCC -0.2;
VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
ISB20.75 5 5 5 mA14
DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 5VCI6 pF4
Input/Output Capacitance (DQ)CI/O8 pF4
July 7, 19984Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 5V +10% for -10 speed grade, VCC = 5V +5% for -7 & -8 speed grades))
*NOTE: VCC = 5V + 5% for these speed grades.
DESCRIPTION- 7*- 8*- 10
SYMMINMAXMINMAXMINMAXUNITSNOTES
READ Cycle
READ cycle timetRC 7 8 10 ns
Address access timetAA 7 8 10 ns
Chip Enable access timetACE7 8 10 ns
Output hold from address changetOH333ns
Chip Enable to output in Low-ZtLZCE333ns4, 7
Chip disable to output in High-ZtHZCE555ns4, 6, 7
Output Enable access timetAOE455ns
Output Enable to output in Low-ZtLZOE000ns
Output Enable to output in High-ZtHZOE455ns4, 6
Chip Enable to power-up timetPU000ns4
Chip disable to power-down timetPD7 8 10 ns4
WRITE Cycle
WRITE cycle timetWC7 8 10 ns
Chip Enable to end of writetCW567ns
Address valid to end of write, with OE#
HIGHtAW567ns
Address setup timetAS 000ns
Address hold from end of writetAH000ns
WRITE pulse widthtWP2 7 8 10 ns
WRITE pulse width, with OE# HIGHtWP1 5 6 7 ns
Data setup timetDS555ns
Data hold timetDH 000ns
Write disable to output in Low-ZtLZWE333ns4, 7
Write Enable to output in High-ZtHZWE555ns4, 6, 7
AC TEST CONDITIONS
Input pulse levels0V to 3.0V
Input rise and fall times1.5ns
Input timing reference levels1.5V
Output reference levels1.5V
Output loadSee Figures 1 and 2
OUTPUT LOADS
Vt = 1.5V
30 pF
Q
Z0 = 50Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50Ω
Q
+5V
480Ω
255Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
July 7, 19985Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +7.0V for t ≤ tRC /2.
Undershoot: VIL ≤ -2.0V for t ≤ tRC /2
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
8. WE# is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and output enables
are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 5V, 25oC and 20ns cycle time.
July 7, 19986Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
LOW VCC DATA RETENTION WAVEFORM
READ CYCLE NO. 1(8, 9)
READ CYCLE NO. 2(7, 8, 10, 12)
VCC
CE#
DATA RETENTION MODE
VDR
4.5V 4.5V
VIH
VIL
tRC
tCDR
ADDR VALID
tRC
DATA VALID
tOH
tAA
PREVIOUS DATA VALID
Q
CE#
tRC
DATA VALID
tLZCE
tACE
OE#
HIGH Z
tAOE
tLZOE
tHZCE
tHZOE
Q
UNDEFINED
DON'T CARE
July 7, 19987Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW))
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
ADDR
tWC
tAH
tDS
DATA VALID
CE#
WE#
D
Q
tDH
tWP2
tAS
tAW
tCW
HIGH Z
tHZWE tLZWE
ADDR
tWC
tAH
tDS
DATA VALID
HIGH Z
CE#
WE#
D
Q
tDH
tWP1
tAS
tAW
tCW
UNDEFINED
DON'T CARE
July 7, 19988Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled)
ADDR
tWC
tAH
tDS
DON'T CARE
DATA VALID
CE#
WE#
D
Q
tDH
tWP1
tAS
tAW tCW
HIGH Z
July 7, 19989Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
Package Dimensions
Note: All dimensions in inches (millimeters)
.730 (18.54)
.697 (17.70)
.305 (7.75)
.292 (7.42)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.014 (0.36)
MAX
MIN or typical, min where noted.
SEATING PLANE
.275 (6.99)
.260 (6.60)
.095 (2.41)
.080 (2.03)
.140 (3.54)
.120 (3.04)
.025 (0.63)
MIN
.347 (8.81)
.327 (8.31)
28-pin 300 Mil Plastic SOJ (SJ)
.319 (8.10)
.311 (7.90)
.011 (0.27)
.006 (0.15)
.468 (11.90)
.460 (11.70)
.022 (0.55) TYP
.047 (1.20) MAX
.536 (13.60)
.520 (13.20)
.008 (0.20)
.002 (0.05)
Note: All dimensions in inches (millimeters) MAX
MIN or typical, max where noted.
28-pin Plastic TSOP (TS)
July 7, 199810 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GVT7232A8
TRADITIONAL PINOUT 32K X 8 SRAM
GALVANTECH, INC.
Ordering Information
GVT 7232A8 XX - XX X
Galvantech Prefix
Part Number
Package (SJ= 300 mil SOJ,
10 = 10ns)
Speed (7 = 7ns, 8= 8ns
TS= TSOP)
Temperature (Blank = Commercial
I = Industrial)
