© Semiconductor Components Industries, LLC, 2017
November, 2018 − Rev. 2
1Publication Order Number:
NCV89803/D
NCV898032
2 MHz Automotive Grade
Non-Synchronous Boost
Controller
The NCV898032 is an adjustable output non−synchronous boost
controller which drives an external N−channel MOSFET. The device
uses peak current mode control with internal slope compensation. The
IC incorporates an internal regulator that supplies charge to the gate
driver.
Protection features include internally−set soft−start, undervoltage
lockout, cycle−by−cycle current limiting and thermal shutdown.
Additional features include low quiescent current sleep mode and
microprocessor compatible input pin.
Features
•Peak Current Mode Control with Internal Slope Compensation
•0.2 V $3% Reference Voltage for Constant Current Loads
•2 MHz Fixed Frequency Operation
•Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump
•Input Undervoltage Lockout (UVLO)
•Internal Soft−Start
•Low Quiescent Current in Sleep Mode (< 10 mA Typical)
•Cycle−by−Cycle Current Limit Protection
•Hiccup−Mode Overcurrent Protection (OCP)
•Thermal Shutdown (TSD)
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•LED Lighting
•Headlamps
•Backlighting
MARKING
DIAGRAM
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SOIC−8
D SUFFIX
CASE 751
1
8
PIN CONNECTIONS
1 8
2
3
4
7
6
5
(Top View)
EN
ISNS
GND
GDRV
VFB
VC
VIN
VDRV
8980xx = Specific Device Code
xx = 32
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
8980xx
ALYW
G
1
8
Device Package Shipping†
ORDERING INFORMATION
NCV898032D1R2G SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCV898032
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2
Gm 8
3
2
4
6
GND
ISNS
GDRV
VIN
VFB
5VDRV
CSA
OSC Q
NRVBS260T3G
L
SC
TEMP
VDRV
DRIVE
LOGIC
CL
SS
FAULT
LOGIC
CLK
1
EN
EN
7
VC
PWM
+
RC
CC
RSNS
RF1
Vref
CDRV
Vg
Vo
Cg
Co
Figure 1. Simplified Block Diagram and Application Schematic
D2
Dn
NVTFS5C680NLWFTAG
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin
Symbol Function
1 EN Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable
time−out period.
2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3 GND Ground reference.
4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance in addition to the internal.
5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to ground.
6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-
tion to a diode from the output voltage to VDRV and/or VIN.
7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.
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ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating Value Unit
Dc Supply Voltage (VIN) −0.3 to 40 V
Peak Transient Voltage (Load Dump on VIN) 45 V
Dc Supply Voltage (VDRV, GDRV) 12 V
Peak Transient Voltage (VFB) −0.3 to 6 V
Dc Voltage (VC, VFB, ISNS) −0.3 to 3.6 V
Dc Voltage (EN) −0.3 to 6 V
Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V
Operating Junction Temperature −40 to 150 °C
Storage Temperature Range −65 to 150 °C
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C265 peak °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.
PACKAGE CAPABILITIES
Characteristic Value Unit
ESD Capability (All Pins) Human Body Model
Machine Model
w2.0
w200
KV
V
Moisture Sensitivity Level 1
Package Thermal Resistance Junction−to−Ambient, RqJA (Note 1) 100 °C/W
1. 1 in2, 1 oz copper area used for heatsinking.
Ordering Options
The NCV898032 features several variants to better fit a
multitude of applications. The table below shows the typical
values of parameters for the parts that are currently
available.
TYPICAL VALUES
YY Dmax SCE tss SaVcl Isrc Isink VDRV
NCV898032 88% No 800 ms204 mV/ms200 mV 800 mA 600 mA 6.3 V
DEFINITIONS
Symbol Characteristic Symbol Characteristic Symbol Characteristic
Dmax Maximum duty cycle tss Soft−start time
SaSlope compensating ramp Vcl Current limit trip voltage Isrc Gate drive sourcing current
Isink Gate drive sinking current VDRV Drive voltage SCE Short Circuit Enable
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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic Symbol Conditions Min Typ Max Unit
GENERAL
Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C−2.0 −mA
Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C−2.0 6.0 mA
Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching −1.9 2.9 mA
Quiescent Current, Switching,
normal operation
Iq,on Into VIN pin, EN = 1, Switching −7.5 10 mA
OSCILLATOR
Minimum pulse width ton,min 30 65 90 ns
Maximum duty cycle Dmax YY = 32 85 87.5 91 %
Switching frequency fsYY = 32 1.8 2.0 2.2 MHz
Soft−start time tss From start of switching with VFB = 0 until
reference voltage = VREF
YY = 32 650 800 950
ms
Soft−start delay tss,dly From EN → 1 until start of switching with
VFB = 0 with floating VC pin 80 100 280
ms
Slope compensating ramp SaYY = 32 179 204 240 mV/ms
ENABLE
EN pull−down current IEN VEN = 5 V −5.0 10 mA
EN input high voltage Vs,ih VIN > VUVLO 2.0 −5.0 V
EN input low voltage Vs,il 0−800 mV
EN time−out ratio %ten From EN falling edge, to oscillator control
(EN high) or shutdown (EN low), Percent of
typical switching frequency
− − 350 %
CURRENT SENSE AMPLIFIER
Low−frequency gain Acsa Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V
Bandwidth BWcsa Gain of Acsa − 3 dB 2.5 − − MHz
ISNS input bias current Isns,bias Out of ISNS pin −30 50 mA
Current limit threshold voltage Vcl Voltage on ISNS pin
YY = 32 180 200 220
mV
Current limit,
Response time
tcl CL tripped until GDRV falling edge,
VISNS = Vcl(typ) + 60 mV
−80 125 ns
Overcurrent protection,
Threshold voltage
%Vocp Percent of Vcl 125 150 175 %
Overcurrent protection,
Response Time
tocp From overcurrent event, Until switching
stops, VISNS = VOCP + 40 mV
−80 125 ns
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance gm,vea VFB – Vref = ± 20 mV 0.80 1.20 1.63 mS
VEA output resistance Ro,vea 2.0 − − MW
VFB input bias current Ivfb,bias Current out of VFB pin −0.5 2.0 mA
Reference voltage Vref 0.194 0.200 0.206 V
VEA maximum output voltage Vc,max 2.5 − − V
VEA minimum output voltage Vc,min − − 0.3 V
VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 −mA
VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 −mA
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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic UnitMaxTypMinConditionsSymbol
GATE DRIVER
Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V
YY = 32 600 800 −
mA
Sinking current Isink VGDRV ≥ 2 V
YY = 32 500 600 −
mA
Driving voltage dropout Vdrv,do VIN − VDRV, IvDRV = 25 mA −0.3 0.6 V
Driving voltage source current Idrv VIN − VDRV = 1 V 35 45 −mA
Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA − − 0.7 V
Driving voltage VDRV VIN = 12 V, IVDRV = 0.1 − 25 mA
YY = 32 6.0 6.3 6.6
V
Pull−down resistance Rpd −15 −kW
UVLO
Undervoltage lock−out,
Threshold voltage
Vuvlo VIN falling 2.95 3.05 3.15 V
Undervoltage lock−out,
Hysteresis
Vuvlo,hys VIN rising 50 150 250 mV
THERMAL SHUTDOWN
Thermal shutdown threshold Tsd TJ rising 160 170 180 °C
Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C
Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns
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TYPICAL PERFORMANCE CHARACTERISTICS
010203040
VIN, INPUT VOLTAGE (V)
Figure 2. Sleep Current vs. Input Voltage
Iq,sleep, SLEEP CURRENT (mA)
TJ = 25°C
Figure 3. Sleep Current vs. Temperature
Figure 4. Quiescent Current vs. Temperature Figure 5. Minimum On Time vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Normalized Current Limit vs.
Temperature
−40 10 60 110 160
NORMALIZED CURRENT LIMIT (25°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Reference Voltage vs. Temperature
Vref, REFERENCE VOLTAGE (V)
−40 10 60 110 16
0
−50 0 50 100 20
0
Iq,sleep, SLEEP CURRENT (mA)
VIN = 13.2 V
0
1
2
3
4
5
6
150
TJ, JUNCTION TEMPERATURE (°C)
0
1
2
3
4
5
7
6
0.990
0.995
1.000
1.005
1.010
201.2
201.4
201.6
201.8
202.2
202
−50 50 100 150 200
TJ, JUNCTION TEMPERATURE (°C)
ton,min MINIMUM ON TIME (ns)
TJ, JUNCTION TEMPERATURE (°C)
−50 0 50 100 200
Iq,on, QUIESCENTCURRENT (mA)
7.1
7.2
7.4
7.5
7.6
7.7
61.5
62.0
62.5
63.0
64.5
64.0
0
VIN = 13.2 V
7.3
7.8
150
63.5
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Enable Pulldown Current vs. Voltage
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Enable Pulldown Current vs.
Temperature
Ienable, PULLDOWN CURRENT (mA)
01234
Venable, VOLTAGE (V)
Ienable, PULLDOWN CURRENT (mA)
TJ = 25°C
56 −40 10 60 110 16
0
0
1
2
3
4
5
7
6
5.0
5.5
6.0
6.5
7.0
7.5
8.0
NCV898032
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THEORY OF OPERATION
Current Mode Control
The NCV898032 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows for a simpler compensation.
The NCV898032 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
Current Limit
The NCV898032 features a peak current−mode current
limit protection. When the current sense amplifier detects a
voltage above the peak current limit between ISNS and
GND after the current limit leading edge blanking time, the
peak current limit causes the power switch to turn off for the
remainder of the cycle. Set the current limit with a resistor
from ISNS to GND, with R = VCL / Ilimit.
If the voltage across the current sense resistor exceeds the
over current threshold voltage the part enters over current
hiccup mode. The part will remain off for the hiccup time
and then go through the soft−start procedure.
EN
This pin has two modes. When a dc logic high
(CMOS/TTL compatible) voltage is applied to this pin the
NCV898032 operates at the programmed frequency. When
a dc logic low voltage is applied to this pin the NCV898032
enters a low quiescent current sleep mode. If an Enable
command is received during normal operation, the
minimum duration of the Enable low−state must be greater
than 7 clock cycles. The NCV898032 requires 2 clock cycles
after the falling edge of the Enable signal to stop switching.
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
It is highly recommended to keep EN pin voltage at a
lower amplitude than the VIN pin voltage during a UVLO
event.
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV898032 features a soft start which charges
a capacitor with a fixed current to ramp up the reference
voltage.
NCV898032
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APPLICATION INFORMATION
Figure 10. Current Mode Control Schematic
Gm
CSA
Slope
Compensation
Q
D1
PWM
Comparator
Compensation
D2
Dn
NCV898032
Q
S
Gate
Driver
Vg
ISNS
GDRV
RF1
VFB
VO
Oscillator
L
CO
RSNS
VREF
R
Boost LED Design Methodology
This section details an overview of the component
selection process for the NCV898032 in discontinuous
conduction mode (DCM) Boost converter operation with a
high brightness LED (100−150 mA typical) string as a load.
LED current is used for the feedback signal. It is intended to
assist with the design process but does not remove all
engineering design work. Many of the equations make use
of the small ripple approximation. This process entails the
following steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
ILED: LED current [A]
ICL: desired typical cycle-by-cycle current limit [A]
Vref: NCV898032 feedback reference voltage = 0.2 V
IL: inductor current [A]
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
Mmin +Vout
Vin(max)
Mmax +Vout
Vin(min)
Rout +Vout
ILED
Dmin +Lfs
2Rout ƪǒ2Mmin *1Ǔ2*1ƫ
Ǹ
Dmax +Lfs
2Rout ƪ(2Mmax *1)2*1ƫ
Ǹ
d+2Vout 2
VinRoutIL,peak *D,
Where: (D + d) < 1 for DCM operation IL.
Both duty cycles will actually be slightly higher due to
power loss in the conversion. The exact duty cycles depend
on conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be a complex value. This is because a Boost
converter cannot have an output voltage lower than the input
voltage. In situations where the input voltage is higher than
the output, the output will follow the input (minus the diode
drop of the Boost diode) and the converter will not attempt
to switch.
If the inductor value is too large, continuous conduction
mode (CCM) operation will occur and a right-half-plane
(RHP) zero appears which can result in operation instability.
If the calculated Dmax is higher than the Dmax of the
NCV898032, the conversion will not be possible. It is
important for a Boost converter to have a restricted Dmax,
because while the ideal conversion ration of a Boost
converter goes up to infinity as D approaches 1, a real
converter’s conversion ratio starts to decrease as losses
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overtake the increased power transfer. If the converter is in
this range it will not be able to maintain output regulation.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Dmin
fswton(min)
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor between the MOSFET source and ground. The sense
resistor should be selected as follows:
RSNS +VCL
ICL
Where: RSNS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desired current limit [A]
3. Select the Boost Inductor
The Boost inductor controls the current ripple that occurs
over a switching period. A discontinuous current ripple will
result in superior transient response and lower switching
noise at the expense of higher transistor conduction losses
and operating ripple current requirements. A low current
ripple will result in CCM operation having a slower response
current slew rate in case of load steps (e.g. introducing an
LED series dimming circuit). A good starting point is to
select components for DCM operation at Vin(min), but
operation should be verified empirically. Calculate the
maximum inductor value as follows:
Lmax +ǒ1*1
MmaxǓVin(min) 2ǒVout
ILEDǓ
2fsVout 2
The maximum average inductor current can be calculated
as follows:
IL,avg +VOUTIOUT(max)
VIN(min)
The peak inductor current can be calculated as follows:
IL,peak +VIN(min)Dmax
Lfs
Where: IL,peak: Peak inductor current value [A]
4. Select Output Capacitor
The output capacitor smoothes the output voltage and
reduces the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
VOUT(ripple) +ILEDǒ1*d(Mmax)Ǔ
fsCOUT
The capacitors must withstand an RMS ripple current as
follows:
ICout(RMS) +ILED 2)d(Mmax)ǒIL,pk 2
3*IL,pkILEDǓ
Ǹ
A 1−2.2 mF ceramic capacitor is usually sufficient for high
brightness LED applications for fs = 2 MHz.
5. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
ICin(RMS) +ǒD(Mmax))d(Mmax)
3ǓIL,pk 2*IL,avg 2
Ǹ
6. Select Feedback Resistors
The feedback resistor provides LED current sensing for
the feedback signal. It may be calculated as follows:
RF1 +Vref
ILED
7. Select Compensator Components
Current Mode control method employed by the
NCV898032 allows the use of a simple Type II
compensation to optimize the dynamic response according
to system requirements. A transconductance amplifier is
used, so compensation components must be connected
between the compensation pin and ground.
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out,
the selected MOSFET must not violate the following
inequality:
Qg(total) vIdrv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
IQ(max) +IL,peak
D(Mmax)
3
Ǹ
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltage:
VQ(max) +VOUT(max)
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9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
ID(avg) +IOUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage or the maximum input voltage:
VD(max) +VOUT
The maximum power dissipation in the diode can be
calculated as follows:
PD+Vf(max)IOUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode
[V]
Low Voltage Operation
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In Boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
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SEPIC TOPOLOGY APPLICATION INFORMATION
Oscillator
+
Q
S
R
NCV898032
Voltage Error
VEA
CSA
PWM Comparator Gate
Drive
Compensation
GDRV
L2
L1
Figure 11. SEPIC Current Mode Schematic
VFB
ISNS
VIN
RL
Co
CCPL
SEPIC Design Methodology
This section details an overview of the component
selection process for the NCV898032 in continuous
conduction mode SEPIC. It is intended to assist with the
design process but does not remove all engineering design
work. Many of the equations make heavy use of the small
ripple approximation. This process entails the following
steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select SEPIC Inductors
4. Select Coupling Capacitor
5. Select Output Capacitors
6. Select Input Capacitors
7. Select Feedback Resistors
8. Select Compensator Components
9. Select MOSFET(s)
10. Select Diode
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle−by−cycle current limit [A]
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
Dmin +VOUT
VIN(max) )VOUT
Dmax +VOUT
VIN(min) )VOUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses.
If the calculated DWC (worst case) is higher than the Dmax
limit of the NCV898032, the conversion will not be
possible. It is important for a SEPIC converter to have a
restricted Dmax, because while the ideal conversion ratio of
a SEPIC converter goes up to infinity as D approaches 1, a
real converter’s conversion ratio starts to decrease as losses
overtake the increased power transfer. If the converter is in
this range it will not be able to regulate properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Dmin
fswton(min)
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
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2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. Note that the
ICL equals the sum of the currents from both inductors. The
easiest method of generating this signal is to use a current
sense resistor from the source of the MOSFET to device
ground. The sense resistor should be selected as follows:
RS+VCL
ICL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
3. Select SEPIC Inductors
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is the minimum input voltage. After choosing a peak current
ripple value, calculate the inductor value as follows:
L+VIN(WC) DWC
DIL,max fs
Where: VIN(WC): VIN value as close as possible to half of
VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated as
follows:
IL,AVG +VOUT IOUT(max)
VIN(min)h
The Peak Inductor current can be calculated as follows:
IL1,peak +IL1,avg )DIL1
2
IL2,peak +IOUT(max) )DIL2
2
Where (if L1 = L2): DIL1 = DIL2
4. Select Coupling Capacitor
Coupling capacitor RMS current is significant. A low
ESR ceramic capacitor is required as a coupling capacitor.
Selecting a capacitor value too low will result in high
capacitor ripple voltage which will distort ripple current and
diminish input line regulation capability. Budgeting 2−5%
coupling capacitor ripple voltage is a reasonable guideline.
DVcoupling +Iout DWC
Ccoupling fs
Current mode control helps resolve some of the resonant
frequencies that create issues in voltage mode SEPIC
converter designs, but some resonance issues may occur. A
resonant frequency exists at
fresonance +1
2p(L1 )L2)Ccoupling
Ǹ
It may become necessary to place an RC damping network
in parallel with the coupling capacitor if the resonance is
within ~1 decade of the closed−loop crossover frequency.
The capacitance of the damping capacitor should be ~5
times that of the coupling capacitor. The optimal damping
resistance (including the ESR of the damping capacitor) is
calculated as
Rdamping +L1 )L2
Ccoupling
Ǹ
5. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
VOUT(ripple) +
IOUT(max)DWC
COUT fs)ǒIOUT(max)
1*DWC )DWCVIN(min)
2fsL2ǓResr
The capacitors need to survive an RMS ripple current as
follows:
ICout(RMS) +IOUT(max) 2DWC )ǒI2
a)I2
r
3*IaIrǓDȀWC
Ǹ
where
Ia+IL1_peak )IL2_peak *Iout
Ir+DIL1 )DIL2
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
6. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
ICin(RMS) +DIL1
12
Ǹ
7. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
Rupper +Rlower
ǒVout *VrefǓ
Vref
NCV898032
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14
The total feedback resistance (Rupper + Rlower) should be
in the range of 1 kW – 100 kW.
8. Select Compensator Components
Current Mode control method employed by the
NCV898032 allows the use of a simple, Type II
compensation to optimize the dynamic response according
to system requirements.
9. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Qg(total) vIdrv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
ID(max) +DWCǒIQ(peak) 2)ǒDIL1 )DIL2Ǔ2
3*IQ(peak)ǒDIL1 )DIL2ǓǓ
Ǹ
where
IQ(peak) +IL1_peak )IL2_peak
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
VQ(max) +VOUT(max) )VIN(max)
10. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
ID(avg) +IOUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
VD(max) +VOUT(max) )VIN(max)
The maximum power dissipation in the diode can be
calculated as follows:
PD+Vf(max) IOUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
NCV898032
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15
BOOST TOPOLOGY APPLICATION INFORMATION
Oscillator
Slope
Compensation
+
NCV898032
Voltage Error
VEA
CSA
PWM Comparator Gate
Drive
Compensation
L
GDRV
Figure 12. Boost Current Mode Schematic
S
R
Q
CORL
VOUT
VFB
ISNS
VIN
Boost Converter Design Methodology
This section details an overview of the component
selection process for the NCV898032 in continuous
conduction mode boost. It is intended to assist with the
design process but does not remove all engineering design
work. Many of the equations make heavy use of the small
ripple approximation. This process entails the following
steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Determine Feedback Loop Compensation Network
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle−by−cycle current limit [A]
From this the ideal minimum and maximum duty cycles can
be calculated as follows:
Dmin +1*VIN(max)
VOUT
DWC +1*VIN(WC)
VOUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated DWC is higher than the Dmax limit of the
NCV898032, the conversion will not be possible. It is
important for a boost converter to have a restricted Dmax,
because while the ideal conversion ratio of a boost converter
goes up to infinity as D approaches 1, a real converter’s
conversion ratio starts to decrease as losses overtake the
increased power transfer. If the converter is in this range it
will not be able to regulate properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
Dmin
fswton(min)
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
NCV898032
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2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
RS+VCL
ICL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
3. Select Output Inductor
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is half of VOUT, or whatever VIN is closest to half of VIN.
After choosing a peak current ripple value, calculate the
inductor value as follows:
L+VIN(WC) 2DWC
DIL,max fsVOUT
Where: VIN(WC): VIN value as close as possible to half of
VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated as
follows:
IL,avg +VOUTIOUT(max)
VIN(min)
The Peak Inductor current can be calculated as follows:
IL,peak +IL,avg )VIN(min) 2DWC
LfsVOUT
Where: IL,peak: Peak inductor current value [A]
4. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
VOUT(ripple) +
DIOUT(max)
fCOUT )ǒIOUT(max)
1*D)VIN(min)D
2fLǓRESR
The capacitors need to survive an RMS ripple current as
follows:
ICout(RMS) +IOUT
DWC
DȀWC )DWC
12 ǒDȀWC
L
ROUT TSWǓ2
Ǹ
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
5. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
ICin(RMS) +VIN(WC) 2DWC
LfsVOUT23
Ǹ
6. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
Rupper +Rlower
ǒVout *VrefǓ
Vref
The total feedback resistance (Rupper + Rlower) should be
in the range of 1 kW – 100 kW.
7. Select Compensator Components
Current Mode control method employed by the
NCV898032 allows the use of a simple, Type II
compensation to optimize the dynamic response according
to system requirements.
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
Qg(total) vIdrv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
IQ(max) +Iout
DWC
Ǹ
DȀWC
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
VQ(max) +VOUT(WC)
9. Select Diode
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
ID(avg) +IOUT(max)
NCV898032
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Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
VD(max) +VOUT(max)
The maximum power dissipation in the diode can be
calculated as follows:
PD+Vf(max) IOUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
10. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC-VC signal if R2 is of similar order of magnitude as RESD.
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type-I compensation is not possible due to the presence
of R
ESD. The Figures 13 and 14 compensation networks
correspond to a Type-II network in series with R
ESD.
The resulting control-output transfer function is an accurate
mathematical model of the IC in a boost converter topology.
The model does have limitations and a more accurate SPICE
model should be considered for a more detailed analysis:
•The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
•The CCM Boost control-output transfer function
includes operating efficiency as a correction factor to
improve modeling accuracy under low input voltage
and high output current operating conditions where
operating losses becomes significant.
Rds(on)
Vd
L
GND
ISNS
VFB
GDRV
VC
Ri
COUT
VOUT
C1
R2
VCTRL
OTA
VIN rL
rCf
C2
ROUT
RESD
R0
R1
Rlow
Figure 13. NCV898032 Boost Converter OTA and Compensation
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Rds(on)
Vd
GND
ISNS
VFB
GDRV
VC
Ri
COUT
VOUT
C1
R2
VCTRL
OTA
VIN
rCf
C2
ROUT
RESD
R0
R1
Rlow
Lp
1:N
VREF
Figure 14. NCV898032 Flyback Converter OTA and Compensation
The following equations may be used to select compensation
components R
2, C1, C2 for Figures 13 & 14 power supply.
Required input design parameters for analysis are:
Vd = Output diode Vf (V)
VIN = Power supply input voltage (V)
N = Ns/Np (Flyback transformer turns ratio)
Ri = Current sense resistor (W)
RDS(on) = MOSFET RDS(on) (W)
(Rsw_eq = RDS(on) + Ri for the boost continuous conduction
mode (CCM) expressions)
COUT = Bulk output capacitor value (F)
rCF = Bulk output capacitor ESR (W)
ROUT = Equivalent resistance of output load (W)
Pout = Output Power (W)
L = Boost inductor value or flyback transformer primary
side inductance (H)
rL = Boost inductor ESR (W)
T
s = 1/fs, where fs = 2 MHz clock frequency
R1 and Rlow = Feedback resistor divider values used to set the
output voltage (W)
VOUT = Device specific output voltage (defined by R1 and
Rlow values) (V)
R0 = OTA output resistance = 3 MW
Sa= IC slope compensation (e.g. 34 mV/ms for NCV898032)
gm = OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
Necessary equations for describing the modulator gain
(Vctrl-to-Vout gain) Hctrl_output(f) are described next. Boost
continuous conduction mode (CCM) and discontinuous
conduction mode (DCM) transfer function expressions are
summarized in Table 1. Flyback CCM and DCM transfer
function expressions are summarized in Table 2.
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Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM DCM
Duty Ratio (D)
ȧ
ȧ
ȧ
ȡ
Ȣ
2ROUTVdVIN*ƪRsw_eq)ROUTǒVIN
VOUT*2ǓƫVOUT2
-VOUT ROUTǒROUTVIN2)2Rsw_eqVINVOUT*4VdRsw_eqVIN
-4Rsw_eqVOUT2*4rLVdVIN*4rLVOUT2Ǔ)Rsw_eq2VOUT2
Ǹȧ
ȧ
ȧ
ȣ
Ȥ
2ROUTǒVOUT2)VdVINǓ
Where:
2tLM(M *1)
Ǹ
tL+L
ROUTTs
VOUT/VIN DC
Conversion Ratio
(M)
1
1*Dƪ1*(1 *D)Vd
VOUT ƫȧ
ȧ
ȧ
ȱ
Ȳ
1
1)1
(1*D)2ǒrL)DRsw_eq
ROUT Ǔ
ȧ
ȧ
ȧ
ȳ
ȴ
1
2ǒ1)1)2D2
tL
ǸǓ
Inductor On-slope
(Sn), V/s VIN *ILaveǒrL)Rsw_eqǓ
LRi
Where average inductor current: ILave +
Pout
VINh
VIN
LRi
Compensation
Ramp (mc)1)Sa
Sn
1)Sa
Sn
Cout ESR Zero
(w
z1)
1
rCFCOUT
1
rCFCOUT
Right-Half-Plane
Zero (w
z2)(1*D)2
LǒROUT *
rCFROUT
rCF )ROUTǓ*
rL
L
ROUT
M2L
Low Frequency
Modulator Pole
(w
p1)
2
ROUT )Ts
LM3mc
COUT
1
RCFCOUT
@2M *1
M*1
High Frequency
Modulator Pole
(w
p2)−2FSWǒ1*1
M
DǓ2
Sampling Double
Pole (w
n)
p
Ts
−
Sampling Quality
Coefficient (Qp)
1
p(mc(1*D)*0.5)−
Fm1
2M )ROUTTs
LM2ǒ1
2)Sa
SnǓ1
SnmcTs
HdhROUT
Ri
2VOUT
D@M*1
2M *1
Control-Output
Transfer Function
(Hctrl_output (f))FmHd
ǒ1)j2pf
wz1Ǔǒ1*j2pf
wz2Ǔ
ǒ1)j2pf
wp1Ǔǒ1)j2pf
wnQp)ǒj2pf
wnǓ2ǓFmHd
ǒ1)j2pf
wz1Ǔǒ1*j2pf
wz2Ǔ
ǒ1)j2pf
wp1Ǔǒ1)j2pf
wp2Ǔ
NCV898032
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Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM DCM
Duty ratio (D)
VOUT
VOUT )NVIN Where:
VOUT
NVIN
2tL
Ǹ
tL+
N2Lp
TsROUT
VOUT/VIN DC Conversion
Ratio (M)N@D
1*D
N@D
2@tL
Ǹ
Inductor On-slope (Sn), V/s VIN
Lp
Ri
VIN
Lp
Ri
Compensation Ramp (mc)
1)Sa
Sn
1)Sa
Sn
Cout ESR Zero (w
z1)1
rCFCOUT
1
rCFCOUT
Right-Half-Plane Zero (w
z2)(1*D)2ROUT
DLpN2
ROUT
N2Lp
@1
M(M )1)
Modulator Pole (w
p1)DȀ3
2tL
ǒ1)2 Sa
SnǓ)1)D
ROUTCOUT
2
ROUTCOUT
w
p2
−2FSWǒ1
D
1)1
MǓ2
Fm1
DȀ2
tLǒ1)2 Sa
SnǓ)2M )1
1
SnmcTs
HdROUT
RiN
VIN1
2tL
Ǹ
Control-output Transfer
Function (Hctrl_output (f))
FmHd
ǒ1)j2pf
wz1Ǔǒ1*j2pf
wz2Ǔ
ǒ1)j2pf
wp1ǓFmHd
ǒ1)j2pf
wz1Ǔǒ1*j2pf
wz2Ǔ
ǒ1)j2pf
wp1Ǔǒ1)j2pf
wp2Ǔ
Once the desired cross-over frequency (fc) gain
adjustment and necessary phase boost are determined from
the Hctrl_output(f) gain and phase plots, the Table 3 equations
may be used. It should be noted that minor compensation
component value adjustments may become necessary when
R2 ≤ ~10·Resd as a result of approximations for determining
components R2, C1, C2.
NCV898032
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Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES
Desired OTA Gain at Cross-over Frequency fc (G)
10
desired_Gfc_gain_db
20
Desired Phase Boost at Cross-over Frequency fc (boost)ǒqmargin *argǒHctrl_output(fc)Ǔ180°
p*90° Ǔp
180°
Select OTA Compensation Zero to Coincide
with Modulator Pole at fp1 (fz)
wp1e
2p
Resulting OTA High Frequency Pole Placement (fp)fzfc)fc2tan(boost)
fc*fztan(boost)
Compensation Resistor R2
fpG
fp*fz
VOUT
1.2gm
1)ǒfc
fpǓ2
Ǹ
1)ǒfz
fpǓ
Ǹ
Compensation Capacitor C11
2pfzR2
Compensation Capacitor C21
2pfpG@
Rlowgm
Rlow )R1
OTA DC Gain (G0_OTA)Rlow
Rlow )R1
@gm@R0
Low Frequency Zero (w
z1e)
1
2
ǒR2)ResdǓ
R2ResdC2ȧ
ȱ
Ȳ1*1*4R2ResdC2
ǒR2)ResdǓ2C1
Ǹ
ȧ
ȳ
ȴ
High Frequency Zero (w
z2e)
1
2
ǒR2)ResdǓ
R2ResdC2ȧ
ȱ
Ȳ1)1*4R2ResdC2
ǒR2)ResdǓ2C1
Ǹ
ȧ
ȳ
ȴ
Low Frequency Pole (w
p1e)
1
2
ǒR0)R2)ResdǓ
R2ǒR0)ResdǓC2ȧ
ȱ
Ȳ1*1*4R2ǒR0)ResdǓC2
ǒR0)R2)ResdǓ2C1
Ǹ
ȧ
ȳ
ȴ
High Frequency Pole (w
p2e)
1
2
ǒR0)R2)ResdǓ
R2ǒR0)ResdǓC2ȧ
ȱ
Ȳ1)1*4R2ǒR0)ResdǓC2
ǒR0)R2)ResdǓ2C1
Ǹ
ȧ
ȳ
ȴ
OTA Transfer Function (GOTA(f))
-G0_OTA
ǒ1)j2pf
wz1eǓ
ǒ1)j2pf
wp1eǓ
ǒ1)j2pf
wz2eǓ
ǒ1)j2pf
wp2eǓ
The open-loop-response in closed-loop form to verify the
gain/phase margins may be obtained from the following
expression.
T(f) +GOTA(f) Hctrl_output(f)
Low Voltage Operation
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
NCV898032
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PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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NCV89803/D
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