DesignObjects (R) IC Master Interface Features n Support of IC fast-mode up to 400 kHz n System clock up to 50 MHz n Reading and writing of data bursts n Special mode for IC read and write access to a slave device internal register address n Wait state generation supported n Spike filtering Purpose of the IC Master Interface The IC Master Interface IIC_M provides an interface between a host CPU and an IC bus. The external components at the IC bus can be controlled by the host CPU over IC Master Interface. Basically, the IC Master Interface is a parallel to serial and serial to parallel converter. The parallel data received from the host CPU has to be converted to a suitable serial form for the external components on the IC bus. Also the serial data received from the IC bus has to be converted to a suitable parallel form for the host CPU. The IC Master Interface also takes care of the interface timing, data structure and error handling. IC Master Interface DesignObjects (R) The IC Master Interface supports four operating modes: n Direct Write, writing of a data burst n Direct Read, reading of a data burst n Random Access Write, writing of one data byte to a specified address n Random Access Read, reading of one data byte from a specified address The IC Master Interface supports both data transfer modes on the IC bus with data transfer rates up to 100 kbit/s in standard-mode and up to 400 kbit/s in fast-mode. Interface to Host CPU The IC Master Interface includes three register elements for communication between the host CPU and the IC bus. They are addressed with signal HIF_adr[1:0]: n Writeable 32 bit data register, HIF_adr[1:0]: 0x0 and HIF_adr[1:0]: 0x1 n Writeable 16 bit configuration register, HIF_adr[1:0]: 0x2 n Readable 16 bit data register, HIF_adr[1:0]: 0x3 DATA Register 32 bit The 32 bit writeable data register is divided into two 16 bit registers conform to the 16 bit data bus of the host CPU. These two separate parts of the register are called data_reg_high[15:0] and data_reg_low[15:0]. At the beginning of a read/write access this 32 bit register is loaded with the information from the host CPU needed for the data transfer on the IC bus. This information consists of 7 bit device code, 8 bit address, 8 bit data and 2 bit for the read or write mode. 7 of the 32 bits are not used. If the device number doesn't change, only the lower part of the data register has to be loaded to start a new data transfer. Data transfer on the IC bus begins always, when data_reg_low[15:0] has been loaded. Configuration Register The 16 bit writeable configuration register is needed for some special configuration information, which can be changed by the host CPU. Interrupt masking is one example of that kind of configuration. Some bits are also used as a reference frequency for the clock signal generation on the IC bus and programming of the spike filter. Data Register 16 bit The 16 bit readable data register contains the 8 bit data received from the IC bus in Random Access Read mode and Direct Read mode. This register contains also an error bit, an interrupt bit and a write_allowed bit. The error bit is generated (set to `1') if data transfer has failed. If the interrupt bit is set to `1', the register includes new data which has to be read by the host CPU. After the data has been read, the interrupt bit is reset to `0'. When the interrupt signal is disabled (irq bit in configuration register is set to `0'), the interrupt information is request from the host CPU by polling. The interrupt bit in the data register is generated without respect to the irq bit in the configuration register. The IICCLK signal can be stalled by any IC device so that no data can be transmitted via the IC bus. If a proceeding write access has not been completed, the next write access will not be acknowledged. To prevent this, the 16 bit readable data register provides a write_allowed bit. This write_allowed bit is set to `0', if the 32 bit data register is ready for a new write access. The host CPU might read the write_allowed register before a new write access. Gate Count and RAM Requirements IC Master Interface Gate Count Estimation: about 2,000 Gates. No RAM required. Related Patents I2C is a trademark of Philips, Inc. Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components of the I2C system, provided the system conforms to the I2C specifications defined by Philips. For I2C licensing information please contact the Philips Corporate Intellectual Property department. sci-worx GmbH, Garbsener Landstr. 10, 30419 Hannover, Germany Phone +49 511 277.1491, fax .2490, web www.sci-worx.com, email info@sci-worx.com US Office : sci-worx Microelectronics Corp., 1032 Elwell Court, Suite 222, Palo Alto, CA 94303 Phone +1 650 625.1888, fax .1818, web www.sci-worx.com, email info@sci-worx.com Technical data is subject to change without notice. All rights reserved. All trademarks are registered trademarks of their respective owner. Copyright (c) sci-worx GmbH.