DS073 (v1.5) October 9, 2001 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA device s
• Simple interf ace to the FPGA
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS Floating Gate process
• 3.3V supply voltage
• Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Dual configuration modes for the XC17V16 and
XC17V 08 devices
- Serial slow/fast configuration (up to 33 Mb/s)
- Parallel (up to 264 Mb/s at 33 MHz)
• Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstre ams. In iti al devices in t he 3.3V family ar e available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1
and Figure 2 for simpl ified block dia grams of the XC17V00
family.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
D ATA output pin that is connected to the FPGA DIN pin. The
FPGA gene rates the app ro pr iate number of cl ock puls es t o
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the f ollowing rising edge of the
CCLK. A free-running oscillator may be used to drive CCLK.
See Figure 3.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programmin g, eithe r the Xi linx Al lianc e or Foun-
dation series development system compiles the FPGA
design fi le into a standard Hex for mat, which is then tran s-
ferred to most commercial PROM programmers.
0XC17V00 Series Configuration
PROM
DS073 (v1.5 ) October 9, 2001 08Advance Product Specification
R
XC17V00 Series Configuration PROM
2www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Pr odu ct Specifi cati on
R
Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit)
Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
VCC VPP GND
DS073_01_072600
TC
OE
RESET/
OE/
RESET
or
CEO
EPROM
Cell
Matrix
Address Counter
CE
D0 Data
(Serial or Parallel Mode)
OE
8
Output
CLK
BUSY
VCC VPP GND
DS073_02_072600
TC
OE
RESET/
OE/
RESET
or
D[1:7]
(SelectMAP Interface)
CEO
77
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 3
Advance Product Specification 1-800-255-7778
R
Pin Description
DATA[0:7]
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the D0 pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
Note: XC17V04 , XC 17 V02, and XC 17 V01 have serial ou tpu t
only.
CLK
Each rising edge on the CLK input increments the inter nal
address counter, if both CE and OE are active.
RESET/OE
When High, th is input holds the add ress counte r reset an d
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at “0”, and puts the DATA output in a
high-im ped anc e state. The po larity of thi s inpu t is pr ogram-
mable. The default is active High RESE T, but the p referred
option is active Low RESET, because it can connected to
the FPGAs INIT pin and a pullup resistor.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW -130 Programmer. Third-party programmers have diff er-
ent methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-ICC standby mode.
CEO
Chip Enable o utput, to be conn ected to the C E input of the
next PROM in the dais y ch ain. Th is outp ut is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE i s active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
BUSY (XC17V16 and XC17V08 only)
If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to be internally tied to a
pull-down resistor. When asserted High, output data are
held and when BUSY pin goes Low, data output will
resume.
VPP
Programming voltage. No overshoot above the specified
max voltage is p ermitted on this p in . For normal rea d oper -
ation, this pin must be connected to VCC. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
VPP floating!
VCC and GND
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
(Pins not listed are “no connect”)
Capacity
Pin Name 44-pin VQFP 44-pin PLCC
BUSY 24 30
D0 40 2
D1 29 35
D2 42 4
D3 27 33
D4 9 15
D5 25 31
D6 14 20
D7 19 25
CLK 43 5
RESET/OE
(OE/RESET)13 19
CE 15 21
GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43
CEO 21 27
VPP 35 41
VCC 8, 16, 17, 26, 36,
38 14, 22, 23, 32,
42, 44
Devices Configuration Bits
XC17V16 16,777,216
XC17V08 8,388,608
XC17V00 Series Configuration PROM
4www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Product Specifi cati on
R
PROM Pinouts for XC17V04, XC17V02, and
XC17V01 (Pins not listed are “no connect”)
Capacity
Controlling PROMs
Connecting the FPGA device with the PROM.
•The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
•The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
•The CEO output of a PROM dr ives th e CE input of the
next PROM in a daisy chain (if any).
•The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connect ion assur es that th e PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a VCC glitch.
•The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
•SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
Pin Name
8-pi
VOIC
(1)
20-pin
SOIC
(1)
20-pin
PLCC
(1,2)
44-pin
VQFP
(2)
44-pin
PLCC
(2)
DATA 1 1 1 40 2
CLK 2 3 3 43 5
RESET/OE
(OE/RESET)38 8 1319
CE 410101521
GND 5 11 11 18, 41 24, 3
CEO 613132127
VPP 718183541
VCC 820203844
Notes:
1. XC17V01 available in these packages.
2. XC17V02 and XC17V04 available in these packages.
Devices Configuration Bits
XC17V04 4,194,304
XC17V02 2,097,152
XC17V01 1,679,360
Xilinx FPGAs and Compatible PROMs
Device Configuration
Bits PROM
XC2V40 360,160 XC17V01
XC2V80 635,360 XC17V01
XC2V250 1,697,248 XC17V02
XC2V500 2,761,952 XC17V04
XC2V1000 4,082,656 XC17V04
XC2V1500 5,659,360 XC17V08
XC2V2000 7,492,064 XC17V08
XC2V3000 10,494,432 XC17V16
XC2V4000 15,660,000 XC17V16
XC2V6000 21,849, 568 XC17V16 +
XC17V08
XC2V8 000 2 9,06 3,0 72 2 of XC17V16
XCV50 559,200 XC17V01
XCV100 781,216 XC17V01
XCV150 1,040,096 XC17V01
XCV200 1,335,840 XC17V01
XCV300 1,751,808 XC17V02
XCV400 2,546,048 XC17V04
XCV600 3,607,968 XC17V04
XCV800 4,715,616 XC17V08
XCV1000 6,127,744 XC17V08
XCV50E 630,048 XC17V01
XCV100E 863,840 XC17V01
XCV200E 1,442,106 XC17V01
XCV300E 1,875,648 XC17V02
XCV400E 2,693,440 XC17V04
XCV405E 3,430,400 XC17V04
XCV600E 3,961,632 XC17V04
XCV812E 6,519,648 XC17V08
XCV1000E 6,587,520 XC17V08
XCV1600E 8,308,992 XC17V08
XCV2000E 10,159,648 XC17V16
XCV2600E 12,922,336 XC17V16
XCV3200E 16,283,712 XC17V16
Notes:
1. The suggested PROM is determined b y compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Xilinx FPGAs and Compatible PROMs
Device Configuration
Bits PROM
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 5
Advance Product Specification 1-800-255-7778
R
FPGA Master Serial Mode Summary
The I/O and lo gic fun ctions of the Con figurable Logi c Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the thr ee FP G A mo de p ins. In M aster Se rial
mode, the FP GA auto matic ally lo ads th e con figuration pro-
gram from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial
mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, two control lines, and a clock
line are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up/down resistor or keeper circuit.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded P ROMs provide a dditional memo r y. Aft er the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 3.
After c onfiguration is complete, the a ddress coun ters of all
cascaded PROMs are reset if the FPGA PROGRAM pin
goes Low, assuming the PROM reset polarity option has
been inverted.
XC17V00 Series Configuration PROM
6www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Product Specifi cati on
R
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode
(dotted lines indicates optional connection)
PROGRAM
DIN
CCLK
INIT
DONE
First
PROM
DATA
CEO
BUSY BUSY
CLK
CE
OPTIONAL
Slave FPGAs
with identical
configurations
FPGA
(Low Resets the Address Pointer)
VCC Vpp
OPTIONAL
Daisy-chained
FPGAs with
different
configurations
OE/RESET
DOUT
Modes(1)
BUSY BUSY
Virtex SelectMAP Mode, XC17V16 and XC17V08 only.
4.7K
4.7K
VCC VCC
VCC Vpp
VCC
VCC
VCC
(2)
Master Serial Mode
DS073_03_100901
(1) For Mode pin connections, refer to the appropriate FPGA data sheet.
(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.
Cascaded
PROM
DATA
CLK
CE
OE/RESET
PROGRAM
VIRTEX
SelectMAP
BUSY
CS
WRITE
INIT
D[0:7]
CCLK
DONE
CLK
D[0:7]
CE
OE/RESET
First
PROM Second
PROM
Modes(3)
3.3V
External
Osc(4)
CEO
4.7K
(2)
VCC
VCC Vpp
VCC
1K
I/O(1)
8
I/O(1)
1K
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet.
(4) External oscillator required for Virtex/E SelectMAP or Virtex-II slave SelectMAP modes.
CLK
D[0:7]
CE
OE/RESET
CEO
VCC
VCC Vpp
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 7
Advance Product Specification 1-800-255-7778
R
Standby Mode
The PROM enters a low-power standby mode whenev er CE
is asser ted High. The output remains in a high impedance
state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Table 1: Truth Table for XC17V00 Control Inputs
Control Inputs
Internal Address
Outputs
RESET CE DATA CEO ICC
Inactive Low If address < TC(1): increment
If address > TC(1): don’t change Active
High-Z High
Low Active
Reduced
Active Low Held reset High-Z High Active
Inactive High Not changing High-Z High Standby
Active High Held reset High-Z High Standby
Notes:
1. The XC17V00 RESET input has programmable polarity
1. TC = Terminal Count = highest address value. TC + 1 = address 0.
XC17V00 Series Configuration PROM
8www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Product Specifi cati on
R
Absolute Maxim um Ratings
Operating Conditions (3V Supply)
DC Characteristics Over Operating Condition
Symbol Description Conditions Units
VCC Supply voltage relative to GND –0.5 to +7.0 V
VPP Supply voltage relative to GND –0. 5 to +12.5 V
VIN Input voltage relative to GND –0.5 to VCC +0.5 V
VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) –65 to +150
p
C
TSOL Maximum soldering temperature (10s @ 1/16 in.) +260
p
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and func tio nal o peration of th e device at the se o r any other co ndi tio ns beyond tho se li sted under Operating Condi tions
is not implied. Expo sure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
VCC(1) Supply voltage relative to GND (TA = 0
p
C to +70
p
C) Commercial 3.0 3.6 V
Supply voltage relative to GND (TA = –40
p
C to +85
p
C) Industrial 3.0 3.6 V
TVCC VCC rise time from 0V to nominal voltage 1.0 50 ms
Notes:
1. During normal read operation VPP must be connected to VCC.
2. At pow er up , the de vi ce require s the VCC po wer s upply to mon otonicall y rise from 0V to nominal v olt age withi n the spec ified VCC ris e
time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly.
Symbol Description Min Max Units
VIH High-level in put voltage 2 VCC V
VIL Low-level input voltage 0 0.8 V
VOH High-level output voltage (IOH = –3 mA) 2.4 - V
VOL Low-level output voltage (IOL = +3 mA) - 0.4 V
ICCA Supply current, active mode (at maximum frequency)
(XC17V16 and XC17V08 only) -100mA
ICCA Supply current, active mode (at maximum frequency)
(XC17V04, XC17V02, and XC17V01 only) -15mA
ICCS Supply current, standby mode - 1 mA
ILInput or output leakage current –10 10
N
A
CIN Input capacitance (VIN = GND, f = 1.0 MHz) - 15 pF
COUT Output capacitance (VIN = GND, f = 1.0 MHz) - 15 pF
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 9
Advance Product Specification 1-800-255-7778
R
AC Characteristics Over Operating Condition for XC17V04, XC17V02, and
XC17V01
Symbol Description Min Max Units
TOE OE to data delay - 30 ns
TCE CE to data delay - 45 ns
TCAC CLK to data delay - 45 ns
TDF CE or OE to data float delay(2,3) -50ns
TOH Data hold from CE, OE , or CLK(3) 0-ns
TCYC Clock periods 67 - ns
TLC CLK Low time(3) 25 - ns
THC CLK High time(3) 25 - ns
TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns
THCE CE hold time to CLK (to guarantee proper counting) 0 - ns
THOE OE hold time (guarantees counters are reset) 25 - ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
RESET/OE
CE
CLK
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC TOH TDF
TOH
THC
DS073_04_072600
TCYC
XC17V00 Series Configuration PROM
10 www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Product Specifi cati on
R
AC Characteristics Over Operating Condition for XC17V16 and XC17V08
Symbol Description Min Max Units
TOE OE to data delay - 15 ns
TCE CE to data delay - 20 ns
TCAC CLK to data delay(2) -20ns
TDF CE or OE to data float delay(3,4) -35ns
TOH Data hold from CE, OE , or CLK(4) 0-ns
TCYC Clock periods 50 - ns
TLC CLK Low time(4) 25 - ns
THC CLK High time(4) 25 - ns
TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns
THCE CE hold time to CLK (to guarantee proper counting) 0 - ns
THOE OE hold time (guarantees counters are reset) 25 - ns
TSBUSY BUSY setup time 5 - ns
THBUSY BUSY hold time 5 - ns
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
RESET/OE
CE
CLK
BUSY
DATA
TCE
TOE
TLC
TSCE TSCE THCE
THOE
TCAC
TSBUSY THBUSY
TOH TDF
TOH
THC
DS073_05_072600
TCYC
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 11
Advance Product Specification 1-800-255-7778
R
AC Characteristics Over Operating Condition When Cascading
Symbol Description Min Max Units
TCDF CLK to data float delay(2,3) -50 ns
TOCK CLK to CEO delay(3) -30 ns
TOCE CE to CEO delay(3) -35 ns
TOOE RESET/OE to CEO delay(3) -30 ns
Notes:
1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady
state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
CLK
DATA
CE
CEO
First Bit
Last Bit
TCDF
DS026_07_020300
OE/RESET
TOCK TOOE
TOCE
XC17V00 Series Configuration PROM
12 www.xilinx.com DS073 (v1.5) October 9, 2001
1-800-255-7778 Advance Product Specifi cati on
R
Ordering Information
Valid Ordering Comb inatio ns
Marking Information
Due to the smal l s ize of the c ommer cial ser i al PROM packag es, the com plete order ing part numb er cann ot be marked o n
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16VQ44C XC17V08VQ44C XC17V04PC20C XC17V02PC20C XC17V01PC20C
XC17V16PC44C XC17V08PC44C XC17V04PC44C XC17V02PC44C XC17V01VO8C
XC17V16VQ44I XC17V08VQ44I XC17V04VQ44C XC17V02VQ44C XC17V01SO20C
XC17V16PC44I XC17V08PC44I XC17V04PC20I XC17V02PC20I XC17V01PC20I
XC17V04PC44I XC17V02PC44I XC17V01VO8I
XC17V04VQ44I XC17V02VQ44I XC17V01SO20I
XC17V16 PC44 C
Operating Range/Processing
C = Commercial (TA = 0
p
to +70
p
C)
I = Industrial (TA = –40
p
to +85
p
C)
Package Type
VQ44 = 44-pin Pl astic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
Device Number
XC17V16
XC17V08
XC17V04
XC17V02
XC17V01
XC17V16 PC44 C
Operating Range/Processing
C = Commercial (TA = 0
p
to +70
p
C)
I = Industrial (TA = –40
p
to +85
p
C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Pack age
PC44 = 44-pin Plastic Chip Carrier
V08 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
Device Number
XC17V16
XC17V08
XC17V04
XC17V02
XC17V01
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001 www.xilinx.com 13
Advance Product Specification 1-800-255-7778
R
Revision History
The following table shows the revision history for this document.
Date Version Revision
07/26/00 1.0 Initial Xilinx release.
10/09/00 1.1 Updated 20-pin PLCC Pinouts.
11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, ICCA DC Ch aracteristic from sta n dby to ac t ive
mode; CIN and COUT from 10 pF to 15 pF, added ICCS f or XC17V16 and XC17V08 at 500
N
A.
02/20/01 1.3 Added note to pinouts for “no connect,” updated Figure 3.
04/04/01 1.4 Added XC2V products to Compatible PROM table, updated Figure 3, updated text for
Virtex-II FPGAs.
10/09/01 1.5 Corrected bitstream length for SCV405E, added power-on supply requirements and note for
power-on reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3,
and updated FPGA list.
