128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347B
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 40 8-943-2600
February 9, 2000
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zer o w ait states
• Fully registered inputs and outputs f or pi pelined oper-
ation
• 128K by 36 com m on I/ O architecture
• 3 .3 V co re p ower s u pp ly
• 2 .5 V /3 .3 V I/O ope ra ti o n
• Fast clock-to-output times
—3.5 ns (f or 166-MHz device)
—4.0 ns (f or 133-MHz device)
—5.5 ns (f or 100-MHz device)
• User-selectable burst counter supporting Intel Pen-
tium interl eaved or linear burst sequences
• Sep arate processor and contr oller addr ess strobes
• Synchronous self-timed writes
• Asy nchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
• Avai lable in Industrial and Commercial Temperature
ranges
Functional Description
The CY7 C1347B i s a 3 .3V, 12 8K b y 3 6 s ynch ronous- pipeline d
cache SRAM designed to support zero-wait-state secondary
cache with minimal glue logic.
The CY7C1347B I/ O pins can operat e at ei ther the 2. 5V or t he
3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V.
All sync hronous i nputs pass through i nput regi ster s control led
by the risi ng edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1347B supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the P owerPC. The burst
sequence is select ed through the MODE pi n. Accesses can be
initi ated by asserting either the proces sor address strobe (AD-
SP) or t he control ler address st robe (ADSC) at cloc k rise. Ad-
dress advancement through the burst sequence is controlled
by the ADV input. A 2-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A G lobal Writ e Enable (GW) overrides
all b yte write inpu ts and writes data to all four b ytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state con trol . In order to provi de prop-
er data during depth expansion, OE is m asked duri ng the fi rst
clock of a read c ycle when emergi ng from a deselect ed state.
Pentium and Intel are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
A[16:0]
GW
BWE
BW3
BW2
BW1
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
OUTPUT
REGISTERS INPUT
REGISTERS
128KX36
MEMORY
ARRAY
CLK CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
36 36
17
15
15
17
(A[1;0])2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
DP[3:0]
DQ[31:24], DP[3]
BYTEWRITE
REGISTERS
DQ
DQ[23:16], DP[2]
BYTEWRITE
REGISTERS
DQ
DQ
DQ[15:8], DP[1]
BYTEWRITE
REGISTERS
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
DQ
ENABL E CE
REGISTER
DQ
ENABLE DELAY
REGISTER
DQ
CY7C1347B
2
Pin Configuration
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
DP1
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
DP0
DP2
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
DP3
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE0
BYTE1
BYTE3
BYTE2
100-Pin TQFP
CY7C1347B
CY7C1347B
3
Pin Configuration (continued )
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC DQPc
DQc
DQd
DQc
DQd
AA AAADSP VDDQ
CE2A
DQc
VDDQ
DQc
VDDQ
VDDQ
VDDQ
DQd
DQd
NC
NC VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
VDD
TDOTCKTDITMS NCNC NC
VDDQ
VDDQ
VDDQ
AAAA
NC
AA
A
AA
AA0
A1
DQa
DQc
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
DQb
VDD
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS DQPa
MODE
DQPd
DQPb
BWb
BWc
NC VDD NC
BWa
NC
BWE
BWd
ZZ
119-Ball BGA
A
Selection Guide
7C1347B-166 7C1347B-133 7C1347B-100
Maximum Access Time (ns) 3.5 4.0 5.5
Maxim um Operating Current (mA) Commercial 420 375 325
Maximum CMOS Standby Current (mA) Commercial 10 10 10
CY7C1347B
4
Pin Definitions
Pin Number Name I/O Description
50–44, 81,
82, 99, 100,
32–37
A[16:0] Input-
Synchronous Address Input s used to select one of the 64K address locations. Sampl ed at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
96–93 BW[3:0] Input-
Synchronous Byte W rite Select Inputs, active LOW. Qual ified with BWE to co n duct by te write s
to the SRAM. Sampl ed on the rising edge of CLK.
88 GW Input-
Synchronous Global Write Enabl e Input, acti ve LO W . When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL byt es are written, regardless of the values
on BW[3:0] and BWE).
87 BWE Input-
Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LO W to conduct a byt e write.
89 CLK Input-Clock Clock Input. Used to captu re all synchronous inputs to the device. Also used to
increment t he burst c ounter when ADV is asserted LOW, during a bur st operation.
98 CE1Input-
Synchronous Chip Enable 1 Input, ac ti ve LOW. Sampled on the rising edge of CLK. Used in
conj unction with CE2 and CE3 to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampl ed on the ri sing edge of CLK. Used in
conj unction with CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, ac ti ve LOW. Sampled on the rising edge of CLK. Used in
conj unction with CE1 and CE2 to sel ect/desel ect the device.
86 OE Input-
Asynchronous Output Enable, asynchronous input , active LO W. Controls the direction of the I/O
pins. When LOW , the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are t hree-st ated, and a ct as i nput dat a pins . OE is m ask ed during t he fi rst cl oc k of
a read cycle when emergin g fro m a dese lected state.
83 ADV Input-
Synchronous Adva nce I nput sig nal, sa mpled on the risi ng edge of CLK. When asserted, it auto-
mat ically increments the add ress in a burst cyc le.
84 ADSP Input-
Synchronous Address Strobe from Proce ssor , sampled on the rising edge of CLK. When assert-
ed LOW , A[16:0] is captur ed in t he ad dress r egist ers. A[1:0] are also loaded i nt o the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE1 is deassert ed HIGH.
85 ADSC Input-
Synchronous Address Strobe from Cont roll er , samp led on t he rising e dge of CLK. W hen assert-
ed LOW , A[16:0] is captur ed in t he ad dress r egist ers. A[1:0] are also loaded i nt o the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
64 ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time-critic al
“sleep” condition with data i ntegrity preserved. For normal operati on, this pin has
to be LOW or left float ing.
30–28,
25–22, 19,
18, 13, 12,
9–6, 3–1,
80-78, 75–72,
69, 68, 63, 62
59–56, 53–51
DQ[31:0]
DP[3:0] I/O-
Synchronous Bidirectional Data I/O li nes. As input s, they f eed into an on-chip data register that
is trigger ed b y the rising edge of CLK. As outp uts, they deliv er the data contai ned
in the memory location specif ied by A[16:0] during the pre vious cloc k rise of the
read cycle. The direction of the pins is controlled by OE. When OE i s asserted
LO W, the pins beha v e as output s . When HIGH, DQ[31:0] and DP[3:0] are placed i n
a three- state condi ti on.
15, 41, 65, 91 VDD Power Supply P o wer suppl y i nputs to t he c ore of the de vice . Shou ld be conn ected t o 3.3V po wer
supply.
17, 40, 67, 90 VSS Ground G round for the core of the de vice. Should be connected to gr ound of the system.
4, 11, 20, 27,
54, 61, 70, 77 VDDQ I/O Power
Supply Power supply fo r the I/O ci rcuitry. Should be connected to a 3.3V or 2.5V po wer
supply.
5, 10, 21, 26,
55, 60, 71, 76 VSSQ I/O Ground Ground for th e I/O circuitry. Should be connected to ground of the syst em .
31 MODE Input-
Static Selects burst order. Whe n ti ed to GND selects linear burst sequence. When tied
to VDDQ or left f loating selects interlea ved burst sequence. Th is is a strap pin an d
should remain static during device ope ration.
14, 16, 38, 39,
42, 43, 66 NC No Connects.
CY7C1347B
5
Introduction
Functional Overview
All synchrono us inp uts pass th rough inp ut regi sters con tr olle d
by the rising edge of the clock. All data outputs pass through
outpu t regist ers contr olled b y the rising ed ge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns
(166-MHz device).
The CY7C1347B supports secondary ca che in systems utiliz-
ing either a linear or interleaved burst sequence. The inter-
lea ved burst o rder supports P en tium and i486 proces sors. Th e
linear burst sequence is suited for processors that utilize a
li near burst sequence. The burst order is user selectable, and
is determined b y sampling t he M ODE input. Acc esses can be
initiated with either the Processor Address Strobe (ADSP) or
the Cont roller Addres s Strobe (ADSC). Addres s adv ancement
through the burst sequence is contr olled by the ADV input. A
two- bit on-ch ip wrap around burst co unter captu res the f irst ad-
dress in a burst sequence and automatically increments the
address for t h e rest of t h e burst a ccess.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Wr ite
Enable (GW) overrides al l byte writ e inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed wri te ci rcuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE ) provide for easy bank se-
lection and output three-state control. ADSP is ignor ed if CE1
is HIGH.
Singl e Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE 2, CE3 ar e all ass erted act ive , and (3) the write s ignals
(GW, B W E) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address pre sented to the addr ess inputs (A[16:0])
is st ored in to the addr ess adv anc ement logi c and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Regist ers. At the rising edge of the next clock the dat a
is al lowed to propagat e through t he Output Register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LO W. The only e xcept ion occur s when the SRAM is emergin g
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once t he SRAM is deselect ed at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Singl e Writ e Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE 2, CE3 a re all a sserted activ e. Th e addres s pr esente d
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW [3:0]) and ADV inputs are ig-
nored duri ng thi s first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is ass erted LO W on the se cond clo ck rise , the
data pr esen ted to the DQ[31:0] and DP[3:0] inputs is writt en int o
the corr esponding address location in the RAM core. If G W is
HIGH, then the write operation is controlled by BWE and
BW[3:0] signals . The CY7C1347B provides b yte write capabi l-
ity that is described in t he Writ e Cycle Description table. As-
serting the Byte Write Enable input (BWE) with the selected
Byte Wr ite (BW[3:0]) input will selectively wr ite to only the de-
s ired by t e s.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347B is a commo n I/ O de vice , the Outpu t
Enabl e (OE) must be d easserted HIGH b efore presentin g data
to the DQ[31:0] and DP[3:0] i nputs . Doing so will th ree-st ate the
output driv ers. As a saf et y precaut ion, DQ[31:0] and DP[3:0] are
automati cally three-stated whenever a write cycle is detec ted,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, C E3 are all asserted active,
and (4) the appropriate combinat ion of t he write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-tr iggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into the address regi ster and the address ad-
vancement logic whi le being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ[31:0] and DP[3:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347B is a commo n I/ O de vice , the Outpu t
Enabl e (OE) must be d easserted HIGH b efore presentin g data
to the DQ[31:0] and DP[3:0] i nputs . Doing so will th ree-st ate the
output driv ers. As a saf et y precaut ion, DQ[31:0] and DP[3:0] are
automati cally three-stated whenever a write cycle is detec ted,
regardless of the state of OE.
Burst Sequences
The CY7C1347B provides a two- bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence . The inte rleaved b urst s equence i s design ed s pecif -
ically to support Intel Pentium applications. The linear burst
sequence is designed to suppor t processors that follow a lin-
ear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asser ting ADV LOW at clock rise will automatically inc rement
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
CY7C1347B
6
Sleep Mode
The ZZ input pin is an asyn chronous input. Assertin g ZZ plac-
es the SRAM in a pow er conserv ation “sleep” mode. Tw o clock
cycles are req uired t o ent er i nto or exit from thi s “sleep” mo d e .
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device m ust be deselected p rior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for t he
duration of tZZREC after the ZZ input returns LOW .
Interleaved B u rst S eq u en ce
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Chara cteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mo de
standby current ZZ > VDD − 0.2V 10 mA
tZZS Device operation to
ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ reco very time ZZ < 0.2V 2tCYC ns
CY7C1347B
7
Cycle Des cr i p t i o n s[1 , 2, 3]
Next Cycle Ad d. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write
Unselected None L X X 1 X 0 X X Hi-Z X
Unselected None L 1 X 0 0 X X X Hi-Z X
Unselected None L X 0 0 0 X X X Hi-Z X
Unselected None L 1 X 0 1 0 X X Hi-Z X
Unselected None L X 0 0 1 0 X X Hi-Z X
Begin ReadExternal L010 0 XXXHi-ZX
Begin ReadExternal L010 1 0XXHi-ZRead
Continue Read Next L X X X 1 1 0 1 Hi-Z Read
Continue Read Next L X X X 1 1 0 0 DQ Read
Continue Read Next L X X 1 X 1 0 1 Hi-Z Read
Continue Read Next L X X 1 X 1 0 0 DQ Read
Suspend Read Current L X X X 1 1 1 1 Hi-Z Read
Suspend Read Current L X X X 1 1 1 0 DQ Read
Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read
Suspend Read Current L X X 1 X 1 1 0 DQ Read
Begin Write Current L X X X 1 1 1 X Hi-Z Write
Begin Write Current L X X 1 X 1 1 X Hi-Z Write
Begin WriteExternal L010 1 0XXHi-ZWrite
Conti n ue W ri te Next L X X X 1 1 0 X H i- Z Wr ite
Conti n ue W ri te Next L X X 1 X 1 0 X H i- Z Wr i t e
Suspend W rite Curr ent L X X X 1 1 1 X Hi-Z Write
Suspend W rite Curr ent L X X 1 X 1 1 X Hi-Z Write
ZZ “Sleep” None HXXX X XXXHi-ZX
Notes:
1. X=Don't Care, 1=HIGH, 0=LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Description Table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
CY7C1347B
8
Maximum Ratings
(Above which the useful l ife may be impair ed. For user guide-
li nes, not tes ted.)
Storage Temperature .....................................−65°C to +1 5 0°C
Ambient Temperature with
Po wer Applied..................................................−55°C to +1 2 5°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Appli ed to Output s
in High Z State[7] ....................................... −0.5V to VDD + 0.5V
DC Input Volt age[7].................................... −0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ...... .. ......... ...... ......... .. ...... .. >2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Curr ent... .. ............. ....... .. .. ....................... >200 mA
Notes:
4. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, B WE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ[31:0];DP[3:0]=High-Z when OE is
inactive or when the device is deselected, and DQ[31:0];DP[3:0]=data when OE is active.
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
Wr i te C ycl e D escr i p ti o n [4, 5, 6]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write Byte 0 - DQ[7:0] 101110
Write Byte 1 - DQ[15:8] 101101
Write Bytes 1, 0 101100
Write Byte 2 - DQ[23:16] 101011
Write Bytes 2, 0 101010
Write Bytes 2, 1 101001
Write Bytes 2, 1, 0 101000
Write Byte 3 - DQ[31:24] 100111
Write Bytes 3, 0 100110
Write Bytes 3, 1 100101
Write Bytes 3, 1, 0 100100
Write Bytes 3, 2 100011
Write Bytes 3, 2, 0 100010
Write Bytes 3, 2, 1 100001
Write All Bytes 100000
Write All Bytes 0 XXXXX
Operating Range
Range Ambient
Temperature[8] VDD VDDQ
Com’l 0°C to +70°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
Ind’l–40°C to +85°C 3.3V
−5%/+10% 2.5V −5%
3.3V /+10%
CY7C1347B
9
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.3V −5%/+10% 3.135 3.6 V
VDDQ I/O Suppl y Voltage 2.5V −5% to 3.3V +10% 2.375 3.6 V
VOH Output HIGH Volt age VDD = Min., IOH = −4.0 mA 2.4 V
VOL Output LOW Vo lt age VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VDD + 0.3V V
VIL Input LOW Voltage[7] –0.3 0.8 V
IXInput Load Current
except ZZ and MODE GND ≤ VI ≤ VDDQ −55µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Out put Leakage
Current GND ≤ VI ≤ VDDQ, Output Di sabled −55µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA ,
f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 420 mA
7.5-ns cycl e, 133 MHz 375 mA
10-ns cycle, 100 MHz 325 mA
ISB1 Autom a ti c C S
Power-Down
Current—TTL Inputs
Max. VDD, Device D ese l e cted ,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz 35 mA
7.5-ns cycl e, 133 MHz 30 mA
10-ns cycle, 100 MHz 25 mA
ISB2 Autom a ti c C S
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected, VIN
≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 All speeds 10 mA
ISB3 Autom a ti c C S
Power-Down
Current—CMOS Inputs
Max. VDD, Devi ce Desel ected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz 10 mA
7.5-ns cycl e, 133 MHz 10 mA
10-ns cycle, 100 MHz 10 mA
ISB4 Autom a ti c C S
Power-Down
Current—TTL Inputs
Max. VDD, Device D ese l e cted ,
VIN ≥ VIH or VIN ≤ VIL, f = 0 18 mA
Capacitance[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 3.3V
6pF
CCLK Clock Input Capa citance 8pF
CI/O Input/Out put Capacitance 8pF
CY7C1347B
10
AC Test Loads a nd Waveforms
OUTPUT
R=317Ω
R=351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL=50Ω
Z0=50Ω
VL= 1. 5V
3.3V ALL INPUT PULSES[10]
2.5V
GND
90%
10% 90%
10%
≤2.5 ns ≤2.5 ns
(c)
Switching Characteristics Over the Operating Range[11, 12, 13]
-166 -133 -100
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tCYC C lo ck Cy cle Ti m e 6.0 7.5 10 ns
tCH Clock HIGH 1.7 1.9 3.5 ns
tCL Clo ck LOW 1.7 1.9 3.5 ns
tAS Ad dress Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tAH Ad dress Hold After CLK Rise 0.5 0.5 0.5 ns
tCO Da ta Out put Valid Af ter CLK Rise 3.5 4.0 5.5 ns
tDOH Data Output Hold After CLK Rise 1.5 2.0 2.0 ns
tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns
tWES BWE, GW, BW[3:0] Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tWEH BWE, GW, BW[3:0] Hol d Aft er CLK Rise 0.5 0.5 0.5 ns
tADVS ADV Set-Up Before CLK Rise 2.0 2.5 2.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns
tDS Data Input Set-U p Before CLK Rise 2.0 2.5 2.5 ns
tDH Da ta I nput Hold After CLK Rise 0.5 0.5 0.5 ns
tCES Chip Select Set- Up 2.0 2.5 2.5 ns
tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns
tCHZ Clock to High-Z[12] 3.5 3.5 3.5 ns
tCLZ Clock to Low-Z[12] 0 0 0 ns
tOEHZ OE HIGH to Output High- Z[12, 13] 3.5 3.5 5.5 ns
tOELZ OE LOW to Output Low-Z[12, 13] 0 0 0 ns
tOEV OE LOW to Output Va lid[12] 3.5 4.0 5.5 ns
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference lev els of 1.5V, input pulse lev els of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ .
CY7C1347B
11
1
Swi tch i n g Wavefo rms
Write Cycle Tim i n g[14, 15]
Notes:
14. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data-
In
tCYC
tCH
tCL
tADS
tADH
tADS tADH
tADVS tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single Write Burst W rite Unselected
ADSP ignored with CE1 inac tiv e
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipelined Write
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unselected with CE2
ADV M u st Be Inactive for ADSP Write
ADSC initiated write
CY7C1347B
12
Read Cycle Timing[14, 16]
Note:
16. RDx stands for Read Data from Address X.
Swi tch i n g Wavefo rms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCO
tEOV
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 i nactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipel ined Read
ADSC initiated read
Unsele ct ed with CE2
CY7C1347B
13
Read/Writ e Cycle Ti ming[14, 15, 16, 17]
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Swi tch i n g Wavefo rms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Da ta In/Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 WD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tEOLZ
tCO
tEOV
3a 3c 3d
1a
tEOHZ tDOH
tCHZ
Singl e Read Burst Read Unselected
ADSP ignored with CE1 inactiv e
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipeli ned Read
Out 2a
In 3b
Out
Out Out Out
Single Write
tDS tDH
2a
Out
See Note.
CY7C1347B
14
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Swi tch i n g Wavefo rms (continued)
tAS
= DON’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In/Out
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCO
Pipeline Timing[18, 19]
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back t o B a ck R ead s
ADSP initiated Reads
ADSC initiated Reads
CY7C1347B
15
Swi tch i n g Wavefo rms (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
IDD IDD(active)
Three-state
I/Os
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
ZZ Mode Timing [20 , 21]
CE2
IDDZZ
HIGH
CY7C1347B
16
Document #: 38-00909
Ordering Information
Speed
(MHz) Orderi ng Code Package
Name Package Type Operating
Range
166 CY7C1347B-166AC A101 100-Lead Thin Quad Flat Pack Commercial
CY7C1347B-166BG C BG119 119-Ball BGA
133 CY7C1347B-133AC A101 100-Lead Thin Quad Flat Pack
CY7C1347B-133BG C BG119 119-Ball BGA
100 CY7C1347B-100AC A101 100-Lead Thin Quad Flat Pack
CY7C1347B -100BGC BG119 119-Ball BGA
CY7C1347B-100AI A101 100-Lead Thin Quad Flat Pack Industri al
Package D i ag ra ms
100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
CY7C1347B
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. C ypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusi on of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra ms (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
