Converting FP GAs and PLDs
to
Atmel Gate Arrays
FPGA/PLD
to Gate Array
Conversion
Application
Note
Converting FPGAs and PLDs to
Atmel Gate Arrays
Introduction
Atmel is one of the only companies that
designs and manufactures field
programmable gate arrays (FPGAs),
progr ammable logic devi ces ( PLD s) and
high performance gate arrays. Atmel
offers a seamless, direct conversion
path for designs implemented on most
PLDs and FPGAs to its gate array
families. The potential benefits to the
system desig ner of such a capabil ity are
fourfold:
•Component cost savings. Atmel’s
conversion process will convert a
single FPGA or P LD into a low er cost
gate array that is a pin-for-pin
compat ibl e replaceme nt.
•Board space savings. Atmel converts
to a true gate array, not a hardwired
FPGA/PLD. Multiple FPGAs or PLDs
can be converted and consolidated
into a single gate array, reducing
system component count and
provi ding even mor e cost savings.
•Enhanced performance. Conversion
to a gate array grants the designer
access to all of the macrocells and
functions contained in the ce ll library.
Included are higher order logic
functions, i nclusion of S RAM, PCI and
other buffers and testability
improvement circuitry that cannot be
realized on an FPGA or PLD. Gate
array routing schem es all ow a gr eater
degree of flexibility t o optimize timing
performance or logic area.
•Reduction in design cycle time. An
ASIC desi gn can be prototyped using
programmable logic and migrat ed to a
gate array for production without the
tim e and cost of a re-desi gn.
In all cases, Atmel uses the existing
FPGA or PLD design database so that
little additional engineering effort is
required from the customer. This
ap plica tion note discusses some f actors
to consider when deciding to convert,
describes the conversion process, and
details the required information for
select ed FPGA and PLD products.
0145D
CMOS ASIC
9-99
ATL60 Array Organ ization - 0.6µm CMOS
Device
Number Raw
Gates Routable
Gates Max Pin
Count Max I/O
Pins Gate(1)
Speed
ATL60/4 4,000 3,000 44 36 200 ps
ATL60/15 15,000 10,000 68 60 200 ps
ATL60/25 25,000 16,900 84 76 200 ps
ATL60/40 38,000 25,400 100 92 200 ps
ATL60/60 58,000 34,600 120 112 200 ps
ATL60/85 86,000 51,900 144 136 200 ps
ATL60/110 110,000 65,900 160 152 200 ps
ATL60/150 149,000 89,300 184 176 200 ps
ATL60/200 195,000 116,900 208 200 200 ps
ATL60/235 232,000 139,500 226 218 200 ps
ATL60/300 301,000 181,000 256 248 200 ps
ATL60/435 430,000 260,000 304 296 200 ps
ATL60/550 545,000 288,000 340 332 200 ps
ATL60/700 693,000 363,000 380 372 200 ps
ATL60/870 870,000 456,000 424 416 200 ps
ATL60/1100 1,119,000 590,000 480 472 200 ps
Notes: 1. Nominal two input NAND gate with a fan out of two at 5.0 volts.
ATL50 Array Organization - 0 .5µm CMOS
Device
Number Raw
Gates Routable
Gates Max Pin
Count Max I/O
Pins Gate(1)
Speed
ATL50/4 4,000 3,000 44 36 200 ps
ATL50/15 15,000 10,000 68 60 200 ps
ATL50/25 25,000 16,900 84 76 200 ps
ATL50/40 38,000 25,400 100 92 200 ps
ATL50/60 58,000 34,600 120 112 200 ps
ATL50/85 86,000 51,900 144 136 200 ps
ATL50/110 110,000 65,900 160 152 200 ps
ATL50/150 149,000 89,300 184 176 200 ps
ATL50/200 195,000 116,900 208 200 200 ps
ATL50/235 232,000 139,500 226 218 200 ps
ATL50/300 301,000 181,000 256 248 200 ps
ATL50/435 430,000 260,000 304 296 200 ps
ATL50/550 545,000 288,000 340 332 200 ps
ATL50/700 693,000 363,000 380 372 200 ps
ATL60/870 870,000 456,000 424 416 200 ps
ATL60/1100 1,119,000 590,000 480 472 200 ps
Notes: 1. Nominal 2-input NAND gate with a fan out of two at 3.3 volts.
9-100 CMOS ASIC
Pr ogr ammable Logic vs Gate Array
Programmable logic devices have enjoyed tremendous
popularity and growth over the last several years, primarily
because the user saves both time and money. Designers
may work with multiple design tools that run on inexpensive
platforms. Designs can be implemented in hours and
mo dif i ed easily, al l owi ng fo r sys t em perf or m ance evaluati on
in the same week. Thi s inst ant f eedbac k al low s d esi gners t o
validate system operation and rectify any errors without
addit i onal ex pense. P ro gr am ma bl e lo gic devices prov i de an
id eal so lution for low to moderate production volu mes and fo r
fast prototyping of more com plex logic designs. As volumes
increase, however, programmable devices may become
pr ohibi t i vely expens ive.
Gate arrays provide an efficient implementation of the
design. They off er superi or perform ance, higher den si t y, and
lower cost-per-gate in production volumes when compared
to programmable logic devices. Design tools that support
gate ar rays are typically more compreh ensive and exp ensive
than FPGA/PLD design tools. However, many ASIC design
pla tform s now s u pp ort FPGA d es ig n. Th e ab ility to s imulate
both the programmable device and the gate array in the
same design environment allows the designer to compare
and verify the conversion. However, while gate array
prototypes can be deliver ed in days or weeks, that is still a
much longer period than the verification cycle of a
programmable logic device. Gate array designs typically
require a nonrecurring expense for design implementation,
and design revisions may require additional time and
expense.
Why Conver t ?
There are four instances when converting from a
progra mmable logic devi ce t o a gate arra y offe rs the user
a direct benefit.
Save Money at High Volumes. If the cost of one year’s
supply of programmable devices approxi mates t he cost of
the nonrecur ring expense plus the i niti al year ’s supply of a
gate arr ay device, ser i ous consideration should be gi ven to
conversion. After the nonrecurring expense is amortized,
the cost savings become even more dramatic.
Time To Market Versus Cost Reduction. Using a
program mable dev ice for logic verification and prototyping
and then convert ing to a gat e array gives the designer t he
best of both wo rl ds - a fast, accurate design cycle and a
lo w cost compon ent in producti on.
Higher Performance. Gate arrays have lower standby
and operating current, plus offer greater speed than an
FPGA/PLD. The designer also has a greater selectio n of
buffer types, dr ive currents, and a wide select ion of higher
order logic and mem ory (S RA M) f unct ions.
Integration. Converting several FPGAs or PLDs and
con solidati ng the logic i nto a single gate a rray uses less
printed circuit board space, reduces the component
count, consumes less power, and im pr oves t he r eliabil it y
of the system.
ATLS60 Array Organization
Device
Number Raw
Gates Routable
Gates Max Pin
Count Max I/O
Pins Gate(1)
Speed
A TLS60/80 12, 500 8, 000 80 72 200 ps
ATLS60/1 00 20, 400 13,000 100 92 200 ps
ATLS60/1 20 30, 200 17,500 120 112 200 ps
ATLS60/1 44 44, 600 26,000 144 136 200 ps
ATLS60/1 60 55, 300 32,500 160 152 200 ps
ATLS60/2 08 96, 500 57,000 208 200 200 ps
ATLS60/2 25 113, 500 67,500 225 217 200 ps
ATLS60/2 56 148, 200 88,000 256 248 200 ps
Note: 1. Nominal 2 input NAND Gate with a Fan Out of 2
CMOS ASIC
9-101
Conv erting FP GA s/PL Ds
Atmel’s conversion process is designed to minimize the
amoun t of e ngineering sup port requ ired from the system
designers, provided the requisite design database is
received. The inputs required vary depending on the
origi nal manufactur er of the FPGA/ PLD . Figur e 1 out li nes
the conv er sion process flow.
Figure 1. FPGA /PLD to Gate Ar ray Conversion
9-102 CMOS ASIC
The fi rst step towar d m eet ing Data Acceptance (DA) is the
subm issi on of the design dat abase to A tmel. If all required
elements for DA are present, the design database can
quickly be accepted. Frequently issu es ari se with format
of the vect ors ( or anot her el ement) or w ith m issi ng i tems
which require some work to be done to meet DA.
Because Atmel can never be certain what type of
database will be received from the customers, all
schedules for the design use DA as the starting point. In
other wor ds, the clo ck st arts once DA has been met.
Once Atmel database acceptance has been met, the
or igi nal design is converted into an equivalent net list using
the Atmel cell libr ar y via Synopsys. Synopsys t ools can
read a va riety of f ormats, including our preferred formats
of EDIF and Verilog. Figure 2 outlines the process by
which synopsys conve rts the FPGA netlist into Ve rilog -XL
format.
The dat abase i s input t o a pr opr iet ary Atmel mapping f il e
for translation into Atmel cells. When the design is
mapped in its entirety, a Verilog netlist in Atmel cells is
produced. The equivalent netlist ensures that both the
functionality and timing of the new design match the
original. Using this technique, almost any FPGA/PLD
design can be converted to a gate arr ay.
Mapping FileVerilog Netlist
Synopsys
FPGA Netlist (EDIF)
Hierarchical Verilog Netlist
Synopsys
Flattened Verilog Netlist
Verilog Netlist in Atmel Cells
Figure 2. FPGA Conversion
CMOS ASIC
9-103
The original te st v ectors a re a ls o conver te d and are used to
verify the gate ar ray design . Goo d functio nal ve ctors must b e
provided or developed. This is important because the
fu nctional t est vec to rs ar e t he veri f icat i on ve hi cl e fo r t he new
gate array design. The final approval of the vectors to be
used fal ls u pon t he o rig in al designer ; one is bet t er ser ved to
produce and verify the test vectors prior to database
submission than to attempt to re construct them after the fact.
Al l vectors must be in the same five groups ( Input, Output,
Tri-state, B i-direct ional , and Enable) and have a stated
pur pose. Output s ar e sampled once per clock cycle at the
75% cycle point. Test vectors must include a 1 MHz set for
wafer probe and an "at speed" set for final test. "At speed"
m ay be a 1 M Hz set with certain critical paths identif ied f or
testing "at speed". Test vectors must pass Atmel’s Test
Vector Checke r (tvc), a tool provided with our libraries to
verify the format of the vector set. Design data base
formats, simulation/test vector formats, specifications, and
documentat ion requir ements are li sted bel ow.
Requ ired Dat aba se
Design Database For m at
- EDIF 2.0.0
- Synopsys .db files
- Ver il og structural netlist
- Xil inx .xnf f il es
The source cel l li brary is:
- Actel FPGA
- Altera FPGA/PLD
- Atme l F PGA
- X ilinx FPGA
- Other
Simulation/Test Vec tor Forma t
- ALTER A Format
- ASCII Tabular Format
- COMPA SS Tabul ar Trace Format
- ORCAD Format
- Quicksim Logfile Format
- Q uicksim List Form at
- Verilog Format
- VIEWlogic Tabular Format
- VLAIF Tabular Format
Specifications
- O per ati ng conditions of volt age and t em peratur e
- System loading requirement s by pin
- Operating clock speed and number of clocks
- I/ O def inition i ncluding pin out and enable f or Tri-state
and bi-directional buff ers
- I dent if ication of criti cal pat hs
- D efi nition of asynchr onous behavio r
Documentation
- Full hierarchi c al schematics
- Clock tr ee and reset diagram
- Timi ng diagra ms showi ng r el ationship of clocks to dat a
applied and val id out puts
After the design has been converted and verified for
functional performance, the optimization process b egins.
The design can be optimized to match the timing
perfo rmance of the origi nal FPG A/PLD desi gn or to meet
new performance goals. Additional logic functions or
memo ry can be added to the gat e array as we ll.
Before physical design of the chip begins, a joint
Preliminary Design Review is held with Atmel and the
customer to approve the results of the converted d esign.
From this poi nt on, the d esign process is i dentical to that
of a traditionally designed gate array. The design is
physically placed and routed on the gate array and verified
for electrical and design rules. Atmel uses Cadence’s
Verilog-XL as a golden simulator. Atmel guarantees
performance equal to or better than that predicted by
V erilog-XL post route simulation.
Back annotation data i s extracted from t he actual layout
and in corporat ed i nto t he post-rou te funct io nal and tim i ng
si mulation. Minor layout mod ificat ions may be required to
meet the timing specification. A Final Design Review is
held to approve the post-route simulation data. After
customer approval, the design is released for mask
generation and prototyping. Prototypes can be delivered
in as little as three weeks and production units in as shor t
as six weeks after customer approval of prototypes.
Atmel guarantees the gate array will be a pin-for-pin
compatible replacement for the FPGA/P LD.
Tables 1-5 list the recommended Atmel gate arrays for
conversion from various Actel, Altera, Xilinx,
Cypress, and Latt ice programmable devices.
Gat e Array Imple mentation
After database acceptance, the design database is
convert ed int o an equival ent ne tlist of primitiv e cells from
Atmel’s gate array library. The vectors from the original
FP GA or PLD desi gn are also conver ted and are used as
functional simulation vectors to validate the gate array
netlist. As these vectors are used to perform any timing
simulation and form the core of the gate array tester
program, it is vitally important that an accurate and
complete vect or set is provided.
After the FPGA or PLD databases have been converted
and validated, any additional circuitry, such as memory
blocks, testability improvement elements, o r higher order
logic functions, can be incorporated into the netlist. Any
optimization that is necessary to match timing or to
improve performance can be performed at this point as
9-104 CMOS ASIC
well. At this point, boundary and internal scan can be
added and ATPG vectors generated. A Preliminary
Design Review i s then held with the customer to review
and to appro ve t he r esul ts of the design conver sio n.
Preli minar y Design R eview (PDR)
The follow ing it ems are review ed at the PD R:
•Confirm Netlist Checke r (v3) and Test Vector Checker
(tvc) files corr ect
•I /O buffer li sti ng and bonding diagram
•Pr eli minary t estabili ty compiler report
•R out e cl ock t ree and analysi s of w or st case and best
case dela y
•Ver il og simulat ion at-speed
-nominal, w or st case, best case (w ith no t iming
violations)
•Review critical path information (tSU, tHOLD, tPD)
-Veri log or Veritime estimates
•I/O electrical specification s
•E lectro migration calcu lation
Fina l Desi gn Revi ew (FDR )
Beyond this point, the design process follows that of a
tradit i onally desi gned gate arra y. The cells are placed and
routed, a post - route sim ulation is per f ormed, and checks
are performed to verify conformance with electrical and
design r ules, and t o confirm t he Logi c Versu s Schemat ic
(LVS) is correct. An FDR is held with the customer to
review and appr ove t he post r oute data, and t o author ize
mask m aking and prototype fabric ation.
The FDR is the last joint review between Atmel and the
customer before committing to prototypes. Prior to this
meetin g, both A tmel and the customer will have r evie wed
the post-route Verilog-XL simulation incorporating the
back annotation data. The customer may receive back
annotation data for complete post-route simulation on
their CAE systems. Atmel guarant ees si li con perfor mance
equal to or better than that predicted by the post-route
Verilog-XL simulations. T he it ems to be reviewed at FDR
ar e as follows:
•Updates of cell m apping and timing (if any)
•P ost-route netlist check (v 3)
-post-route netlist changes
•Post -route t iming simulation to specificat ion
-review clock timing
-at speed
-clock skew (if req uired)
-listing of timing war nings with explanation
•S tatic path anal ysis (as speci fi ed)
•E lectro migration calcu lation
•Bo nding diagrams and pi n list
-bond pad plot
•LVS/DRC/ERC
P r oto type Delivery
Atmel will deliver 10 prototypes in ceramic or TQFP
packages to the customer. The units are to verify the
functional ity and el ectrical perf ormance of the gat e ar ra y.
S ynt hesis f r om a Hardw ar e Descr iptio n
L a nguage ( HDL)
T here has been an incr ease in the use of HDLs to desi gn
FPGA s and P LDs as more of the de sign platforms offer
this capability. Two of the most popular languages are
VHDL and Verilog-HDL. Using a logic synthesis
technique, the behavioral l evel description of an FP GA or
PLD can be mapped into a functionally equivalent gate
array netlist. Both hardware description languages are
supported by the Synopsys Design Compiler. This
FPGA/PLD to gate array conversion methodology
requi res the least amount of data conversion and allows
the flexibility to incorporate such features as memory,
testability, or higher order logic functions into the gate
array. This technique is also effective when the need to
co nsolidate several FPGA or PLD designs into one gate
array exists. Synthesis from an HDL offers the most
efficient utilization of the gate array, at the expense of
timing matching. Should the user require them, VHDL
descriptions of the convert ed FPG As or PLD s, as well as
the gate array implementation, can be provided by
exporting the net li sts thr ough Synopsys.
Testabili ty Improvement and Auto matic Test
P atter n Generation
The incorpor ation of te stability impr oveme nt circuitry in to an
ASI C design becomes more impor tant as the density of the
des ig n i ncr eases . The sa me can be said for conve rs i on and
consolidation of large numbers of dense FPGAs or PLDs
into a gate array. The insert i on of scan path s w i t hin an AS I C
and testing via ATPG can provide an easy means of
scr eening m anufact ur i ng-r el ated def ects duri ng te st i ng, w it h
a rela tively small silic o n usage penalty. Using ATPG is only
a supplem ent t o f unc t i onal t es t v ect or s, not a replacement .
The process consists of replacing existing flip-flops with
scan flip-flops and connecting them up to form scan
chains. An in put pin and output pi n m ust be i dent if ied for
each scan chain. In general, scan chains should not
e x ceed 64 flip- flops in length. T hus, for a design with 600
flip-flops, 10 input pins and their corresponding output
p ins must be ident ified. E xist ing p ins may be m ultiplexed
for thi s use if the design i s pin li m it ed. Additional pins are
required for the Test Enable (TE) signal and a Test M ode
(TM) signal. The TE pin is used to control the flip-flops,
placi ng them in eit her normal mode or scan mode.
CMOS ASIC
9-105
The TM pin is required to bypass violations of testability
guidelines, an example of which would be gated clocks.
D uring testing, all flip-flops in t he scan chains must t oggle
on the same clock. If gated clocks exist in the design, logic
must be designed so that it bypasses this gating when
Test Mode is active. Since Test Mode is active only during
A TPG test, the basic function of the design is unaf fected.
The Synopsys Test Compiler Guidelines table outlines
other testability rules and suggested w orkarounds uti lizing
the Test Mode signal. When all test guidelines are
followed, testability insertion and vector generation are
easily accomplished. Past experience has shown
extremely high fault coverage (up to 99%) with small
ATPG vector set s. If t hese r ules ar e not f oll owed closel y,
incorporati ng scan and A TPG can re quire sever al we eks.
It is highly recommended that the FPGA be designed
using the rules in Table 6 if the customer intends to
som eday convert to a gate array and use scan/ATPG.
Testability Ru le Effec ts of I nfraction Work around
Synch ronous Desi gn
- No cross coupled gat es
- No unregist ered feedback
Associated logic u ntestable Break f eedback path with te st mode
Single Edge C locki ng Clocked device not all owed in
scan chain - red uced f ault In test mode, create single edge
clocki ng with inverters and M UXs
No C lock Gat ing Clocked device not all owed in
scan chain - red uced f ault
coverage
Use dat a disable f li p-flops instead
of clock enable s, disabl e gating
in test mode
No Lat ches Not al lowed in scan chain,
r educed faul t coverage Use alter nate test methods, f orce
latches to transpar ent m ode with
test mode
Single Ext er nal Reset
- No asynchronous r esets or
pr esets generat ed on chip
- No combinational logic in
reset path
Not al lowed in scan chain,
r educed faul t coverage Reset OR’d with test mode
No Internal Tri-st ate Buses Reduced fault coverage, possible
Tri-state contention during scan t est Use MU Xs or AO I gates, i nser t
gating of controls to prevent
contention
No Direct Q t o D C onnections Dynamic Ha zard
Synopsys Test Compiler G uidelines
9-106 CMOS ASIC
Xilinx®
FPGA Equivalent
U s a b le Ga te s I/O
Pins
Ta rg et At me l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
XC2064
XC2064L 1000 58 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
XC2018
XC2018L 1500 74 ATLS60/80
ATLS60/100 ATL60/15
ATL60/25 ATL50/15
ATL50/25
XC3020A
XC3020L 1500 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
XC3030A
XC3030L 2000 100 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
XC3042A
XC3042L 3000 144 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
XC3064A
XC3064L 5000 224 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
XC3090A
XC30090L 6000 320 ATL60/435
ATL60/550 ATL50/435
ATL50/550
XC3120A 1500 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
XC3130A 2000 80 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
XC3142A
XC3142L 3000 96 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
XC3164A 4500 120 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
XC3190A
XC3190L 6000 144 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
XC3195A 7500 176 ATLS60/160
ATLS60/208 ATL60/150 ATL50/150
XC4003E 3000 80 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
XC4005E
XC4005L 5000 112 ATLS60/120 ATL60/60 ATL50/60
XC4006E 6000 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
XC4008E 8000 144 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
XC4010E
XC4010L 10000 160 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
XC4013E
XC4013L 13000 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
XC4020E 20000 224 ATLS60/208
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
Note: 1. Target array dependent on number of I/O pins used, and pinout.
Tab le 1. Xilinx® FPGA/CPLD/Atmel Gate Array Cross Reference
CMOS ASIC
9-107
Xilinx®
FPGA Equivalent
U s a b le Ga te s I/O
Pins
Ta rg et At me l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
XC4025E 25000 256 ATLS60/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
XC4028EX
XC4028LX 28000 256 ATLS60/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
XC4036EX
XC4036LX 36000 288 ATL60/300
ATL60/435 ATL50/300
ATL50/435
XC4044EX
XC4044LX 44000 320 ATL60/435
ATL60/550 ATL50/435
ATL50/550
XC4052XL 52000 352 ATL60/550
ATL60/700 ATL50/550
ATL50/700
XC4062XL 62000 384 ATL60/700
ATL60/870 ATL50/700
ATL50/870
XC5202/L 3000 84 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
XC5204 6000 124 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
XC5206/L 10000 148 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
XC5210 16000 196 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
XC5215/L 23000 244 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
XC6209 13000 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
XC6216 24000 256 ATL560/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
XC6236 55000 384 ATL60/700
ATL60/870 ATL50/700
ATL50/870
XC6264 100000 512 ATL60/1100(3) ATL50/1100(3)
Note: 1. Target array dependent on number of I/O pins used, and pinout.
2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins.
3. ATL60/1100 has 472 I/O pins and will only accommodate devices with no more than 472 I/O pins.
Table 1 (continued). Xilinx® FPGA/CPLD/Atmel Gate Array Cros s Reference
9-108 CMOS ASIC
Xilinx®
CPLD Equivalent
Us able Ga tes (1) I/O
Pins
Ta rg et At me l
Ga te Array(2)
ATLS60 Series ATL60 Series ATL50
XC7236A 30 ATLS60/80 ATL60/4 ATL50/4
XC7272A 42 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
XC7318 17 ATLS60/80 ATL60/4 ATL50/4
XC7336 32 ATLS60/80 ATL60/4 ATL50/4
XC7354 42 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
XC7372 42 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
XC73108 78 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
XC73144 120 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
XC9536 34 ATLS60/80 ATL60/4 ATL50/4
X C9572 69, 72 ATLS60/80 AT L60/15
ATL60/25 ATL50/15
ATL50/25
XC 95108 69, 81, 108 ATLS60/80
ATLS60/100
ATLS60/120
ATL60/15
ATL60/25
ATL60/40
ATL60/60
ATL50/15
ATL50/25
ATL50/40
ATL50/60
XC 95144 81, 133 AT LS60/ 100
ATLS60/120
ATLS60/144
ATL60/25
ATL60/40
ATL60/60
ATL60/85
ATL50/25
ATL50/40
ATL50/60
ATL50/85
XC95180 133, 166 ATLS60/12 0
ATLS60/144
ATLS60/160
ATLS60/208
ATL60/60
ATL60/85
ATL60/110
ATL60/150
ATL50/60
ATL50/85
ATL50/110
ATL50/150
XC95216 133, 166 ATLS60/12 0
ATLS60/144
ATLS60/160
ATLS60/208
ATL60/60
ATL60/85
ATL60/110
ATL60/150
ATL50/60
ATL50/85
ATL50/110
ATL50/150
XC95288 168, 192 ATLS60/16 0
ATLS60/208 ATL60/110
ATL60/150
ATL60/200
ATL50/110
ATL50/150
ATL50/200
XC95432 232 ATLS60/208
ATLS60/225
ATLS60/256
ATL60/235
ATL60/300 ATL50/235
ATL50/300
XC95576 232 ATLS60/208
ATLS60/225
ATLS60/256
ATL60/235
ATL60/300 ATL50/235
ATL50/300
Note: 1. Equivalent usable gate data not available.
2. Target array dependent on number of I/O pins used, and pinout.
Table 1 (continued). Xilinx® FPGA/CPLD/Atmel Gate Array Cros s Reference
CMOS ASIC
9-109
Altera
FPGA Equivalent
Usa ble Ga tes I/O
Pins
Target Atme l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
Flex 10K
EPF10K10 31000 134 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
EPF10K20 63000 189 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
EPF10K30 69000 246 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
EPF10K40 93000 189 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
EPF10K50 116000 310 ATL60/435
ATL60/550 ATL50/435
ATL50/550
EPF10K70 118000 358 ATL60/550
ATL60/700 ATL50/550
ATL50/700
EPF10K100 158000 406 ATL60/700
ATL60/870 ATL50/700
ATL50/870
Flex 8000
EPF8282A
EPF8282AV 2500 78 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
EPF8452
EPF8452A 4000 120 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
EPF8636A 6000 136 ATLS60/144 ATL60/85 ATL50/85
EPF8820
EPF8820A 8000 152 ATLS60/160 ATL60/110 ATL50/110
EPF81188
EPF81188A 12000 184 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
EPF81500
EPF81500A 16000 208 ATLS60/208
ATLS60/225 ATL60/200
ATL60/235 ATL50/200
ATL50/235
Note: 1. Target array dependent on number of I/O pins used, and pinout.
Tab le 2. Altera FPGA/PLD/Atmel Gate Array Cross Reference
9-110 CMOS ASIC
Altera
PLD Equivalent
Usa ble Ga tes I/O
Pins
Target Atme l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
Max 9000
EPM9320 6000 168 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
EPM9400 8000 184 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
EPM9480 10000 200 ATLS60/208 ATL60/200 ATL50/200
EPM9560 12000 216 ATLS60/208
ATLS60/225 ATL60/200
ATL60/235 ATL50/200
ATL50/235
Max 7000
Max
7000S
EPM7032
EPM7032V
EPM7032S
600 36 ATLS60/80 ATL60/4 ATL50/4
EPM7064
EPM7064S 1250 68 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
EPM7096
EPM7096S 1800 76 ATLS60/80
ATLS60/100 ATL60/25 ATL50/25
EPM7128E
EPM7128S 2500 100 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
EPM7160E
EPM7160S 3200 104 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
EPM7192E
EPM7192S 3750 124 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
EPM7256E
EPM7256S 5000 164 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
Max 5000
EPM5032 600 24 ATLS60/80 ATL60/4 ATL50/4
EPM5064 1250 36 ATLS60/80 ATL60/4 ATL50/4
EPM5128
EPM5128A 2500 60 ATLS60/80 ATL60/15 ATL50/15
EPM5130 2500 100 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
RPM5192 3200 104 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
Classic
EP610 300 20 ATLS60/80 ATL60/4 ATL50/4
EP910 450 36 ATLS60/80 ATL60/4 ATL50/4
EP1810 900 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
Note: 1. Target array dependent on number of I/O pins used, and pinout.
Table 2 (continued). Altera FPGA/PLD/Atmel Gate A rray Cross Reference
CMOS ASIC
9-111
Actel
FPGA Equivalent
Usa ble Ga tes I/O
Pins
Targ et At m el
Gate Array(1)
AT LS60 Seri es ATL60 Ser ies A TL50
Integrator
Series
1200XL
and
3200DX
A1225XL 2500 83 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
A1240XL 4000 104 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
A3265DX 6500 126 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
A1280XL 8000 140 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
A32100DX 10000 152 ATLS60/160 ATL60/110 ATL50/110
A32140DX 14000 176 ATLS60/160
ATLS60/208 ATL60/150 ATL50/150
A32200DX 20000 202 ATLS60/208
ATLS60/225 ATL60/200
ATL60/235 ATL50/200
ATL50/235
A32300DX 30000 250 ATLS60/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
A32400DX 40000 288 ATL60/300
ATL60/435 ATL50/300
ATL50/435
Accelerator
Series
ACT 1
A1010B
A10V10B 1200 57 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
A1020B
A10V20B 2000 69 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
ACT 2
A1225A 2500 83 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
A1240A 4000 104 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
A1280A 8000 140 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
ACT 3
A1415 1500 80 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
A1425 2500 100 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
A1440 4000 140 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
A1460 6000 168 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
A14100 10000 228 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
Notes: 1. Target array dependent on number of I/O pins used, and pinout.
2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins.
Tabl e 3. Ac te l F PG A/A tmel G a te Array Cros s Re fere n c e
9-112 CMOS ASIC
Actel
FPGA Equivalent
Usa ble Ga tes I/O
Pins
Target Atme l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
ACT 3
PCI
Compliant
A1440BP 4000 140 ATLS60/144
ATLS60/160 ATL60/85
ATL60/110 ATL50/85
ATL50/110
A1460BP 6000 168 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
A14100BP 10000 228 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
Note: 1. Target array dependent on number of I/O pins used, and pinout.
Tabl e 3 ( cont inue d). Actel FPGA/Atmel Gate Array Cross Reference
CMOS ASIC
9-113
Lattice
PLD
Equivalent
Us a ble Ga tes
(PLD Gates) I/O
Pins
Ta rg et At me l
Gate Array(1)
ATLS60 Ser ies ATL60 Series ATL50
ispLSI®
1000/E
1016E 2000 36 ATLS60/80 ATL60/4 ATL50/4
1024 4000 54 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
1032E 6000 72 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
1048E 8000 110 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
ispLSI® 2000
and
ispLSI®
2000LV
2032
2032LV 1000 34 ATLS60/80 ATL60/4 ATL50/4
2064
2064LV 2000 68 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
2096
2096LV 4000 102 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
2128
2128LV 6000 136 ATLS60/144 ATL60/85 ATL50/85
ispLSI® 3000
3160 7000 160 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
3192 9000 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
3256 11000 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
3256E 12000 256 ATLS60/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
3320 14000 160 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
Notes: 1. Target array dependent on number of I/O pins used, and pinout.
2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 248 I/O pins.
Table 4. Lattice PLD/Atmel Gate Ar ray Cross Ref erence
9-114 CMOS ASIC
Cypress
FPGA Equivalent
Usa ble Ga tes I/O
Pins
Target Atme l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
Ulta38000
CY7C38003
CY7C338003 3000 120 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
CY7C38005
CY7C338005 5000 156 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
CY7C38007
CY7C38007 7000 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
CY7C38009
CY7C338009 9000 228 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
CY7C380012
CY7C3380012 12000 264 ATLS60/256(2) ATL60/300
ATL60/435 ATL50/300
ATL50/435
CY7C380016
CY7C3380016 16000 300 ATL60/435
ATL60/550 ATL50/435
ATL50/550
CY7C380020
CY7C3380020 20000 336 ATL60/550
ATL60/700 ATL50/550
ATL50/700
pASIC380
CY7C381P
CY7C3381A 1000 32 ATLS60/80 ATL60/4 ATL50/4
CY7C382P
CY7C3382A 1000 56 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
CY7C383A
CY7C3383A 2000 56 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
CY7C384A
CY7C3384A 2000 80 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
CY7C385P
CY7C3385A 4000 80 ATLS60/80
ATLS60/100 ATL60/25
ATL60/40 ATL50/25
ATL50/40
CY7C386P
CY7C3386A 4000 114 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
CY7C387P
CY7C3387P 8000 116 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
CY7C388P
CY7C3388P 8000 172 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
Note: 1. Target array dependent on number of I/O pins used, and pinout.
2. ATLS60/256 has 248 I/O pins and will accommodate devices with no more than 256 I/O pins.
Tabl e 5. Cypress FPG A/ PLD/Atmel Gate Array Cross Reference
CMOS ASIC
9-115
Cypress
PLD Equivalent
U s a b le Ga te s (1) I/O
Pins
Target Atme l
Gate Array( 2)
ATLS60 Series ATL60 Series ATL50
Ultra3900(3)
39192 (84) 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
(160) 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
39256 (160) 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
(208) 160 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
39320 (208) 160 ATLS60/160
ATLS60/208 ATL60/110
ATL60/150 ATL50/110
ATL50/150
(240) 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
39384 (240) 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
39448 (240) 192 ATLS60/160
ATLS60/208 ATL60/150
ATL60/200 ATL50/150
ATL50/200
(304) 224 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/300
39512 (304) 224 ATLS60/225
ATLS60/256 ATL60/235
ATL60/300 ATL50/235
ATL50/30
Flash370
371 32 ATLS60/80 ATL60/4 ATL50/4
372 32 ATLS60/80 ATL60/4 ATL50/4
373 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
374 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
375 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
Flash370i
371i 32 ATLS60/80 ATL60/4 ATL50/4
372i 32 ATLS60/80 ATL60/4 ATL50/4
373i(84/100) 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
374i(84/100) 64 ATLS60/80 ATL60/15
ATL60/25 ATL50/15
ATL50/25
375i 128 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
Note: 1. Equivalent usable gate data not available.
2. Target array dependent on number of I/O pins used, and pinout.
3. Numbers given in parenthesis indicates optional pin counts.
Tabl e 5 ( cont inue d). Cypress FPGA/PLD/Atme l Gate A rray C ross Re ference
9-116 CMOS ASIC
Atmel
PLD/FPGA Equivalent
Usa ble Ga tes I/O
Pins
Target Atme l
Ga te Array(1)
ATLS60 Series ATL60 Series ATL50
PLD
ATF1500 1500 32 ATLS60/80 ATL60/4 ATL50/4
ATV2500 2500 24 ATLS60/80 ATL60/4 ATL50/4
ATV5000 5000 52 ATLS60/80 ATL50/4
ATL60/15 ATL50/4
ATL50/15
ATV5100 5100 52 ATLS60/80 ATL60/4
ATL60/15 ATL50/4
ATL50/15
FPGA
AT6002 2000-4000 96 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
AT6003 3000-6000 120 ATLS60/120
ATLS60/144 ATL60/60
ATL60/85 ATL50/60
ATL50/85
AT6005 5000-10000 108 ATLS60/100
ATLS60/120 ATL60/40
ATL60/60 ATL50/40
ATL50/60
AT6010 10000-20000 204 ATLS60/208
ATLS60/225 ATL60/200
ATL60/235 ATL50/200
ATL50/235
Note: 1. Target array dependent on number of I/O pins used, and pinout.
At mel FPGAs /PL Ds - Cr os s Re f eren ce
Table 6 lists the target Gate Arrays for conversion of Atmel FPGAs and PLDs.
Table 6. Atmel PLD and FPGA/Atm el Gate Array Cross Reference
CMOS ASIC
9-117
