Rev.2.00, Jul.21.2004, page 1 of 91
HN29V2G74WT-30
(128M × 8-bit) ×2 AG-AND Flash Memory REJ03C0182-0200Z
Rev. 2.00
Jul.21.2004
Description
The HN29V2G74 is a 2G-bit AG-AND flash memory. It mounts two 1G-bit AG-AND flash memories
with multi-level memory cells, which are programmable and erasable automatically with a single 3.0 V
power supply. It achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesas's previous
multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate-AND) type
Flash memory cell using multi level cell technology provides both the most cost effective solution and high
speed programming.
Features
• On-board single power supply: VCC = 2.7 V to 3.6 V
• Operation Temperature range: Ta = 0 to +70°C
• Memory organization
Memory array: (2048+64) bytes × 16384 page × 4 Bank × 2
Page size: (2048+64) bytes × 2
Block size: (2048+64) bytes × 2 page × 2
Page Register: (2048+64) bytes × 4 Bank × 2
• Multi level memory cell
2bit/cell
• Automatic program
Page program
Multi bank program
Cache program
2 page cache program
• Automatic Erase
Block Erase
Multi Bank Block Erase
• Access time
Memory array to register (1st access time): 120 µs max
Serial access: 35 ns min
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 2 of 91
• Low power dissipation
ICC1 = 10 mA (typ) : Read (50 ns cycle) (1-chip operation)
ICC1 = 20 mA (typ) : Read (50 ns cycle) (2-chip operation)
ICC2 = 15 mA (typ) : Read (35 ns cycle) (1-chip operation)
ICC2 = 30 mA (typ) : Read (35 ns cycle) (2-chip operation)
ICC3 = 10 mA (typ) : Program (single bank) (1-chip operation)
ICC3 = 20 mA (typ) : Program (single bank) (2-chip operation)
ICC4 = 20 mA (typ) : Program (Multi bank) (1-chip operation)
ICC4 = 40 mA (typ) : Program (Multi bank) (2-chip operation)
ICC5 = 10 mA (typ) : Erase (single bank) (1-chip operation)
ICC5 = 20 mA (typ) : Erase (single bank) (2-chip operation)
ICC6 = 15 mA (typ) : Erase (Multi bank) (1-chip operation)
ICC6 = 30 mA (typ) : Erase (Multi bank) (2-chip operation)
Isb1 = 1 mA (max) : Standby (TTL) (1-chip operation)
Isb1 = 2 mA (max) : Standby (TTL) (2-chip operation)
Isb2 = 50 µA (max) : Standby (CMOS) (1-chip operation)
Isb2 = 100 µA (max) : Standby (CMOS) (2-chip operation)
Isb3 = 5 µA (max) : Deep standby (1-chip operation)
Isb3 = 10 µA (max) : Deep standby (2-chip operation)
• Program time: 600 µs (typ) (Single/Multi bank)
transfer rate: 10 MB/s (Multi bank )
• Erase time: 650 µs (typ) (Single/Multi bank)
• The following architecture is required for data reliability
Error correction: 3 bit error correction per 512byte are recommended.
Block replacement: When an error occurs in program page, block replacement including
corresponding page should be done. When an error occurs in erase operation, future access to this
bad block is prohibited. It is required to manage it creating a table or using another appropriate
scheme by the system (Valid blocks: Initial valid blocks for more than 98% per Bank.
Replacement blocks must be ensured more than 1.8% of valid blocks per Bank).
Wear leveling: Wear leveling is to level Program and Erase cycles in one block in order to reduce
the burden for one block and let the device last for long time. Actually, it does detect the block
which is erased and rewritten many times and replace it with less accessed block.
To secure 105 cycles as the program/erase endurance, need to control not to exceed Program and
Erase cycles to one block. You should adopt wear leveling once in 5000 Program and Erase cycles.
It is better to program it as a variable by software.
• Program/Erase Endurance: 105 cycles
• Package line up
WSOP: WSOP 48pin package (TFP-48DBV)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 3 of 91
Ordering Information
Type No. Operating voltage (VCC) Organization Package
HN29V2G74WT-30 2.7 V to 3.6 V ×8 12.0 × 17.0 mm2
0.5 mm pitch
48-pin plastic WSOP (TFP-48DBV)
Lead free
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 4 of 91
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O8_1
I/O7_1
I/O6_1
I/O5_1
VCC1
VSS1
NC
R/B1
RE1
NC
CE1
PRE1
VCC1
NC
VSS1
RES1
CLE1
ALE1
WE1
WP1
I/O4_1
I/O3_1
I/O2_1
I/O1_1
(Left side chip) (Right side chip)
PIN NAME PIN No. PIN NAMEPIN No.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I/O8_2
I/O7_2
I/O6_2
I/O5_2
VCC2
VSS2
R/B2
NC
RE2
CE2
NC
PRE2
VCC2
NC
VSS2
RES2
CLE2
ALE2
WE2
WP2
I/O4_2
I/O3_2
I/O2_2
I/O1_2
48-pin WSOP
(Top view)
Pin configuration
Pin name Function
I/O 1_1 to I/O 8_1,
I/O 1_2 to I/O 8_2 Command, address, data Input/output
CLE1, CLE2 Command Latch Enable
ALE1, ALE2 Address Latch Enable
CE1, CE2 Chip Enable
RE1, RE2 Read Enable
WE1, WE2 Write Enable
WP1, WP2 Write Protect
R/B1, R/B2 Ready/Busy
PRE1, PRE2 Power on Auto Read Enable
RES1, RES2 Reset
VCC1, VCC2*1 Power
VSS1, VSS2*2 Ground
NC No Connection
Notes: 1. In this datasheet, VCC means both VCC1 and VCC2, unless otherwise noted.
2. In this datasheet, VSS means both VSS1 and VSS2, unless otherwise noted.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 5 of 91
Block Diagram
Page address buffer
Left side chip
X-
decoder
Memory array
(2048+64)
x 16384 page
Data register
2048+64 byte
Y-Gating
Y-Decoder
Y-Gating
Y-Decoder
Data register
2048+64 byte
Data
output buffer
X-
decoder
Memory array
(2048+64)
x 16384 page
Multi-
plexer
Control
signal
buffer
Data
input
buffer
Input data
control
Column address
counter
Read/Program/Erase
control
8
16
8
12
16
8
Bank0 Bank3Bank
1
Bank
2
I/O1_1
to
I/O8_1
V
CC1
V
SS1
R/B1
CE1
RE1
WE1
WP1
CLE1
ALE1
PRE1
RES1
Page address buffer
Right side chip
X-
decoder
Memory array
(2048+64)
x 16384 page
Data register
2048+64 byte
Y-Gating
Y-Decoder
Y-Gating
Y-Decoder
Data register
2048+64 byte
Data
output buffer
X-
decoder
Memory array
(2048+64)
x 16384 page
Multi-
plexer
Control
signal
buffer
Data
input
buffer
Input data
control
Column address
counter
Read/Program/Erase
control
8
16
8
12
16
8
Bank0 Bank3Bank
1
Bank
2
I/O1_2
to
I/O8_2
V
CC2
V
SS2
R/B2
CE2
RE2
WE2
WP2
CLE2
ALE2
PRE2
RES2
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 6 of 91
Memory map and address
Memory Map
Bank Organization
Addressing
FFFFH
FFFEH
FFFDH
0006H
0005H
0004H
0003H
0002H
0001H
0000H 2048bytes
Data register
64bytes
2048bytes 64bytes
Block 2
Block 1
Block 0
1Page = (2048+64)Bytes: Program Size
1Block = (2048+64)Bytes x 2Pages: Erase Size
= (4096+128)Bytes: Erase Size
1Device = (2048+64)Bytes x 2Pages x 32768Blocks
Bank0
(8192Blocks)
(16384pages)
Block 0
page 0
page 4
Block 4
page 8
page 12
Block 32764
page 65528
page 65532
Bank1
(8192Blocks)
(16384pages)
Block 1
page 1
page 5
Block 5
page 9
page 13
Block 32765
page 65529
page 65533
Bank2
(8192Blocks)
(16384pages)
Block 2
page 2
page 6
Block 6
page 10
page 14
Block 32766
page 65530
page 65534
Bank3
(8192Blocks)
(16384pages)
Block 3
page 3
page 7
Block 7
page 11
page 15
Block 32767
page 65531
page 65535
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
Column
address
Row
address
A12, A13: Bank select
A14: Page select
A15 to A27: Block select
Symbol I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
CA1 A7 A6 A5 A4 A3 A2 A1 A0
CA2LLLLA11A10A9A8
RA1 A19 A18 A17 A16 A15 A14 A13 A12
RA2 A27 A26 A25 A24 A23 A22 A21 A20
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 7 of 91
Pin Functions
Chip Enable: CE1, CE2
CE1 and CE2 are used, to select the left side chip or the right side chip, respectively, of the device. In this
datasheet, CE means both CE1 and CE2, unless otherwise noted.
It goes to the standby mode when CE goes to ‘H’ level when the device is in the Output disable state.
When the device is in the Busy state during Program or Erase or Read operation, CE signal is ignored and
the device does not return to the standby mode even if CE goes to High.
Read Enable: RE1, RE2
The RE1 and RE2 signals control, serial data output of the left side chip or the right side chip, respectively.
In this datasheet, RE means both RE1 and RE2, unless otherwise noted. Data is available tREA after the
falling edge of RE.
The internal address counter is also incremented by one (Address = Address + 1) on this falling edge.
Write Enable: WE1, WE2
WE1 and WE2 are the signals to latch each data from the I/O port, in the left side chip or the right side
chip, respectively, of the device. In this datasheet, WE means both WE1 and WE2, unless otherwise noted.
Data are latched in the device on the rising edge of WE.
Command Latch Enable: CLE1, CLE2
The CLE1 and CLE2 input signals are used to control loading of the operation mode command into the
internal register, of the left side chip or the right side chip, respectively. In this datasheet, CLE means both
CLE1 and CLE2, unless otherwise noted.
The command is latched into the internal register from the I/O port on the rising edge of WE when CLE is
high.
Address Latch Enable: ALE1, ALE2
The ALE1 and ALE2 input signals are used to control loading of the input address information or input
data into the internal address/data register, of the left side ch ip or the right side chip , respectively. In this
datasheet, ALE means both ALE1 and ALE2, unless otherwise noted.
Address is latched on the rising edge of WE with ALE high and Data is latched with ALE low.
I/O port: I/O1_1 to I/O8_1
The I/O1_1 to I/O8_1 and I/O1_2 to I/O8_2 pins are used as a port for transferring address, command and
input/output data to and from the device.
I/O1_1 to I/O8_1 are used to the left side chip, I/O1_2 to I/O8_2 are used to the right side chip,
respectively. In this datasheet, for example, I/O1 means both I/O1_1 and I/O1_2, unless otherwise noted.
Write Protect: WP1, WP2
The WP1 and WP2 signals are used to protect, the left side chip or the right side chip of the device,
respectively, from accidental programming or erasing. In this datasheet, WP means both WP1 and WP2,
unless otherwise noted.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 8 of 91
The WP low reset internal progr am/erase operation. It is usually used for pr otecting the data with the WP
low during the power-on/off sequence when input signals are invalid.
Ready Busy: R/B1, R/B2
The R/B 1 and R/B2 output signals indicate the status of the device operation, of the left side chip or the
right side chip, respectively. In this datasheet, R/B means both R/B 1 and R/B 2, unless otherwise noted.
When R/B is low, it indicates that the Program, Erase or Read operation is in process. After the operation
is completed, R/B turns back to the high impedance state.
The output buffer for this signal is an open-drain and has to be pulled up to VCC with appropriate register.
Reset: RES1, RES2
The RES1 and RES2 signals control reset operation, for the left side chip or the right side chip,
respectively, of the device. In this datasheet, RES means both RES1 and RES2, unless otherwise noted.
When power on and power off, keep the RES pin VILD level (VSS ± 0.2V), and keep pin VIHD level (VCC ±
0.2V) during program, erase, read operation.
The transition to deep standby mode is executed when RES set VILD level during standby mode.
Power on auto Read Enable: PRE1, PRE2
The PRE1 and PRE2 control auto read operation executed during power-on, in the left side chip or the
right side chip, respectively. In this datasheet, PRE means both PRE1 and PRE2, unless otherwise noted.
The power-on auto-read is enabled when PRE pin is tied to VCC. Please contact Renesas Technology’s
sales office before using the power-on auto-read.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 9 of 91
Mode selection
The address input, command input, and data input/output operation of the device are controlled by RES,
WP, WE, CE, CLE, ALE, RE, PRE signals. The following shows the operation logic table.
Logic Table
Mode RES*3 WP*3 CE WE CLE ALE RE PRE*3
Command Input H × L H L H ×*2 Read Mode
Address Input
(4clock) H × L L H H ×*2
Command Input H H L H L H ×*2 Write Mode
Address Input
(4clock) H H L
L H H ×*2
Data Input H H L L L H ×*2
Data Output H × L H L L ×*2
During Read (Busy) H × L H L L H ×*2
During Program (Busy) H H × × × × × ×*2
During Erase (Busy) H H × × × × × ×*2
Write Protect H L × × × × × ×*2
Stand-by H VSS ± 0.2 V
/VCC ± 0.2 V H × × × × V
SS ± 0.2 V
/VCC ± 0.2 V
Deep Stand-by VSS ± 0.2 V VSS ± 0.2 V
/VCC ± 0.2 V × × × × × V
SS ± 0.2 V
/VCC ± 0.2 V
Notes: 1. H: ViH, L: ViL, ×: ViH or ViL
2. PRE must be “H” fix when using Power On Auto Read and “L” fix when not using it.
3. RES, WP, PRE must be set L: ViLD, H: ViHD, ×: ViHD or ViLD
Program/Erase Characteristics
Symbol Min Typ Max Unit Notes
Program Time tPROG 0.6 2.4 ms
Cache Program Time tCPROG 0.6 4.8 ms
Dummy Busy for Cache Program tCBSY 3 2400 µs
Dummy Busy Time tDBSY 1 4 µs
Number of Partial Program Cycles in a Same Page N 8 cycles
Block Erase Time tBERS 0.65 20 ms
Page mode Erase Verify Time tPEV 50 µs
Block mode Erase Verify Time tBEV 70 µs
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 10 of 91
Command Definition
Command Sets 1st. cycle 2nd. cycle acceptable while Busy
Read 00h 30h
Multi Bank Read 00h 31h
Random Data output in a Page 05h E0h
Read for copy back 00h 35h
Copy Back Program 85h 10h
Page Data output 06h E0h
Multi Bank Copy Back Program 85h 11h
Data Recovery Read 06h E0h
Data Recovery Program 85h 10h
Reset FFh Acceptable
Page Program 80h 10h Acceptable*2
Random Data Input in a Page 85h Acceptable*2
Multi Bank Page Program 80h 11h Acceptable*2
Cache Program 80h 15h
Block Erase 60h D0h
Multi Bank Block Erase 60h−60h D0h
Read Status 70h Acceptable
Read Error Status 72h Acceptable
Read Multi Block Status 71h Acceptable
Read Multi Block Error Status*1 73h, 74h, 75h, 76h Acceptable
Status mode Reset 7Fh
Page mode Erase Verify 60h D2h
Block mode Erase Verify 60h D3h
Read ID 90h
Device Recovery 00h 38h
Notes: 1. Read Multi Block Error Status
73h: Bank0 Error Status, 74h: Bank1 Error Status, 75h: Bank2 Error Status, 76h: Bank3 Error
Status
2. The input of the program data can be done only in Busy state of Erase operation.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 11 of 91
Device Operation
Page Read
It becomes Busy state with WE rising edge after writing 00h along with four address cycles and 30h and
data transfer starts from memory array to the data register. The device output the data serially from
specified column address when inputting addr ess by the repetitive high to low transition of the RE clock
after it is Ready state.
It is possible to shorten Busy time after the 2nd page when the data of page overlapped to 4 bank
consecutively like Page 0, Page1, Page 2, Page 3 is read out (Please see 4 page read below).
The data of Page 1 to Page 3 are transferred to the data register when writing 00h and 30h specifying
column address and Page 0.
The device output the data of Page 0 serially by clocking RE after transferring it from memory array to the
data register.
The data of Page 1, Page 2, Page 3 which are transferred to the data register can be output using Page data
out command (06h/E0h) after the data of Page 0 output.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 12 of 91
00h
CLE
ALE
I/O
Page N
M
Memory array
Data register
4page read
(1) (2) (3)
(A)
R/B (A)
(B)
column J
pageN
N=0,4,8,12... columnKpageN pageN+1
CE
R/B
I/O
R/B
WE
RE
CA1
00h CA1 CA2 RA1 RA2 DOUT DOUT DOUT DOUT
30h 06h CA1 CA2 RA1 RA2 E0h
CA2
column address M Page address N
Page address N
RA1 RA2 30h M M+1 M+2
tR
tR
Busy
Memory array
Bank 0
Page N
Data register
Bank 1
Page N+1
Bank 2
Page N+2
Bank 3
Page N+3
Memory array
Bank 0
Page N
column J
Data register
(4)
(1)
(2)
(5)
columnL pageN+2 columnM pageN+3
I/O (B) 06h CA1 CA2 RA1 RA2 DOUT DOUT DOUT DOUT
E0h 06h CA1 CA2 RA1 RA2 E0h
Bank 1
Page N+1
column K
(3)
Bank 3
Page N+3
column M
(5)
Bank 2
Page N+2
column L
(4)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 13 of 91
Random Data output in a Page Read
When the device output the data serially in Page read mode operation, the data from any column address in
a Page which is reading can be output by writing 05h and E0h with two column address cycles.
There is no restriction on an order of column address which can be specified and it is possible to specify
many times including same column address in the same Page address.
CLE
ALE
Page N
ML
Memory array
Data register
CE
R/B
WE
Page
address N
Column
address L
Column
address M
pageN pageN
I/O
00h CA1 CA2 RA1 RA2 L L+1 L+2 M M+1 M+230h 05h CA1 CA2 E0h
RE
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 14 of 91
Multi Bank Read
Multi Bank Read operation enables to read the data of any Page address in 4 bank. Writing 00h command
with four address cycles can be specified to maximum 4 Bank. There is no restriction on an order of a
Bank to specify.
Page address specified later becomes effective when it is specified twice in the same Bank.
The device become Ready state at rising edge of WE after writing 31h command with specifying address
and the data transfer from the memory array to the data register is started.
After it becomes Ready state, it executes specifying a bank for read and column address for starting read by
writing 06h and E0h command with four address cycles. After that the device output the data serially from
column address which is specified by clocking RE. It is possible to specify any bank for read and to read
the data which is transferred to th e data register repeatedly.
(1)
(4) (5)
(A)
(2) (3)
(A)
(B)
column J
page N
column K
page P
column L
page Q
column M
page R
column J’
page N
column K’
page P
I/O
R/B
(B)
I/O
R/B
00h Address 00h Address 00h Address 00h 31hAddress
column L’
page Q
column M’
page R
06h Address E0h
06h E0h D
OUT
D
OUT
06h Address E0h
D
OUT
D
OUT
D
OUT
D
OUT
Address 06h E0h D
OUT
D
OUT
Address
tR
Memory array
Bank 0
Page N
Data register
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Bank 0
Page N
column J’
Data register
(1)
(2)
Bank 1
Page P
column K’
(3)
Bank 3
Page R
column M’
(5)
Bank 2
Page Q
column L’
(4)
Bank0 Bank1 Bank2 Bank3 Bank0 Bank1
Bank2 Bank3
Note: 1. (2) (3) (4) (5): repeatable
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 15 of 91
Multi Bank Read with Random Data Output
The data can be read out setting column address freely on the way to the read operation of Page address
data in each Bank in Multi Bank Read operation. It is possible to read out the data by writing 05h and E0h
command with two column address cycles. There is no restriction to specify any column address and it is
possible to specify it including same one in the same page address many times.
(1) (2)
(A)
(B)
(C)
(D)
column J
page N
column K
page P
column L
page Q
column M
page R
column J’
page N column J’’
I/O
R/B
00h Address 00h Address 00h Address 00h 31hAddress 06h E0h DOUT DOUT
Address 05h E0h DOUT DOUT
Address
tR
(A)
R/B
R/B
(C)
(3) (4)
(B)
I/O
column K’
page P
column L’
page Q
column K’’ column L’’
06h Address E0h DOUT 06h Address E0h05h Address E0h
DOUT DOUT DOUT
(5)
(D)
I/O
column M’
page R column M’’
06h Address E0h DOUT 05h Address E0h
DOUT DOUT DOUT
05h Address E0h
DOUT DOUT DOUT DOUT
Memory array
Bank 0
Page N
Data register
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Bank 0
Page N
column J’
column J’’
Data register
(1)
(2)
Bank 1
Page P
column K’
(3)
Bank 3
Page R
column M’
(5)
Bank 2
Page Q
column L
’
(4)
column K’’ column L’’ column M’’
Note: 1. (2) (3) (4) (5): repeatable
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 16 of 91
Page Program
Page program operation enables to write the data into one Page address. The data is stored into the data
register after writing 80h command with four address input (Column address, Page address) and data input.
It is also stored serially from column address which is input and then automatic program operation starts
after writing 10h command (Program command). Program operation must be executed to a Page address
which the data is erased. A number of additional program in the same Page address is maximum 8 times.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 17 of 91
Page Program Random Data input in a Page
This operation enables to input the program data in the Page address randomly writing 85h command with
two column address input on the way to the program operation in the Page program mode.
It can input the data by specifying a column address in the same page which you want to program the data
using this mode.
After completion of the data input, program it to the specified column address is executed automatically by
writing 10h command (Program start command). Program operation must be executed to a Page address
which the data is erased.
A number of additional program in the same Page address is maximum 8 times.
The data of 1 byte or more need to be input when it is in random data input.
80h
CLE
ALE
I/O
Page N
Program
LM
Memory array
Data register
CE
R/B
WE
RE
CA1
Column
address L
Page
address N
Column
address M
CA2 RA1 RA2 D
IN
D
IN
D
IN
t
PROG
85h CA1 CA2 D
IN
D
IN
D
IN
10h 70h status
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 18 of 91
Multi Bank Page Program
It is possible to program the data to any one page address in each bank simultaneously since this device
adopts 4 bank structure. The bank to be programmed the data is chosen from 1 bank to maximum 4 bank.
Address and data for next bank can be input consecutively by writing 11h command (dummy command)
after writing 80h command with column and page address, data as well as usual page program.
Program operation to several banks specified automatically are executed simultaneously by writing 10h
command (program start command) after data input to the maximum 4 bank completes.
R/B
(1) (2)
(B)
(A)
(A)
(B)
column J page N column K page P
I/O
80h CA1 CA2 RA1 RA2 DIN DIN DIN DIN
80h11h CA1 CA2 RA1 RA2 11h
(3) (4)
column L page Q column M page R
I/O
80h CA1 CA2 RA1 RA2 DIN DIN DIN DIN
80h11h CA1 CA2 RA1 RA2 10h 71h status
out
t
DBSY
t
DBSY
R/Bt
DBSY
t
PROG
Memory array
Bank 0
Page N
Program
Program Program Program
column J column K column L column M
Data register
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
(1) (2) (3) (4)
Bank0 Bank1
Bank2 Bank3
(5) (5) (5) (5)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 19 of 91
Multi Bank Page Program with Random Data Input in a Page
This mode enables to input program data specifying an address in a page which the data is programmed
when it is in Multi Bank Page Program operation. The data can be input serially by writing 85h command
with column address to on the way to the data input to the page address to be programmed as well as
random data input in page mode. After the data input, program and address/data input to next bank is
executed by writing 11h command (dummy command) and then 80h command as well as Multi Bank Page
Program.
Program operation to several banks specified automatically is executed simultaneously by writing 10h
command (program start command) after the completion of data input to the final bank.
Address of the random data can be set in every page for program freely.
R/B
(A)
column J page N column J’
I/O
t
DBSY
Memory array
Bank 0
Page N
Program
column J
Data register
(1) (2) (3) (4)
(B)
DIN 85h CA1 CA2 11hDIN DIN
(1)
80h CA1 CA2 RA1 RA2 Din80h CA1 CA2 RA1 RA2 DIN
R/B
(C)
column K page P column K’
I/O
t
DBSY
(D)
DIN 85h CA1 CA2 11hDIN DIN
(2)
80h CA1 CA2 RA1 RA2 Din80h CA1 CA2 RA1 RA2 DIN
(E)
column L page Q column L’
t
DBSY
(F)
DIN 85h CA1 CA2 11hDIN DIN
(3)
80h CA1 CA2 RA1 RA2 Din80h CA1 CA2 RA1 RA2 DIN
column M page R column M’
t
PROG
DIN 85h CA1 CA2 10hDIN DIN
(4)
80h CA1 CA2 RA1 RA2 Din80h CA1 CA2 RA1 RA2 DIN
(A)
(B)
R/B
I/O
(C)
(D)
R/B
I/O
(E)
(F)
71h status
out
(5)
column J’
Bank 1
Page P
Program
column K column K’
Bank 2
Page Q
Program
column L column L’
Bank 3
Page R
Program
column M column M’
(5) (5) (5) (5)
Bank2
Bank3
Bank1
Bank0
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 20 of 91
Cache Program
Cache program operation enables to use the data register of the bank which do not program as the cache
register.
The program data for next page address is transferred to Flash memory from external data buffer by using
the cache register while programming the primary data.
Setup for program starts after writing 15h command following 80h command and program address/data
transfer.
After that the device is in the Busy state. The data register of the bank which do not program is cleared
when program operation inside the device starts and then it is ready to receive the data of next page
address.
In this case next page address must be different page address of the bank with one which programs just
before.
It is prohibited to program the data to page address in same bank consecutively using cache program.
Next page address for program should specify one in different bank.
The data of next page address can be transferred to Flash memory by writing 80h command as well as the
data transfer of the1st page address and then 15h command (program dummy command) input is required
after program address/data input. It becomes Busy state until the program operation to the 1st page address
completes and the data of data register is cleared. If the program operation to the 1st page address does not
complete, it becomes Busy state until the data of data register ex cept for one of the b ank which prog rams
next.
70h command is issued to find out the status in cache program operation after Ready/Busy becomes Ready.
The True Ready/Busy status (I/O5) in cache program becomes busy when CPU is active and shows that the
internal program operation is in the process. The True Ready/Busy status (I/O6) should be verified to find
out the program completion if 15h command is used for the last programming. Reset operation is required
by writing FFh when program operation completes using 15h command and moves to the other operation
except for cache program. Reset operation is not required if 10h command (program start command) is
used for the last programming.
t
CBSY
I/O 80h 15h 70h 80h
R/B
Address,
Data
15h 70h Status 80h Status Address,
Data
t
CBSY
t
CBSY
2nd page 3rd page
(1) (2) (3) (4) (5)
(A)
(B)
t
CBSY
I/O (B) 80h 15h 70h 80h
R/B (A)
Address,
Data
Address,
Data
15h 70h Status 80h Status Address,
Data 15h
t
CBSY
t
CPROG
(M-1) th page M th page (M+1) th page
(7) (8)
70h Status
Memory Array
Bank 0
Page N
Program
Program Program Program
Data Register
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
(1) (3) (5) (7)
(2) (4) (6) (8)
15h
10h
1st page
Address,
Data
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 21 of 91
2page Cache Program
2 page cache program operation is available using both Multi Bank Program and Cache Program operation.
It enables to input the program data for the address of next bank consecutively by writing 11h command
(dummy command) following 80h command and program address/data input. Setup for program starts by
writing 15h command after data input and then the device is in the Busy state (tCBSY). The data registers of
two banks which do not program are cleared when program operation inside the device starts and then it is
ready to receive the data of next two page address.
In this case next two page address must be different page address of the bank with ones which programs
just before.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 22 of 91
Copy Back Program
Copy Back Program operation enables to copy the data to different page address of same bank without
taking it to external data register. Th e data transfer to the data register is started to co py memory array data
of 1 page address writing 35h command following 00h command and address input with 4 cycles. Then
copy of the data is started by writing 10h command following 85h command and address with 4 cycles for
post-copy. Address for post-copy must be chosen page address which has erased (FFh).
Column
address J
Page
address M
Column
address K
Page
address N
status
00h CA1 CA2 RA1 RA2 35h 85h CA1 CA2 RA1 RA2 10h 70h
CLE
CE
WE
ALE
RE
I/O
R/B
t
PROG
(2)(1)
Memory array
Data register
(1)
Page M
Bank 0 Bank 1 Bank 2 Bank 3
Memory array
Data register
(2)
Page N
Program
Bank 0 Bank 1 Bank 2 Bank 3
Note: 1. Post copy address must be specified one in same bank.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 23 of 91
Copy Back Program with Random Data Input In a Page
Source copy data which has transferred to the data register can be updated when copy back program
operation is executed.
Memory array data which has taken out to the data register is updated to the input data after storing source
copy data to the data register and inputting the data following 85h command and 4 address input with 4
cycles. 1 byte data or more must be input when random data input is executed. Program to post-copy page
address is executed by writing 10h command after data input.
Address for post-copy must be chosen page address which has erased (FFh).
Memory array
Data register
Column
address J
Page
address M
Column
address K
Column
address L
Page
address N
Memory array
Data register
Memory array
Data register
00h
CA1 CA2 RA1 RA2
85h
CA1 CA2
85h 10h 70h
statusCA1 CA2RA1 RA2
DIN
DIN
DIN
DIN
35h DIN DIN
(3)(1)
(1)
(3)
(2)
(2)
column K column L
Page M
Page N
Program
Bank 0 Bank 1 Bank 2 Bank 3
Bank 0 Bank 1 Bank 2 Bank 3
Bank 0 Bank 1 Bank 2 Bank 3
CLE
CE
WE
ALE
RE
I/O
R/B
Note: 1. Post copy address must be specified one in same bank.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 24 of 91
Copy Back Program with Data Output
When copy back program operation is executed, it is possible to confirm the source copy data outputting
one which has transferred to the data register to external. It is possible to output the source copy data after
storing it to the data register and inputting E0h command following 06h command and address input with 4
cycles. Program to post-copy page address is executed by writing 10h command following 85h command
and post copy address input with 4 cycles after data output. Address for post-copy must be chosen page
address which has erased (FFh). Copy data can be updated after post copy address input with 4 cycles and
the data input.
column J page M column J’
column J’
column K
page M page N
00h
CA1 CA2 RA1 RA2
06h
CA1 CA2
85h 10h 70h
status
out
CA1 CA2RA1 RA2 RA2
E0h DOUT DOUT
35h
RA1
R/B
I/O
Memory array
Data register
(1)
DOUT
(2)
Page M
Bank 0 Bank 1 Bank 2 Bank 3
Memory array
Data register
Bank 0 Bank 1 Bank 2 Bank 3
Memory array
Data register
(3)
Page N
Program
Bank 0 Bank 1 Bank 2 Bank 3
(1) (2) (3)
Note: 1. Post copy address must be specified one in same bank.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 25 of 91
Copy Back Program with Data Output and Random Data Input in a Page
column J page M column J’
column J’
column K
page M
page N
00h
CA1 CA2 RA1 RA2
06h
CA1 CA2
85h D
IN
D
IN
CA1 CA2RA1 RA2 RA2
E0h D
OUT
D
OUT
35h
RA1
(1)
column L
85h
CA1 CA2
D
IN
D
IN
10h 70h
(4) (5)
(2) (3)
Memory array
Data register
(1)
D
OUT
(2)
Page M
Bank 0 Bank 0Bank 1 to 3
Memory array
Data register
Bank 0 Bank 1 to 3
status
out
Memory array
Data register
Memory array
Data register
D
IN
D
IN
(5)
column K
(3) column L
(4)
Page N
Program
Bank 1 to 3
Bank 1 to 3Bank 0
(A)
(B)
(A)
(B)
I/O
R/B
I/O
R/B
Note: 1. Post copy address must be specified one in same bank.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 26 of 91
Multi Bank Copy Back Program
Multi Bank Copy Back Pro gram enables to execute copy back program to a multiple bank simultaneous ly.
The data is transferred to the data register from memory array simultaneously by writing 35h command
after specifying post copy address consecutively. Data read and update can be executed as well as copy
back program.
Bank0
(A)
(B)
page N page P page Q page R
I/O
R/B
00h CA1 CA2 RA1 RA2 00h CA1 CA2 RA1 RA2 00h CA1 CA2 RA1 RA2 00h CA1 CA2 RA1 RA2 35h
Memory array
Bank 0
Page N
Program Program Program
Program
(1)
(2) (2)
(2)
(2)
(1) (1) (1)
Data register
Bank 1
Page P
Bank 2
Page Q
Bank 3
Page R
Memory array
Bank 0
Page N’
Data register
R/B (A)
I/O (B)
Bank 1
Page P’
Bank 3
Page R’
Bank 2
Page Q’
Bank1 Bank2 Bank3
(1)
page N’ page P’ page Q’ page R’
85h CA2 CA1 RA1 RA2 11h 85h CA1 CA2 RA1 RA2 11h 85h CA1 CA2 RA1 RA2 11h 85h CA1 CA2 RA1 RA2 10h 71h status
out
(2)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 27 of 91
Data Recovery Read
Data recovery read enables to output the data itself which is transferred from external after program
completion.
It is possible to read out the data which is programmed by writing E0h command following 06h command
and read address input with 4 cycles. It is also possible to read out the data of any column address in same
page address by writing E0h command following 05h command and column address input with 2 cycles on
the way to outputting the data by clocking RE.
(2)(1) (3)
I/O
R/B
column NPage Mcolumn L
Page M
10h 06h CA1 CA2 RA1 RA2 E0h 05h CA1 CA1 E0h
D
OUT
D
OUT
D
OUT
D
OUT
Memory array Page M
Program
(1)
Data register
Memory array
Data register
column L
Dout
(2) column N
Dout
(3)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 28 of 91
Data Recovery Program
Data recovery program enables to re-program the program data itself which is transferred from external to
different page address in same bank. Program to newly specified page address is executed by writing 10h
command following 85h command and address for re-programming with 4 cycles as well as copy back
program. Same page address cannot be chosen during this operation.
It is possible to update the re-program data by inputting the data after specifying address for re-
programming.
Address for re-programming must be chosen page address which has erased (FFh).
(2)
(1)
I/O
R/B
Page Ncolumn K
tPROG tPROG
Page M
10h 85h CA1 CA2 RA1 RA2 10h 70h
status
out
Memory array Page M
Program
(1)
Data register
Memory array
Page N
Program (2)
Data register
Note: 1. Page M and Page N are different page address.
85h CA1 CA2 10h 70h status
out
D
IN
D
IN
(2)
(1)
I/O
R/B
page Ncolumn K column L
10h 85h CA1 CA2 RA1 RA2 D
IN
D
IN
(3) (4)
Memory array Page M
Program
(1)
Data register
Memory array
Page N
Program (4)
Data register
Memory array
column K
(2)
Din
column L
(3)
Data register
Din
tPROG tPROG
Note: 1. Page M and Page N are different page address.
It is possible to combine erasing the data of the block with re-programming, as shown below, in the data
recovery program operation.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 29 of 91
To program, update the data next, then erase, and then re-programming.
I/O
R/B
I/O
R/B
80h CA × 2 RA × 2 Data 10h
tPROG
tBERS tPROG
Status
Check 85h CA × 2 RA × 2 Data 85h CA × 2 Data
60h
Erase
Specify a page in the same bank
same as RA in setting 1.
Specify the address for
re-programming (same as *1)
*1 Program 1 data update specify a page program
RA × 2 D0h Status
Check
Program
Status
85h CA × 2 RA × 2 10h 70h
Program1
Program2
Program2 Start
1
Program1
80h−CA1−RA1−Data−10h
RA1 = PageM
85h−CA2−RA2−10h
1
2
4
3
Page M
Program2
4
Erase
60h−RA2−D0h
3
Page N, N+4
col.K col.L
data update
85h−CA2−RA2−Data−85h−CA3−Data
RA2 = PageN
CA2 = col.K
CA3 = col.L
2
To program, erase next, then update the data, and then re-programming.
I/O
R/B
I/O
R/B
80h CA × 2 RA × 2 Data 10h
tPROG
tPROG
Status
out
70h Status
out
70h60h RA × 2 D0h
Program
Specify the address for re-programming
(in the same bank as *1)
Within the same bank
as the page specified in *1
Status
out
85h CA × 2 Data 10h 70h
Program1 *1
Program2 Start
1
Program1
80h−CA1−RA1−Data−10h
RA1 = PageM
1
2
4
3
Page M
Page N
Program2
4
Erase
3
col.K col.L
data update
60h−RA2−D0h
RA2 = PageN
CA2 = col.K
CA3 = col.L
2
85h CA × 2 RA × 2 Data
85h−CA2−RA2−Data−85h−CA3−Data
tBERS
Erase
10h
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 30 of 91
Program Data Input in Erase Busy
Program Data input in Erase Busy enables to program the data of any page address during busy status in
erase operation.
It is possible to prog ram the data in both block erase mode and multi bank block erase mode if they are in
busy state.
There is no restriction between page address for programming and block for erase.
It needs 1µs wait time after the erase status becomes busy to write 80h command for program address and
data input.
It can confirm the status by writing 70h or 71h command after program data input.
The input data is possible to input in both single bank and multi bank mode and corresponds to the data
input mode specifying column address in same page address. It needs to keep 4µs or more from writing
11h command to writing 80h command when the data to a multiple bank is programmed. 10h command
(program start command) must be issued after completion of erase operation.
Program data input in single bank
Note: 1. Status command available
Program data input with random data mode in single bank mode
Note: 1. Status command available
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 31 of 91
Program data input in multi bank program mode (In case of completing data input during busy
status)
Note: 1. Status command available
Program data input in multi bank program mode (In case of not completing data input during busy
status)
Note: 1. Status command available
The correspondence when the erase error occurred in Program Data Input in Erase Busy mode.
In the Program Data Input in Erase Busy mode, after an erase error occurred in one block at a two-blocks
simultaneous erase operation, a certain operation is needed in a particular case. In case of an erase
operation of one block in the same bank as the error-occurred block, the reset command FFh is needed just
before, as shown in Figure 1.
Otherwise, an illegal two-blocks erase operation will be executed, because the address data of two pages to
program remains.
After the one-block erase operation succeed, it is possible to program by specifying the address to program
again with the command 85h, because the data to be programmed stored in the buffer is maintained.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 32 of 91
Program Data Input in Erase Busy (recommend pattern when error occurred) Multi Bank Mode
I/O
R/B
I/O
R/B
Specify the address (same as *1, *2)
again for programming
Erase
Status
FFh
Reset
address
infornation Block2 in Bank0 erase execute Pass
80h–CA0–RA0
–(Data0)–11h
RA × 2 RA × 2 Erase
Status
60h 60h D0h
RA × 2
60h D0h CA × 2
85h RA × 2 11h CA × 2
85h RA × 2 10h70h
CA × 2 RA × 2
80h Data 11h CA × 2 RA × 2
80h Data 70h
Block0 (Bank0),
Erase Block1 (Bank1)
1*1 Specify a page program
Page0 (Bank0)
1
*2 Specify a page program Error only Block0
(Bank0)
Page1 (Bank1) 1
5
5
5
4
3
2
tBERS
tBERS
tDBSY tPROG
1
Block0
Bank0
Erase
Data0
80h–CA0–RA1
–(Data1)
Block1
Bank1
Erase
Data1
4
60h–RA2–D0h
(erase only block2) 85h–CA0–RA2
–11h 85h–CA0–RA1
–10h
Block2
Bank0
Erase
Data0
Block1
Bank1
Data1
Block2
Bank0
Program
Data0
Block1
Bank1
Program
Data1
3
2
Block0
erase error
FFh
command
Address
reset
It is not necessary to reset by command FFh, when transmit the writing data in erase block and 1 page in
same bank, and execute writing during erasing 1 block data, or erasing error occurs and erasing another
block in same bank. But in this case, as shown in following figure, it is necessary to specify the address for
re-programming, after erasing another block address.
Write address specifying it by command 85h at the address for re-programming in the same bank, when
writing it as shown in following figure.
Program Data Input in Erase Busy (recommend pattern when error occurred) Single Bank Mode
I/O
R/B
I/O
R/BtPROG
Specify the address (same as *1)
for re-programming
Another address in Same Bank
(same as *1) erase execute input
*1 Specify a page program
error
Status
Check
Program
Status
85h CA × 2 RA × 2 10h70h 70h
60h RA × 2 D0h 60h RA × 2 D0h
Erase
Status
80h CA × 2 RA × 2 Data 70h
Pass
tBERS tBERS
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 33 of 91
Block Erase
Erase operation for one block which is consisted of 2 page can be executed. One block is consisted of
pageN and page(N+4)
(Ex: page0 and page4, page1 and page5).
Input page address (A14 = VIL) in lower side, when erase block address input.
Multi Block Erase
Erase operation for one block in maximum 4 bank is executed simultaneously. Any block in a bank can be
chosen. Input page address (A14 = VIL) in lower side, when erase block address input.
Page mode Erase Verify
Whether any one page address is erased or not is verified in this mode. Verification starts internally inside
the device after writing D2h command after 60h command and row address input. It can be verified
whether the page address is erased or not after by writing 70h command (status read command) after it
becomes ready.
Block mode Erase Verify
Whether any one block is erased or not is verified in this mode. Verification starts internally inside the
device after writing D3h command after 60h command and row address input. It can be verified whether
the block is erased or not after by writing 70h command (status read command) after it becomes ready.
Multi Bank Page mode Erase Verify
Page mode erase verify for each page in maximum 4bank is executed. It can be verified whether page
address in each bank is erased or not by writing 71h command (status read command) after it becomes
ready.
Multi Bank Block mode Erase Verify
Block mode erase verify for each block in maximum 4bank is executed. It can be verified whether the
block in each bank is erased or not by writing 71h command (status read command) after it becomes ready.
Read ID
ID code can be read out by inputting the address (00h) after writing 90h command.
Manufacturer code (07h) and Device code (01h) can be read out serially by clocking RE.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 34 of 91
Power on Auto Read
The data of the lowest page address can be read out serially without command and address input after
power is on.
Power on auto read mode is activated when VCC reaches about 2.7V. It is enabled only when PRE pin is
tied to VCC.
PRE pin must be connected to VCC when using power on auto read and VSS when not using it.
After power on auto read is executed, reset operation is required by reading out 1 page (2112 byte) data or
writing FFh command.
Note: Please contact Renesas Technology’s sales office before using this mode.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 35 of 91
Status Read at Read mode
The content of status register can be read out writing 70h command (status read command) and by clocking
RE in read operation. The data of memory array cannot be read out even by clocking RE since status read
mode is set after the device becomes ready. 7Fh command needs to be written in case of releasing status
read mode in read operation.
The data of memory array can be read out without address input in this operation.
Operation status of status register
Operation status can be output by status read.
Command Output
70h Single bank operation status
71h Multi bank operation status
72h Single bank operation error status
73h Multi bank operation bank0 error status
74h Multi bank operation bank1 error status
75h Multi bank operation bank2 error status
76h Multi bank operation bank3 error status
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 36 of 91
Status Register check flow (single bank operation)
Start
70h Write
read status register
I/O7=1
R/B=1 or
YES
YES
NO
NO
YES
NO
Not 1 bit error
1 bit error
Fail
Fail
I/O1=0
72h Write
read errorstatus register
I/O6=1
Read ECC check
ECC possible
Program/erase completed
70h command status in single bank operation
status
Program/Erase Cache Program Output
I/O 8 Write protect Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready/Busy Ready: 1 Busy: 0
I/O 6 Ready/Busy True Ready/Busy*1 Ready: 1 Busy: 0
I/O 5 Not Used Not Used 0
I/O 4 Not Used Not Used 0
I/O 3 Not Used Not Used 0
I/O 2 Not Used Pass/Fail (N-1) 0 / Pass: 0 Fail: 1 (cache program)
I/O 1 Pass/Fail Pass/Fail (N) Pass: 0 Fail: 1
Note: 1. True Ready/Busy shows Ready/Busy status of CPU
(R/B output status is same as I/O7).
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 37 of 91
72h command status in single bank operation
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Program/Erase ECC check Ecc available: 1 Ecc Not available: 0
I/O 5 Erase check Pass: 0 Fail: 1
I/O 4 Program check Pass: 0 Fail: 1
I/O 3 Not Used 0
I/O 2 Not Used 0
I/O 1 Pass/Fail Pass: 0 Fail: 1
Status Register check flow (Multi bank program/erase)
YES
YES
NO
NO
NO
Not 1 bit error
YES
1 bit error
NO
YES
Start
71h Write
read status register
I/O7=1
R/B=1 or
I/O1=0
Error bank check
73-76h Write
read errorstatus register *1
I/O6=1
Read ECC check
Fail
Fail ECC possible
Error bank check end
Program/erase completed
73h:Bank0 error status
74h:Bank1 error status
75h:Bank2 error status
76h:Bank3 error status
Note:1.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 38 of 91
71h Command Status in Multi Bank Operation
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Ready/Busy Ready: 1 Busy: 0
I/O 5 Bank3 Pass/Fail Pass: 0 Fail: 1
I/O 4 Bank2 Pass/Fail Pass: 0 Fail: 1
I/O 3 Bank1 Pass/Fail Pass: 0 Fail: 1
I/O 2 Bank0 Pass/Fail Pass: 0 Fail: 1
I/O 1 All Pass/Fail Pass: 0 Fail: 1
73h, 74h, 75h, 76h Command Status in Multi Bank Operation / Cache program / 2page cache
program
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Program/Erase ECC check Ecc available: 1 Ecc Not available: 0
I/O 5 Erase check Pass: 0 Fail: 1
I/O 4 Program check Pass: 0 Fail: 1
I/O 3 Not Used 0 (Don't care)
I/O 2 Not Used 0 (Don't care)
I/O 1 Pass/Fail Pass: 0 Fail: 1
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 39 of 91
Status Register check flow (Cache program operation)
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
15h
10h
(Last program)
Next bank
Cache program end
Error bank operate end
ECC possible
Cache program error so
substitute operation
Read ECC check
ECC may be possible
FFh Write
cache mode clear
Error bank
check end
ECC impossible ECC may be possible
I/O6=1
73-76h Write
read errorstatus register
check
I/O2-5
71h Write
read status register
I/O6=1
70h Write
read status register
I/O1=0 & I/O2=0
I/O2=0
Next cache program
Cache program
pass
Start
70h Write
read status register
I/O7=1
R/B=1 or
Program command
10h or 15h
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 40 of 91
Status Register (Cache program operation)
The status is output by writing 70h command in cache program / 2 page cache program operation.
I/O1, 2 which shows pass/fail and I/O6, 7 which shows Ready/Busy is output OR data of 2 page address
which programs simultaneously. In other words, if either 2 page address is Busy status, I/O6 or I/O7
outputs “0”. If either 2 page address fails, I/O1 or I/O2 outputs “1”.
It verifies the status writing 70h command in cache program operation and verification of detail error code
which page address fails in program is executed by writing 73h-76h command which output error content
corresponding to bank address.
It can also verify the status writing 70h in 2 page cache program operation and if either 2 page address
which programs simultaneously fails with program error, it outputs fail status. We recommend verifying
page address writing 71h command.
If error occurs in (N-1) page address, error management of (N-1) page (taking the data to replacement page
address) address needs to be executed after program completion of N page address.
70h command status in Cache program / 2page cache program operation
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Tr ue Ready/Busy*1 Ready: 1 Busy: 0
I/O 5 Not Used 0
I/O 4 Not Used 0
I/O 3 Not Used 0
I/O 2 Pass/Fail (N-1) Pass: 0 Fail: 1
I/O 1 Pass/Fail (N) Pass: 0 Fail: 1
Note: 1. True Ready/Busy shows Ready/Busy status of CPU.
71h command status in 2page cache program operation
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Ready/Busy Ready: 1 Busy: 0
I/O 5 Bank3 Pass/Fail (N or N-1) Pass: 0 Fail: 1
I/O 4 Bank2 Pass/Fail (N or N-1) Pass: 0 Fail: 1
I/O 3 Bank1 Pass/Fail (N or N-1) Pass: 0 Fail: 1
I/O 2 Bank0 Pass/Fail (N or N-1) Pass: 0 Fail: 1
I/O 1 Pass/Fail (N or N-1) Pass: 0 Fail: 1
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 41 of 91
73h, 74h, 75h, 76h command status in Cache program / 2page cache program operation
status Output
I/O 8 Write protect Protect: 0 Not Protect: 1
I/O 7 Ready/Busy Ready: 1 Busy: 0
I/O 6 Program/Erase ECC check (N or N-1) Ecc available: 1 Ecc Not available: 0
I/O 5 Erase check (N or N-1) Pass: 0 Fail: 1
I/O 4 Program check (N or N-1) Pass: 0 Fail: 1
I/O 3 Not Used 0
I/O 2 Pass/Fail (N-1) Pass: 0 Fail: 1
I/O 1 Pass/Fail (N) Pass: 0 Fail: 1
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 42 of 91
Reset operation
This device can enter standby mode interrupting each operation mode by writing FFh command (reset
command) during each operation. Page address data during program operation, block data during erase
operation are not guaranteed after completing reset operation.
Reset operation in the Cache program (R/B = Ready, True R/B = Busy)
I/O
R/B
tRSTP
80h 15h FFh
Reset operation in the Cache program (R/B = Ready, True R/B = Busy)
I/O
R/B
tRSTP
≥
tRSTP
80h 15h
RES
Reset operation in the Erase Verify
I/O
R/B
tRSTEV
60h FFh
D2h/D3h
Reset operation in the Erase Verify
≥
tRSTEV
I/O
R/B
RES
tRSTEV
60h D2h/D3h
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 43 of 91
Reset operation in the Program
tRSTP
I/O 80h/85h FFh 00h
R/B
10h/15h
Program start
Program busy
Reset operation in the Erase
t
RSTE
I/O
R/B
Erase start
Erase busy
60h D0h FFh 00h
Reset operation in the Read
t
RSTR
I/O 00h FFh 00h30h/31h/35h
R/B
Read start
Read busy
This device can enter deep standby mode interrupting each operation mode by making RES pin low during
each operation.
Page address data during program operation, block data during erase operation are not guaranteed after
completing reset operation.
Reset operation in the Program
tRSTP
≥
tRSTP
I/O
R/B
RES
Program start
Program busy
80h/85h 10h/15h
*1
Note: 1. Power on sequence.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 44 of 91
Reset operation in the Erase
t
RSTE
≥
t
RSTE
I/O
R/B
RES
Erase start
Erase busy
60h D0h
*
1
Note: 1. Power on sequence.
Reset operation in the Read
t
RSTR
≥
t
RSTR
I/O 30h/31h/35h
R/B
RES
Read start
Read busy
00h
*
1
Note: 1. Power on sequence.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 45 of 91
Usage for WP
WP at the low level prohibits the erase operation and the program operation. When use WP, use it as
follows.
Program operation
t
WWH
t
WWS
I/O 80h/85h
R/B
WP
WE
10h/15h
Prohibition of the Program operation
t
WWH
t
WWS
I/O 80h/85h
R/B
WP
WE
10h/15h
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 46 of 91
Erase operation
t
WWH
t
WWS
I/O 60h
R/B
WP
WE
D0h/D2h/D3h
Prohibition of the Erase operation
t
WWH
t
WWS
I/O 60h
R/B
WP
WE
D0h/D2h/D3h
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 47 of 91
Status Transition
FFH
1st Access
End
Copy Back Program Operation1 (Read)
35H 1st Access SRAM Read Access
Dout
RE
WE Input (Not Status Command)
2nd Access State End
2nd Access
State
Random Output Operation
E0H 2nd Access
State2
WE Input
2nd Access State End
SRAM Read Access
Dout
RE
FFH
1st Access
End
Memory Read Access Operation
30H, 31H
1st Access SRAM Read Access
Dout
RE
WE Input (Not Status Command)
2nd Access State End
2nd Access
State
FFH
Read Address Setup
00H CA1
Address
Input Setup
CA2 RA1 RA2
CA1
Setup
CA2
Setup
RA1
Setup
FFH
Random Output Setup
06H CA1
Address
Input Setup
CA2 RA1 RA2
CA1
Setup
CA2
Setup
RA1
Setup
FFH
Random Output Setup2
05H CA1
Address
Input Setup
CA2
CA1
Setup
FFH
Operation End
Deplete Recovery Operation
38H Deplete
Recovery
CE
PRE=L Deep Standby
(RES=L) Power Off
VCC
Standby
(RES=H,
CE=H) Output
disable
(CE=L)
: BUSY Status
FFH or
2Kbyte Read
PRE=H
Power On &
Power On Read
Reset Operation
Any Operation
State
RES
=H→LDeep Standby
Reset
Operation
Operation
End
Power On
Power On Read
2nd Access State
Dout
RE
ID Read
90H
Any Command Input
ID Read Operation End
ID Read Setup RE RE Device Code
Manufacture Code
Status Register Read
Any State 70H to 76H
Status
Output
RE
7Fh
Status Read
State
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 48 of 91
Cache Program Operation
15H
FFH
Operation End
Program Operation
10H
FFH
Operation End Program
85H
FFH
CA1 CA2 Din is need
at lowest 1Cycle
85H
CA1
Setup
Address
Input Setup
Random Data Input Setup
FFH
CA1
Address
Input Setup
CA2 RA1
CA1
Setup
CA2
Setup
RA1
Setup
RA2
80H
80H
85H
FFH
CA1 CA2 RA1
CA2
Setup
RA1
Setup
RA2
85H
Program Address Setup
Din
WE
Dummy
Busy
11H
RA2/CA2
Setup
Data Input
State
Copy Back Program Operation2 (Program)
Data Recovery Program Setup
: BUSY Status
FFH
Cache Program Standby
True Busy State Program
FFH
Erase Address Setup
Erase Verify Address Setup
60H RA1
Address
Input Setup
RA2
RA1
Setup
FFH
Operation End
Erase Operation
D0H Erase
(Program Data
input available)
FFH
Operation End
Erase Verify Operation
D2H
D3H Erase Verify
Address
Input Setup
CA1
Setup
CE
Standby
(RES=H,
CE=H)
Output
disable
(CE=L)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 49 of 91
Absolute Maximum Ratings
Parameter Symbol Value Unit Notes
VCC voltage VCC −0.6 to +4.6 V 1
VSS voltage VSS 0 V
All input and output voltage Vin, Vout −0.6 to +4.6 V 1, 2
Operating temperature range Topr 0 to + 70 °C
Storage temperature range Tstg −25 to +85 °C 3
Notes: 1. Relative to VSS.
2. Vin/Vout = −2.0 V for pulse width with 20ns or less.
3. Device Storage temperature before programming.
Capacitance
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance Cin 6 pF Vin = 0 V, Ta = +25°C, f = 1 MHz
Output capacitance Cout 10 pF Vout = 0 V, Ta = +25°C, f = 1
MHz
Valid Block (Left side chip)
Parameter Symbol Min Typ Max Unit
Valid Block Number Bank0 NVB0 8029 8192 blocks
Bank1 NVB1 8029 8192 blocks
Bank2 NVB2 8029 8192 blocks
Bank3 NVB3 8029 8192 blocks
Spare Block (Left side chip)
Parameter Symbol Min Typ Max Unit
Spare Block Number Bank0 NSB0 145 blocks
Bank1 NSB1 145 blocks
Bank2 NSB2 145 blocks
Bank3 NSB3 145 blocks
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 50 of 91
Valid Block (Right side chip)
Parameter Symbol Min Typ Max Unit
Valid Block Number Bank0 NVB0 8029 8192 blocks
Bank1 NVB1 8029 8192 blocks
Bank2 NVB2 8029 8192 blocks
Bank3 NVB3 8029 8192 blocks
Spare Block (Right side chip)
Parameter Symbol Min Typ Max Unit
Spare Block Number Bank0 NSB0 145 blocks
Bank1 NSB1 145 blocks
Bank2 NSB2 145 blocks
Bank3 NSB3 145 blocks
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 51 of 91
DC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test conditions
Operating VCC voltage VCC 2.7 3.3 3.6 V
Operating VCC current (1-chip operation) ICC1 10 20 mA tRC = 50ns, CE = ViL, Iout =
0mA
(Read) (2-chip operation) ICC1 20 40 mA
Operating VCC current (1-chip operation) ICC2 15 30 mA tRC = 35ns, CE = ViL, Iout =
0mA
(Read) (2-chip operation) ICC2 30 60 mA
Operating VCC current (1-chip operation) ICC3 10 20 mA Single Bank Operation
(Program) (2-chip operation) ICC3 20 40 mA
Operating VCC current (1-chip operation) ICC4 20 30 mA Multi Bank Operation
(Program) (2-chip operation) ICC4 40 60 mA
Operating VCC current (1-chip operation) ICC5 10 20 mA Single Bank Operation
(Erase) (2-chip operation) ICC5 20 40 mA
Operating VCC current (1-chip operation) ICC6 15 30 mA Multi Bank Operation
(Erase) (2-chip operation) ICC6 30 60 mA
Standby current (1-chip operation) ISB1 1 mA
(TTL) (2-chip operation) ISB1 2 mA
Standby current (1-chip operation) ISB2 10 50 µA
(CMOS) (2-chip operation) ISB2 20 100 µA
Deep standby current (1-chip operation) ISB3 5 µA
(CMOS) (2-chip operation) ISB3 10 µA
Input Leakage Current ILi ±10 µA Vin = 0 to 3.6 V
Output Leakage Current ILo ±10 µA Vin = 0 to 3.6 V
Input voltage ViH 2.0 VCC
+ 0.3 V
V
iL −0.3 0.8 V
Input voltage
(RES, WP, PRE) ViHD V
CC
− 0.2 VCC
+ 0.2 V
V
iLD −0.2 +0.2 V
Output High voltage Level VoH 2.4 V IOH = −400 µA
Output Low voltage Level VOL 0.4 V IOL = 2.1 mA
Output Low Current (R/B) IOL(R/B)5 8 mA VOL = 0.4 V
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 52 of 91
AC Characteristics
(VCC = 2.7 V to 3.6 V, Ta = 0 to +70°C)
Test Conditions
• Input pulse levels: 0.4 to 2.4 V
• Input rise and fall time: 3 ns
• Input and output timing levels: 1.5 V / 1.5 V
• Output load: 1TTL GATE and 50 pF (3.0 V ± 10%)
1TTL GATE and 100 pF (3.3 V ± 10%)
AC Timing Characteristics for Command / Address / Data Input
Parameter Symbol Min Typ Max Unit Note
CLE Setup Time tCLS 0 ns
CLE Hold Time tCLH 9 ns
CE Setup Time tCS 0 ns
CE Hold Time tCH 6 ns
WE Pulse Width tWP 15 ns 1
ALE Setup Time tALS 0 ns
ALE Hold Time tALH 6 ns
Data Setup Time tDS 9 ns
Data Hold Time tDH 9 ns
Write cycle Time tWC 33 ns
WE High Hole Time tWH 12 ns
CE High to WE low setup time tCHWS 5 ns
WE High to CE low hold time tWHCH 5 ns
CE High to RE low setup time tCHRS 5 ns
RE High to CE low hold time tRHCH 5 ns
Note: 1. If tCS is set less than 5 ns, tWP must be minimum 20 ns. Otherwise, tWP is minimum 15 ns.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 53 of 91
AC Timing Characteristics for Operation
Parameter Symbol Min Typ Max Unit Note
Data Transfer from Cell to Register tR 120 µs
ALE to RE Delay (ID Read) tAR1 20 ns
ALE to RE Delay (Read cycle) tAR2 30 ns
CLE to RE Delay (Read cycle) tCLR 6 ns
Ready to RE Low tRR 20 ns
RE Pulse Width tRP 20 ns
WE High to Busy tWB 100 ns
Read cycle time tRC 35 ns
RE Access Time tREA 20 ns
CE Access Time tCEA 25 ns
RE High to Output Hi-Z tRHZ 10 20 ns 1
CE High to Output Hi-Z tCHZ 0 20 ns 1
RE High Hold Time tREH 10 ns
Output Hi-Z to RE Low tIR 0 ns
WE High to RE Low tWHR 50 ns
Device Resetting Time Read tRSTR 20 µs
Program tRSTP 70 µs
Erase tRSTE 400 µs
Erase Verify tRSTEV 30 µs
Device recovery tRSTDR 350 µs
Power on busy Time tPON 200 µs
VCC Setup time to Reset tVRS 100 µs
VCC to Ready tVRDY 100 µs
Reset to Busy tBSY 100 ns
WP setup time to WE High tWWS 15 ns
WP hold time to WE High tWWH 15 ns
CE setup time to Deep standby tCSD 100 ns
Note: 1. The time until it becomes Hi-Z depends on the earliest signal which CE and RE go to high.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 54 of 91
Timing Waveform
Command Latch Cycle
Address Latch Cycle
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 55 of 91
Input Data Latch Cycle
Serial Access Cycle after Read (CLE = L, WE = H, ALE = L)
Note: 1. The time until it becomes Hi-Z depends on the earliest signal which CE and RE go to high.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 56 of 91
Invalid input cycle
I/O1 to
I/O8
V
IH
or V
IL
t
WHCH
(Invalid)
t
CHWS
ALE
CE
WE
CLE
D
IN
Invalid output cycle
VIH or VIL
tRHCH
tCHRS
I/O1 to
I/O8
ALE
CE
RE
CLE
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 57 of 91
Status Read Cycle
Note: 1. 70h: Single Bank operation Status
72h: Single Bank operation Error Status
71h: Multi Bank operation Status
73h: Multi Bank operation / Bank0 Error Status
74h: Multi Bank operation / Bank1 Error Status
75h: Multi Bank operation / Bank2 Error Status
76h: Multi Bank operation / Bank3 Error Status
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 58 of 91
Read Operation
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 59 of 91
Read Operation (Intercepted by CE)
t
CLR
t
WB
00h CA1 CA2 RA1 RA2 30h
D
OUT
N
Busy
Column address
N
Row address
D
OUT
N+1 D
OUT
N+2
t
RC
t
AR2
t
CHZ
t
RR
t
WC
t
R
CLE
ALE
I/Ox
R/B
CE
WE
RE
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 60 of 91
Random Data Output in a Page
CLE
ALE
I/Ox
R/B
CE
WE
RE
t
WB
t
AR2
t
RR
t
WHR
t
CLR
t
R
t
RC
00h CA1 CA2 RA1 RA2 30h 05h CA1 CA2 E0h
DOUT
N
Busy
Column address N Column address MRow address
DOUT
N+1
DOUT
M
DOUT
M+1
*
1
Note: 1. The head column address can be specified over and over.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 61 of 91
Multi Bank Read
tWC
tRtWHR tWHR
00h CA1 CA2 RA1 RA2 31h 06h CA1 CA2 05h CA1 CA2RA1 RA2 E0h E0h
DOUT
J
DOUT
K
DOUT
L
DOUT
M
Column
address
Row
address
Column
address
Column
address
Row
address
*1
*3
*2
CLE
ALE
I/Ox
R/B
CE
WE
RE
Notes: 1. A maximum 4 bank from Bank0 to Bank3 can be repeated.
2. Read out specified bank.
3. It is repeated over and over within the same page setup.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 62 of 91
Page program Operation
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 63 of 91
Page Program Operation with Random Data Input
CLE
ALE
I/Ox
R/B
CE
WE
RE
Busy
CA1 CA2 CA1 CA2
RA1 RA2
80h 85h 10h 70h I/O1
DIN
N
DIN
M
Column
address
Serial
input
Data
command
Row
address
Column
address
Serial
input
Serial input Serial input
Data
command
DIN
K
DIN
J
t
WC
t
WC
t
WC
t
WB
t
PROG
*
1
Note: 1. It is repeated over and over within the same page setup.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 64 of 91
Multi Bank Program (1/2)
Note: 1. A maximum 4 bank from Bank0 to Bank3 can be repeated.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 65 of 91
Multi Bank Program (2/2)
CLE
ALE
I/Ox
R/B
CE
WE
RE
t
WB
t
DBSY
t
WB
t
PROG
Bank3Bank2
DIN
N
DIN
M
11h
DIN
N
DIN
M
10h 71h I/O1
80h CA1 CA2 RA1 RA2
Column
address
Row
address Program data
(1)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 66 of 91
Multi Bank Program Operation with Random Data Input (1/2)
t
WB
t
DBSY
DIN
K
DIN
J
11h
DIN
N
DIN
M
t
WC
80h CA1 CA2 85h CA1 CA2RA1 RA2 80h CA1 CA2 RA1 RA2
Column
address
Column
address
Row
address
Column
address
Row
address
Program data
*
1
(1)
last bank
CLE
ALE
I/Ox
R/B
CE
WE
RE
Note: 1. Maximum three times repeatable.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 67 of 91
Multi Bank Program Operation with Random Data Input (2/2)
Note: 1. Maximum three times repeatable.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 68 of 91
Cache Program
CLE
ALE
I/Ox
R/B
CE
WE
RE
Column
address
Program
command
(Dummy)
Row
address Program data Column
address
Program
command
(True)
Row
address Program data
last page
*
2
t
WC
t
WC
t
WB
t
CBSY
t
WB
t
CPROG
80h CA1 CA2 RA1 RA2 80h CA1 CA2 RA1 RA2
15h
D
IN
M
D
IN
N
10h
D
IN
M
D
IN
N
70h I/O
*
1
Notes: 1. There is no limitation in the number of Page address which can specify consecutively.
2. Don’t specify a Page address inside the same bank consecutively.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 69 of 91
2 Page Cache Program (1/2)
CLE
ALE
I/Ox
R/B
CE
WE
RE
t
WC
t
WC
t
WC
t
WB
t
CBSY
Column
address
Program
command
(Dummy)
Row
address Program data Column
address
Program
command
(Dummy)
Row
address
Column
address
Row
address
Program data
80h CA1 CA2 RA1 RA2 80h CA1 CA2 RA1 RA2 80h CA1 CA2 RA1 RA2
11h
D
IN
M
D
IN
N
15h
D
IN
M’
D
IN
N’
1st page 2nd page 3rd page
*
1
t
WB
t
DBSY
(1)
Note: 1. Don’t specify a Page address inside the same bank consecutively.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 70 of 91
2 Page Cache Program (2/2)
CLE
ALE
I/Ox
R/B
CE
WE
RE
t
WC
t
WB
t
CPROG
Column
address
Program
command
(Dummy)
Row
address Program data Column
address
Program
command
(True)
Row
address Program data
80h CA1 CA2 RA1 RA2 80h CA1 CA2 RA1 RA2
11h
D
IN
M’’
D
IN
N’’
10h 70h I/O
D
IN
M’’’
D
IN
N’’’
t
WB
t
DBSY
t
CBSY
3rd page 4th page2nd page
(1)
t
WC
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 71 of 91
Copy Back Program Operation
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 72 of 91
Copy Back Program with Data Output (1/2)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 73 of 91
Copy Back Program with Data Output (2/2)
Note: 1. Updating copy data
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 74 of 91
Multi Bank Copy Back Program (1/3)
CLE
ALE
I/Ox
R/B
CE
WE
RE
t
WC
00h CA1 CA2 RA1 RA2 00h 35hCA1 CA2 RA1 RA2 06h E0h E0hCA1 CA2 05h CA1 CA2RA1 RA2
(1)
*
3
*
4
*
1
*
2
t
WB
t
WHR
t
WHR
t
R
D
OUT
J
D
OUT
K
D
OUT
M
D
OUT
N
Column
address
Row
address
Column
address
Row
address
Notes: 1. Specifying the address of a source of copy.
2. Specifying the address of a source of copy.
3. A maximum 4 bank can be specified.
4. Read out the data of a source of copy.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 75 of 91
Multi Bank Copy Back Program (2/3)
Note: 1. Updating a source data which did Copy Back Read.
Specifying Page address for post-copy.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 76 of 91
Multi Bank Copy Back Program (3/3)
CLE
ALE
I/Ox
R/B
CE
WE
RE
(2)
*
1
85h 10h 71h I/O111h CA1 CA2 RA1 RA2
D
IN
U
D
IN
V
85h CA1 CA2
D
IN
W
D
IN
X
Column
address
Column
address
Row
address Program data
t
WB
t
PROG
t
DBSY
Note: 1. Updating a source data which did Copy Back Read.
Specifying Page address for post-copy.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 77 of 91
Program Data Input in Erase busy
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 78 of 91
Block Erase Operation
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 79 of 91
Multi Bank Block Erase
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 80 of 91
Page mode Erase Verify
Block mode Erase Verify
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 81 of 91
Multi Bank Page mode Erase verify
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 82 of 91
Multi Bank Block mode Erase verify
Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 83 of 91
Read ID Operation
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 84 of 91
Power on Auto Read
CLE
ALE
V
CC
WP
PRE
R/B
I/O
CE
WE
RE
RES
t
VRDY
t
VRS
t
VRS
t
CEA
V
CC
= 2.7 V
t
PON
+t
R
t
BSY
t
RR
t
REA
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 85 of 91
Power on and off sequence
2.7 V
don’t
care
2.7 V
t
VRS
t
VRS
t
BSY
t
PON
t
VRDY
don’t
care
don’t
care
invalid
operation
V
CC
PRE
CLE, ALE
R/B
CE, WE, RE
WP
RES
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 86 of 91
Deep Standby Mode
RES
R/B
CE
RES
R/B
CE
tCSD
tRST
tRST min
tVRS
Standby state Standby stateDeep standby state Power on state
Standby state
Deep standby state
Operation state Power on state
tBSY
100 ns min
tPON
tBSY tPON
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 87 of 91
Notes on usage
1. Prohibition of undefined command input
The commands listed in the command definition can only be used in this device. It is prohibited to issue a
command that is not defined in the list. If an undefined command is issued, the data held in the device may
be lost.
Only the commands defined can be issued, in only defined timings. Otherwise, illegal operations may
occur.
2. Limitation of command input in the busy state
In the busy state, following two commands are acceptable. Do not issue any other command except below
two commands.
• Status read 70h, 71h, 72h, 73h, 74h, 75h, 76h
• Read command FFh
3. Commands limitation after commands (80h, 85h) are input at the first cycle of a program
After commands (80h, 85h) are input at the first cycle of a program, only the second cycle of the program
commands (10h, 11h, 15h) and reset command (FFh) can be used. After a command 80h or 85h is input,
the commands are prohibit.
4. R/B (Ready/busy) pin handing
R/B pins are open-drain output pins, and they should be pulled up to VCC with a resistances (more than
2kΩ).
5. Notes on RE signal
If the RE clock is sent before the address is input, the internal read operation may start unintentionally.
Be sure to send the RE clock after the address is input.
If the RE clock is input after the data of the last address is read during the read operation, invalid data is
output.
6. Notes on Address taking
This product takes the address data by four cycles, and when five cycles or more are input, the address data
since the fifth cycle becomes invalid.
7. Deep standby mode
During command waiting or standby state, when RES pin goes to low, the device transfers to deep standby
state.
When RES goes to high, the device returns form the deep standby state.
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 88 of 91
During command execution, going RES low stops command operation. If RES goes to low during
erase/program/read operation, the command operation is forced to terminate and the applied page data is
not guaranteed.
8. Notes on the power supply down
Please do not turn off a power supply in erase busy operation.
It is required to take the following measures on system side for expected power down.
When the power down is recognized to have occurred during erase busy operation, device recovery mode
after the power on. The data in other blocks are protected, though the data in the applied block is invalid,
by doing this.
I/O
R/B
00h CA1 CA2 RA2 38h
tDRC
Busy
RA1 00h CA1 CA2 RA4 38hRA3
Address input
tDRC
Busy
Notes: 1. Please input any address for CA1 and CA2. Input an arbitrary address to CA1 and CA2.
2. The address input is necessary for RA1 and RA2 and RA4. Input 00h respectively.
For RA3, input 04h.
3. Busy time (tDRC) is as follows. When the data protect operation is unnecessary, end at the typ
time in normal operation. When the data protect operation is executed, the time of 100ms or
less is needed.
4. This protect operation is pause to input FF command or RES = L. In case of this pause, the
protect operation is not guaranteed.
typ max
tDRC 890µs 100ms
I/O
R/B
RA200h CA1 CA2 RA1 38h FFh
tRSTDR
=350µs max
I/O
R/B
RES
RA200h CA1 CA2 RA1 38h
tRSTDR
=350µs max
350µs min
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 89 of 91
9. Unusable Block
Initially, the HN29V2G74 includes unusable blocks. The usable blocks must be distinguished from the
usable blocks bye the system as follows.
1. Confirm the blocks which cannot be used after mounting on the system. The following data is written
on each page of the blocks which can be used. One block is composed of two pages, and following
data is written in both pages co mmonly (Refer to “The Unusable Blocks Indication Flow”).
Initial Data of Usable Pages
Column address 0h to 81Fh 820h 821h 822h 823h 824h 825h 826h to 83Fh
Data FFh 1Ch 71h C7h 1Ch 71h C7h FFh
2. Do not Program and Erase to the partial invalid blocks by the system.
NO
YES
YES
YES
YES
NO
NO
NO
m = 0
m = m + 1
k = k + 1
k = 0
Page number = (8k + m + n)
Bad block
Check data
Check data
Start
END
m = 4
k = 8192
Notes: 1. Refer to table "Initial data of usable pages".
2. Bad pages are installed in system.
n = 0
n = n + 4
*
1
*
2
*
1
The Unusable Blocks Indication Flow (per 1 chip)
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 90 of 91
10. Measures for don’t care in timing waveforms for Program Data Input in Erase Busy
The timing waveforms in any mode is specified “Don’t care”, during CE = H other control signals become
“Don’t care”. When CE = H, specify ALE and CLE = H, WE and RE = H.
11. Status read during read mode (data output)
Input the status mode reset command (7Fh), when the device returns to the read mode, after the status read
is executed the status read command (70h), during the busy status in the read mode.
12. Status read during read mode (data output)
The memory data cannot be output only by the RE clock, after the transition from the status read mode to
the read mode by the 7Fh, when the device is set to the status read mode during the data output, in the read
mode.
In this case, 06h command, column address, page address and E0h command must be input to the read
operation.
13. Status read in Multibank program mode
When execute status read during a dummy busy period after input command 11h in multibank program,
judge only Ready/Busy.
I/O
R/B
Judge only R/B
tDBSY tPROG
80h 11h 71h
Col.
Add.
Row
Add. Data Status
Data 80h 10h 71h
Col.
Add.
Row
Add. Data Status
Data
HN29V2G74WT-30
Rev.2.00, Jul. 21.2004, page 91 of 91
Package Dimensions
HN29V2G74WT-30 (TFP-48DBV)
0.08
0.08
M
0.50
12.00
17.00 ± 0.20
0.70 Max
15.40
0˚ – 8˚
48
124
25
12.10 Max
0.45 Max
*0.12 ± 0.055
0.50 ± 0.10
0.80
0.18 ± 0.06
0.10 ± 0.030
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-48DB,TFP-48DBV
Conforms
Conforms
0.26 g
*Dimension including the plating thickness
Base material dimension
Unit: mm
+ 0.07
– 0.03
0.80
+ 0.07
– 0.03
*0.20
Revision History HN29V2G74WT-30 Data Sheet
Contents of Modification Rev. Date
Page Description
0.01 Feb. 20, 2004 Initial issue
1.00 Jun. 18, 2004
1, 53
9
88
Deletion of Preliminary
VCC: 3.0 V/3.6 V to 2.7 V/3.6 V
tR Max (1st access time): 100µs to120µs
Program/Erase Characteristics
tPROG Max: 1ms to 2.4 ms
tCPROG Max: 2ms to 4.8 ms
tCBSY Max: 1000µs to 2400 µs
tBERS Max: 2.4ms to 20 ms
Notes on usage: Change of 8. Notes: 2., 4.
Change of description
“The address input is necessary for RA1 and RA2. Input 00h
respectively.” to “The address input is necessary for RA1 and RA2 and
RA4. Input 00h respectively.”
“For RA3 and RA4, input 04h respectively.” to “For RA3, input 04h.”
“Before confirmation of this command, the protect operation is not
guaranteed.” to “In case of this pause, the protect operation is not
guaranteed.”
2.00 Jul. 21, 2004 53 AC Characteristics
tVRS Min: 20µs to 100µs
tVRDY Max: 20µs to 100µs
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
RENESAS SALES OFFICES
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0
