LTC2165/LTC2164/LTC2163
1
216543f
Typical applicaTion
DescripTion
16-Bit, 125/105/80Msps
Low Power ADCs
The LTC
®
2165/LTC2164/LTC2163 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 76.8dB SNR and 90dB spurious free dynamic
range (SFDR). Ultralow jitter of 0.07psRMS allows unders-
ampling of IF frequencies with excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
2-Tone FFT, fIN = 70MHz and 69MHz
FeaTures
applicaTions
n 76.8dB SNR
n 90dB SFDR
n Low Power: 194mW/163mW/108mW
n Single 1.8V Supply
n CMOS, DDR CMOS, or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 550MHz Full Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n 48-Pin (7mm × 7mm) QFN Package
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multichannel Data Acquisition
n Nondestructive Testing
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
2165 TA01b
S/H
OUTPUT
DRIVERS
16-BIT
ADC CORE
CLOCK
CONTROL
D15
•
•
•
D0
125MHz
CLOCK
ANALOG
INPUT
2165 TA01a
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
GND OGND
LTC2165/LTC2164/LTC2163
2
216543f
absoluTe MaxiMuM raTings
Supply Voltages (VDD, OVDD) .......................–0.3V to 2V
Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE)
(Note 3) ................................... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK)
(Note 4) ................................................ –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
(Notes 1, 2)
FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
49
GND
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
VCM 1
AIN+ 2
AIN– 3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
VDD 12
36 D11
35 D10
34 D9
33 D8
32 OVDD
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D7
27 D6
26 D5
25 D4
48 VDD
47 VDD
46 SENSE
45 VREF
44 SDO
43 GND
42 OF
41 DNC
40 D15
39 D14
38 D13
37 D12
VDD 13
GND 14
ENC+ 15
ENC– 16
CS 17
SCK 18
SDI 19
GND 20
D0 21
D1 22
D2 23
D3 24
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
49
GND
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
VCM 1
AIN+ 2
AIN– 3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
VDD 12
36 D10_11
35 DNC
34 D8_9
33 DNC
32 OVDD
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D6_7
27 DNC
26 D4_5
25 DNC
48 VDD
47 VDD
46 SENSE
45 VREF
44 SDO
43 GND
42 OF
41 DNC
40 D14_15
39 DNC
38 D12_13
37 DNC
VDD 13
GND 14
ENC+ 15
ENC– 16
CS 17
SCK 18
SDI 19
GND 20
DNC 21
D0_1 22
DNC 23
D2_3 24
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
pin conFiguraTion
Digital Output Voltage ................–0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2165C, LTC2164C, LTC2163C............. 0°C to 70°C
LTC2165I, LTC2164I, LTC2163I ............ –40°C to 85°C
Storage Temperature Range ...................–65°C to 150°C
LTC2165/LTC2164/LTC2163
3
216543f
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2165CUK#PBF LTC2165CUK#TRPBF LTC2165UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2165IUK#PBF LTC2165IUK#TRPBF LTC2165UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2164CUK#PBF LTC2164CUK#TRPBF LTC2164UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2164IUK#PBF LTC2164IUK#TRPBF LTC2164UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2163CUK#PBF LTC2163CUK#TRPBF LTC2163UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2163IUK#PBF LTC2163IUK#TRPBF LTC2163UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
pin conFiguraTion
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
49
GND
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
VCM 1
AIN+ 2
AIN– 3
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
PAR/SER 9
GND 10
GND 11
VDD 12
36 D10_11+
35 D10_11–
34 D8_9+
33 D8_9–
32 OVDD
31 OGND
30 CLKOUT+
29 CLKOUT–
28 D6_7+
27 D6_7–
26 D4_5+
25 D4_5–
48 VDD
47 VDD
46 SENSE
45 VREF
44 SDO
43 GND
42 OF+
41 OF–
40 D14_15+
39 D14_15–
38 D12_13+
37 D12_13–
VDD 13
GND 14
ENC+ 15
ENC– 16
CS 17
SCK 18
SDI 19
GND 20
D0_1– 21
D0_1+ 22
D2_3– 23
D2_3+ 24
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
LTC2165/LTC2164/LTC2163
4
216543f
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
converTer characTerisTics
PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l16 16 16 Bits
Integral Linearity Error Differential Analog Input
(Note 6)
l–6 ±2 6 –6 ±2 6 –6 ±2 6 LSB
Differential Linearity Error Differential Analog Input l–0.9 ±0.5 0.9 –0.9 ±0.5 0.9 –0.9 ±0.5 0.9 LSB
Offset Error (Note 7) l–7 ±1.5 7 –7 ±1.5 7 –7 ±1.5 7 mV
Gain Error Internal Reference
External Reference
l
–1.8
±1.5
–0.5
0.7
–1.8
±1.5
–0.5
0.7
–1.8
±1.5
–0.5
0.7
%FS
%FS
Offset Drift ±10 ±10 ±10 µV/°C
Full-Scale Drift Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise External Reference 3.4 3.5 3.2 LSBRMS
analog inpuT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l0.7 VCM 1.25 V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V
IINCM Analog Input Common Mode Current Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
200
170
130
µA
µA
µA
IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l–1 1 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA
IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode
Differential Encode
0.07
0.09
psRMS
psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full Power Bandwidth Figure 6 Test Circuit 550 MHz
DynaMic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input
70MHz Input
140MHz Input
l
75
76.8
76.6
76.3
75
76.7
76.5
76
75.3
77.1
76.9
76.4
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
2nd Harmonic
5MHz Input
70MHz Input
140MHz Input
l
80
90
89
84
80
90
89
84
82
90
89
84
dBFS
dBFS
dBFS
SFDR Spurious Free Dynamic Range
3rd Harmonic
5MHz Input
70MHz Input
140MHz Input
l
82
90
89
84
81
90
89
84
82
90
89
84
dBFS
dBFS
dBFS
LTC2165/LTC2164/LTC2163
5
216543f
DynaMic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SFDR Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
70MHz Input
140MHz Input
l
88
95
95
95
89
95
95
95
90
95
95
95
dBFS
dBFS
dBFS
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l
74
76.6
76.2
75.1
74.1
76.5
76.1
75
74.6
76.9
76.5
75.3
dBFS
dBFS
dBFS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.5•VDD – 25mV 0.5•VDD 0.5•VDD + 25mV V
VCM Output Temperature Drift ±25 ppm/°C
VCM Output Resistance –600µA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±25 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
inTernal reFerence characTerisTics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
DigiTal inpuTs anD ouTpuTs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
DIFFERENTIAL ENCODE MODE (ENC– NOT TIED TO GND)
VID Differential Input Voltage (Note 8) l0.2 V
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)
l
1.1
1.2
1.6
V
V
VIN Input Voltage Range ENC+, ENC– to GND l0.2 3.6 V
RIN Input Resistance (See Figure 10) 10 kΩ
CIN Input Capacitance (Note 8) 3.5 pF
SINGLE-ENDED ENCODE MODE (ENC– TIED TO GND)
VIH High Level Input Voltage VDD = 1.8V l1.2 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
VIN Input Voltage Range ENC+ to GND l0 3.6 V
RIN Input Resistance (See Figure 11) 30 kΩ
CIN Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD = 1.8V l1.3 V
VIL Low Level Input Voltage VDD = 1.8V l0.6 V
IIN Input Current VIN = 0V to 3.6V l–10 10 µA
LTC2165/LTC2164/LTC2163
6
216543f
DigiTal inpuTs anD ouTpuTs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA
COUT Output Capacitance (Note 8) 3 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH High Level Output Voltage IO = –500µA l1.750 1.790 V
VOL Low Level Output Voltage IO = 500µA l0.010 0.050 V
OVDD = 1.5V
VOH High Level Output Voltage IO = –500µA 1.488 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
OVDD = 1.2V
VOH High Level Output Voltage IO = –500µA 1.185 V
VOL Low Level Output Voltage IO = 500µA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l247 350
175
454 mV
mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l1.125 1.250
1.250
1.375 V
V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
SYMBOL PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V
IVDD Analog Supply Current DC Input
Sine Wave Input
l108
110
123 91
92
103 60
61
69 mA
mA
IOVDD Digital Supply Current Sine Wave Input, OVDD =1.2V 5 4 3 mA
PDISS Power Dissipation DC Input
Sine Wave Input, OVDD =1.2V
l194
204
222 163
170
186 108
113
125 mW
mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current Sine Wave Input 1.75mA Mode
3.5mA Mode
l
112
113
127
94
95
107
62
63
72
mA
mA
IOVDD Digital Supply Current
(OVDD = 1.8V)
Sine Wave Input 1.75mA Mode
3.5mA Mode
l
22
42
47
22
42
47
22
42
46
mA
mA
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2165/LTC2164/LTC2163
7
216543f
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
PDISS Power Dissipation Sine Wave Input, 1.75mA Mode
Sine Wave Input, 3.5mA Mode
l
241
279
314
209
247
278
151
189
213
mW
mW
All Output Modes
PSLEEP Sleep Mode Power 1 1 1 mW
PNAP Nap Mode Power 10 10 10 mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No Increase for Nap or Sleep Modes)
20 20 20 mW
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
TiMing characTerisTics
SYMBOL PARAMETER CONDITIONS
LTC2165 LTC2164 LTC2163
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 10) l1 125 1 105 1 80 MHz
tLENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
tHENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2
4
4
500
500
4.52
2
4.76
4.76
500
500
5.93
2
6.25
6.25
500
500
ns
ns
tAP Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.7 3.1 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.4 2.6 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
DIGITAL DATA OUTPUTS (LVDS MODE)
tDENC to Data Delay CL = 5pF (Note 8) l1.1 1.8 3.2 ns
tCENC to CLKOUT Delay CL = 5pF (Note 8) l1 1.5 2.7 ns
tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l0 0.3 0.6 ns
Pipeline Latency 6.5 Cycles
SPI PORT TIMING (Note 8)
tSCK SCK Period Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
tSCS to SCK Setup Time l5 ns
tHSCK to CS Setup Time l5 ns
tDS SDI Setup Time l5 ns
tDH SDI Hold Time l5 ns
tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l125 ns
LTC2165/LTC2164/LTC2163
8
216543f
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2165), 105MHz
(LTC2164), or 80MHz (LTC2163), LVDS outputs, differential ENC+/ENC–
= 2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2165), 105MHz (LTC2164), or
80MHz (LTC2163), CMOS outputs, ENC+ = single-ended 1.8V square wave,
ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on each
digital output unless otherwise noted.
Note 10: Recommended operating conditions.
TiMing DiagraMs
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tH
tD
tC
tL
N – 6 N – 5 N – 4 N – 3 N – 2
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
CLKOUT+
CLKOUT–
D0–D15, OF
2165 TD01
LTC2165/LTC2164/LTC2163
9
216543f
Double Data Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
TiMing DiagraMs
tH
tD
•
•
•
tD
tCtC
tL
OFN-6 OFN-5 OFN-4 OFN-3
D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3
D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
D0_1
D14_15
CLKOUT+
CLKOUT–
OF
2165 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
tH
tDtD
tCtC
tL
OFN-6 OFN-5 OFN-4 OFN-3
D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3
D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
D0_1+
D0_1–
D14_15+
D14_15–
CLKOUT+
CLKOUT–
OF+
OF–
2165 TD03
•
•
•
LTC2165/LTC2164/LTC2163
10
216543f
TiMing DiagraMs
A6
tStDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
2165 TD04
CS
SCK
SDI R/W
SDO
HIGH IMPEDANCE
LTC2165/LTC2164/LTC2163
11
216543f
LTC2165 Integral
Non-Linearity (INL)
LTC2165 Differential
Non-Linearity (DNL)
LTC2165 64k Point FFT,
fIN = 5MHz, –1dBFS, 125Msps
Typical perForMance characTerisTics
LTC2165 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
125Msps LTC2165 Shorted Input Histogram
LTC2165 SNR vs Input Frequency,
–1dBFS, 2V Range, 125Msps
LTC2165 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
LTC2165 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
LTC2165 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
OUTPUT CODE
0
–4.0
–3.0
–2.0
–1.0
INL ERROR (LSB)
0
1.0
4.0
3.0
2.0
16384 32768 49152 65536
2165 G01
OUTPUT CODE
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
2165 G02
016384 32768 49152 65536
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
2165 G03
010 20 30 40 50 60
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
2165 G04
10 20 30 40 50 60
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
2165 G05
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
2165 G06
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
2165 G07
OUTPUT CODE
32750
1000
0
3000
2000
COUNT
4000
5000
10000
9000
8000
7000
6000
32756 32762 32768 32774
2165 G08
INPUT FREQUENCY (MHz)
0
72
71
70
78
77
76
75
74
73
SNR (dBFS)
50 100 150 200 250 300
2165 G09
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
LTC2165/LTC2164/LTC2163
12
216543f
Typical perForMance characTerisTics
LTC2164 Integral Non-Linearity
(INL)
LTC2164 Differential
Non-Linearity (DNL)
LTC2164 64k Point FFT,
fIN = 5MHz, –1dBFS, 105Msps
LTC2165 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS,
5pF on Each Data Output
LTC2165 SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2165 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 125Msps
LTC2165: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
LTC2165 IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2165 SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
SAMPLE RATE (Msps)
0
80
IVDD (mA)
90
100
120
110
25 50 75 100 125
2165 G13
CMOS OUTPUTS
3.5mA LVDS OUTPUTS
SAMPLE RATE (Msps)
0
0
IOVDD (mA)
10
20
30
50
40
25 50 75 100 125
2165 G14
3.5mA LVDS
1.8V CMOS
1.2V CMOS
1.75mA LVDS
SENSE PIN (V)
0.6
71
70
72
73
78
77
76
75
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
2165 G15
OUTPUT CODE
0
–4.0
–3.0
–2.0
–1.0
INL ERROR (LSB)
0
1.0
4.0
3.0
2.0
16384 32768 49152 65536
2165 G16
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
2165 G17
OUTPUT CODE
016384 32768 49152 65536
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
2165 G18
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G10
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G11
2ND
3RD
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
80
70
SFDR (dBc AND dBFS)
90
100
130
120
110
–70 –60 –50 –40 –30 –20 –10 0
2165 G12
dBFS
dBc
LTC2165/LTC2164/LTC2163
13
216543f
LTC2164 64k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
Typical perForMance characTerisTics
LTC2164 Shorted Input Histogram
LTC2164 SNR vs Input Frequency,
–1dBFS, 2V Range, 105Msps
LTC2164 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 105Msps
LTC2164 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
LTC2164 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
LTC2164 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
105Msps
LTC2164: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
LTC2164 SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
2165 G19
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
2165 G20
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
2165 G21
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
2165 G22
OUTPUT CODE
32790
1000
0
3000
2000
COUNT
4000
5000
10000
9000
8000
7000
6000
32796 32802 32808 32814
2165 G23
INPUT FREQUENCY (MHz)
0
72
71
70
78
77
76
75
74
73
SNR (dBFS)
50 100 150 200 250 300
2165 G24
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G25
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G26
2ND
3RD
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
80
70
SFDR (dBc AND dBFS)
90
100
130
120
110
–70 –60 –50 –40 –30 –20 –10 0
2165 G27
dBFS
dBc
LTC2165/LTC2164/LTC2163
14
216543f
Typical perForMance characTerisTics
LTC2163 64k Point FFT, fIN = 5MHz,
–1dBFS, 80Msps
LTC2163 64k Point FFT,
fIN = 30MHz, –1dBFS, 80Msps
LTC2163 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
LTC2163 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
LTC2164 SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2163 Integral Non-Linearity
(INL)
LTC2163 Differential
Non-Linearity (DNL)
LTC2164 IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2164 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS,
5pF on Each Data Output
SAMPLE RATE (Msps)
0
60
IVDD (mA)
70
80
100
90
25 50 75 100
2165 G28
CMOS OUTPUTS
3.5mA LVDS OUTPUTS
1.2V CMOS
SAMPLE RATE (Msps)
0
0
IOVDD (mA)
10
20
30
50
40
25 50 75 100
2165 G29
3.5mA LVDS
1.8V CMOS
1.75mA LVDS
SENSE PIN (V)
0.6
71
70
72
73
78
77
76
75
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
2165 G30
OUTPUT CODE
0
–4.0
–3.0
–2.0
–1.0
INL ERROR (LSB)
0
1.0
4.0
3.0
2.0
16384 32768 49152 65536
2165 G31
–1.0
–0.4
–0.2
–0.6
–0.8
DNL ERROR (LSB)
0
0.4
0.2
0.6
0.8
1.0
2165 G32
OUTPUT CODE
016384 32768 49152 65536
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
2165 G33
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
2165 G34
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
2165 G35
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
2165 G36
LTC2165/LTC2164/LTC2163
15
216543f
LTC2163 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
80Msps LTC2163 Shorted Input Histogram
Typical perForMance characTerisTics
LTC2163 IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2163 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2163 SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2163 SNR vs Input Frequency,
–1dBFS, 2V Range
LTC2163 2nd or 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 80Msps
LTC2163 SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
LTC2163 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
80Msps, 1V Range
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40
2165 G37
OUTPUT CODE
32817
1000
0
3000
2000
COUNT
4000
5000
10000
9000
8000
7000
6000
32823 32829 32835 32841
2165 G38
INPUT FREQUENCY (MHz)
0
72
71
70
78
77
76
75
74
73
SNR (dBFS)
50 100 150 200 250 300
2165 G39
DIFFERENTIAL
ENCODE
SINGLE-ENDED
ENCODE
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G40
2ND
3RD
0 50 100 150 200 250 300
INPUT FREQUENCY (MHz)
90
85
80
75
70
65
100
95
2ND AND 3RD HARMONIC (dBFS)
2165 G41
2ND
3RD
INPUT LEVEL (dBFS)
–80
60
50
40
30
20
80
70
SFDR (dBc AND dBFS)
90
100
130
120
110
–70 –60 –50 –40 –30 –20 –10 0
2165 G27
dBFS
dBc
SAMPLE RATE (Msps)
0
40
IVDD (mA)
50
70
60
20 40 60 80
2165 G43
CMOS OUTPUTS
3.5mA LVDS OUTPUTS
SAMPLE RATE (Msps)
0
0
IOVDD (mA)
10
20
30
50
40
20 40 60 80
2165 G44
3.5mA LVDS
1.2V CMOS
1.75mA LVDS
1.8V CMOS
SENSE PIN (V)
0.6
71
70
72
73
78
77
76
75
74
SNR (dBFS)
0.7 0.8 0.9 1.1 1.2 1.31
2165 G45
LTC2165/LTC2164/LTC2163
16
216543f
pin FuncTions
(Pins That Are the Same for All Digital Output Modes)
VCM (Pin 1): Common Mode Bias Output. Nominally
equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
AIN+ (Pin 2): Positive Differential Analog Input.
AIN– (Pin 3): Negative Differential Analog Input.
GND (Pins 4, 10, 11, 14, 20, 43, Exposed Pad Pin 49):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
REFH (Pins 5, 7): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 6, 8): ADC Low Reference. See the Applications
Information section for recommended bypassing circuits
for REFH and REFL.
PAR/SER (Pin 9): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or VDD and not be driven by a logic signal.
VDD (Pins 12, 13, 47, 48): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 15): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 16): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 17): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD),
CS controls the clock duty cycle stabilizer (see Table 2).
CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 18): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK controls the digital output mode
(see Table 2). SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 19): Serial Interface Data Input. In serial program-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registers on the rising edge of SCK. In the parallel program-
ming mode (PAR/SER = VDD), SDI can be used together
with SDO to power down the part (Table 2). SDI can be
driven with 1.8V to 3.3V logic.
OGND (Pin 31): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 32): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 44): Serial Interface Data Output. In serial pro-
gramming mode, (PAR/SER = 0V), SDO is the optional
serial interface data output. Data on SDO is read back
from the mode control registers and can be latched on
the falling edge of SCK. SDO is an open-drain NMOS
output that requires an external 2kΩ pull-up resistor to
1.8V – 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected. In the parallel programming
mode (PAR/SER = VDD), SDO can be used together with
SDI to power down the part (Table 2). When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1kΩ series resistor.
VREF (Pin 45): Reference Voltage Output. Bypass to
ground with a 2.2µF ceramic capacitor. The output voltage
is nominally 1.25V.
SENSE (Pin 46): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
LTC2165/LTC2164/LTC2163
17
216543f
pin FuncTions
FULL RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D15 (Pins 21-28, 33-40): Digital Outputs. D15 is
the MSB.
CLKOUT– (Pin 29): Inverted version of CLKOUT+.
CLKOUT+ (Pin 30): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 41): Do not connect this pin.
OF (Pin 42): Overflow/Underflow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D14_15 (Pins 22, 24, 26, 28, 34, 36, 38, 40):
Double Data Rate Digital Outputs. Two data bits are mul-
tiplexed onto each output pin. The even data bits (D0,
D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13,
D15) appear when CLKOUT+ is high.
DNC (Pins 21, 23, 25, 27, 33, 35, 37, 39, 41): Do not
connect these pins.
CLKOUT– (Pin 29): Inverted version of CLKOUT+.
CLKOUT+ (Pin 30): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
OF (Pin 42): Overflow/Underflow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D14_15–/D14_15+ (Pins 21/22, 23/24,
25/26, 27/28, 33/34, 35/36, 37/38, 39/40): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each differential output pair. The even data bits (D0, D2,
D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low.
The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)
appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 41/42): Overflow/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
LTC2165/LTC2164/LTC2163
18
216543f
FuncTional block DiagraM
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2µF
0.1µF 0.1µF
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
ENC+
REFH REFL
ENC–SDOCS
OGND
OF
OVDD
D15
CLKOUT–
CLKOUT+
D0
2165 BD
SENSE
VREF
2.2µF
VCM
0.1µF
VDD/2
MODE
CONTROL
REGISTERS
OUTPUT
DRIVERS
SCKPAR/SER SDI
•
•
•
REFL INTERNAL CLOCK SIGNALSREFH
S/H
ANALOG
INPUT
16-BIT
ADC CORE
CORRECTION
LOGIC
VDD
GND
LTC2165/LTC2164/LTC2163
19
216543f
CONVERTER OPERATION
The LTC2165/LTC2164/LTC2163 are low power, 16-bit,
125/105/80Msps A/D converters that are powered by a
single 1.8V supply. The analog inputs should be driven
differentially. The encode input can be driven differentially
or single-ended for lower power consumption. The digital
outputs can be CMOS, double data rate CMOS (to halve
the number of output lines), or double data rate LVDS
(to reduce digital noise in the system). Many additional
features can be chosen by programming the mode control
registers through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range,
the inputs should swing from VCM – 0.5V to VCM + 0.5V.
There should be 180° phase difference between the inputs.
Single-Ended Input
For applications less sensitive to harmonic distortion, the AIN+
input can be driven single-ended with a 1VP-P signal centered
around VCM. The AIN– input should be connected to VCM and
applicaTions inForMaTion
Figure 2. Equivalent Input Circuit
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
CSAMPLE
5pF
RON
15Ω
RON
15Ω
VDD
VDD
LTC2165
AIN+
2165 F02
CSAMPLE
5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10Ω
10Ω
the VCM bypass capacitor should be increased to 2.2µF.
With a single-ended input the harmonic distortion and INL
will degrade, but the noise and DNL will remain unchanged.
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 through 6) has better bal-
ance, resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 4
through 6) should convert the signal to differential before
driving the A/D.
25Ω
25Ω 25Ω
25Ω
50Ω
AIN+
AIN–
12pF
0.1µF
VCM
LTC2165
ANALOG
INPUT
0.1µF T1
1:1
T1: MA/COM MABAES0060 RESISTORS,
CAPACITORS ARE 0402 PACKAGE SIZE 2165 F03
0.1µF
LTC2165/LTC2164/LTC2163
20
216543f
applicaTions inForMaTion
Figure 4. Recommended Front End Circuit for
Input Frequencies from 5MHz to 150MHz
Figure 5. Recommended Front End Circuit for
Input Frequencies from 150MHz to 250MHz
Figure 6. Recommended Front End Circuit for
Input Frequencies Above 250MHz
Figure 7. Front End Circuit Using a
High Speed Differential Amplifier
25Ω
25Ω
50Ω
12Ω
12Ω
0.1µF
AIN+
AIN–
8.2pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
2165 F04
LTC2165
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
1.8pF
0.1µF
VCM
ANALOG
INPUT
0.1µF
0.1µF
T1
T2
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
2165 F05
LTC2165
25Ω
25Ω
50Ω
0.1µF
4.7nH
4.7nH
AIN+
AIN–
0.1µF
VCM
ANALOG
INPUT
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2165 F06
LTC2165
T1
0.1µF
0.1µF
25Ω
25Ω
200Ω
200Ω
0.1µF AIN+
AIN–
12pF
0.1µF
VCM
LTC2165
2165 F07
–
+
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
12pF
LTC2165/LTC2164/LTC2163
21
216543f
applicaTions inForMaTion
Figure 8a. Reference Circuit
VREF
REFH
REFH
SENSE
C1
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.625V < VSENSE < 1.300V
1.25V
REFL
REFL
INTERNAL ADC
HIGH REFERENCE
BUFFER
2165 F08
LTC2165
5Ω
0.8x
DIFF AMP
INTERNAL ADC
LOW REFERENCE
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
2.2µF
C2
0.1µF
C3
0.1µF
+
+
–
–
–
–
+
+
Reference
The LTC2165/LTC2164/LTC2163 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to VDD. For a 1V input range
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8a. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
At sample rates below 110Msps an interdigitated capaci-
tor is not necessary for good performance and C1 can
be replaced by a standard 2.2µF capacitor between REFH
and REFL. The capacitor should be as close to the pins
as possible (not on the back side of the circuit board).
Figure 8b. Alternative REFH/REFL Bypass Circuit
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
REFH
REFH
REFL
REFL
2165 F08b
LTC2165
CAPACITORS ARE 0402 PACKAGE SIZE
C3
0.1µF
C1
2.2µF
C2
0.1µF
Figures 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d, the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
Figure 9. Using an External 1.25V Reference
SENSE
1.25V
EXTERNAL
REFERENCE
2.2µF
1µF
VREF
2165 F09
LTC2165
LTC2165/LTC2164/LTC2163
22
216543f
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
applicaTions inForMaTion
Figure 12. Sinusoidal Encode Drive
Figure 13. PECL or LVDS Encode Drive
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
50Ω
100Ω
0.1µF
0.1µF
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2165
2165 F12
ENC–
ENC+
T1
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1µF
0.1µF
2165 F13
LTC2165
Figure 10. Equivalent Encode Input
Circuit for Differential Encode Mode
VDD
LTC2165
2165 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
30k
ENC+
ENC–
2165 F11
0V
1.8V TO 3.3V
LTC2165
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input
Circuit for Single-Ended Encode Mode.
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12, 13).
The encode inputs are internally biased to 1.2V through
10kΩ equivalent resistance. The encode inputs can be
taken above VDD (up to 3.6V), and the common mode
range is from 1.1V to 1.6V. In the differential encode
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single-ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
The single ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
LTC2165/LTC2164/LTC2163
23
216543f
applicaTions inForMaTion
to make the sampling clock have a 50%(±5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2165/LTC2164/LTC2163 can operate in three digital
output modes: full rate CMOS, double data rate CMOS (to
halve the number of output lines), or double data rate LVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D0 to D15),
overflow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of digital lines by eight, simplifying board routing
and reducing the number of input pins needed to receive
the data. The data outputs (D0_1, D2_3, D4_5, D6_7, D8_9,
D10_11, D12_13, D14_15), overflow (OF), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
When using double data rate CMOS at sample rates above
100Msps, the SNR may degrade slightly, about 0.2dB to
0.5dB depending on load capacitance and board layout.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There are
eight LVDS output pairs (D0_1+/D0_1– through D14_15+/
D14_15–) for the digital output data. Overflow (OF+/OF–)
and the data output clock (CLKOUT+/CLKOUT–) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the
analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
LTC2165/LTC2164/LTC2163
24
216543f
Phase-Shifting the Output Clock
In full rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup and hold time when latching the data, the CLKOUT+
signal may need to be phase-shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
Figure 14. Phase-Shifting CLKOUT
The LTC2165/LTC2164/LTC2163 can also phase-shift the
CLKOUT+/CLKOUT– signals by serially programming mode
control register A2. The output clock can be shifted by 0°,
45°, 90°, or 135°. To use the phase-shifting feature the
clock duty cycle stabilizer must be turned on. Another
control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase-shift. The combina-
tion of these two features enables phase-shifts of 45° up
to 315° (Figure 14).
applicaTions inForMaTion
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D15 – D0
(OFFSET BINARY)
D15 – D0
(2’S COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1
0
0
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
0
0
0
0
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
< –1.000000V
0
0
1
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
0
0
0
1
1
1
1
CLKPHASE1
MODE CONTROL BITS
0
0
1
1
0
0
1
1
CLKPHASE0
0
1
0
1
0
1
0
1
2165 F14
ENC+
LTC2165/LTC2164/LTC2163
25
216543f
applicaTions inForMaTion
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital Output Signal
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode is
enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13,
D15) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12, D14), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
that is centered around mid-scale, the digital outputs toggle
between mostly 1’s and mostly 0’s. This simultaneous
switching of most of the bits will cause large currents in the
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
CLKOUT CLKOUT
OF
D15/D0
D14/D0
•
•
•
D2/D0
D1/D0
D0
2165 F15
OF
D15
D14
D2
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
•
•
•
D2
D1
D0
2165 F16
D0
D1/D0
D2/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2165
LTC2165/LTC2164/LTC2163
26
216543f
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13, D15.) The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function can
be on at the same time. The alternate bit polarity mode is
enabled by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D15 to D0) to known values:
All 1s: all outputs are 1
All 0s: all outputs are 0
Alternating: outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: outputs change from
10101010101010101 to 01010101010101010
on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high-impedance
disabled state is intended for in-circuit testing or long
periods of inactivity—it is too slow to multiplex a data
bus between multiple converters at full speed. When the
outputs are disabled the ADC should be put into either
sleep or nap mode.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of
time required to recover from sleep mode depends on
the size of the bypass capacitors on VREF, REFH, and
REFL. For the suggested values in Figure 8, the A/D will
stabilize after 2ms.
applicaTions inForMaTion
In nap mode the A/D core is powered down while the internal
reference circuits stay active, allowing faster wake-up than
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50µs should be
allowed so the on-chip references can settle from the
slight temperature shift caused by the change in supply
current as the A/D leaves nap mode.
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
DEVICE PROGRAMMING MODES
The operating modes of the LTC2165/LTC2164/LTC2163
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flex-
ibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V, or
3.3V CMOS logic. When used as an input, SDO should be
driven through a 1kΩ series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Digital Output Mode Control Bit
0 = Full Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI/SDO Power-Down Control Bits
00 = Normal Operation
01 = Not Used
10 = Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
LTC2165/LTC2164/LTC2163
27
216543f
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serial interface that program the A/D mode control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serial data is only written and read back is not needed, then
SDO can be left floating and no pull-up resistor is needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
applicaTions inForMaTion
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bits 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are reset to 00h. The ADC is momentarily placed in sleep mode.
This bit is automatically set back to zero at the end of the SPI write command.
The reset register is write only. Data read back from the reset register will be random.
Bits 6-0 Unused, Don’t Care Bits
REGISTER A1: POWER DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X PWROFF1 PWROFF0
Bits 7-2 Unused, Don’t Care Bits
Bits 1-0 PWROFF1: PWROFF0 Power Down Control Bits
00 = Normal Operation
01 = Not Used
10 = Nap Mode
11 = Sleep Mode
LTC2165/LTC2164/LTC2163
28
216543f
applicaTions inForMaTion
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, Don’t Care Bits
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1: CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period × 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period × 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period × 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0
Bit 7 Unused, Don’t Care Bit
Bits 6-4 ILVDS2: ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3 TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0.
LTC2165/LTC2164/LTC2163
29
216543f
Bit 2 OUTOFF Output Disable Bit
0 = Digital outputs are enabled.
1 = Digital outputs are disabled and have high output impedance.
Note: If the digital outputs are disabled the part should also be put in sleep mode or nap mode.
Bits 1-0 OUTMODE1: OUTMODE0 Digital Output Mode Control Bits
00 = Full Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP
Bits 7-6 Unused, Don’t Care Bits
Bits 5-3 OUTTEST2: OUTTEST0 Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D15-D0 alternate between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010.
111 = Alternating Output Pattern. OF, D15-D0 alternate between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111.
Note: Other bit combinations are not used.
Bit 2 ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On. Forces the output format to be Offset Binary.
Bit 1 RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bits 0 TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
applicaTions inForMaTion
LTC2165/LTC2164/LTC2163
30
216543f
GROUNDING AND BYPASSING
The LTC2165/LTC2164/LTC2163 requires a printed circuit
board with a clean unbroken ground plane in the first
layer beneath the ADC. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Size 0402 ceramic capacitors are recommended. The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
applicaTions inForMaTion
the circuit board as the A/D, and as close to the device
as possible. A low inductance interdigitated capacitor is
suggested for REFH/REFL if the sampling frequency is
greater than 110Msps.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2165/LTC2164/
LTC2163 is transferred from the die through the bottom-
side exposed pad and package leads onto the printed circuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
LTC2165/LTC2164/LTC2163
31
216543f
Typical applicaTions
Silkscreen Top
Top Side
LTC2165/LTC2164/LTC2163
32
216543f
Inner Layer 2
Inner Layer 3
Typical applicaTions
LTC2165/LTC2164/LTC2163
33
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Inner Layer 4
Bottom Side
Inner Layer 5
Typical applicaTions
LTC2165/LTC2164/LTC2163
34
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Typical applicaTions
VCM
AIN+
AIN–
GND
REFH
REFL
REFH
REFL
PAR/SER
GND
GND
VDD
AIN+
AIN–
PAR/SER
D11
D10
D9
D8
OVDD
OGND
CLKOUT+
CLKOUT–
D7
D6
D5
D4
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
SPI PORT
2165 TA02
GND ENC+ENC–CS SCK SDIVDD
VDD D0 D1 D2 D3
24232221191817161514
37383940414243444647 4548
13
VDD
VDD
VDD SENSE VREF SDO
SDO
GND OF D15DNC D14 D13 D12
0VDD
C37
0.1µF
LTC2165
C15
0.1µF
C21
0.1µF
C18
0.1µF
GND
20
SENSE
DIGITAL
OUTPUTS
C32
0.1µF
R51
100Ω
ENCODE
CLOCK
C28
0.1µF
C19
0.1µF
C23
2.2µF
C51
0.1µF
+
–
+
–
–
+
–
+
CN1
LTC2165/LTC2164/LTC2163
35
216543f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
7.00 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER
C = 0.35
0.40 0.10
4847
1
2
BOTTOM VIEW—EXPOSED PAD
5.50 REF
(4-SIDES)
0.75 0.05 R = 0.115
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UK48) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 0.05
5.50 REF
(4 SIDES) 6.10 0.05 7.50 0.05
0.25 0.05
0.50 BSC
PACKAGE OUTLINE
5.15 0.10
5.15 0.10
5.15 0.05
5.15 0.05
R = 0.10
TYP
LTC2165/LTC2164/LTC2163
36
216543f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2011
LT 0611 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2259-14/LTC2260-14/
LTC2261-14
14-Bit, 80Msps/105Msps/125Msps
1.8V ADCs, Ultralow Power
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
LTC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow
Power
149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-40
LTC2266-14/LTC2267-14/
LTC2268-14
14-Bit, 80Msps/105Msps/125Msps
1.8V Dual ADCs, Ultralow Power
216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-12/LTC2267-12/
LTC2268-12
12-Bit, 80Msps/105Msps/125Msps
1.8V Dual ADCs, Ultralow Power
216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
RF Mixers/Demodulators
LTC5517 40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5557 400MHz to 3.8GHz High Linearity
Downconverting Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
LTC5575 800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412 800MHz, 31dB Range, Analog-Controlled
Variable Gain Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,
4mm × 4mm QFN-24
LTC6605-7/LTC6605-10/
LTC6605-14
Dual Matched 7MHz/10MHz/14MHz
Filters with ADC Drivers
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
Signal Chain Receivers
LTM9002 14-Bit Dual Channel IF/Baseband
Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
2165 TA03
2-Tone FFT, fIN = 70MHz and 69MHz
S/H
OUTPUT
DRIVERS
16-BIT
ADC CORE
CLOCK
CONTROL
D15
•
•
•
D0
125MHz
CLOCK
ANALOG
INPUT
2165 TA03a
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
GND OGND
