74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0
January 2008
74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
Features
Input and output interface capability to systems at
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 125
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
General Description
The LVTH125 contains four independent non-inverting
buffers with 3-STATE outputs.
These buffers are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH125 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing a low power dissipation.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVTH125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 2
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
Pin Names Description
A
n
, B
n
Inputs
O
n
3-STATE Outputs
Inputs Output
A
n
B
n
O
n
LLL
LHH
HXZ
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 3
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +4.6V
V
I
DC Input Voltage –0.5V to +7.0V
V
O
DC Output Voltage
Output in 3-STATE –0.5V to +7.0V
Output in HIGH or LOW State
(1)
–0.5V to +7.0V
I
IK
DC Input Diode Current, V
I
<
GND –50mA
I
OK
DC Output Diode Current, V
O
<
GND –50mA
I
O
DC Output Current, V
O
>
V
CC
Output at HIGH State 64mA
Output at LOW State 128mA
I
CC
DC Supply Current per Supply Pin ±64mA
I
GND
DC Ground Current per Ground Pin ±128mA
T
STG
Storage Temperature –65°C to +150°C
Symbol Parameter Min Max Units
V
CC
Supply Voltage 2.7 3.6 V
V
I
Input Voltage 0 5.5 V
I
OH
HIGH-Level Output Current –32 mA
I
OL
LOW-Level Output Current 64 mA
T
A
Free-Air Operating Temperature –40 85 °C
t
/
V Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V 0 10 ns/V
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 4
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
DC Electrical Characteristics
Notes:
2. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
5. This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Symbol Parameter V
CC
(V) Conditions
T
A
=
–40°C to +85°C
Units
Min. Typ.
(2)
Max.
V
IK
Input Clamp Diode Voltage 2.7 I
I
=
–18mA –1.2 V
V
IH
Input HIGH Voltage 2.7–3.6 V
O
0.1V or
V
O
V
CC
– 0.1V
2.0 V
V
IL
Input LOW Voltage 2.7–3.6 0.8 V
V
OH
Output HIGH Voltage 2.7–3.6 I
OH
=
–100µA V
CC
– 0.2 V
2.7 I
OH
=
–8mA 2.4
3.0 I
OH
=
–32mA 2.0
V
OL
Output LOW Voltage 2.7 I
OL
=
100µA 0.2 V
I
OL
=
24mA 0.5
3.0 I
OL
=
16mA 0.4
I
OL
=
32mA 0.5
I
OL
=
64mA 0.55
I
I(HOLD)
Bushold Input Minimum Drive 3.0 V
I
=
0.8V 75 µA
V
I
=
2.0V –75
I
I(OD)
Bushold Input Over-Drive
Current to Change State
3.0
(3)
500 µA
(4)
–500
I
I
Input Current 3.6 V
I
=
5.5V 10 µA
Control Pins 3.6 V
I
=
0V or V
CC
±1
Data Pins 3.6 V
I
=
0V –5
V
I
=
V
CC
1
I
OFF
Power Off Leakage Current 0 0V VI or VO 5.5V ±100 µA
IPU/PD Power up/down 3-STATE
Output Current
0–1.5 VO = 0.5V to 3.0V,
VI = GND or VCC
±100 µA
IOZL 3-STATE Output Leakage Current 3.6 VO = 0.5V –5 µA
IOZH 3-STATE Output Leakage Current 3.6 VO = 3.0V 5 µA
IOZH+ 3-STATE Output Leakage Current 3.6 VCC < VO 5.5V 10 µA
ICCH Power Supply Current 3.6 Outputs HIGH 0.19 mA
ICCL Power Supply Current 3.6 Outputs LOW 5 mA
ICCZ Power Supply Current 3.6 Outputs Disabled 0.19 mA
ICCZ+Power Supply Current 3.6 VCC VO 5.5V,
Outputs Disabled
0.19 mA
ICC Increase in Power Supply
Current(5) 3.6 One Input at VCC – 0.6V,
Other Inputs at VCC or
GND
0.2 mA
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 5
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Dynamic Switching Characteristics(6)
Notes:
6. Characterized in SOIC package. Guaranteed parameter, but not tested.
7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Notes:
8. All typical values are at VCC = 3.3V, TA = 25°C.
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance(10)
Note:
10. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012.
Symbol Parameter VCC (V)
Conditions TA = 25°C
UnitsCL = 50 pF, RL = 500Min. Typ. Max.
VOLP Quiet Output Maximum
Dynamic VOL
3.3 (7) 0.8 V
VOLV Quiet Output Minimum
Dynamic VOL
3.3 (7) –0.8 V
Symbol Parameter
TA = –40°C to +85°C,
CL = 50pF, RL = 500
Units
VCC = 3.3V ± 0.3V VCC = 2.7V
Min. Typ.(8) Max. Min. Max.
tPLH Propagation Delay, Data to Output 1.0 3.5 1.0 4.5 ns
tPHL 1.0 3.9 1.0 4.9
tPZH Output Enable Time 1.0 4.0 1.0 5.5 ns
tPZL 1.1 4.0 1.1 5.4
tPHZ Output Disable Time 1.5 4.5 1.5 5.7 ns
tPLZ 1.3 4.5 1.3 4.0
tOSHL, tOSLH Output to Output Skew(9) 1.0 1.0 ns
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC = 0V, VI = 0V or VCC 4pF
COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 8pF
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 6
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25 0.25
0.10 0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 7
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 8
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVTH125 Rev. 1.4.0 9
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Rev. I33
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs