ADC108S102CIMTX - National Semiconductor

ADC108S102

ADC108S102 8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter

Literature Number: SNAS336A

ADC108S102

March 18, 2011

8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter

General Description

The ADC108S102 is a low-power, eight-channel CMOS 10-

bit analog-to-digital converter specified for conversion

throughput rates of 500 kSPS to 1 MSPS. The converter is

based on a successive-approximation register architecture

with an internal track-and-hold circuit. It can be configured to

accept up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is compatible with

several standards, such as SPI™, QSPI™, MICROWIRE™,

and many common DSP serial interfaces.

The ADC108S102 may be operated with independent analog

and digital supplies. The analog supply (VA) can range from

+2.7V to +5.25V, and the digital supply (VD) can range from

+2.7V to VA. Normal power consumption using a +3V or +5V

supply is 2.1 mW and 9.4 mW, respectively. The power-down

feature reduces the power consumption to 0.09 µW using a

+3V supply and 0.30 µW using a +5V supply.

The ADC108S102 is packaged in a 16-lead TSSOP package.

Operation over the extended industrial temperature range of

−40°C to +105°C is guaranteed.

Features

■Eight input channels

■Variable power management

■Independent analog and digital supplies

■SPI/QSPI/MICROWIRE/DSP compatible

■Packaged in 16-lead TSSOP

Key Specifications

■Conversion Rate 500 kSPS to 1 MSPS

■DNL (VA = VD = 5.0 V) ±0.5 LSB (max)

■INL (VA = VD = 5.0 V) ±0.5 LSB (max)

■Power Consumption

■—3V Supply 2.1 mW (typ)

—5V Supply 9.4 mW (typ)

Applications

■Automotive Navigation

■Portable Systems

■Medical Instruments

■Mobile Communications

■Instrumentation and Control Systems

Connection Diagram

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Ordering Information

Order Code Temperature Range Description

ADC108S102CIMT −40°C to +105°C 16-Lead TSSOP Package

ADC108S102CIMTX −40°C to +105°C 16-Lead TSSOP Package, Tape & Reel

ADC108S102EVAL Evaluation Board

SPI™ is a trademark of Motorola, Inc.

ADC108S102 8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter

Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF.

DIGITAL I/O

16 SCLK

Digital clock input. The guaranteed performance range of

frequencies for this input is 8 MHz to 16 MHz. This clock directly

controls the conversion and readout processes.

15 DOUT Digital data output. The output samples are clocked out of this pin

on the falling edges of the SCLK pin.

14 DIN Digital data input. The ADC108S102's Control Register is loaded

through this pin on rising edges of the SCLK pin.

1 CS Chip select. On the falling edge of CS, a conversion process

begins. Conversions continue as long as CS is held low.

POWER SUPPLY

2VA

Positive analog supply pin. This voltage is also used as the

reference voltage. This pin should be connected to a quiet +2.7V

to +5.25V source and bypassed to GND with 1 µF and 0.1 µF

monolithic ceramic capacitors located within 1 cm of the power pin.

13 VD

Positive digital supply pin. This pin should be connected to a +2.7V

to VA supply, and bypassed to GND with a 0.1 µF monolithic

ceramic capacitor located within 1 cm of the power pin.

3 AGND The ground return for the analog supply and signals.

12 DGND The ground return for the digital supply and signals.

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ADC108S102

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Digital Supply Voltage VD−0.3V to VA + 0.3V,

max 6.5V

Voltage on Any Pin to GND −0.3V to VA +0.3V

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current(Note 3) ±20 mA

Power Dissipation at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

2500V

250V

For soldering specifications:

see product folder at www.national.com and

www.national.com/ms/MS/MS-SOLDERING.pdf

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature −40°C ≤ TA ≤ +105°

VA Supply Voltage +2.7V to +5.25V

VD Supply Voltage +2.7V to VA

Digital Input Voltage 0V to VA

Analog Input Voltage 0V to VA

Clock Frequency 8 MHz to 16 MHz

Package Thermal Resistance

Package θJA

16-lead TSSOP on 4-

layer, 2 oz. PCB 96°C / W

ADC108S102 Converter Electrical Characteristics (Note 7)

The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500

kSPS to 1 MSPS, and CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°

Symbol Parameter Conditions Typical Limits

(Note 6)Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 10 Bits

INL Integral Non-Linearity (End Point

Method) ±0.2 ±0.5 LSB (max)

DNL Differential Non-Linearity ±0.2 ±0.5 LSB (max)

VOFF Offset Error +0.3 ±0.7 LSB (max)

OEM Offset Error Match ±0.07 ±0.4 LSB (max)

FSE Full Scale Error +0.2 ±0.4 LSB (max)

FSEM Full Scale Error Match ±0.07 ±0.4 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth (−3dB) 8 MHz

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 40.2 kHz, −0.02 dBFS 61.8 61.3 dB (min)

SNR Signal-to-Noise Ratio fIN = 40.2 kHz, −0.02 dBFS 61.8 61.4 dB (min)

THD Total Harmonic Distortion fIN = 40.2 kHz, −0.02 dBFS −87.0 −73.8 dB (max)

SFDR Spurious-Free Dynamic Range fIN = 40.2 kHz, −0.02 dBFS 83.1 76.0 dB (min)

ENOB Effective Number of Bits fIN = 40.2 kHz 9.98 9.89 Bits (min)

ISO Channel-to-Channel Isolation fIN = 20 kHz 79.7 dB

IMD

Intermodulation Distortion, Second

Order Terms fa = 19.5 kHz, fb = 20.5 kHz −83.9 dB

Intermodulation Distortion, Third Order

Terms fa = 19.5 kHz, fb = 20.5 kHz −82.4 dB

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

CINA Input Capacitance Track Mode 33 pF

Hold Mode 3 pF

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ADC108S102

Symbol Parameter Conditions Typical Limits

(Note 6)Units

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage VA = VD = +2.7V to +3.6V 2.1 V (min)

VA = VD = +4.75V to +5.25V 2.4 V (min)

VIL Input Low Voltage VA = VD = +2.7V to +5.25V 0.8 V (max)

IIN Input Current VIN = 0V or VD±0.01 ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VD − 0.5 V (min)

VOL Output Low Voltage ISINK = 200 µA to 1.0 mA, 0.4 V (max)

IOZH, IOZL Hi-Impedance Output Leakage Current ±1 µA (max)

COUT

Hi-Impedance Output Capacitance

(Note 7) 2 4pF (max)

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (CL = 10 pF)

VA, VDAnalog and Digital Supply Voltages VA ≥ VD 2.7 V (min)

5.25 V (max)

IA + ID

Total Supply Current

Normal Mode ( CS low)

VA = VD = +2.7V to +3.6V,

fSAMPLE = 1 MSPS, fIN = 40 kHz 0.70 1.4 mA (max)

VA = VD = +4.75V to +5.25V,

fSAMPLE = 1 MSPS, fIN = 40 kHz 1.88 2.7 mA (max)

Total Supply Current

Shutdown Mode (CS high)

VA = VD = +2.7V to +3.6V,

fSCLK = 0 kSPS 30 nA

VA = VD = +4.75V to +5.25V,

fSCLK = 0 kSPS 60 nA

Power Consumption

Normal Mode ( CS low)

VA = VD = +3.0V

fSAMPLE = 1 MSPS, fIN = 40 kHz 2.1 4.2 mW (max)

VA = VD = +5.0V

fSAMPLE = 1 MSPS, fIN = 40 kHz 9.4 13.6 mW (max)

Power Consumption

Shutdown Mode (CS high)

VA = VD = +3.0V

fSCLK = 0 kSPS 0.09 µW

VA = VD = +5.0V

fSCLK = 0 kSPS 0.30 µW

AC ELECTRICAL CHARACTERISTICS

fSCLKMIN Minimum Clock Frequency 0.8 8MHz (min)

fSCLK Maximum Clock Frequency 16 MHz (max)

Sample Rate

Continuous Mode 50 500 kSPS (min)

1MSPS (max)

tCONVERT Conversion (Hold) Time 13 SCLK cycles

DC SCLK Duty Cycle 30 40 % (min)

70 60 % (max)

tACQ Acquisition (Track) Time 3SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

tAD Aperture Delay 4 ns

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ADC108S102

ADC108S102 Timing Specifications

The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500

kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits

(Note 6)Units

tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min)

tCSS

CS Setup Time prior to SCLK Rising

Edge 5 10 ns (min)

tEN CS Falling Edge to DOUT enabled 5 30 ns (max)

tDACC

DOUT Access Time after SCLK Falling

Edge 17 27 ns (max)

tDHLD

DOUT Hold Time after SCLK Falling

Edge 4 ns (typ)

tDS

DIN Setup Time prior to SCLK Rising

Edge 3 10 ns (min)

tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min)

tCH SCLK High Time 0.4 x tSCLK ns (min)

tCL SCLK Low Time 0.4 x tSCLK ns (min)

tDIS

CS Rising Edge to DOUT High-

Impedance

DOUT falling 2.4 20 ns (max)

DOUT rising 0.9 20 ns (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA.

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. In the 16-

pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum operating ambient temperature of 105°C. Note that the power consumption

of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC108S102

is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).

Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms

Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 7: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

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ADC108S102

Timing Diagrams

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FIGURE 1. ADC108S102 Operational Timing Diagram

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FIGURE 2. ADC108S102 Serial Timing Diagram

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FIGURE 3. SCLK and CS Timing Parameters

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ADC108S102

Specification Definitions

ACQUISITION TIME is the time required for the ADC to ac-

quire the input voltage. During this time, the hold capacitor is

charged by the input voltage.

APERTURE DELAY is the time between the fourth falling

edge of SCLK and the time when the input signal is internally

acquired or held for conversion.

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

CHANNEL-TO-CHANNEL ISOLATION is resistance to cou-

pling of energy from one channel into another channel.

CROSSTALK is the coupling of energy from one channel into

another channel. This is similar to Channel-to-Channel Isola-

tion, except for the sign of the data.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02

and says that the converter is equivalent to a perfect ADC of

this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition

(111...110) to (111...111) from the ideal (VREF - 1.5 LSB), after

adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to an individual ADC input at the

same time. It is defined as the ratio of the power in either the

second or the third order intermodulation products to the sum

of the power in both of the original frequencies. Second order

products are fa ± fb, where fa and fb are the two sine wave

input frequencies. Third order products are (2fa ± fb ) and

(fa ± 2fb). IMD is usually expressed in dB.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC108S102 is guaranteed not

to have any missing codes.

OFFSET ERROR is the deviation of the first code transition

(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal where a spurious signal

is any signal present in the output spectrum that is not present

at the input, including harmonics but excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dBc, of the rms total of the first five harmonic

components at the output to the rms level of the input signal

frequency as seen at the output. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversions. It is the acquisition

time plus the conversion time.

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ADC108S102

Typical Performance Characteristics TA = +25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz

unless otherwise stated.

DNL

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DNL

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INL

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INL

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DNL vs. Supply

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INL vs. Supply

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ADC108S102

SNR vs. Supply

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THD vs. Supply

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ENOB vs. Supply

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DNL vs. VD with VA = 5.0 V

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INL vs. VD with VA = 5.0 V

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DNL vs. SCLK Duty Cycle

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ADC108S102

INL vs. SCLK Duty Cycle

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SNR vs. SCLK Duty Cycle

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THD vs. SCLK Duty Cycle

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ENOB vs. SCLK Duty Cycle

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DNL vs. SCLK

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INL vs. SCLK

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ADC108S102

SNR vs. SCLK

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THD vs. SCLK

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ENOB vs. SCLK

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DNL vs. Temperature

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INL vs. Temperature

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SNR vs. Temperature

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ADC108S102

THD vs. Temperature

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ENOB vs. Temperature

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SNR vs. Input Frequency

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THD vs. Input Frequency

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ENOB vs. Input Frequency

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Power Consumption vs. SCLK

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ADC108S102

1.0 Functional Description

The ADC108S102 is a successive-approximation analog-to-

digital converter designed around a charge-redistribution dig-

ital-to-analog converter.

1.1 ADC108S102 OPERATION

Simplified schematics of the ADC108S102 in both track and

hold operation are shown in Figure 4 and Figure 5 respec-

tively. In Figure 4, the ADC108S102 is in track mode: switch

SW1 connects the sampling capacitor to one of eight analog

input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC108S102 is in this state for

the first three SCLK cycles after CS is brought low.

Figure 5 shows the ADC108S102 in hold mode: switch SW1

connects the sampling capacitor to ground, maintaining the

sampled voltage, and switch SW2 unbalances the compara-

tor. The control logic then instructs the charge-redistribution

DAC to add or subtract fixed amounts of charge to or from the

sampling capacitor until the comparator is balanced. When

the comparator is balanced, the digital word supplied to the

DAC is the digital representation of the analog input voltage.

The ADC108S102 is in this state for the last thirteen SCLK

cycles after CS is brought low.

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FIGURE 4. ADC108S102 in Track Mode

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FIGURE 5. ADC108S102 in Hold Mode

1.2 SERIAL INTERFACE

An operational timing diagram and a serial interface timing

diagram for the ADC108S102 are shown in The Timing Dia-

grams section. CS, chip select, initiates conversions and

frames the serial data transfers. SCLK (serial clock) controls

both the conversion process and the timing of serial data.

DOUT is the serial data output pin, where a conversion result

is sent as a serial data stream, MSB first. Data to be written

to the ADC108S102's Control Register is placed on DIN, the

serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. Each frame must contain an integer

multiple of 16 rising SCLK edges. The ADC's DOUT pin is in

a high impedance state when CS is high and is active when

CS is low. Thus, CS acts as an output enable. Similarly, SCLK

is internally gated off when CS is brought high.

During the first 3 cycles of SCLK, the ADC is in the track

mode, acquiring the input voltage. For the next 13 SCLK cy-

cles the conversion is accomplished and the data is clocked

out. SCLK falling edges 1 through 4 clock out leading zeros,

falling edges 5 through 14 clock out the conversion result,

MSB first, and falling edges 15 and 16 clock out trailing zeros.

If there is more than one conversion in a frame (continuous

conversion mode), the ADC will re-enter the track mode on

the falling edge of SCLK after the N*16th rising edge of SCLK

and re-enter the hold/convert mode on the N*16+4th falling

edge of SCLK. "N" is an integer value.

The ADC108S102 enters track mode under three different

conditions. In Figure 1, CS goes low with SCLK high and the

ADC enters track mode on the first falling edge of SCLK. In

the second condition, CS goes low with SCLK low. Under this

condition, the ADC automatically enters track mode and the

falling edge of CS is seen as the first falling edge of SCLK. In

the third condition, CS and SCLK go low simultaneously and

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ADC108S102

the ADC enters track mode. While there is no timing restriction

with respect to the falling edges of CS and SCLK, see Figure

3 for setup and hold time requirements for the falling edge of

CS with respect to the rising edge of SCLK.

During each conversion, data is clocked into a control register

through the DIN pin on the first 8 rising edges of SCLK after

the fall of CS. The control register is loaded with data indicat-

ing the input channel to be converted on the subsequent

conversion (see Tables 1, 2, 3).

The user does not need to incorporate a power-up delay or

dummy conversions as the ADC108S102 is able to acquire

the input signal to full resolution in the first conversion imme-

diately following power-up. The first conversion result after

power-up will be that of IN0.

TABLE 1. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

TABLE 2. Control Register Bit Descriptions

Bit #: Symbol: Description

7, 6, 2, 1, 0 DONTC Don't care. The values of these bits do not affect the device.

5 ADD2 These three bits determine which input channel will be sampled and converted

at the next conversion cycle. The mapping between codes and channels is

shown in Table 3.

4 ADD1

3 ADD0

TABLE 3. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

0 0 0 IN0 (Default)

0 0 1 IN1

0 1 0 IN2

0 1 1 IN3

1 0 0 IN4

1 0 1 IN5

1 1 0 IN6

1 1 1 IN7

1.3 ADC108S102 TRANSFER FUNCTION

The output format of the ADC108S102 is straight binary.

Code transitions occur midway between successive integer

LSB values. The LSB width for the ADC108S102 is VA / 1024.

The ideal transfer characteristic is shown in Figure 6. The

transition from an output code of 00 0000 0000 to a code of

00 0000 0001 is at 1/2 LSB, or a voltage of VA / 2048. Other

code transitions occur at steps of one LSB.

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FIGURE 6. Ideal Transfer Characteristic

1.4 ANALOG INPUTS

An equivalent circuit for one of the ADC108S102's input chan-

nels is shown in Figure 7. Diodes D1 and D2 provide ESD

protection for the analog inputs. The operating range for the

analog inputs is 0 V to VA. Going beyond this range will cause

the ESD diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 7 has a typical value of 3 pF and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch and is

typically 500 ohms. Capacitor C2 is the ADC108S102 sam-

pling capacitor, and is typically 30 pF. The ADC108S102 will

deliver best performance when driven by a low-impedance

source (less than 100 ohms). This is especially important

when using the ADC108S102 to sample dynamic signals. Al-

so important when sampling dynamic signals is a band-pass

or low-pass filter which reduces harmonics and noise in the

input. These filters are often referred to as anti-aliasing filters.

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FIGURE 7. Equivalent Input Circuit

1.5 DIGITAL INPUTS AND OUTPUTS

The ADC108S102's digital inputs (SCLK, CS, and DIN) have

an operating range of 0 V to VA. They are not prone to latch-

up and may be asserted before the digital supply (VD) without

any risk. The digital output (DOUT) operating range is con-

trolled by VD. The output high voltage is VD - 0.5V (min) while

the output low voltage is 0.4V (max).

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ADC108S102

2.0 Applications Information

2.1 TYPICAL APPLICATION CIRCUIT

A typical application is shown in Figure 8. The split analog and

digital supply pins are both powered in this example by the

National LP2950 low-dropout voltage regulator. The analog

supply is bypassed with a capacitor network located close to

the ADC108S102. The digital supply is separated from the

analog supply by an isolation resistor and bypassed with ad-

ditional capacitors. The ADC108S102 uses the analog supply

(VA) as its reference voltage, so it is very important that VA be

kept as clean as possible. Due to the low power requirements

of the ADC108S102, it is also possible to use a precision ref-

erence as a power supply.

To minimize the error caused by the changing input capaci-

tance of the ADC108S102, a capacitor is connected from

each input pin to ground. The capacitor, which is much larger

than the input capacitance of the ADC108S102 when in track

mode, provides the current to quickly charge the sampling

capacitor of the ADC108S102. An isolation resistor is added

to isolate the load capacitance from the input source.

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FIGURE 8. Typical Application Circuit

2.2 POWER SUPPLY CONSIDERATIONS

There are three major power supply concerns with this prod-

uct: power supply sequencing, power management, and the

effect of digital supply noise on the analog supply.

2.2.1 Power Supply Sequence

The ADC108S102 is a dual-supply device. The two supply

pins share ESD resources, so care must be exercised to en-

sure that the power is applied in the correct sequence. To

avoid turning on the ESD diodes, the digital supply (VD) can-

not exceed the analog supply (VA) by more than 300 mV, not

even on a transient basis. Therefore, VA must ramp up before

or concurrently with VD.

2.2.2 Power Management

The ADC108S102 is fully powered-up whenever CS is low

and fully powered-down whenever CS is high, with one ex-

ception. If operating in continuous conversion mode, the AD-

C108S102 automatically enters power-down mode between

SCLK's 16th falling edge of a conversion and SCLK's 1st

falling edge of the subsequent conversion (see Figure 1).

In continuous conversion mode, the ADC108S102 can per-

form multiple conversions back to back. Each conversion

requires 16 SCLK cycles and the ADC108S102 will perform

conversions continuously as long as CS is held low. Contin-

uous mode offers maximum throughput.

In burst mode, the user may trade off throughput for power

consumption by performing fewer conversions per unit time.

This means spending more time in power-down mode and

less time in normal mode. By utilizing this technique, the user

can achieve very low sample rates while still utilizing an SCLK

frequency within the electrical specifications. The Power Con-

sumption vs. SCLK curve in the Typical Performance Curves

section shows the typical power consumption of the AD-

C108S102. To calculate the power consumption (PC), simply

multiply the fraction of time spent in the normal mode (tN) by

the normal mode power consumption (PN), and add the frac-

tion of time spent in shutdown mode (tS) multiplied by the

shutdown mode power consumption (PS) as shown in Figure

20164315

FIGURE 9. Power Consumption Equation

2.2.3 Power Supply Noise Considerations

The charging of any output load capacitance requires current

from the digital supply, VD. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations on the digital supply. If these variations are large

enough, they could degrade SNR and SINAD performance of

the ADC. Furthermore, if the analog and digital supplies are

tied directly together, the noise on the digital supply will be

coupled directly into the analog supply, causing greater per-

formance degradation than would noise on the digital supply

alone. Similarly, discharging the output capacitance when the

digital output goes from a logic high to a logic low will dump

current into the die substrate, which is resistive. Load dis-

charge currents will cause "ground bounce" noise in the sub-

strate that will degrade noise performance if that current is

large enough. The larger the output capacitance, the more

current flows through the die substrate and the greater the

noise coupled into the analog channel.

15 www.national.com

ADC108S102

The first solution to keeping digital noise out of the analog

supply is to decouple the analog and digital supplies from

each other or use separate supplies for them. To keep noise

out of the digital supply, keep the output load capacitance as

small as practical. If the load capacitance is greater than 50

pF, use a 100 Ω series resistor at the ADC output, located as

close to the ADC output pin as practical. This will limit the

charge and discharge current of the output capacitance and

improve noise performance. Since the series resistor and the

load capacitance form a low frequency pole, verify signal in-

tegrity once the series resistor has been added.

2.3 LAYOUT AND GROUNDING

Capacitive coupling between the noisy digital circuitry and the

sensitive analog circuitry can lead to poor performance. The

solution is to keep the analog circuitry separated from the

digital circuitry and the clock line as short as possible.

Digital circuits create substantial supply and ground current

transients. The logic noise generated could have significant

impact upon system noise performance. To avoid perfor-

mance degradation of the ADC108S102 due to supply noise,

do not use the same supply for the ADC108S102 that is used

for digital logic.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any ex-

ternal component (e.g., a filter capacitor) connected between

the converter's input pins and ground or to the reference input

pin and ground should be connected to a very clean point in

the ground plane.

We recommend the use of a single, uniform ground plane and

the use of split power planes. The power planes should be

located within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry and I/

O lines should be placed over the digital power plane. Fur-

thermore, all components in the reference circuitry and the

input signal chain that are connected to ground should be

connected together with short traces and enter the analog

ground plane at a single, quiet point.

www.national.com 16

ADC108S102

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead TSSOP

Order Number ADC108S102CIMT, ADC108S102CIMTX

NS Package Number MTC16

17 www.national.com

ADC108S102

Notes

ADC108S102 8-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter

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