© Semiconductor Components Industries, LLC, 2005
August, 2019 Rev. 1
1Publication Order Number:
NC7WZ38/D
NC7WZ38
TinyLogic UHS Dual
2-Input NAND Gate
(Open Drain Output)
Description
The NC7WZ38 is a dual 2Input NAND Gate with open drain
output stage from ON Semiconductors Ultra High Speed Series of
TinyLogic. The device is fabricated with advanced CMOS technology
to achieve ultra high speed with high output drive while maintaining
low static power dissipation over a very broad VCC operating range.
The device is specified to operate over the 1.65 V to 5.5 V VCC range.
The inputs and output are high impedance when VCC is 0 V. Inputs
tolerate voltages up to 5.5 V independent of VCC operating voltage.
The open drain output stage will tolerate voltages up to 5.5 V
independent of VCC when in the high impedance state.
Features
Space Saving US8 Surface Mount Package
MicroPak PbFree Leadless Package
Open Drain Output Stage for OR Tied Applications
Ultra High Speed: tPD 2.2 ns Typ. into 50 pF at 5 V VCC
High Output Sink Drive: ±24 mA at 3 V VCC
Broad VCC Operating Range: 1.65 V to 5.5 V
Matches the Performance of LCX when Operated at 3.3 V VCC
Power Down High Impedance Inputs / Output
Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation
Patented Noise / EMI Reduction Circuitry Implemented
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
A2Y2
Figure 1. Logic Symbol
&Y1
A1
B2
B1
IEEE/IEC
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
www.onsemi.com
U5, WZ38 = Specific Device Code
KK = 2Digit Lot Run Traceability Code
XY = 2Digit Date Code Format
Z = Assembly Plant Code
UQFN8
1.6X1.6, 0.5P
CASE 523AY
US8
CASE 846AN
XYKK
WZ38
Z
U5KK
XYZ
ON
NC7WZ38
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2
Connection Diagram
Figure 2. Connection Diagram (Top View)
AAA represents Product Code Top Mark see ordering code
NOTE: Orientation of Top Mark determines Pin One location.
Read the top product code mark left to right, Pin One
is the lower left pin (see diagram).
Figure 3. Pin One Orientation Diagram
Pin One
AAA
Figure 4. Pad Assignments for MicroPak
(Top Thru View)
1
Y1
2
B2
3
A2
A1
7
B1
6
Y2
5
VCC 8 4 GND
A1VCC
1
2
3
8
7
6
45
B1Y1
Y2B2
GND A2
(Top View)
PIN DESCRIPTIONS
Pin Names Description
An, Bn Inputs
Yn Output
FUNCTION TABLE (Y = AB)
Inputs Output
A B Y
L L *H
L H *H
H L *H
H H L
H = HIGH Logic Level
L = LOW Logic Level
*H = HIGH Impedance Output State (Open Drain)
NC7WZ38
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3
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VCC Supply Voltage 0.5 6.5 V
VIN DC Input Voltage 0.5 6.5 V
VOUT DC Output Voltage 0.5 6.5 V
IIK DC Input Diode Current VIN < 0.5 V 50 mA
IOK DC Output Diode Current VOUT < 0.5 V 50 mA
IOUT DC Output Current ±50 mA
ICC / IGND DC VCC / GND Current ±100 mA
TSTG Storage Temperature 65 +150 °C
TJJunction Temperature under Bias 150 °C
TLJunction Lead Temperature (Soldering, 10 Seconds) 260 °C
PDPower Dissipation @ +85°C250 mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Supply Voltage Operating 1.65 5.5 V
Supply Voltage Data Retention 1.5 5.5
VIN Input Voltage 0 5.5 V
VOUT Output Voltage 0 VCC V
TAOperating Temperature 40 +85 °C
tr, tfInput Rise and Fall Time VCC = 1.8 V ±0.15 V, 2.5 V ±0.2 V 0 20 ns/V
VCC = 3.3 V ±0.3 V 0 10
VCC = 5.0 V ±0.5 V 0 5
qJA Thermal Resistance 250 °C/W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Unused inputs must be held HIGH or LOW. They may not float.
NC7WZ38
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4
DC ELECTICAL CHARACTERISTICS
Symbol Parameter VCC (V) Conditions
TA = +25°C TA = 40 to +85°C
Unit
Min Typ Max Min Max
VIH HIGH Level Input
Voltage
1.65 to 1.95 0.65 VCC 0.65 VCC V
2.3 to 5.5 0.7 VCC 0.7 VCC
VIL LOW Level Input
Voltage
1.65 to 1.95 0.35 VCC 0.35 VCC V
2.3 to 5.5 0.3 VCC 0.3 VCC
ILKG HIGH Level Output
Leakage
5.5 VIN = VIL
VOUT = VCC or GND
±5±10 mA
VOL LOW Level Output
Voltage
1.65 VIN = VIH IOL = 100 mA0.0 0.1 0.1 V
2.3 0.0 0.1 0.1
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
1.65 IOL = 4 mA 0.08 0.24 0.24
2.3 IOL = 8 mA 0.10 0.3 0.3
3.0 IOL = 16 mA 0.15 0.4 0.4
3.0 IOL = 24 mA 0.22 0.55 0.55
4.5 IOL = 32 mA 0.22 0.55 0.55
IIN Input Leakage Current 5.5 VIN = 5.5 V, GND ±0.1 ±1mA
IOFF Power Off Leakage
Current
0.0 VIN or VOUT = 5.5 V 110 mA
ICC Quiescent Supply
Current
1.65 to 5.5 VIN = 5.5 V, GND 110 mA
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter VCC (V) Conditions
TA = +25°C TA = 40 to +85°C
Unit
Min Typ Max Min Max
tPZL Propagation Delay
(Figure 5, 7)
1.8 ±0.15 CL = 50 pF,
RU = 500 W,
RD = 500 W,
VI = 2 x VCC
5.2 9.2 9.6 ns
2.5 ±0.2 3.5 5.7 6.1
3.3 ±0.3 2.8 4.1 4.5
5.0 ±0.5 2.2 3.4 3.6
tPLZ Propagation Delay
(Figure 5, 7)
1.8 ±0.15 CL = 50 pF,
RU = 500 W,
RD = 500 W,
VI = 2 x VCC
4.6 9.2 9.6 ns
2.5 ±0.2 3.2 5.7 6.1
3.3 ±0.3 2.4 4.1 4.5
5.0 ±0.5 1.6 3.4 3.6
CIN Input Capacitance 02.5 pF
COUT Output Capacitance 04.2 pF
CPD Power Dissipation Capacitance
(Figure 6)
3.3 (Note 2) 7 pF
5.0 9
2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (see Figure 6) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (fIN) + (ICCstatic).
NC7WZ38
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5
AC Loading and Waveforms
Figure 5. AC Test Circuit
Figure 6. ICCD Test Circuit Figure 7. AC Waveforms
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%.
CL includes load and stray capacitance
Input PRR = 1.0 MHz, tW = 500 ns
A
VCC
INPUT
VCC
CL
INPUT OUTPUT
RD
RU
ORDERING INFORMATION
Order Number Top Mark Package Shipping
NC7WZ38K8X WZ38 8Lead US8, JEDEC MO187, Variation CA
3.1 mm Wide
3000 / Tape & Reel
NC7WZ38L8X U5 8Lead MicroPak, 1.6 mm Wide
(PbFree)
5000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
3. PbFree package per JEDEC JSTD020B.
MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
UQFN8 1.6X1.6, 0.5P
CASE 523AY
ISSUE O
DATE 31 AUG 2016
C
SEATING
PLANE
0.05 C
SIDE VIEW
0.05 C
AB
2X
1.60
1.60
0.05 C
TOP VIEW
PIN#1 IDENT
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO255
VARIATION UAAD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
0.025±0.025
4
123
567
80.30±0.05
(0.15)
(0.20)
0.30±0.05
0.05 C
0.50±0.05
BOTTOM VIEW
1.60±0.05
1.60±0.05
0.50
0.20±0.05 (8X)
1.00±0.05
0.30±0.05 (7X)
0.10 C A B
0.05 C
(0.20)3X
(0.09)
DETAIL A
DETAIL A
SCALE : 2X
(0.10)
RECOMMENDED
LAND PATTERN
1.60
0.45
(2X)
0.40
(6X)
1.61
0.25
(8X)
0.50
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13591G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
UQFN8 1.6X1.6, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
US8
CASE 846AN
ISSUE O
DATE 31 DEC 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13778G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
US8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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1
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PUBLICATION ORDERING INFORMATION
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Phone: 011 421 33 790 2910
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