3D7220
MONOLITHIC 10-TAP
FIXED DELAY LINE
(SERIES 3D7220)
FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 0.75ns through 7000ns
• Delay tolerance: 2% or 0.5ns
• Temperature stability: ±2% typical (-40C to 85C)
• Vdd stability: ±1% typical (4.75V-5.25V)
• Minimum input pulse width: 15% of total delay
• 14-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
FUNCTIONAL DESCRIPTION
The 3D7220 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 700ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D7220 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7220 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and space saving
surface mount 14-pin SOIC and 16-pin SOL packages.
PACKAGES
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
O2
O4
O6
O8
GND
VDD
O1
O3
O5
O7
O9
O10
3D7220-xx DIP
3D7220G-xx Gull-Wing
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
N/C
N/C
O2
O4
O6
O8
GND
VDD
N/C
O1
O3
O5
O7
O9
O10
3D7220S-xx SOL
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IN
N/C
O2
O4
O6
O8
GND
VDD
O1
O3
O5
O7
O9
O10
3D7220D-xx SOIC
PIN DESCRIPTIONS
IN Delay Line Input
O1 Tap 1 Output (10%)
O2 Tap 2 Output (20%)
O3 Tap 3 Output (30%)
O4 Tap 4 Output (40%)
O5 Tap 5 Output (50%)
O6 Tap 6 Output (60%)
O7 Tap 7 Output (70%)
O8 Tap 8 Output (80%)
O9 Tap 9 Output (90%)
O10 Tap 10 Output (100%)
VDD +5 Volts
GND Ground
For mechanical dimensions, click here.
For package marking details, click here.
TABLE 1: PART NUMBER SPECIFICATIONS
TOLERANCES INPUT RESTRICTIONS DASH
NUMBER TOTAL
DELAY (ns)
TAP-TAP
DELAY (ns)
Rec’d Max
Frequency
Absolute Max
Frequency
Rec’d Min
Pulse Width
Absolute Min
Pulse Width
-.75 6.75 ± 0.5* 0.75 ± 0.4 28.4 MHz 166.7 MHz 17.6 ns 3.00 ns
-1 9.0 ± 0.5* 1.0 ± 0.5 23.8 MHz 166.7 MHz 21.0 ns 3.00 ns
-1.5 13.5 ± 0.5* 1.5 ± 0.7 18.0 MHz 166.7 MHz 27.8 ns 3.00 ns
-2 18.0 ± 0.5* 2.0 ± 0.8 14.5 MHz 166.7 MHz 34.5 ns 3.00 ns
-2.5 22.5 ± 0.5* 2.5 ± 1.0 12.1 MHz 125.0 MHz 41.2 ns 4.00 ns
-4 36.0 ± 0.7* 4.0 ± 1.3 8.33 MHz 133.3 MHz 60.0 ns 6.00 ns
-5 50.0 ± 1.0 5.0 ± 1.5 6.67 MHz 66.7 MHz 75.0 ns 7.50 ns
-10 100.0 ± 2.0 10.0 ± 2.0 3.33 MHz 33.3 MHz 150 ns 15.0 ns
-20 200.0 ± 4.0 20.0 ± 4.0 1.67 MHz 16.7 MHz 300 ns 30.0 ns
-50 500.0 ± 10 50.0 ± 10 0.67 MHz 6.67 MHz 750 ns 75.0 ns
-100 1000 ± 20 100 ± 20 0.33 MHz 3.33 MHz 1500 ns 150 ns
-700 7000 ± 140 700 ± 140 0.05 MHz 0.48 MHz 10500 ns 1050 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns
NOTE: Any dash number between .75 and 700 not shown is also available as standard. 2005 Data Delay Devices
Doc #03004 DATA DELAY DEVICES, INC. 1
5/8/2006 3 Mt. Prospect Ave. Clifton, NJ 07013
3D7220
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7220 ten-tap delay line architecture is
shown in Figure 1. The delay line is composed of
a number of delay cells connected in series.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time. The
delay cells are matched and share the same
compensation signals, which minimizes tap-to-
tap delay deviations over temperature and supply
voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input frequency
and a Minimum and an Absolute Minimum
operating pulse width have been specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency specification
determines the highest frequency of the delay
line input signal for which the output delay
accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7220 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY DEVICES
be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse Width
(high or low) specification, tabulated in Table 1,
determines the smallest Pulse Width of the delay
line input signal that can be reproduced, shifted
in time at the device output, with acceptable
pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7220 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
VDD
O1
IN O2 O3 O4
Temp & VDD
Compensation
GND
Figure 1: 3D7220 Functional Diagram
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
O5 O6 O7 O8 O9 O10
Doc #03004 DATA DELAY DEVICES, INC. 2
5/8/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7220
Doc #03004 DATA DELAY DEVICES, INC. 3
5/8/2006 3 Mt. Prospect Ave. Clifton, NJ 07013
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at DATA
DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7220 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of ±2% from the room-
temperature delay settings and/or 1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to ±1% of the delay settings at
the nominal 5.0VDC power supply and/or 1.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VDD -0.3 7.0 V
Input Pin Voltage VIN -0.3 VDD+0.3 V
Input Pin Current IIN -1.0 1.0 mA 25C
Storage Temperature TSTRG -55 150 C
Lead Temperature TLEAD 300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Static Supply Current* IDD 3.5 5.5 mA
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Input Current IIH 1.0
µA VIH = VDD
Low Level Input Current IIL 1.0
µA VIL = 0V
High Level Output
Current
IOH -35.0 -4.0 mA VDD = 4.75V
VOH = 2.4V
Low Level Output Current IOL 4.0 15.0 mA VDD = 4.75V
VOL = 0.4V
Output Rise & Fall Time TR & TF 2.0 2.5 ns CLD = 5 pf
*IDD(Dynamic) = 10 * CLD * VDD * F Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/tap (pf) Output Load Capacitance (CLD) = 25 pf max
F = Input frequency (GHz)
3D7220
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Rload: 10KΩ ± 10%
Supply Voltage (Vcc): 5.0V ± 0.1V Cload: 5pf ± 10%
Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
10KΩ
470Ω5pf
Device
Under
Test
Digital
Scope
Rise/Fall Time: 3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width: PWIN = 1.25 x Total Delay
Period: PERIN = 2.5 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUT1
OUT2
OUT4
OUT3
OUT
TRIG
IN
REF
TRIG
Figure 2: Test Setup
DEVICE UNDER
TEST (DUT)
DIGITAL SCOPE/
TIME INTERVAL COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
OUT5
OUT6
OUT8
OUT7
OUT10
OUT9
Figure 3: Timing Diagram
tPLH tPHL
PERIN
PWIN
tRISE tFALL
0.6V0.6V 1.5V1.5V
2.4V 2.4V
1.5V1.5V
VIH
VIL
VOH
VOL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #03004 DATA DELAY DEVICES, INC. 4
5/8/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
