Rev. 1.2 / Sep. 2013 1
204pin DDR3L SDRAM SODIMM
DDR3L SDRAM
Unbuffered SODIMMs
Based on 2Gb E-die
HMT325S6EFR8A
HMT351S6EFR8A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.2 /Sep. 2013 2
Revision History
Revision No. History Draft Date Remark
1.0 Initial Release Jun. 2012
1.1 IDD5B spec modified Nov. 2012
1.2 Changed module maximum thickness
to reflect the measured maximum
Sep. 2013
Rev. 1.2 /Sep. 2013 3
Description
SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-
Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM
devices. These Unbuffered DDR3L SDRAM DIMMs are intended for use as main memory when installed in
systems such as mobile personal computers.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)
• VDDQ = 1.35V (1.283V to 1.45V)
• VDDSPD=3.0V to 3.6V
• Backward Compatible with 1.5V DDR3 Memory module
• 8 internal banks
• Data transfer rates:PC3-12800, PC3-10600, PC3-8500
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
• On Die Termination (ODT) supported
• This product is in Compliance with the RoHS directive
Ordering Information
Part Number Density Organization Component Composition # of
ranks
HMT325S6EFR8A-G7/H9/PB 2GB 256Mx64 256Mx8(H5TC2G83EFR)*8 1
HMT351S6EFR8A-G7/H9/PB 4GB 512Mx64 256Mx8(H5TC2G83EFR)*16 2
Rev. 1.2 /Sep. 2013 4
Key Parameters
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Address Table
MT/s Grade tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns) CL-tRCD-tRP
DDR3L-1066 -G7 1.875 713.125 13.125 37.5 50.625 7-7-7
DDR3L-1333 -H9 1.5 9 13.5
(13.125)*
13.5
(13.125)* 36 49.5
(49.125)* 9-9-9
DDR3L-1600 -PB 1.25 11 13.75
(13.125)*
13.75
(13.125)* 35 48.75
(48.125)* 11-11-11
Grade
Frequency [MHz]
Remark
CL5 CL6 CL7 CL8 CL9 CL10 CL11
-G7 667 800 1066 1066
-H9 667 800 1066 1066 1333 1333
-PB 667 800 1066 1066 1333 1333 1600
2GB(1Rx8) 4GB(2Rx8)
Refresh Method 8K/64ms 8K/64ms
Row Address A0-A14 A0-A14
Column Address A0-A9 A0-A9
Bank Address BA0-BA2 BA0-BA2
Page Size 1KB 1KB
Rev. 1.2 /Sep. 2013 5
Pin Descriptions
Pin Name Description Num
ber Pin Name Description Num
ber
CK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/Output 64
CK[1:0] Clock Input, negative line 2 DM[7:0] Data Masks 8
CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8
RAS Row Address Strobe 1 DQS[7:0] Data strobes, negative line 8
CAS Column Address Strobe 1 EVENT Temperature event pin 1
WE Write Enable 1 TEST Logic Analyzer specific test pin (No
connect on SODIMM) 1
S[1:0] Chip Selects 2 RESET Reset Pin 1
A[9:0],A11,
A[15:13] Address Inputs 14 VDD Core and I/O Power 18
A10/AP Address Input/Autoprecharge 1 VSS Ground 52
A12/BC Address Input/Burst chop 1
BA[2:0] SDRAM Bank Addresses 3 VREFDQ
Input/Output Reference
1
ODT[1:0] On Die Termination Inputs 2 VREFCA 1
SCL Serial Presence Detect (SPD)
Clock Input 1VTT Termination Voltage 2
SDA SPD Data Input/Output 1 VDDSPD SPD Power 1
SA[1:0] SPD Address Inputs 2 NC Reserved for future use 2
Total: 204
Rev. 1.2 /Sep. 2013 6
Input/Output Functional Descriptions
Symbol Type Polarity Function
CK0/CK0
CK1/CK1 IN Cross Point
The system clock inputs. All address and command lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.
CKE[1:0] IN Active
High
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
S[1:0] IN Active
Low
Enables the associated DDR3 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1.
ODT[1:0] IN Active
High
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3
SDRAM mode register.
RAS, CAS, WE IN Active
Low
When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE
define the operation to be executed by the SDRAM.
VREFDQ
VREFCA
Supply Reference voltage for SSTL15 inputs.
BA[2:0] IN — Selects which SDRAM internal bank of eight is activated.
A[9:0],
A10/AP,
A11,
A12/BC
A[15:13]
IN —
During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read of Write com-
mand cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high
autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction
with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used
to define which bank to precharge. A12(BC) is samples during READ and WRITE com-
mands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop:
LOW, burst chopped).
DQ[63:0] I/O — Data Input/Output pins.
DM[7:0] IN Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation
if it is high. In Read mode, DM lines have no effect.
VDD, VDDSPD
VSS
Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
DQS[7:0],
DQS[7:0] I/O Cross Point
The data strobes, associated with one data byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window.
In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead-
ing edge of the data window. DQS signals are complements, and timing is relative to the
crosspoint of respective DQS and DQS.
SA[1:0] IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
Rev. 1.2 /Sep. 2013 7
SDA I/O —
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
SCL IN — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
EVENT
OUT
(open
drain)
Active Low
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
RESET IN The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Symbol Type Polarity Function
Rev. 1.2 /Sep. 2013 8
Pin Assignments
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
Pin
#
Front
Side
Pin
#
Back
Side
1VREFDQ 2VSS 53 DQ19 54 VSS 105 VDD 106 VDD 157 DQ42 158 DQ46
3VSS 4
DQ4
55 VSS 56
DQ28
107
A10/AP
108
BA1
159
DQ43
160
DQ47
5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161 VSS 162 VSS
7DQ18 VSS 59 DQ25 60 VSS 111 VDD 112 VDD 163 DQ48 164 DQ52
9VSS 10
DQS0
61 VSS 62
DQS3
113
WE
114
S0
165
DQ49
166
DQ53
11 DM0 12 DQS0 63 DM3 64 DQS3 115 CAS 116 ODT0 167 VSS 168 VSS
13 VSS 14 VSS 65 VSS 66 VSS 117 VDD 118 VDD 169
DQS6
170 DM6
15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 A132120 ODT1 171 DQS6 172 VSS
17
DQ3
18
DQ7
69
DQ27
70
DQ31
121
S1
122
NC
173 VSS 174
DQ54
19 VSS 20 VSS 71 VSS 72 VSS 123 VDD 124 VDD 175 DQ50 176 DQ55
21 DQ8 22 DQ12 73 CKE0 74 CKE1 125 TEST 126 VREFCA 177 DQ51 178 VSS
23
DQ9
24
DQ13
75 VDD 76 VDD 127 VSS 128 VSS 179 VSS 180
DQ60
25 VSS 26 VSS 77 NC 78 A152129 DQ32 130 DQ36 181 DQ56 182 DQ61
27
DQS1
28 DM1 79 BA2 80 A142131 DQ33 132 DQ37 183 DQ57 184 VSS
29
DQS1
30
RESET
81 VDD 82 VDD 133 VSS 134 VSS 185 VSS 186
DQS7
31 VSS 32 VSS 83 A12/BC 84 A11 135
DQS4
136 DM4 187 DM7 188 DQS7
33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138 VSS 189 VSS 190 VSS
35
DQ11
36
DQ15
87 VDD 88 VDD 139 VSS 140
DQ38
191
DQ58
192
DQ62
37 VSS 38 VSS 89 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63
39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144 VSS 195 VSS 196 VSS
41
DQ17
42
DQ21
93 VDD 94 VDD 145 VSS 146
DQ44
197
SA0
198
EVENT
43 VSS 44 VSS 95 A3 96 A2 147 DQ40 148 DQ45 199 VDDSPD 200 SDA
45
DQS2
46 DM2 97 A1 98 A0 149 DQ41 150 VSS 201 SA1 202 SCL
47
DQS2
48 VSS 99 VDD 100 VDD 151 VSS 152
DQS5
203
V
TT
204
V
TT
49 VSS 50 DQ22 101 CK0 102 CK1 153 DM5 154 DQS5
51 DQ18 52 DQ23 103 CK0 104 CK1 155 VSS 156 VSS
NC = No Connect; RFU = Reserved Future Use
1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be con-
nected to the termination resistor.
Rev. 1.2 /Sep. 2013 9
Functional Block Diagram
2GB, 256Mx64 Module(1Rank of x8)
DQS0
DQS0
DM0
DQ[0:7]
DQS
DQS
DM
DQ [0:7]
D0
RAS
CAS
S0
WE
CK0
CK0
CKE0
ODT0
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
D4
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS2
DQS2
DM2
Q[16:23]
DQS
DQS
DM
DQ [0:7]
D1
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
D5
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS4
DQS4
DM4
Q[32:39]
DQS
DQS
DM
DQ [0:7]
D2
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
D6
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS6
DQS6
DM6
Q[48:55]
DQS
DQS
DM
DQ [0:7]
D3
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
D7
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS1
DQS1
DM1
DQ[8:15]
DQS3
DQS3
DM3
DQ[24:31]
DQS5
DQS5
DM5
DQ[40:47]
DQS7
DQS7
DM7
DQ[56:63]
A2
Temp Se n s or
SDA
D0–D7
V
DD
SPD
SPD/TS
D0–D7
V
REF
CA
SCL
V
tt
D0–D7
V
DD
EVENT
A1
A0
SCL
SA0
SA1 (with SPD)
EVENT
A2
SDA
SCL
WP
A1
A0
SCL
SA0
SA1 (SPD)
Vtt
V
REF
DQ
V
SS
CK0
CK1
CK0
CK1
S1
ODT1
D0–D7, SPD, Temp sensor
D0–D7
D0–D7
NC
NC
NOTES
1. DQ wiring may differ from that
shown however, DQ, DM, DQS, and
DQS relationships are maintained as
shown
Address and Control Lines
Rank 0
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
D0 D1 D2 D3
Vtt
D4 D5 D6 D7
Vtt
V1 V2 V4V3
V1 V2 V4V3
CKE1
EVENT
RESET
Temp Sensor
D0-D7
NC
Terminated near
card edge
Rev. 1.2 /Sep. 2013 10
4GB, 512Mx64 Module(2Rank of x8)
DQS3
DQS3
DM3
DQ[24:31]
DQS
DQS
DM
DQ [0:7]
D11
RAS
CAS
S1
WE
CK1
CK1
CKE1
ODT1
A[O:N]/BA[O:N]
240ohm
ZQ
+/-1%
Vtt
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D3
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
CK0
CK0
CKE0
ODT0
S0
A2
Tem p S e ns o r
SDA
D0–D15
V
DD
SPD
SPD/TS
D0–D15
V
REF
CA
SCL
V
tt
D0–D15
V
DD
EVENT
A1
A0
SCL
SA0
SA1 (with SPD)
EVENT
A2
SDA
SCL
WP
A1
A0
SCL
SA0
SA1 (SPD)
V
tt
V
REF
DQ
V
SS
CK0
CK0
CK1
CK1
CKE0
CKE1
D0–D15, SPD, Temp sensor
D0–D7
D8–D15
D0-D7
D8-D15
NOTES
1. DQ wiring may differ from that shown
however, DQ, DM, DQS, and DQS rela-
tionships are maintained as shown
Rank 0
D0–D7
D8–D15
Rank 1
DQS1
DQS1
DM1
DQ[8:15]
DQS
DQS
DM
DQ [0:7]
D1
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D9
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS0
DQS0
DM0
DQ[0:7]
DQS
DQS
DM
DQ [0:7]
D0
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D8
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:43]
DQS5
DQS5
DM5
DQ[40:47]
Vtt Vtt
VDD VDD
Cterm Cterm
D12
D4
DQS
DQS
DM
DQ [0:7]
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
D6
D14
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
D7
D15
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
DQS2
DQS2
DM2
DQ[6:23]
DQS
DQS
DM
DQ [0:7]
D2
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
LDQS
LDQS
LDM
DQ [0:7]
D10
240ohm
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
D5
D13
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
DM
DQ [0:7]
ZQ
+/-1%
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
240ohm 240ohm
S0
ODT0
S1
ODT1
EVENT
RESET
D0–D7
D8–D15
Temp Sensor
D0-D15
D0–D7
D8–D15
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
D0
V9
D1 D11
D2
D14
D15
D9
D8 D10
D3 D12
D5 D7
D6
Vtt
V1V2
V3
V4 V5 V6
V8
V7
V6
V8
V7
V5
V9V1
V4
V3
V2
D13
D4
Rev. 1.2 /Sep. 2013 11
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tFEFI requirements in the Extended Temperature Range.
Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.8 V V 1, 3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.8 V V 1, 3
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.8 V V 1
TSTG Storage Temperature -55 to +100 oC1, 2
Temperature Range
Symbol Parameter Rating Units Notes
TOPER
Normal Operating Temperature Range 0 to 85 oC 1,2
Extended Temperature Range 85 to 95 oC1,3
Rev. 1.2 /Sep. 2013 12
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.283 1.35 1.45 V 1,2,3,4
VDDQ Supply Voltage for Output 1.283 1.35 1.45 V 1,2,3,4
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3L specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - DDR3 (1.5V) operation
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2,3
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2,3
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.2 /Sep. 2013 13
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
Ta
CK,CK#
RESET#
Tb Tc Td Te Tf Tg Th Ti Tj Tk
MRS1) 1)MRS MRS
CKE
DON’T CARE
READ MRS
T = 500us
COMMAND
ODT
BA
RTT
MR3 MR1 MR0READ MR2
READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
ZQCL VALID
VALID
VALID
VALID
Tmin = 200us
Tmin = 10ns
Tmin = 10ns tCKSRX
Tmin = 10ns
tIS
tIS tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
tDLLK
TIME BREAK
Rev. 1.2 /Sep. 2013 14
AAC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 27.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for refer-
ence: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single
Ended AC and DC Input Levels for DQ and DM" on page 15), the respective levels in JESD79-3 (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/
L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when
the device is operated in the 1.35 voltage range.
Single Ended AC and DC Input Levels for Command and Address
Symbol Parameter
DDR3L-800/1066 DDR3L-1333/1600
Unit Notes
Min Max Min Max
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 Vref + 0.160 Note2 V 1,2,5
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 Note2 Vref - 0.160 V 1,2,5
VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5
VIH.CA(AC125)AC Input logic high----V1,2,5
VIL.CA(AC125)AC input logic low----V1,2,5
VRefCA(DC)Reference Voltage for
ADD, CMD inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4
Rev. 1.2 /Sep. 2013 15
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Opera-
tion”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 27.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:
approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on
page 14) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is
operated in the 1.35 voltage range.
Single Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
DDR3L-800/1066 DDR3L-1333/1600
Unit Notes
Min Max Min Max
VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.DQ(AC160) AC input logic high Vref + 0.160 Note2 - - V 1, 2, 5
VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160 - - V 1, 2, 5
VIH.DQ(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5
VIL.DQ(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1, 2, 5
VIH.DQ(AC130) AC Input logic high - - - - V 1, 2, 5
VIL.DQ(AC130) AC input logic low - - - - V 1, 2, 5
VRefDQ(DC)Reference Voltage
for DQ, DM inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4
Rev. 1.2 /Sep. 2013 16
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 22. Further-
more VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
Illustration of VRef(DC) tolerance and VRef ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are depen-
dent on VRef.
“VRef” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
VDD
VSS
VDD/2
VRef(DC)
VRef ac-noise
voltage
time
VRef(DC)max
VRef(DC)min
VRef(t)
Rev. 1.2 /Sep. 2013 17
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
Definition of differential ac-swing and “time above ac-level” tDVAC
time
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
V
IL.DIFF.AC.MAX
V
IL.DIFF.MAX
0
V
IL.DIFF.MIN
V
IL.DIFF.AC.MIN
t
DVAC
half cycle
t
DVAC
Rev. 1.2 /Sep. 2013 18
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 27.
note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become
equal to or less than VIL(ac) level.
Differential AC and DC Input Levels
Symbol Parameter
DDR3L-800, 1066, 1333, 1600
Unit Notes
Min Max
VIHdiff Differential input high + 0.180 Note 3 V 1
VILdiff Differential input logic low Note 3 - 0.180 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
DDR3L-800/1066/1333/1600
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 320mV
tDVAC [ps]
@ |VIH/Ldiff (ac)| = 270mV
min max min max
> 4.0 189 - 201 -
4.0 189 - 201 -
3.0 162 - 179 -
2.0 109 - 134
1.8 91 - 119 -
1.6 69 - 100 -
1.4 40 - 76 -
1.2 note - 44 -
1.0 note - note -
< 1.0 note - note -
Rev. 1.2 /Sep. 2013 19
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) also
has to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-
ended signals CK and CK.
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
VDD or VDDQ
VSEHmin
VDD/2 or VDDQ/2
VSEH
VSELmax
VSS or VSSQ
CK or DQS
VSEL
time
Symbol Parameter
DDR3L-800, 1066, 1333 & 1600
Unit Notes
Min Max
VSEH Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V1,2
Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V1,2
VSEL Single-ended low level for strobes Note 3 (VDD / 2) - 0.175 V1,2
Single-ended low level for CK, CK Note 3 (VDD / 2) - 0.175 V1,2
Rev. 1.2 /Sep. 2013 20
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 27.
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Rev. 1.2 /Sep. 2013 21
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Symbol Parameter
DDR3L-800, 1066, 1333, 1600, 1866
Unit Notes
Min Max
VIX(CK) Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150 150 mV 2
-175 175 mV 1
VIX(DQS) Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS -150 150 mV 2
Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -
CK is larger than 3 V/ns.
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix (Max)) 25mV
Cross point voltage for differential input signals (CK, DQS)
Rev. 1.2 /Sep. 2013 22
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Operation” for single-ended
slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3L Device Operation” for single-ended slew
rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Notes:
Delta
TFdiff
Delta
TRdiff
VIHdiffmin
VILdiffmax
0
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Differential Input Slew Rate Definition
Description
Measured
Defined by
Min Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
Rev. 1.2 /Sep. 2013 23
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with
a driver impedance of 40Ω and an effective test load of 25 Ω to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with
a driver impedance of 40Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
Single-ended AC and DC Output Levels
Symbol Parameter
DDR3L-800, 1066,
1333 and 1600
Unit Notes
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V1
Differential AC and DC Output Levels
Symbol Parameter
DDR3L-800, 1066,
1333 and 1600
Unit Notes
VOHdiff (AC) AC differential output high measurement level (for output SR) + 0.2 x VDDQ V1
VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ V1
Rev. 1.2 /Sep. 2013 24
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output slew Rate Definition
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 Units
Parameter Symbol Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 1.75 51) 1.75 51) 1.75 51) 1.75 51) V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular
maximum limite of 5 V/ns applies.
Single-ended Output slew Rate Definition
Description
Measured
Defined by
From To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse
Output Slew Rate (single-ended)
Delta TFse
Delta TRse
VOH(AC)
VOl(AC)
V∏
Single Ended Output Voltage(l.e.DQ)
Rev. 1.2 /Sep. 2013 25
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output slew Rate Definition
Differential Output Slew Rate Definition
Description
Measured
Defined by
From To
Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Slew Rate
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 Units
Parameter Symbol Min Max Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12 3.5 12 V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Delta
TFdiff
Delta
TRdiff
VOHdiff(AC)
VOLdiff(AC)
O
Differential Output Voltage(i.e. DQS-DQS)
Rev. 1.2 /Sep. 2013 26
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Reference Load for AC Timing and Output Slew Rate
Rev. 1.2 /Sep. 2013 27
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter DDR3L-
800
DDR3L-
1066
DDR3L-
1333
DDR3L-
1600 Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.67 0.5 0.4 0.33 V-ns
Maximum undershoot area below VSS (See Figure below) 0.67 0.5 0.4 0.33 V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDD
VSS
Maximum Amplitude
Undershoot Area
Time (ns)
Volts
(V)
Rev. 1.2 /Sep. 2013 28
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter DDR3L-
800
DDR3L-
1066
DDR3L-
1333
DDR3L-
1600 Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.25 0.19 0.15 0.13 V-ns
Maximum undershoot area below VSS (See Figure below) 0.25 0.19 0.15 0.13 V-ns
(CK, CK, DQ, DQS, DQS, DM)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
Volts
(V)
Rev. 1.2 /Sep. 2013 29
Refresh parameters by device density
Notes:
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices
support the following options or requirements referred to in this materia.
Refresh parameters by device density
Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units
REF command ACT or
REF command time tRFC 90 110 160 260 350 ns
Average periodic
refresh interval tREFI 0 C TCASE 85 C7.8 7.8 7.8 7.8 7.8 us
85 C TCASE 95 C3.9 3.9 3.9 3.9 3.9 us
Rev. 1.2 /Sep. 2013 30
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 34.
Speed Bin DDR3L-800E
Unit Notes
CL - nRCD - nRP 6-6-6
Parameter Symbol min max
Internal read command to first data
t
AA 15 20 ns
ACT to internal read or write delay time
t
RCD 15 — ns
PRE command period
t
RP 15 — ns
ACT to ACT or REF command period
t
RC 52.5 — ns
ACT to PRE command period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1, 2, 3, 4, 10
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3
Supported CL Settings 5, 6
n
CK 10
Supported CWL Settings 5
n
CK
Rev. 1.2 /Sep. 2013 31
DDR3L-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 34.
Speed Bin DDR3L-1066F
Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to
first data
t
AA 13.125 20 ns
ACT to internal read or
write delay time
t
RCD 13.125 — ns
PRE command period
t
RP 13.125 — ns
ACT to ACT or REF
command period
t
RC 50.625 — ns
ACT to PRE command
period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1, 2, 3, 4, 6, 10
CWL = 6
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 6
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 7 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4
CL = 8 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3
Supported CL Settings 5, 6, 7, 8
n
CK 10
Supported CWL Settings 5, 6
n
CK
Rev. 1.2 /Sep. 2013 32
DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 34.
Speed Bin DDR3L-1333H
Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read
command to first data
t
AA
13.5
(13.125)5,9 20 ns
ACT to internal read or
write delay time
t
RCD
13.5
(13.125)5,9 —ns
PRE command period
t
RP
13.5
(13.125)5,9 —ns
ACT to ACT or REF
command period
t
RC
49.5
(49.125)5,9 —ns
ACT to PRE command
period
t
RAS 36 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1, 2, 3, 4, 7, 10
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 7
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 7
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG)
1.875 < 2.5 ns 1, 2, 3, 4, 7
(Optional)5,9
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 7
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 9 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 4
CL = 10
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG)
1.5 <1.875 ns 1, 2, 3
(Optional) ns
Supported CL Settings 5, 6,(7), 8, 9, (10)
n
CK
Supported CWL Settings 5, 6, 7
n
CK
Rev. 1.2 /Sep. 2013 33
DDR3L-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 34.
Speed Bin DDR3L-1600K
Unit Note
CL - nRCD - nRP 11-11-11
Parameter Symbol min max
Internal read
command to first data
t
AA
13.75
(13.125)5,9 20 ns
ACT to internal read or
write delay time
t
RCD
13.75
(13.125)5,9 —ns
PRE command period
t
RP
13.75
(13.125)5,9 —ns
ACT to ACT or REF
command period
t
RC
48.75
(48.125)5,9 —ns
ACT to PRE command
period
t
RAS 35 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) 3.0 3.3 ns 1, 2, 3, 4,
8, 10
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 8
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG)
1.875 < 2.5 ns 1, 2, 3, 4, 8
(Optional)5,10
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 8
t
CK(AVG) Reserved ns 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 8
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4, 8
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 9
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG)
1.5 <1.875 ns 1, 2, 3, 4, 8
(Optional)5,9
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 10
CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 8
CWL = 8
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 11 CWL = 5, 6,7
t
CK(AVG) Reserved ns 4
CWL = 8
t
CK(AVG) 1.25 <1.5 ns 1, 2, 3
Supported CL Settings 5, 6, (7), 8, (9), 10, 11
n
CK
Supported CWL Settings 5, 6, 7, 8
n
CK
Rev. 1.2 /Sep. 2013 34
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.35V +/- 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
10. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-
tory in SPD coding.
Rev. 1.2 /Sep. 2013 35
Environmental Parameters
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and
device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum
rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Symbol Parameter Rating Units Notes
TOPR Operating temperature 0 to 65 oC1, 3
HOPR Operating humidity (relative) 10 to 90 % 1
TSTG Storage temperature -50 to +100 oC1
HSTG Storage humidity (without condensation) 5 to 95 % 1
PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2
Rev. 1.2 /Sep. 2013 36
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= VILAC(max).
• ”1” and “HIGH” is defined as VIN >= VIHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.2 /Sep. 2013 37
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
VDD
DDR3L
SDRAM
VDDQ
RESET
CK/CK
DQS, DQS
CS
RAS, CAS, WE
A, BA
ODT
ZQ VSS VSSQ
DQ, DM,
TDQS, TDQS
CKE RTT = 25 Ohm
VDDQ/2
IDD IDDQ (optional)
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Channel IO Power
Number
IDDQ
Test Load
Correction
Rev. 1.2 /Sep. 2013 38
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol DDR3L-1066 DDR3L-1333 DDR3L-1600 Unit
7-7-7 9-9-9 11-11-11
t
CK 1.875 1.5 1.25 ns
CL 7 9 11 nCK
n
RCD 7911nCK
n
RC 27 33 39 nCK
n
RAS 20 24 28 nCK
n
RP 7911nCK
n
FAW
1KB page size 20 20 24 nCK
2KB page size 27 30 32 nCK
n
RRD
1KB page size 4 4 5 nCK
2KB page size 6 5 6 nCK
n
RFC -512Mb 486072nCK
n
RFC-1 Gb 59 74 88 nCK
n
RFC- 2 Gb 86 107 128 nCK
n
RFC- 4 Gb 139 174 208 nCK
n
RFC- 8 Gb 187 234 280 nCK
Symbol Description
I
DD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
I
DD1
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.2 /Sep. 2013 39
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
I
DD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Symbol Description
Rev. 1.2 /Sep. 2013 40
I
DD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
I
DD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
I
DD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
I
DD6
Self-Refresh Current: Normal Temperature Range
T
CASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD6ET
Self-Refresh Current: Extended Temperature Range
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Symbol Description
Rev. 1.2 /Sep. 2013 41
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
I
DD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a,f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
Symbol Description
Rev. 1.2 /Sep. 2013 42
Table 3 - IDD0 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1111 0 0000 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3, 4 D, D 1111 0 0000 0 F 0 -
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 1.2 /Sep. 2013 43
Table 4 - IDD1 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT001100000000 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3,4 D, D 1111000000F0 -
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 1.2 /Sep. 2013 44
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D
1111 0 0 0 0 0 F 0 -
3D
1111 0 0 0 0 0 F 0 -
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D
1111 0 0 0 0 0 F 0 -
3D
1111 0 0 0 0 0 F 0 -
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Rev. 1.2 /Sep. 2013 45
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1D100000000000-
2,3 D,D 1111 0 0000 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5D1000000000F0-
6,7 D,D 1111 0 0000 0 F 0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1D100010000000-
2,3 D,D 1111 1 0000 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5D1000100000F0-
6,7 D,D 1111 1 0000 0 F 0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
Rev. 1.2 /Sep. 2013 46
Table 9 - IDD5B Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00REF 0 0 0 1 0 0 0 0 0 0 0 -
11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1111 0 0000 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Rev. 1.2 /Sep. 2013 47
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
22*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
33*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
44*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
Assert and repeat above D Command until nFAW - 1, if necessary
5nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
9nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Assert and repeat above D Command until 2* nFAW - 1, if necessary
10
2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
2&nFAW+2 D 1 0 0 0 0 0 00 0 0 F 0 -
Repeat above D Command until 2* nFAW + nRRD - 1
11
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
2&nFAW+nRRD+2 D 1 0 0 0 0 1 00 0 0 0 0 -
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 0 0 0 0 -
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 0 0 -
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.2 /Sep. 2013 48
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
2GB, 256M x 64 SO-DIMM: HMT325S6EFR8A
4GB, 512M x 64 SO-DIMM: HMT351S6EFR8A
Symbol DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit note
IDD0 208 224 224 mA
IDD1 256 272 272 mA
IDD2N 104 120 128 mA
IDD2NT 128 144 160 mA
IDD2P0 80 80 80 mA
IDD2P1 104 104 104 mA
IDD2Q 112 120 136 mA
IDD3N 144 144 160 mA
IDD3P 96 96 96 mA
IDD4R 424 504 584 mA
IDD4W 440 520 600 mA
IDD5B 1280 1280 1280 mA
IDD6 80 80 80 mA
IDD6ET 96 96 96 mA
IDD7 840 928 936 mA
Symbol DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit note
IDD0 312 344 384 mA
IDD1 360 392 432 mA
IDD2N 208 240 256 mA
IDD2NT 256 288 320 mA
IDD2P0 160 160 160 mA
IDD2P1 208 208 208 mA
IDD2Q 224 240 272 mA
IDD3N 288 288 320 mA
IDD3P 192 192 192 mA
IDD4R 528 624 744 mA
IDD4W 544 640 760 mA
IDD5B 1384 1400 1440 mA
IDD6 160 160 160 mA
IDD6ET 192 192 192 mA
IDD7 944 1048 1096 mA
Rev. 1.2 /Sep. 2013 49
Module Dimensions
256Mx64 - HMT325S6EFR8A
Front
Back
SPD
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail-A
3.37mm max
4.00 0.10
1.65 0.10
1.00 mm
0.08
1.80 0.102
X
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13
Units: millimeters
Side
2.55
1.00
Detail of Contacts A
0.3
0.3~1.0
0.15
0.05
0.45
0.03
4.00
0.10
0.60
Rev. 1.2 /Sep. 2013 50
512Mx64 - HMT351S6EFR8A
Front
Back
30.0mm
67.60mm
20.0mm
6.00
2.0
21.00 39.00
2.15
3.00
pin 1 pin 203
Detail-
A
SPD
3.37mm max
Detail-B
4.00 0.10
1.65 0.10
1.00 mm
0.08
1.80 0.102
X
Side
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13
Units: millimeters
2.55
1.00
Detail of Contacts A
0.3
0.3~1.0
0.15
0.05
0.45
0.03
4.00
0.10
0.60