TC1301A-SFAVMFTR - Microchip Technology

TC1301A/B

Features

• Dual Output LDO with Microcontroller Reset

Monitor Functionality:

-V

OUT1 = 1.5V to 3.3V @ 300 mA

-V

OUT2 = 1.5V to 3.3V @ 150 mA

-V

RESET = 2.20V to 3.20V

• Output Voltage and RESET Threshold Voltage

Options Available (See Table 8-1)

• Low Dropout Voltage:

-V

OUT1 = 104 mV @ 300 mA (typical)

-V

OUT2 = 150 mV @ 150 mA, (typical)

• Low Supply Current: 116 µA (typical),

TC1301A/B with both output voltages available

• Reference Bypass Input for Low-Noise Operation

• Both Output Voltages Stable with a Mini mum of

1 µF Ceramic Output Capacitor

• Separate Input for RESET Detect Voltage

(TC1301A)

• Separate VOUT1 and VOUT2 SHDN pins

(TC1301B)

• RESET Output Duration: 300 ms (typical)

• Power-Saving Shutdown Mode of Operation

• Wake-up from SHDN: 5.3 µs (typical)

• Small 8-pin DFN and MSOP Package Op tions

• Operating Junction Temperature Range:

- -40°C to +125°C

• Overtemperature and Overcurrent Protection

Applications

• Cellular/GSM/PHS Phones

• Battery-Operated Systems

• Hand-Held Medical Instruments

• Portable Computers/PDAs

• Linear Post-Regulators for SMPS

• Pagers

Related Literature

• AN765, “Using Microchip’s Micropower LDOs”,

DS00765, Microchip Technology Inc., 2002

• AN766, “Pin-Compatible CMOS Upgrades to

BiPolar LDOs”, DS00766, Microchip Technology

Inc., 2002

• AN792, “A Method to Determine How Much

Power a SOT23 Can Dissipate in an Application”,

DS00792, Microchip Technology Inc., 2001

Description

The TC1301A/B combines two Low Dropout (LDO)

regulators and a microcontroller RESET function into a

single 8-pin MSOP or DFN package. Both regulator

outputs feature low dropout voltage, 104 mV

@ 300 mA for VOUT1, 150 mV @ 150 mA for VOUT2,

low quiescent current consumption, 58 µA each and a

typical regulation accuracy of 0.5%. Several fixed-

output voltage and detector voltage combinations are

available. A reference bypass pin is available to further

reduce output noise and improve the power supply

rejection ratio of both LDOs.

The TC1301A/B is stable over all line and load

conditions with a minimum of 1 µF of ceramic output

capacitance, and utilizes a unique compensation

scheme to provide fast dynamic response to sudden

line voltage and load current changes.

For the TC1301A, the microcontroller RESET function

operates independently of both VOUT1 and VOUT2. The

input to the RESET function is connected to the V DET

pin.The SHDN2 pin is used to control the output of

VOUT2 only. VOUT1 will power-up and down with VIN.

In the case of the TC1301B, the detect voltage input of

the RESET function is connected internally to VOUT1.

Both VOUT1 and VOUT2 have independent shutdown

capability.

Additional features include an overcurrent limit and

overtemperature protection that, when combined,

provide a robust design for all load fault conditions.

Package Types

8-Pin DFN/MSOP

RESET

SHDN2

Bypass

GND

VDET

VOUT2

VIN

VOUT1

TC1301A

RESET

SHDN2

Bypass

GND

VDET

VOUT2

VIN

VOUT1

DFN8 MSOP8

RESET

SHDN2

Bypass

GND

SHDN1

VOUT2

VIN

VOUT1

TC1301B

RESET

SHDN2

Bypass

GND

SHDN1

VOUT2

VIN

VOUT1

DFN8 MSOP8

Dual LDO with Microcontroller RESET Function

TC1301A/B

Functional Block Diagrams

Typical Application Circuits

LDO #2

150 mA

LDO #1

300 mA

LDO #2

150 mA

VIN VOUT1

VOUT2

Bandgap

Reference

1.2V

SHDN2

Threshold

Detector Time Delay

300 ms, typ

RESET

VDET

GND

Bypass

TC1301A

VDET

TC1301B

VIN

SHDN2

GND

Bypass

SHDN1 LDO #1

300 mA

Threshold

Detector Time Delay

300 ms typ

VOUT1

VOUT2

RESET

VOUT1

Bandgap

Reference

1.2V

VOUT1

RESET

GND

VDET BATTERY

COUT1

1 µF Ceramic

X5R CIN

1µF

TC1301A

COUT2

1 µF Ceramic

X5R

CBYPASS(Note)

10 nF Ceramic

Bypass

VIN 7

VOUT2 6

SHDN2

ON/OFF Control VOUT2

System RESET

2.8V @ 300 mA

2.6V @ 150 mA

VOUT1

RESET

GND

SHDN1

BATTERY

COUT1

1 µF Ceramic

X5R

CIN

1µF

TC1301B

1 µF Ceramic

X5R

Bypass

VIN 7

2.7V

4.2V

VOUT2 6

SHDN2

ON/OFF Control VOUT2

System RESET

2.8V @ 300 mA

2.6V @ 150 mA

ON/OFF Control VOUT1

Note: CBYPASS is optional

2.7V

4.2V

COUT2

TC1301A/B

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD...................................................................................6.5V

Maximum Voltage on Any Pin ...... (VSS – 0.3) to (VIN + 0.3)V

Power Dissipation ..........................Interna lly Limited (Note 7)

Storage temperature .....................................-65°C to +150°C

Maximum Junction Temperature, TJ...........................+150°C

Continuous Operating Temperature Range ..-40°C to +125°C

ESD protection on all pins, HBM, MM..................... 4 kV, 400V

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended per iods

may affect device reliability.

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF,

CBYPASS = 10 nF, SHDN > VIH, TA = +25°C.

Boldface type specifications apply for junction temperatures of -40°C to +125°C.

Parameters Sym Min Typ Max Units Conditions

Input Operating Voltage VIN 2.7 —6.0 VNote 1

Maximum Output Current IOUT1Max 300 ——mAV

IN = 2.7V to 6.0V (Note 1)

Maximum Output Current IOUT2Max 150 ——mAV

IN = 2.7V to 6.0V (Note 1)

Output Voltage Tolerance

(VOUT1 and VOUT2)VOUT VR – 2.5 VR±0.5 VR + 2.5 %Note 2

Temperature Coefficient

(VOUT1 and VOUT2)TCVOUT — 25 — ppm/°C Note 3

Line Regulation

(VOUT1 and VOUT2)ΔVOUT/

ΔVIN

—0.020.2 %/V (VR+1V) ≤ VIN ≤ 6V

Load Regulation, VOUT ≥ 2.5V

(VOUT1 and VOUT2) ΔVOUT/

VOUT

-1 0.1 +1 %I

OUTX = 0.1 mA to IOUTMax (Note 4)

Load Regulation, VOUT < 2.5V

(VOUT1 and VOUT2)ΔVOUT/

VOUT

-1.5 0.1 +1.5 %I

OUTX = 0.1 mA to IOUTMax (Note 4)

Thermal Regulation ΔVOUT/ΔPD—0.04— %/WNote 5

Dropout Voltage (Note 6)

VOUT1 ≥ 2.7V VIN – VOUT —104180 mV IOUT1 = 300 mA

VOUT2 ≥ 2.6V VIN – VOUT —150250 mV IOUT2 = 150 mA

Supply Current

TC1301A IIN(A) —103180 µA SHDN2 = VIN, VDET = OPEN,

IOUT1 = IOUT2 = 0 mA

TC1301B IIN(B) —114180 µA SHDN1 = SHDN2 = VIN,

IOUT1 = IOUT2 = 0 mA

Note 1: The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT.

2: VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2).

3: TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT).

4: Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested

over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating

effects are covered by the thermal regulation specification.

5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,

excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for

t = 10 ms.

6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value

measured at a 1V differential.

7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

temperature and the thermal resistance from junction-to-air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power

dissipation causes the device to initiate thermal shutdown.

TC1301A/B

Shutdown Supply Current

TC1301A IIN_SHDNA—5890 µA SHDN2 = GND, VDET = OPEN

Shutdown Supply Current

TC1301B IIN_SHDNB— 0.1 1 µA SHDN1 = SHDN2 = GND

Power Supply Rejection Ratio PSRR — 58 — dB f ≤ 100 Hz, IOUT1 = IOUT2 = 50 mA,

CIN = 0 µF

Output Noise eN — 830 — nV/(Hz)½f ≤ 1 kHz, IOUT1 = IOUT2 = 50 mA,

CIN = 0 µF

Output Short-Circuit Current (Average)

VOUT1 IOUTsc —200— mAR

LOAD1 ≤ 1Ω

VOUT2 IOUTsc —140— mAR

LOAD2 ≤ 1Ω

SHDN Input High Threshold VIH 45 ——%V

IN VIN = 2.7V to 6.0V

SHDN Input Low Threshold VIL ——15 %VIN VIN = 2.7V to 6.0V

Wake-Up Time (From SHDN

mode), (VOUT2)tWK —5.320 µs

VIN = 5V, IOUT1 = IOUT2 = 30 mA,

See Figure 5-1

Settling Time (From SHDN mode),

(VOUT2)tS—50— µs

VIN = 5V, IOUT1 = IOUT2 = 50 mA,

See Figure 5-2

Thermal Shutdown Die

Temperature TSD —150— °CV

IN = 5V, IOUT1 = IOUT2 = 100 µA

Thermal Shutdown Hysteresis THYS —10— °CV

IN = 5V

Voltage Range VDET 1.0

1.2 —6.0

6.0 VTA = 0°C to +70°C

TA = -40°C to +125°C

RESET Threshold VTH -1.4 — +1.4 %

-2.8 —+2.8 %T

A = -40°C to +125°C

RESET Threshold Tempco ΔVTH/ΔT— 30 — ppm/°C

VDET RESET Delay tRPD —180— µs

VDET = VTH to (VTH – 100 mV),

See Figure 5-3

RESET Active Time-out Period tRPU 140 300 560 ms VDET = VTH - 100 mV to VTH + 100 mV,

ISINK = 1.2 mA, See Figure 5-3.

RESET Output Voltage Low VOL ——0.2 VVDET = VTHmin, ISINK = 1.2 mA,

ISINK = 100 µA for VDET < 1.8V,

See Figure 5-3

RESET Output Voltage High VOH 0.9

VDET —— V

VDET > VTHmax, ISOURCE = 500 µA,

See Figure 5-3

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF,

CBYPASS = 10 nF, SHDN > VIH, TA = +25°C.

Boldface type specifications apply for junction temperatures of -40°C to +125°C.

Parameters Sym Min Typ Max Units Conditions

Note 1: The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT.

2: VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2).

3: TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT).

4: Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested

over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating

effects are covered by the thermal regulation specification.

5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,

excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for

t = 10 ms.

6: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value

measured at a 1V differential.

7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

temperature and the thermal resistance from junction-to-air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power

dissipation causes the device to initiate thermal shutdown.

TC1301A/B

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +6.0V.

Parameters Sym Min Typical Max Units Conditions

Tempe rature Ranges

Operating Junction Temperature

Range TA-40 — +125 °C Steady State

Storage Temperature Range TA-65 — +150 °C

Maximum Junction Temperature TJ— — +150 °C Transient

Thermal Package Resistances

Thermal Resistance, 8LD MSOP θJA — 208 — °C/W Typical 4-Layer Board

Thermal Resistance, 8LD DFN θJA — 41 — °C/W Typical 4-Layer Board with Vias

TC1301A/B

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, R ESET = OPEN, TA = +25°C.

FIGURE 2-1: Quiescent Current vs. Input

Voltage.

FIGURE 2-2: SHDN Voltage Threshold

vs. Input Voltage.

FIGURE 2-3: Quiescent Current vs.

Junction Temperature.

FIGURE 2-4: Output Voltage vs. Input

Voltage.

FIGURE 2-5: Output Voltage vs. Input

Voltage.

FIGURE 2-6: Dropout Voltage vs. Output

Current (VOUT1).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provide d for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specifie d

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

100

150

200

250

300

350

2.73.03.33.63.94.24.54.85.15.45.76.0

Input Voltage (V)

Quiescent Current (µA)

VOUT2 SHDNVOUT2 Active

TJ = 25°C

IOUT1 = IOUT2 = 0 µA

VOUT1 Active

TC1301B

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6

Input Voltage (V)

SHDN Threshold (V)

OFF

100

110

120

130

140

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C )

Quiescent Current (µA)

VIN = 4.2V

IOUT1 = IOUT2 = 0 µA

VOUT1 Active

VOUT2 SHDN

VOUT2 Active TC1301B

2.60

2.70

2.80

2.90

3.00

2.7 3 3.33.63.94.24.54.85.15.45.7 6

Input Voltage (V)

Output Voltage (V)

TJ = 25°C

IOUT1 = 100 mA

IOUT2 = 50 mA

VOUT1

VOUT2

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.7 3 3.33.63.94.24.54.85.15.45.7 6

Input Voltage (V)

Output Voltage (V)

TJ = +25°C

IOUT1 = 300 mA

IOUT2 = 100 mA

VOUT1

VOUT2

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

0 50 100 150 200 250 300

IOUT1 (mA)

Dropout Voltage VOUT1 (mV)

VR1 = 2.8V

VR2 = 2.6V

IOUT2 = 100 µA

TJ = - 40°C

TJ = +25°C

TJ = +125°C

TC1301A/B

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C.

FIGURE 2-7: Dropout Voltage vs.

Junction Temperature (VOUT1).

FIGURE 2-8: Dropout Voltage vs. Output

Current (VOUT2).

FIGURE 2-9: Dropout Voltage vs.

Junction Temperature (VOUT2).

FIGURE 2-10: VOUT1 and VOUT2 Load

Regulation vs. Junc tion Tempera tu re .

FIGURE 2-11: VOUT1 and VOUT2 Line

Regulation vs. Junc tion Tempera tu re .

FIGURE 2-12: VOUT1 vs. Junction

Temperature.

100

120

140

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Dropout Voltage VOUT1 (mV)

VR1 = 2.8V

VR2 = 2.6V

IOUT2 = 100 µA IOUT1 = 300 mA

IOUT1 = 100 mA

IOUT1 = 50 mA

100

120

140

160

180

0 30 60 90 120 150

IOUT2 (mA)

Dropout Voltage, VOUT2 (mv)

VR1 = 2.8V

VR2 = 2.6V

IOUT1 = 100 µA TJ = +125°C

TJ = +25°C

TJ = - 40°C

100

120

140

160

180

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Dropout Voltage VOUT2 (mV)

VR1 = 2.8V

VR2 = 2.6V

IOUT1 = 100 µA

IOUT2 = 150 mA

IOUT2 = 50 mA

IOUT2 = 10 mA

-0.40

-0.30

-0.20

-0.10

0.00

0.10

0.20

0.30

0.40

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperatur e (125°C)

Load Regulation (%)

IOUT2 = 0.1 mA to 150 mA

IOUT1 = 0.1 mA to 300 mA

VR1 = 2.8V

VR2 = 2.6V

VIN = 4.2

VOUT2

VOUT1

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Line Regulation (%/V)

VIN = 3.8V to 6.0V

VR1 = 2.8V, IOUT1 = 100 µA

VR2 = 2.6V, IOUT2 = 100 µA

VOUT1

VOUT2

2.808

2.812

2.816

2.820

2.824

2.828

2.832

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Te mp erature (°C )

Output Voltage VOUT1 (V)

VIN = 4.2V

VR1 = 2.8V

VR2 = 2.6V, IOUT2 = 100 µA

IOUT1 = 300 mA

IOUT1 = 100 µA

IOUT1 = 100 mA

TC1301A/B

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, R ESET = OPEN, TA = +25°C.

FIGURE 2-13: VOUT1 vs. Junction

Temperature.

FIGURE 2-14: VOUT2 vs. Junction

Temperature.

FIGURE 2-15: VOUT2 vs. Junction

Temperature.

FIGURE 2-16: IDET current vs. Junction

Temperature.

FIGURE 2-17: RESET Active Time vs.

Junction Temperature.

FIGURE 2-18: VDET Trip Point vs. Junction

Temperature.

2.808

2.816

2.824

2.832

2.840

2.848

2.856

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Output Voltage VOUT1 (V)

VR1 = 2.8V, IOUT1 = 300 mA

VR2 = 2.6V, IOUT2 = 100 µA

VIN = 6.0V

VIN = 4.2V

VIN = 3.0V

2.615

2.620

2.625

2.630

2.635

2.640

2.645

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Output Voltage VOUT2 (V)

VIN = 4.2V

VR1 = 2.8V, IOUT1 = 100 µA

VR2 = 2.6V

IOUT2 = 150 mA

IOUT2 = 100 µA

IOUT2 = 50 mA

2.624

2.628

2.632

2.636

2.640

2.644

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Te mp erature (°C )

Output Voltage VOUT2 (V)

VR1 = 2.8V, IOUT1 = 100 µA

VR2 = 2.6V, IOUT2 = 150 mA

VIN = 6.0V

VIN = 3.0V

VIN = 4.2V

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C )

IVDET (µA)

VDET = 6.0V

VDET = 4.2V

VDET = 3.0V

VR1 = 2.8V

VR2 = 2.6V

200

225

250

275

300

325

350

375

400

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

RESET Active Time (ms)

VIN = 4.2V

VR1 = 2.8V

VR2 = 2.6V

VDET = 2.63V

2.6355

2.6360

2.6365

2.6370

2.6375

2.6380

2.6385

2.6390

2.6395

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Te mp erature (°C )

VDET Trip Point (V)

VIN = 4.2V

VR1 = 2.8V

VR2 = 2.6V

VDET = 2.63V

TC1301A/B

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C.

FIGURE 2-19: Power Supply Rejection

Ratio vs. Frequency (without bypass capacitor).

FIGURE 2-20: Power Supply Rejection

Ratio vs. Frequency (with bypass capacitor).

FIGURE 2-21: VOUT1 and VOUT2 Noise vs.

Frequency (without bypass capacitor).

FIGURE 2-22: VOUT1 and VOUT2 Noise vs.

Frequency (with bypass capacitor).

FIGURE 2-23: VOUT1 and VOUT2 Power -up

from Shutdown TC1301B.

FIGURE 2-24: VOUT2 Power-up from

Shutdown Input TC13 01 A.

0.01

0.1

0.01 0.1 1 10 100 1000

Frequency (KHz)

NOISE (μV/Hz)

VIN = 4.2V

VR1 = 2.8V

VR2=2.6V

IOUT1 = 150 mA

IOUT2 = 100 mA

CBYPASS = 0 nF

VOUT1

VOUT2

0.001

0.01

0.1

0.01 0.1 1 10 100 1000

Frequency (KHz)

NOISE (μV/Hz)

VIN = 4.2V

VR1 = 2.8V

VR2=2.6V

IOUT1 = 150 mA

IOUT2 = 100 mA

CBYPASS = 10 nF

VOUT1

VOUT2

TC1301A/B

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, R ESET = OPEN, TA = +25°C.

FIGURE 2-25: VOUT1 and VOUT2 Power-up

from Input Voltage TC1301B.

FIGURE 2-26: Dynamic Line Response.

FIGURE 2-27: 300 mA Dynamic Load S tep

VOUT1.

FIGURE 2-28: 150 mA Dynamic Load S tep

VOUT2.

FIGURE 2-29: RESET Power-Up From VIN

TC1301B.

FIGURE 2-30: TC1301A RESET Power-

Down.

TC1301A/B

Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R),

CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH. For the TC1301A, VDET = VOUT1, RESET = OPEN, TA = +25°C.

FIGURE 2-31: RESET Output Voltage Low

vs. Junction Temperature. FIGURE 2-32: RESET Output Voltage High

vs. Junction Temperature.

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

RESET VOL (V)

VR1 = 2.8V,VR2 = 2.6V

VDET = VTH - 20 mV IOL = 3.2 mA

IOL = 1.2 mA

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

-40 -25 -10 5 20 35 50 65 80 95 110 125

Junction Temperature (° C)

RESET VOH (V)

VR1 = 2.8V,VR2 = 2.6V

VDET = VTH + 20 mV

VDET = 4.2V

RESETISOURCE = 800 µA

VDET = 3.0V

RESETISOURCE = 500 µA

TC1301A/B

3.0 TC1301A PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: TC1301A PIN FUNCTION TABLE

3.1 RESET Output Pin

The push-pull output pin is used to monitor the voltage

on the VDET pin. If the VDET voltage is less than the

threshold voltage, the RESET output will be held in the

low state. As the VDET pin rises above the threshold,

the RESET output will remain in the low state for

300 ms and then change to the high state, indicating

that the voltage on the VDET pin is above the threshold.

3.2 Regulated Output Voltage #1

(VOUT1)

Connect VOUT1 to the positive side of the VOUT1

capacitor and load. It is capable of 300 mA maximum

output current. VOUT1 output is available when VIN is

available; there is no pin to turn i t OFF. See TC1301B

if ON/OFF control of VOUT1 is desired.

3.3 Circuit Ground Pin (GND)

Connect GND to the negative side of the input and

output capacitor. Only the LDO internal circuitry bias

current flows out of this pin (200 µA maximum).

3.4 Reference Bypass Input

By connecting an external 10 nF capacitor (typical) to

the bypass input, both outputs (VOUT1 and VOUT2) will

have less noise and improved Power Supply Ripple

Rejection (PSRR) performance. The LDO output

voltage start-up time will increase with the addition of

an external bypass capacitor. By leaving this pin

unconnected, the start-up time will be minimized.

3.5 Output Voltage #2 Shutdown

(SHDN2)

ON/OFF control is performed by connecting SHDN2 to

its proper level. When the input of this pin is connected

to a voltage less than 15% of VIN, VOUT2 will be OFF. If

this pin is connected to a voltage that is greater than

45% of VIN, VOUT2 will be turned ON.

3.6 Regulated Output Voltage #2

(VOUT2)

Connect VOUT2 to the positive side of the VOUT2

capacitor and load. This pin is capable of a maximum

output current of 150 mA. VOUT2 can be turned ON and

OFF using SHDN2.

3.7 Unregulated Input Voltage Pin

(VIN)

Connect the unregulated input voltage source to VIN. If

the input voltage source is located more than several

inches away, or is a battery , a typical input capacitance

of 1 µF to 4.7 µF is recommende d.

3.8 Input Pin for Voltage Detector

(VDET)

The voltage on the input of VDET is compared with the

preset VDET threshold voltage. If the voltage is below

the threshold, the RESET output will be low. If the

voltage is above the VDET threshold, the RESET output

will be high after the RESET time period. The IDET

supply current is typically 9 µA at room temperature,

with VDET =3.8V.

Pin No. Name Function

1 RESET Push-pull output pin that will remain low while VDET is below the reset threshold and for

300 ms after VDET rises ab ove the reset threshold.

OUT1 Regulated output voltage #1 capable of 300 mA.

3 GND Circuit ground pin.

4 Bypass Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce

output noise and improve PSRR performance.

5 SHDN2 Output #2 shutdown control Input.

OUT2 Regulated output voltage #2 capable of 150 mA.

IN Unregulated input voltage pin.

DET Input pin for Voltage Detector (VDET).

TC1301A/B

4.0 TC1301B PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 4-1.

TABLE 4-1: TC1301B PIN FUNCTION TABLE

4.1 RESET Output Pin

The push-pull output pin is used to monitor the output

voltage (VOUT1). If VOUT1 is less than the threshold

voltage, the RESET output will be held in the low state.

As VOUT1 rises above the threshold, the RESET output

will remain in the low state for 300 ms and then change

to the high state, indicating that the voltage on VOUT1 is

above the threshold.

4.2 Regulated Output Voltage #1

(VOUT1)

Connect VOUT1 to the positive side of the VOUT1

capacitor and load. It is capable of 300 mA maximum

output current. For the TC1301B, VOUT1 can be turned

ON and OFF using the SHDN1 input pi n.

4.3 Circuit Ground Pin (GND)

Connect GND to the negative side of the input and

output capacitor. Only the LDO internal circuitry bias

current flows out of this pin (200 µA maximum).

4.4 Reference Bypass Input

By connecting an external 10 nF capacitor (typical) to

bypass, both output s (VOUT1 and VOUT2) will have less

noise and improved Power Supply Ripple Rejection

(PSRR) performance. The LDO output voltage start-up

time will increase with the addition of an external

bypass capacitor. By leaving this pin unconnected, th e

start-up time will be minimized.

4.5 Output Voltage #2 Shutdown

(SHDN2)

ON/OFF control is performed by connecting SHDN2 to

its proper level. When this pin is connected to a voltage

less than 15% of VIN, VOUT2 will be OFF. If this pin is

connected to a voltage that is greater than 45% of VIN,

VOUT2 will be turned ON.

4.6 Regulated Output Voltage #2

(VOUT2)

Connect VOUT2 to the positive side of the VOUT2

capacitor and load. This pin is capable of a maximum

output current of 150 mA. VOUT2 can be turned ON and

OFF using SHDN2.

4.7 Unregulated Input Voltage Pin

(VIN)

Connect the unregulated input voltage source to VIN. If

the input voltage source is located more than several

inches away or is a battery, a typical minimum input

capacitance of 1 µF and 4.7 µF is recommended.

4.8 Output Voltage #1 Shutdown

(SHDN1)

ON/OFF control is performed by connecting SHDN1 to

its proper level. When this pin is connected to a voltage

less than 15% of VIN, VOUT1 will be OFF. If this pin is

connected to a voltage that is greater than 45% of VIN,

VOUT1 will be turned ON.

Pin No. Name Function

1 RESET Push-pull output pin that will remain low while VDET is below the reset threshold and for

300 ms after VOUT1 rises above the reset threshold

OUT1 Regulated output voltage #1 capable of 300 mA

3 GND Circuit ground pin

4 Bypass Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce

output noise and improve PSRR performance

5 SHDN2 Output #2 shutdown control Input

OUT2 Regulated output voltage #2 capable of 150 mA

IN Unregulated input voltage pin

8 SHDN1 Output #1 shutdown control input

TC1301A/B

5.0 DETAILED DESCRIPTION

5.1 Device Overview

The TC1301A/B is a combination device consisting of

one 300 mA LDO regulator with a fixed output voltage,

VOUT1 (1.5V – 3.3V), one 150 mA LDO regulator with a

fixed output voltage, VOUT2 (1.5V – 3.3V), and a

microcontroller voltage monitor/RESET (2.2V to 3.2V).

For the TC1301A, the 300 mA output (VOUT1) is always

present, independent of the level of SHDN2. The

150 mA output (VOUT2) can be turned on/off by

controlling the level of SHDN2.

For the TC1301B, VOUT1 and VOUT2 each have

independent shutdown input pins (SHDN1 and

SHDN2) to control their respective outputs. In the case

of the TC1301B, the voltage detect input of the

microcontroller RESET function is internally connected

to the VOUT1 output of the device.

5.2 LDO Output #1

LDO output #1 is rated for 300 mA of output current.

The typical dropout voltage for VOUT1 = 104 mV @

300 mA. A 1 µF (minimum) output capacitor is needed

for stability and should be located as close to the VOUT1

pin and ground as possible.

5.3 LDO Output #2

LDO output #2 is rated for 150 mA of output current.

The typical dropout voltage for VOUT2 = 150mV. A 1µF

(minimum) capacitor is needed for stability and should

be located as close to the VOUT2 pin and ground as

possible.

5.4 RESET Output

The RESET output is used to detect whether the level

on the input of VDET (TC1301A) or VOUT1 (TC1301B) is

above or below a preset threshold. If the voltage

detected is below the preset threshold, the RESET

output is capable of sinking 1.2 mA (VRESET < 0.2V

maximum). Once the voltage being monitored is above

the preset threshold, the RESET output pin will

transition from a logic-low to a logic-high after a 300 ms

delay. The RESET output is a push-pull configuration

and will actively pull the RESET output up to VDET

when not in RES ET.

5.5 Input Capacitor

Low input source impedance is necessary for the two

LDO outputs to operate properly. When operating from

batteries or in applications with long lead length

(> 10 inches) between the input source and the LDO,

some input capacitance is recommended. A minimum

of 1.0 µF to 4.7 µF is recommended for most applica-

tions. When using large capacitors on the LDO outputs,

larger capacitance is recommended on the LDO input.

The capacitor should be placed as close to the input of

the LDO as is practical. Larger input capacitors will help

reduce the input impedance and further reduce any

high-frequency noise on the input and output of the

LDO.

5.6 Output Capacitor

A minimum output capacitance of 1 µF for each of the

TC1301A/B LDO outputs is necessary for stability.

Ceramic capacitors are recommended because of their

size, cost and environmental robustness qualities.

Electrolytic (Tantalum or Aluminum) capacitors can be

used on the LDO outputs as well. The Equivalent

Series Resistance (ESR) requirements on the

electrolytic output capacitors are between 0 and 2

ohms. The output capacitor should be located as close

to the LDO output as is practical. Ceramic materials,

X7R and X5R, have low temperature coefficients and

are well within the acceptable ESR range required. A

typical 1 uF X5R 0805 capacitor has an ESR of 50 milli-

ohms. Larger LDO output capacitors can be used with

the TC1301A/B to improve dynamic performance and

power supply ripple rejection performance. A maximum

of 10 µF is recommended. Aluminum electrolytic

capacitors are not recommended for low temperature

applications of < -25°C.

5.7 Bypass Input

The bypass pin is connected to the internal LDO

reference. By adding capacitance to this pin, the LDO

ripple rejection, input voltage transient response and

output noise performance are all increased. A typical

bypass capacitor between 470 pF to 10 nF is

recommended. Larger bypass capacitors can be used,

but results in a longe r time-perio d for the LDO outputs

to reach their rated output voltage when started from

SHDN or VIN.

5.8 GND

For the optimal noise and PSRR performance, the

GND pin of the TC1301A/B should be tied to a quiet

circuit ground. For applications that have switching or

noisy inputs, tie the GND pin to the return of the output

capacitor. Ground planes help lower inductance and

voltage spikes caused by fast transient load currents

and are recommended for applications that are

subjected to fast load transients.

5.9 SHDN1/SHDN2 Operation

The TC1301A SHDN2 pin is used to turn VOUT2 ON

and OFF. A logic-hig h level on SHDN2 will enable the

VOUT2 output, while a logic-low on the SHDN2 pin wi ll

disable the VOUT2 output. For the TC1301A, VOUT1 is

not affected by SHDN2 and will be enabled as lon g as

the input voltage is present.

The TC1301B SHDN1 and SHDN2 pins are used to

turn VOUT1 and VOUT2 ON and OFF. They operate

independent of each other.

TC1301A/B

5.10 TC1301A SHDN2 Timing

VOUT1 will rise independent of the level of SHDN2 for

the TC1301A. Figure 5-1 is used to define the wake-up

time from shutdown (tWK) and the settling time (tS). The

wake-up time is dependant upon the frequency of

operation. The faster the SHDN pin is pulsed, the

shorter the wake-up time will be.

FIGURE 5-1: TC1301A Timing.

5.11 TC1301B SHDN1 / SHDN2 Timing

For the TC1301B, the SHDN1 input pin is used to

control VOUT1. The SHDN2 input pin is used to control

VOUT2, independent of the logic input on SHDN1.

FIGURE 5-2: TC1301B Timing.

5.12 VDET and RESET Operation

The TC1301A/B integrates an independent voltage

reset monitor that can be used for low-battery input

voltage detection or a microprocessor Power-On Reset

(POR) function. The input voltage for the detector is

different for the TC1301A than it is for the TC1301B.

For the TC1301A, the input voltage to the detector is

pin 8 (VDET). For the TC1301B, the input voltage to the

detector is internally connected to the output of LDO #1

(VOUT1). The detected voltage is sensed and com-

pared to an internal threshold. When the voltage on the

VDET pin is below the threshold voltage, the RESET

output pin is low. When the voltage on the VDET pin

rises above the voltage threshold, the RESET output

will remain low for typically 300 ms (RESET time-out

period). After the RESET time-out period, the RESET

output voltage will transition from the low output state

to the high output state if the detected voltage pin

remains above the threshold voltage.

The RESET output will be driven low within 180 µs of

VDET going below the RESET voltage threshold. The

RESET output will remain valid for detected voltages

greater than 1.2V overtemperature.

5.13 TC1301A RESET Timing

Figure 5-3 shows the RESET timing waveforms for the

TC1301A. This diagram is also used to define the

RESET active time-out period (tRPU) and the VDET

RESET delay time (tRPD).

FIGURE 5-3: TC1301A RESET Timing.

VIN

SHDN2

VOUT1

VOUT2

twk

SHDN2

SHDN1

VIN

VOUT1

twk

VOUT2

RESET Time

TRPD

VTH

VDET

RESET

1V VOL

VOH

TC1301A/B

5.14 TC1301B RESET Timing

The timing waveforms for the TC1301B RESET output

are shown in Figure 5-4. Note that the RESET

threshold input for the TC1301B is VOUT1. Th e VOUT1

to RESET threshold detector connection is made

internal in the case of the TC1301B.

FIGURE 5-4: TC1301B RESET Timing.

5.15 Device Protection

5.15.1 OVERCURRENT LIMIT

In the event of a faulted output load, the maximum

current the LDO output will permit to flow is limited

internally for each of the TC1301A/B outputs. The peak

current limit for VOUT1 is typically 1.1A, while the peak

current limit for VOUT2 is typically 0.5A. During short-

circuit operation, the average current is limited to

200 mA for VOUT1 and 140 mA for VOUT2.The VDET

and RESET circuit will continue to operate in the event

of an overcurrent on either output for the TC1301A.

The voltage detect and RESET circuit will continue to

operate in the event of an overcurrent on VOUT1 (or

VOUT2) for the TC1301B. In the event of an overcurrent

on VOUT1, the RESET will detect the absence of VOUT1.

5.15.2 OVERTEMPERATURE

PROTECTION

If the internal power diss ipation within the TC1301A/B

is excessive due to a faulted load or higher-than-

specified line voltage, an internal temperature-sensi ng

element will prevent the junction temperature from

exceeding approximately 150°C. If the junction

temperature does reach 150°C, both outputs will be

disabled until the junction temperature cools to

approximately 140°C. The device will resume normal

operation. If the internal power dissipation continues to

be excessive, the device will again shut off. The VDET

and RESET circuit will continue to operate normally

during an overtemperature fault condition for both the

TC1301A and TC1301B.

RESET Time TRPD

VTH

VOUT1

RESET

1V VOL

VOH

VIN

TC1301A/B

6.0 APPLICATION CIRCUITS/

ISSUES

6.1 Typical Application

The TC1301A/B is used for applications that require

the integration of two LDO’s and a microcontroller

RESET.

FIGURE 6-1: Typical Application Circuit

TC1301A/B.

6.1.1 APPLICATION INPUT CONDITIONS

6.2 Power Calculations

6.2.1 POWER DISSIPATION

The internal power dissipation within the TC1301A/B is

a function of input voltage, output voltage, output

current and quiescent current. The following equation

can be used to calculate the internal power dissipation

for each LDO.

EQUATION 6-1:

In addition to the LDO pass element power dissipation,

there is power dissipation within the TC1301A/B as a

result of quiescent or ground current. The power

dissipation as a result of the ground current can be

calculated using the following equation. The VIN pin

quiescent current and the VDET pin current are both

considered. The VIN current is a result of LDO

quiescent current, while the VDET current is a result of

the voltage detector current.

EQUATION 6-2:

The total power dissipated within the TC1301A/B is the

sum of the power dissipated in both of the LDO’s and

the P(IGND) term. Because of the CMOS construction,

the typical IGND for the TC1301A/B is 116 µA.

Operating at a maximum of 4.2V results in a power

dissipation of 0.5 milliW att s. For most applications, this

is small compared to the LDO pass device power

dissipation and can be neglected.

The maximum continuous operating junction

temperature specified for the TC1301A/B is 125°C. To

estimate the internal junction temperature of the

TC1301A/B, the total internal power dissipation is

multiplied by the thermal resistance from junction to

ambient (RθJA) of the device. The thermal resistance

from junction to ambient for the 3x3 DFN8 pin package

is estimated at 41°C/W.

Package Type = 3x3 DFN8

Input Voltage Range = 2.7V to 4.2V

VIN maximum = 4.2V

VIN typical = 3.6V

VOUT1 = 300 mA maximum

VOUT2 = 150 mA maximum

System RESET Load = 10 kΩ

RESET

GND

VDET BATTERY

COUT1

1µF Ceramic

X5R

CIN

1µF

TC1301A

COUT2

1 µF Ceramic

X5R

Cbypass

10 nF Ceramic

Bypass

VIN 7

2.7V

4.2V

VOUT2 6

SHDN2

ON/OFF Control VOUT2

System RESET

2.8V @ 300 mA 1.8V

VOUT1

RESET BATTERY

COUT1

1 µF Ceramic

X5R

CIN

1µF

TC1301B

COUT2

1µF Ceramic

X5R

Bypass

VIN 7

2.7V

4.2V

VOUT2 6

SHDN2

ON/OFF Control VOUT2

System RESET

2.8V @ 300 mA 1.8V

ON/OFF Control VOUT1

VOUT1 @ 150 mA

GND @ 150 mA

SHDN1

PLDO VIN MAX)()

VOUT MIN()

–()IOUT MAX)()

×=

Where:

PLDO = LDO Pass device internal power

dissipation

VIN(MAX) = Maximum input voltage

VOUT(MIN) = LDO minimum output voltage

PIGND()

VIN MAX()

IVIN IVDET

+()×=

Where:

PI(GND) = Total current in ground pin

VIN(MAX) = Maximum input voltage

IVIN = Current flowing in the VIN pin with

no output current on either LDO

output

IVDET = Current in the VDET pin with

RESET loaded

TC1301A/B

EQUATION 6-3:

The maximum power dissipation capability for a

package can be calculated given the junction to

ambient thermal resistance and the maximum ambient

temperature for the application. The following equation

can be used to determine the package maximum

internal power dissipation.

EQUATION 6-4:

EQUATION 6-5:

EQUATION 6-6:

6.3 Typical Application

Internal power dissipation, junction temperature rise,

junction temperature, and ma ximum power dissipation

are calculated in the following example. The power

dissipation as a result of ground current is small

enough to be neglected.

6.3.1 POWER DISSIPATION EXAMPLE

Device Junctio n Temperature Rise

The internal junction temperature rise is a function of

internal power dissipation and the thermal resistance

from junction to ambient for the application. The

thermal resistance from junction to ambient (RθJA) is

derived from an EIA/JEDEC standard for measuring

thermal resistance for small surface-mount packages.

The EIA/JEDEC specification is JESD51-7, “High

Effective Thermal Conductivity Test Board for Leaded

Surface Mount Packages”. The standard describes the

test method and board specifications for measuring the

thermal resistance from junction to ambient. The actual

thermal resistance for a particular application can vary

depending on many factors such as copper area and

thickness. Refer to AN792, “A Method To Determine

How Much Power a SOT-23 Can Dissipate in Your

Application” (DS00792), for more information regarding

this subject.

TJMAX()

PTOTAL RθJA

×TAMAX

Where:

TJ(MAX) = Maximum continuous junction tem-

perature

PTOTAL = Total device power dissipation

RθJA = Thermal resistance from junction-

to-ambient

TAMAX = Maximum ambient temperature

PDMAX()

TJMAX()

TAMAX()

–()

RθJA

---------------------------------------------------=

Where:

PD(MAX) = Maximum device power

dissipation

TJ(MAX) = Maximum continuous junction

temperature

TAMAX = Maximum ambient temperature

RθJA = Thermal resistance from junction-

to-ambient

TJRISE()

PDMAX()

RθJA

×=

Where:

TJ(RISE) = Rise in device junction

temperat ure over the ambient

temperature

PD(MAX) = Maximum device power

dissipation

RθJA = Thermal resistance from junction-

to-ambient

TJTJRISE()

Where:

TJ= Junction Temperature

TJ(RISE) = Rise in device junction

temperat ure over the ambient

temperature

TA= Ambient Temperature

Package

Package Type = 3x3 DFN8

Input Voltage

VIN = 2.7V to 4.2V

LDO Output Voltages and Currents

VOUT1 = 2.8V

IOUT1 = 300 mA

VOUT2 = 1.8V

IOUT2 = 150 mA

Maximum Ambient Temperature

TA(MAX) = 50°C

Internal Power Dissipation

Internal power dissipation is the sum of the power

dissipation for each LDO pass device.

PLDO1(MAX) =(V

IN(MAX) - VOUT1(MIN)) x

IOUT1(MAX)

PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA

PLDO1 = 441.0 milliWatts

PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA

PLDO2 = 366.8 milliWatts

PTOTAL =P

LDO1 + PLDO2

PTOTAL= 807.8 milliWatts

TJ(RISE) =P

TOTAL x RqJA

TJRISE = 807.8 milliWatts x 41.0° C/W

TJRISE =33.1°C

TC1301A/B

Junction Temperature Estimate

To estimate the internal junction temperature, the

calculated temperature rise is added to the ambie nt or

offset temperature. For this example, the worst-case

junction temperature is estimated below:

Maximum Package Power Dissipation at 50°C

Ambient Temperature

7.0 TYPICAL LAYOUT TC1301A

FIGURE 7-1: MSOP8 Silk Screen Layer.

When doing the physical layout for the TC1301A/B, the

highest priority is placing the input and output

capacitors as close to the device pins as is practical.

Figure 7-1 above represents a typical placement of the

components when using SMT0805 capacitors.

FIGURE 7-2: MSOP8 Wiring Layer.

A wiring example for the TC1301A is shown. The vias

represent the connection to a ground plane that is

below the wiring layer.

FIGURE 7-3: 3x3 DFN Silk-Screen

Example.

8-lead 3X3 DFN physical layout example with bypass

capacitor.

FIGURE 7-4: 3x3 DFN Top Metal Layer

Example.

Vias represent the connection to a ground plane that is

below the wiring layer.

8.0 ADDITIONAL OUTPUT

VOLTAGE AND THRESHOLD

VOLTAGE OPTIONS

8.1 Output Voltage and Threshold

Voltage Range

Table 8-1 describes the range of output voltage options

available for the TC1301A/B. VOUT1 and VOUT2 can be

factory preset from 1.5V to 3.3V in 100 mV increments.

The VDET (TC1301A) or threshold voltage (TC1301B)

can be preset from 2.2V to 3.2V in 10 mV increments.

TABLE 8-1: CUSTOM OUTPUT VOLTAGE

AND THRESHOLD VOLTAGE

RANGES

For a listing of TC1301A/B standard parts, refer to the

Product Identification System on page 25.

TJ =T

JRISE + TA(MAX)

TJ = 83.1°C

3X3DFN8 (41° C/W RθJA)

PD(MAX) = (125°C - 50°C) / 41° C/W

PD(MAX) = 1.83 Watts

MSOP8 (208° C/W RθJA)

PD(MAX) = (125°C - 50°C) / 208° C/W

PD(MAX) = 0.360 Watt s

VOUT1 VOUT2 VDET Threshold

1.5V to 3.3V 1.5V to 3.3V 2.2V to 3.2V

TC1301A/B

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

X1 represents VOUT1 configuration:

X2 represents VOUT2 configuration:

Xr represents the reset voltage range:

For a listing of TC1301A/B standard parts, refer to the

Product Identification System section on page 25.

8-Lead MSOP

XXXXXX

YWWNNN

Example:

AFHA

0435

256

Example:

31AFHA

435256

8-Lead DFN

XXXX

YYWW

NNN

— 31A = TC1301A

— F = 2.8V VOUT1

— H = 2.6V VOUT2

— A = 2.63V Reset

Code VOUT1 Code VOUT1 Code VOUT1

A3.3VJ2.4VS1.5V

B3.2VK2.3VT1.65V

C 3.1V L 2.2V U 2.85V

D 3.0V M 2.1V V 2.65V

E 2.9V N 2.0V W 1.85V

F 2.8V O 1.9V X —

G2.7VP1.8VY —

H 2.6V Q 1.7V Z —

I 2.5V R 1.6V

Code VOUT2 Code VOUT2 Code VOUT2

A3.3VJ2.4VS1.5V

B3.2VK2.3VT1.65V

C 3.1V L 2.2V U 2.85V

D 3.0V M 2.1V V 2.65V

E 2.9V N 2.0V W 1.85V

F 2.8V O 1.9V X —

G2.7VP1.8VY —

H 2.6V Q 1.7V Z —

I 2.5V R 1.6V

Code Voltage Code Voltage

A2.63VJ —

B2.2VK —

C2.32VL —

D2.5VM —

E2.4VN —

F2.6VO —

G—P—

H—Q—

I—R—

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 dig its of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

TC1301A/B

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5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

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KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

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1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

NOTE 1

L1 L

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

TC1301A/B

"#$#%&'&'*+,-3"#

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 3DFNDJHLVVDZVLQJXODWHG

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6WDQGRII $   

&RQWDFW7KLFNQHVV $ 5()

2YHUDOO/HQJWK ' %6&

([SRVHG3DG:LGWK (  ± 

2YHUDOO:LGWK ( %6&

([SRVHG3DG/HQJWK '  ± 

&RQWDFW:LGWK E   

&RQWDFW/HQJWK /   

&RQWDFWWR([SRVHG3DG .  ± ±

BOTTOM VIEW

TOP VIEW

NOTE 1

EXPOSED PAD

NOTE 1

NOTE 2

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

TC1301A/B

APPENDIX A: REVISION HISTORY

Revision C (February 2008)

The following is the list of modificatio ns.

1. Updated Section 9.0 “Packaging Informa-

tion”.

Revision B (January 2005)

The following is the list of modificatio ns.

1. Corrected the incorrect part number options

shown on the Product Identification System

page and changed the “standard” output voltage

and reset voltage combinations.

2. Added Appendix A: Revision History.

Revision A (September 2003)

• Original data sheet release.

TC1301A/B

NOTES:

TC1301A/B

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: TC1301A: Dual LDO with microcontroller RESET function

and single shutdown input.

TC1301B: Dual LDO with microcontroller RESET function

and dual shutdown inpu ts.

Standard

Configurations: * VOUT1/VOUT2/Reset Configuration

Code

TC1301A 3.3 / 3.0 / 2.63

3.3 / 1.8 / 2.63

3.0 / 2.8 / 2.63

3.0 / 1.8 / 2.63

2.8 / 3.0 / 2.63

2.8 / 2.6 / 2.63

1.8 / 2.8 / 2.32

1.5 / 2.8 / 2.32

2.85 / 1.85 / 2.63

ADA

APA

DFA

DPA

FDA

FHA

PFC

SFC

UWA

TC1301B 3.3 / 3.0 / 2.63

3.3 / 1.8 / 2.63

3.0 / 2.8 / 2.63

3.0 / 1.8 / 2.63

2.8 / 3.0 / 2.63

2.8 / 2.6 / 2.63

2.7 / 2.8 / 2.5

2.7 / 3.0 / 2.50

2.85 / 1.85 / 2.63

ADA

APA

DFA

DPA

FDA

FHA

GFD

GDD

UWA

* Contact Factory for Alte rnate Output Voltage and Reset

Voltage Configurations.

Temperature Range: V = -40°C to +125 °C

Package: MF = Dual Flat, No Lead (3x3 mm body), 8-lead

UA = Plastic Micro Small Outline (MSOP), 8-lead

Tube or

Tape and Reel: Blank = Tube

TR = Tape and Reel

Examples:

a) TC1301A-ADAVUA: 3.3, 3.0, 2.63,

MSOP pkg.

b) TC1301A-APAVMFTR: 3.3 , 1.8, 2.63,

8LD DFN pkg.

Tape and Reel

c) TC1301A-DFAVUATR: 3.0, 2.8 , 2.63,

MSOP pkg.

Tape and Reel

d) TC1301A-DPAVMF: 3.0, 1.8 , 2.63,

8LD DFN pkg.

e) TC1301A-FDAVMF: 2.8, 3.0, 2.63,

8LD DFN pkg.

f) TC1301A-FHAVMF: 2.8, 2.6, 2.63,

DFN pkg.

g) TC1301A-PFCVUA: 1.8, 2.8, 2.32,

MSOP pkg.

h) TC1301A-SFCVMFTR: 1.5, 2.8, 2.32,

DFN pkg.

Tape and Reel

i) TC1301A-UWAVUATR: 2.85, 1.85, 2.63,

MSOP pkg.

Tape and Reel

a) TC1301B-ADAVMF: 3.3, 3.0, 2.63,

8LD DFN pkg.

b) TC1301B-APAVMFTR: 3.3, 1.8, 2.63,

8LD DFN pkg.

Tape and Reel

c) TC1301B-DFAVUA: 3.0, 2.8, 2.63,

MSOP pkg.

d) TC1301B-DPAVUATR: 3.0, 1.8 ,2.63,

MSOP pkg.

Tape and Reel

e) TC1301B-FDAVMF: 2.8 ,3.0, 2.63,

8LD DFN pkg.

f) TC1301B-FHAVMFTR: 2.8, 2.6 ,2.63,

8LD DFN pkg.

Tape and Reel

g) TC1301B-GDDVUA: 2.7, 3.0, 2.50,

MSOP pkg.

h) TC1301B-GFDVMF: 2.7, 2.8, 2.5,

8LD DFN pkg.

i) TC1301B-UWAVUATR: 2.85, 1.85, 2.63,

MSOP pkg.

Tape and Reel

PART NO. X- X

VOUT1

Type

A/B

TC1301

VOUT2

Reset

Voltage

Temp

Range

Package

Tube

Tape &

Reel

Standard

Configurations

TC1301A/B

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defen d, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICST ART, PRO MA TE, rfPIC and SmartShunt are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Te chnology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts

allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:200 2 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in Californi a

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and

analog product s. In addition, Microchip ’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

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01/02/08