Order Now Product Folder Technical Documents Support & Community Tools & Software LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 LMV34x-N Single Rail-to-Rail Output CMOS Operation Amplifier With Shutdown 1 Features 3 Description * The LMV34x-N devices are single, dual, and quad low-voltage, low-power operational amplifiers. They are designed specifically for low-voltage portable applications. Other important product characteristics are low input bias current, rail-to-rail output, and wide temperature range. 1 * * * * * * * * Typical 2.7 V Supply Values (Unless Otherwise Noted) Ensured 2.7 V and 5 V Specifications Input Referred Voltage Noise at 10 kHz: 29 nV/Hz Supply Current (Per Amplifier): 100 A Gain Bandwidth Product: 1 MHz Slew Rate: 1 V/s Shutdown Current (LMV341-N): 45 pA Turnon Time From Shutdown (LMV341-N): 5 s Input Bias Current: 20 fA 2 Applications * * * * * * * * * * Cordless or Cellular Phones Laptops PDAs PCMCIA or Audio Portable or Battery-Powered Electronic Equipment Supply Current Monitoring Battery Monitoring Buffers Filters Drivers Sample and Hold Circuit V + V + - VIN + + VOUT The patented class AB turnaround stage significantly reduces the noise at higher frequencies, power consumption, and offset voltage. The PMOS input stage provides the user with ultra-low input bias current of 20 fA (typical) and high input impedance. The industrial-plus temperature range of -40C to 125C allows the LMV34x-N to accommodate a broad range of extended environment applications. LMV341-N expands Texas Instrument's Silicon Dust amplifier portfolio offering enhancements in size, speed, and power savings. The LMV34x-N devices are specified to operate over the voltage range of 2.7 V to 5.5 V and all have rail-to-rail output. The LMV341-N offers a shutdown pin that can be used to disable the device. Once in shutdown mode, the supply current is reduced to 45 pA (typical). The LMV34x-N devices have 29-nV voltage noise at 10 KHz, 1 MHz GBW, 1-V/s slew rate, 0.25 mVos, and 0.1-A shutdown current (LMV341-N). The LMV341-N is offered in the tiny 6-pin SC70 package, the LMV342-N in space-saving 8-pin VSSOP and SOIC packages, and the LMV344-N in 14-pin TSSOP and SOIC packages. These small package amplifiers offer an ideal solution for applications requiring minimum PCB footprint. Applications with area constrained PCB requirements include portable electronics such as cellular handsets and PDAs. Device Information(1) C = 200pF SAMPLE CLOCK PART NUMBER LMV341-N Copyright (c) 2016, Texas Instruments Incorporated LMV342-N LMV344-N PACKAGE BODY SIZE (NOM) SC70 (6) 2.00 mm x 1.25 mm VSSOP (8) 3.00 mm x 3.00 mm SOIC (8) 4.90 mm x 3.91 mm TSSOP (14) 5.00 mm x 4.40 mm SOIC (14) 8.64 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 5 5 5 5 6 7 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics - 2.7 V (DC) ..................... Electrical Characteristics - 2.7 V (AC)...................... Electrical Characteristics - 5 V (DC) ........................ Electrical Characteristics - 5 V (AC)......................... Typical Characteristics .............................................. Detailed Description ............................................ 16 7.1 Overview ................................................................. 16 7.2 Functional Block Diagram ....................................... 16 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 21 21 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (March 2013) to Revision H Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Changed Thermal Information table ....................................................................................................................................... 5 Changes from Revision F (March 2012) to Revision G * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 5 Pin Configuration and Functions DCK Package 6-Pin SC70 Top View 1 6 +IN V 2 + + GND 5 SHDN 4 OUT - -IN 3 Pin Functions - LMV341-N PIN NAME NO. +IN 1 -IN GND TYPE (1) DESCRIPTION I Noninverting input 3 I Inverting input 2 P Negative supply input OUT 4 O Output + V 6 P Positive supply input SHDN 5 I Active low enable input (1) I = Input, O = Output, and P = Power DGK or D Package 8-Pin VSSOP or SOIC Top View Pin Functions - LMV342-N PIN TYPE (1) DESCRIPTION NAME NO. IN A+ 3 I Noninverting input, channel A - IN A 2 I Inverting input, channel A IN B+ 5 I Noninverting input, channel B IN B- 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 P Positive (highest) power supply V- 4 P Negative (lowest) power supply (1) I = Input, O = Output, and P = Power Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 3 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com PW or D Package 14-Pin TSSOP or SOIC Top View Pin Functions - LMV344-N PIN TYPE (1) DESCRIPTION NAME NO. IN A+ 3 I Noninverting input, channel A IN A- 2 I Inverting input, channel A IN B+ 5 I Noninverting input, channel B IN B- 6 I Inverting input, channel B IN C 10 I Noninverting input, channel C IN C- 9 I Inverting input, channel C IN D+ 12 I Noninverting input, channel D - IN D 13 I Inverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V+ 4 P Positive (highest) power supply V- 11 P Negative (lowest) power supply + (1) 4 I = Input, O = Output, and P = Power Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Differential input voltage MAX Supply voltage (V + - V -) 6 Output short circuit to V + See (3) Output short circuit to V - See (4) Lead temperature 235 Wave soldering (10 s) 260 Storage temperature, Tstg (2) (3) (4) (5) V Infrared or convection reflow (20 s) Junction temperature, TJ (5) (1) UNIT Supply voltage -65 C 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Shorting output to V+ will adversely affect reliability. Shorting output to V- will adversely affect reliability. The maximum power dissipation is a function of TJ(MAX), RJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM) (1) 2000 Machine model (MM) (2) 200 UNIT V Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22C101-C (ESD FICDM std. of JEDEC). 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage 2.7 5.5 UNIT V Temperature -40 125 C 6.4 Thermal Information LMV341-N THERMAL METRIC (1) LMV342-N LMV344-N DCK (SC70) D (SOIC) DGK (VSSOP) D (SOIC) PW (TSSOP) 6 PINS 8 PINS 8 PINS 14 PINS 14 PINS 414 190 235 145 155 C/W UNIT RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance 116.1 65.2 68.4 45.9 50.5 C/W RJB Junction-to-board thermal resistance 53.3 61.4 98.8 44.1 66.2 C/W JT Junction-to-top characterization parameter 8.8 16.1 9.8 10.2 6.3 C/W JB Junction-to-board characterization parameter 52.7 60.8 97.3 43.7 65.6 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- -- -- -- C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 5 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com 6.5 Electrical Characteristics - 2.7 V (DC) TJ = 25C, V+ = 2.7 V, V- = 0 V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 M (unless otherwise noted) (1) PARAMETER TEST CONDITIONS LMV341-N VOS Input offset voltage LMV342-N and LMV344-N TCVOS Input offset voltage average drift IB Input bias current IOS Input offset current Supply current 0.25 -40C TJ 125C TJ = 25C 0.55 -40C TJ 125C 0.02 TJ = 25C 100 -40C TJ 125C TJ = 25C 56 -40C TJ 125C 50 TJ = 25C 65 -40C TJ 125C 60 2.7 V V+ 5 V VCM Input common-mode voltage For CMRR 50 dB RL = 10 k to 1.35 V Large signal voltage gain RL = 2 k to 1.35 V 4.5 x 10 -40C TJ 125C Output swing V+ Turnon time from shutdown VSD (1) (2) (3) 6 Shutdown pin voltage 120 pA fA 170 1 80 A dB 82 1.9 0 -0.2 TJ = 25C 78 113 -40C TJ 125C 70 TJ = 25C 72 -40C TJ 125C 64 V- dB 1.7 24 V dB 103 -40C TJ 125C 60 95 TJ = 25C 60 -40C TJ 125C 95 TJ = 25C RL = 10 k to 1.35 V ton V/C 1.5 TJ = 25C RL = 2 k to 1.35 V mV 230 -5 TJ = 25C Power supply rejection ratio Output short-circuit current 5 250 Shutdown mode, VSD = 0 V, LMV341-N PSRR IO 4 6.6 0 V VCM 1.7 V, 0 V VCM 1.6 V UNIT 5.5 -40C TJ 150C Common-mode rejection ratio VO MAX (2) 4.5 TJ = 25C CMRR AV TJ = 25C TYP (3) 1.7 Per amplifier IS MIN (2) 26 5 -40C TJ 125C 30 mV 40 TJ = 25C 30 -40C TJ 125C 40 5.3 Sourcing, LMV341-N and LMV342-N 20 32 Sourcing, LMV344-N 18 24 Sinking 15 24 2.4 1.7 2.7 0 1 0.8 LMV341-N mA 5 ON mode, LMV341-N Shutdown mode, LMV341-N s V Electrical characteristic values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 6.6 Electrical Characteristics - 2.7 V (AC) TJ = 25C, V+ = 2.7V, V- = 0V, VCM = V+/ 2, VO = V+/ 2, and RL > 1 M (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) (4) MAX (2) UNIT SR Slew rate RL = 10 k GBW Gain bandwidth product RL = 100 k, CL = 200 pF m Phase margin RL = 100 k 72 Gm Gain margin RL = 100 k 20 dB en Input-referred voltage noise f = 1 kHz 40 nV/Hz in Input-referred current noise f = 1 kHz 0.001 pA/Hz Total harmonic distortion f = 1 kHz, AV = +1, RL = 600 , VIN = 1VPP THD (1) (2) (3) (4) 1 V/s 1 MHz 0.017% Electrical characteristic values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates. 6.7 Electrical Characteristics - 5 V (DC) TJ = 25C, V+ = 5 V, V- = 0 V, VCM = V+/ 2, VO = V+/ 2, and R L > 1 M (unless otherwise noted) (1) PARAMETER TEST CONDITIONS LMV341-N VOS Input offset voltage LMV342-N and LMV344-N TCVOS Input offset voltage average drift IB Input bias current IOS Input offset current Supply current UNIT 4.5 TJ = 25C 0.7 -40C TJ 125C mV 5 5.5 0.02 V/C 200 375 TJ = 25C 107 -40C TJ 125C TJ = 25C TJ = 25C 56 -40C TJ 125C 50 TJ = 25C 65 -40C TJ 125C 60 Power supply rejection ratio 2.7 V V+ 5 V VCM Input common-mode voltage For CMRR 50 dB RL = 10 k to 2.5 V Large signal voltage gain (4) RL = 2 k to 2.5 V 0.033 -40C TJ 125C fA 200 1 A 1.5 V+ 86 dB 82 4.2 0 -0.2 TJ = 25C 78 116 -40C TJ 125C 70 TJ = 25C 72 -40C TJ 125C 64 V- pA 260 Shutdown mode, VSD = 0 V, LMV341-N PSRR (4) 4 6.6 0 V VCM 4 V, 0 V VCM 3.9 V (2) (3) 0.025 -40C TJ 125C Common-mode rejection ratio (1) MAX (2) -40C TJ 125C TJ = 25C CMRR AV TJ = 25C TYP (3) 1.9 Per amplifier IS MIN (2) dB 4 107 V dB Electrical characteristic values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. RL is connected to mid-supply. The output voltage is GND + 0.2 V VO V+- 0.2 V Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 7 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com Electrical Characteristics - 5 V (DC) (continued) TJ = 25C, V+ = 5 V, V- = 0 V, VCM = V+/ 2, VO = V+/ 2, and R L > 1 M (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) 32 60 TJ = 25C -40C TJ 125C RL = 2 k to 2.5 V VO Output swing IO Output short-circuit current ton Turnon time from shutdown VSD Shutdown pin voltage 95 TJ = 25C 60 -40C TJ 125C 95 34 TJ = 25C 7 -40C TJ 125C RL = 10 k to 2.5 V UNIT 30 mV 40 TJ = 25C 30 -40C TJ 125C 40 7 Sourcing 85 113 Sinking 50 75 4.5 3.1 5 0 1 0.8 LMV341-N mA 5 ON mode, LMV341-N Shutdown mode, LMV341-N s V 6.8 Electrical Characteristics - 5 V (AC) TJ = 25C, V+ = 5 V, V- = 0 V, VCM = V+/ 2, VO = V+/ 2 and R L > 1 M (unless otherwise noted) (1) PARAMETER CONDITIONS MIN (2) TYP (3) MAX (2) UNIT (4) 1 V/s 1 MHz deg SR Slew rate RL = 10 k GBW Gain-bandwidth product RL = 10 k, CL = 200 pF m Phase margin RL = 100 k 70 Gm Gain margin RL = 100 k 20 dB en Input-referred voltage noise f = 1 kHz 39 nV/Hz in Input-referred current noise f = 1 kHz 0.001 pA/Hz Total harmonic distortion f = 1 kHz, AV = +1, RL = 600 , VIN = 1VPP THD (1) (2) (3) (4) 8 0.012% Electrical characteristic values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 6.9 Typical Characteristics 1000 150 VS = 5 V 140 130 125C INPUT CURRENT (pA) SUPPLY CURRENT (PA) 100 85C 120 110 100 90 80 25C 10 1 .1 70 .01 -40C 60 .001 -40 -20 50 2.5 3 3.5 4.5 4 SUPPLY VOLTAGE (V) 5 7.0 34 RL = 10k: RL = 2k: 6.5 OUTPUT VOLTAGE FROM SUPPLY VOLTAGE (mV) OUTPUT VOLTAGE FROM SUPPLY VOLTAGE (mV) 32 30 NEGATIVE SWING 26 24 POSITIVE SWING 22 20 2.5 6.0 POSITIVE SWING 5.5 5.0 4.5 NEGATIVE SWING 4.0 3.5 3.0 3 3.5 4 4.5 SUPPLY VOLTAGE (V) 2.5 5 Figure 3. Output Voltage Swing vs Supply Voltage 100 VS = 2.7 V -40C 3.5 3 5 4.5 4 SUPPLY VOLTAGE (V) Figure 4. Output Voltage Swing vs Supply Voltage 100 25C VS = 5V 10 10 125C 1 85C 0.1 ISOURCE (mA) ISOURCE (mA) 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 2. Input Current vs Temperature Figure 1. Supply Current vs Supply Voltage (LMV341-N) 28 0 -40C 85C 125C 1 25C 0.1 0.01 0.001 0.001 0.01 1 10 0.1 + OUTPUT VOLTAGE REFERENCED TO V (V) Figure 5. ISOURCE vs VOUT 0.01 0.001 0.01 0.1 10 1 + OUTPUT VOLTAGE REFERENCED TO V (V) Figure 6. ISOURCE vs VOUT Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 9 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) 100 100 -40C VS = 5V -40C VS = 2.7V 10 10 25C ISINK (mA) 25C ISINK (mA) 1 0.1 125C 125C 1 85C 0.1 0.01 85C 0.001 0.001 0.01 0.1 1 0.01 0.001 10 0.01 0.1 OUTPUT VOLTAGE REFERENCED TO V (V) Figure 7. ISINK vs VOUT Figure 8. ISINK vs VOUT 3 3 VS = 2.7V VS = 5V -40C 2.5 -40C 2.5 25C 25C 2 2 VOS (mV) VOS (mV) 10 1 - - OUTPUT VOLTAGE REFERENCED TO V (V) 85C 1.5 125C 85C 1.5 1 1 0.5 0.5 125C 0 -0.2 0.3 0.8 1.3 1.8 0 -0.2 2.3 0.5 1 VCM (V) 1.5 2.5 2 3 3.5 4 4.5 VCM (V) Figure 9. VOS vs VCM Figure 10. VOS vs VCM 300 300 VS = 1.35V 200 INPUT VOLTAGE (PV) INPUT VOLTAGE (PV) 200 100 0 RL = 10 k: -100 -200 RL = 10 k: 100 0 RL = 2 k: -100 -200 VS = 2.5V RL = 2 k: -300 -1.5 10 -300 -1 -0.5 0 0.5 1 1.5 -3 -2 -1 0 1 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 11. VIN vs VOUT Figure 12. VIN vs VOUT Submit Documentation Feedback 2 3 Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 Typical Characteristics (continued) 100 80 VIN = VS/2 VS = 5V 70 RL = 5 k: VS = 5 V, -PSRR 90 RL = 5k 80 VS = 2.7 V, +PSRR 60 50 PSRR (dB) CMRR (dB) 70 VS = 2.7V 40 30 60 50 VS = 5 V, +PSRR 40 30 20 20 10 10 0 100 VS = 2.7 V, -PSRR 0 10k 1k 100k 100 1M 1.5 VCM = VS/2 240 220 200 AV = +1 1.4 RL = 10k: 120 100 80 60 40 VS = 2.7V SLEW RATE (V/Ps) 1.3 180 160 140 VIN = 2VPP 1.2 1.1 RISING EDGE 1 0.9 FALLING EDGE 0.8 0.7 20 0 0.6 VS = 5V 0.5 10 1k 100 FREQUENCY (Hz) 10k 2.5 Figure 15. Input Voltage Noise vs Frequency 3 3.5 4 4.5 SUPPLY VOLTAGE (V) 1.2 RISING EDGE RISING EDGE 1 0.8 FALLING EDGE 0.6 AV = +1 SLEW RATE (V/Ps) 1 SLEW RATE (V/Ps) 5 Figure 16. Slew Rate vs VSUPPLY 1.2 0.8 FALLING EDGE 0.6 0.4 AV = +1 RL = 10k: RL = 10k: 0.2 10M Figure 14. PSRR vs Frequency 260 0.4 1M FREQUENCY (Hz) Figure 13. CMRR vs Frequency INPUT VOLTAGE NOISE (nV/ Hz) 100k 10k 1k FREQUENCY (Hz) 0.2 VIN = 2VPP VIN = 2VPP VS = 5V VS = 2.7V 0 0 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE () TEMPERATURE () Figure 17. Slew Rate vs Temperature Figure 18. Slew Rate vs Temperature Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 11 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com Typical Characteristics (continued) 10 10 f = 10KHz AV = +10 VS = 2.7V, VO = 1VPP 1 THD+N (%) THD+N (%) 1 RL = 600 VS = 2.7V, A V = +10 VS = 5V, VO = 2.5VPP 0.1 AV = +1 VS = 5V, AV = +10 0.1 0.01 VS = 5V, AV = +1 VS = 2.7V, AV = +1 VS = 5V, VO = 1VPP VS = 2.7V, VO = 1VPP 0.01 0.00 1 0.001 10 1 10k 100 1k FREQUENCY (Hz) 100k 0.0 1 0.1 Figure 19. THD+N vs Frequency Figure 20. THD+N vs VOUT 100 100 100 100 RL = 2k: 125C PHASE 80 10 1 VO (VPP) PHASE 80 80 80 RL = 600: 60 RL = 100k: GAIN 20 20 -40C 0 0 GAIN (dB) 40 40 PHASE () 40 40 GAIN RL = 100k: 20 20 0 -20 -20 -40 RL = 2k: -40 VS = 2.7V -60 10k -40 -40 RL = 2k: 1k -20 -20 25C VS = 5V 100k 1M FREQUENCY (Hz) -60 10M -60 100 10k 1k Figure 21. Open-Loop Frequency Over Temperature 60 100 100 80 80 CL = 0 80 CL = 1000pF 60 60 20 0 0 GAIN (dB) RL = 100k: PHASE () GAIN (dB) 40 40 20 20 0 0 CL = 1000pF -20 -20 -20 RL = 2k: -40 -40 -40 -60 100k 1M FREQUENCY (Hz) -60 10M Figure 23. Open-Loop Frequency Response -20 CL = 500pF VS = 5V CL = 100pF RL = 600: VS = 5V Submit Documentation Feedback 40 CL = 100pF GAIN RL = 600: 10k 60 CL = 500pF 40 20 10 0 PHASE RL = 100k: GAIN -60 10M Figure 22. Open-Loop Frequency Response RL = 600: 12 100k 1M FREQUENCY (Hz) RL = 2k: PHASE 80 1k 0 RL = 600: 125C PHASE () GAIN (dB) 60 60 25C -40C PHASE () 60 -60 1k 10k 100k 1M FREQUENCY (Hz) -40 CL = 0 -60 10M Figure 24. Gain and Phase vs CL Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 Typical Characteristics (continued) 100 VS = 2.5V CL = 0 3.5 CL = 1000pF 60 CL = 500pF CL = 100pF 40 40 GAIN 20 20 CL = 0 0 0 CL = 1000pF CL = 500pF -20 -20 CL = 100pF VS = 5V -40 PHASE () 60 CAPACITIVE LOAD (nF) 80 80 GAIN (dB) 4 100 PHASE 10k 1k VO = 100mVPP 2.5 2 1.5 1 0.5 -40 0 -2.5 -60 10M 100k 1M FREQUENCY (Hz) RL = 1M: VO = 100mVPP 120 100 80 60 40 20 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0.5 1 1.5 RL = 2k: VS = 2.5V TIME (4 Ps/div) Figure 28. Noninverting Small Signal Pulse Response TA = 25C RL = 2k: OUTPUT SIGNAL (1 V/div) VS = 2.5V (50 mV/div) INPUT SIGNAL Figure 27. Stability vs Capacitive Load INPUT SIGNAL -0.5 0 VO (V) TA = 25C VO (V) OUTPUT SIGNAL -1 (50 mV/div) AV = +1 OUTPUT SIGNAL CAPACITIVE LOAD (pF) VS = 2.5 140 -1.5 INPUT SIGNAL 200 160 -2 Figure 26. Stability vs Capacitive Load Figure 25. Gain and Phase vs CL 180 RL = 2k: 3 RL = 100k: -60 AV = +1 TA = 125C RL = 2k: VS = 2.5V TIME (4 Ps/div) Figure 29. Noninverting Large Signal Pulse Response TIME (4 Ps/div) Figure 30. Noninverting Small Signal Pulse Response Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 13 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com INPUT SIGNAL RL = 2k: VS = 2.5V OUTPUT SIGNAL (50 mV/div) TA = 125C (1 V/div) OUTPUT SIGNAL INPUT SIGNAL Typical Characteristics (continued) TA = -40C RL = 2k: VS = 2.5V TIME (4 Ps/div) OUTPUT SIGNAL INPUT SIGNAL OUTPUT SIGNAL (1 V/div) OUTPUT SIGNAL TIME (4 Ps/div) Figure 34. Inverting Small Signal Pulse Response INPUT SIGNAL Figure 33. Noninverting Large Signal Pulse Response TA = 25C RL = 2k: VS = 2.5V TIME (4 Ps/div) Figure 35. Inverting Large Signal Pulse Response Submit Documentation Feedback RL = 2k VS = 2.5V (50 mV/div) VS = 2.5V TA = 25C TA = 125C RL = 2k VS = 2.5V (50 mV/div) RL = 2k: TIME (4 Ps/div) 14 Figure 32. Noninverting Small Signal Pulse Response INPUT SIGNAL TA = -40C (1 V/div) OUTPUT SIGNAL INPUT SIGNAL Figure 31. Noninverting Large Signal Pulse Response TIME (4 Ps/div) TIME (4 Ps/div) Figure 36. Inverting Small Signal Pulse Response Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 TA = 125C RL = 2k: VS = 2.5V TIME (4 Ps/div) VS = 2.5V TIME (4 Ps/div) Figure 38. Inverting Small Signal Pulse Response 200 VS = 2.5V CROSSTALK REJECTION (dB) 180 (1 V/div) OUTPUT SIGNAL INPUT SIGNAL Figure 37. Inverting Large Signal Pulse Response TA = -40C RL = 2k (50 mV/div) OUTPUT SIGNAL (1 V/div) OUTPUT SIGNAL INPUT SIGNAL INPUT SIGNAL Typical Characteristics (continued) TA = -40C RL = 2k: 160 140 120 100 80 60 40 20 VS = 2.5V 0 100 TIME (4 Ps/div) Figure 39. Inverting Large Signal Pulse Response 1k 10k 100k FREQUENCY (Hz) 1M Figure 40. Crosstalk Rejection vs Frequency Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 15 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com 7 Detailed Description 7.1 Overview TI's LMV34x-N family of amplifiers have 1-MHz bandwidth, 1-V/s slew rate, a rail-to-rail output stage, and consume only 100 A of current per amplifier while active. When in shutdown mode it only consumes 45-pA supply consumption with only 20 fA of input bias current. Lastly, these operational amplifiers provide an inputreferred voltage noise 29 nVHz (at 10 kHz). 7.2 Functional Block Diagram VDD OUT CLASS AB CONTROL InP InM VEE Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Class AB Turnaround Stage Amplifier This patented folded cascode stage has a combined class AB amplifier stage, which replaces the conventional folded cascode stage. Therefore, the class AB folded cascode stage runs at a much lower quiescent current compared to conventional-folded cascode stages. This results in significantly smaller offset and noise contributions. The reduced offset and noise contributions in turn reduce the offset voltage level and the voltage noise level at the input of LMV34x-N. Also the lower quiescent current results in a high open-loop gain for the amplifier. The lower quiescent current does not affect the slew rate of the amplifier nor its ability to handle the total current swing coming from the input stage. The input voltage noise of the device at low frequencies, below 1 kHz, is slightly higher than devices with a BJT input stage; however, the PMOS input stage results in a much lower input bias current and the input voltage noise drops at frequencies above 1 kHz. 7.4 Device Functional Modes 7.4.1 Shutdown Feature The LMV341-N is capable of being turned off to conserve power and increase battery life in portable devices. Once in shutdown mode the supply current is drastically reduced, 1-A maximum, and the output is tri-stated. The device is disabled when the shutdown pin voltage is pulled low. The shutdown pin must never be left unconnected. Leaving the pin floating results in an undefined operation mode and the device may oscillate between shutdown and active modes. The LMV341-N typically turns on 2.8 s after the shutdown voltage is pulled high. The device turns off in less than 400 ns after shutdown voltage is pulled low. Figure 41 and Figure 42 show the turnon and turnoff time of the LMV341-N, respectively. To reduce the effect of the capacitance added to the circuit by the scope probe, in the turnoff time circuit a resistive load of 600 is added. Figure 43 and Figure 44 show the test circuits used to obtain the two plots. 16 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 Device Functional Modes (continued) VS = 5V VOUT VOUT (1 V/div) (1 V/div) VSHDN VSHDN RL = 600: VS = 5V TIME (1 Ps/div) TIME (400 ns/div) Figure 41. Turnon Time Plot Figure 42. Turnoff Time Plot + V V + + VOUT VOUT SHDN SHDN VIN = VS/2 + VIN = VS/2 + - Figure 43. Turnon Time Circuit + - RL = 600: Figure 44. Turnoff Time Circuit 7.4.2 Low Input Bias Current LMV34x-N amplifiers have a PMOS input stage. As a result, they have a much lower input bias current than devices with BJT input stages. This feature makes these devices ideal for sensor circuits. A typical curve of the input bias current of the LMV341-N is shown in Figure 45. 200 VS = 5V TA = 25C INPUT BIAS (fA) 100 0 -100 -200 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VCM (V) Figure 45. Input Bias Current vs VCM Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 17 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMV34x-N amplifier family features low voltage, low power, rail-to-rail output as well as a shutdown capability, making it well suited for low voltage portable applications. 8.2 Typical Application 8.2.1 Sample and Hold Circuit V + V + - VIN + + VOUT C = 200pF SAMPLE CLOCK Copyright (c) 2016, Texas Instruments Incorporated Figure 46. Sample and Hold Circuit 8.2.1.1 Design Requirements The lower input bias current of the LMV341-N results in a very high input impedance. The output impedance when the device is in shutdown mode is quite high. These high impedances, along with the ability of the shutdown pin to be derived from a separate power source, make LMV341-N a good choice for sample and hold circuits. The sample clock must be connected to the shutdown pin of the amplifier to rapidly turn the device on or off. 8.2.1.2 Detailed Design Procedure Figure 46 shows the schematic of a simple sample and hold circuit. When the sample clock is high the first amplifier is in normal operation mode and the second amplifier acts as a buffer. The capacitor, which appears as a load on the first amplifier, is charging at this time. The voltage across the capacitor is that of the noninverting input of the first amplifier because it is connected as a voltage-follower. When the sample clock is low the first amplifier is shut off, bringing the output impedance to a high value. The high impedance of this output, along with the very high impedance on the input of the second amplifier, prevents the capacitor from discharging. There is very little voltage droop while the first amplifier is in shutdown mode. The second amplifier, which is still in normal operation mode and is connected as a voltage follower, also provides the voltage sampled on the capacitor at its output. 18 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 Typical Application (continued) Signal Amplitude 8.2.1.3 Application Curve Sample (5v/div) Vin (1v/div) Vout (1v/div) 0 300 600 900 1200 Time (us) 1500 C002 Figure 47. Sample and Hold Circuit Results 9 Power Supply Recommendations For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For singlesupply, place a capacitor between V+ and V- supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 19 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com 10 Layout 10.1 Layout Guidelines To properly bypass the power supply, several locations on a printed-circuit board need to be considered. A 6.8-F or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1-F ceramic capacitor must be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a 0.1-F capacitor. If the amplifier is operated in a dual power supply, both V+ and V- pins need to be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive ground connection. Surface-mount components in 0805 size or smaller are recommended in the LMV341-N application circuits. Designers can take advantage of the VSSOP miniature sizes to condense board layout to save space and reduce stray capacitance. 10.2 Layout Example Cbyp V+ GND INPUT Rin SHDN OUTPUT Rf Cf Figure 48. PCB Layout Example 20 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N LMV341-N, LMV342-N, LMV344-N www.ti.com SNOS990H - APRIL 2002 - REVISED JUNE 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support For development support see the following: * LMV341-N PSPICE Model (also applicable to the LMV342 and LMV344) * TINA-TI SPICE-Based Analog Simulation Program * DIP Adapter Evaluation Module * TI Universal Operational Amplifier Evaluation Module * TI Filterpro Software 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: AN-31 Op Amp Circuit Collection (SNLA140) 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV341-N Click here Click here Click here Click here Click here LMV342-N Click here Click here Click here Click here Click here LMV344-N Click here Click here Click here Click here Click here 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N Submit Documentation Feedback 21 LMV341-N, LMV342-N, LMV344-N SNOS990H - APRIL 2002 - REVISED JUNE 2016 www.ti.com 11.8 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMV341-N LMV342-N LMV344-N PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV341MG/NOPB ACTIVE SC70 DCK 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A78 LMV341MGX/NOPB ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A78 LMV342MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV34 2MA LMV342MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV34 2MA LMV342MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A82A LMV342MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A82A LMV344MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV344MA LMV344MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV344MA LMV344MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV34 4MT LMV344MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LMV34 4MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LMV341-N, LMV344-N : * Automotive: LMV341-Q1, LMV344-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMV341MG/NOPB SC70 DCK 6 1000 178.0 LMV341MGX/NOPB SC70 DCK 6 3000 LMV342MAX/NOPB SOIC D 8 2500 LMV342MM/NOPB VSSOP DGK 8 LMV342MMX/NOPB VSSOP DGK B0 (mm) K0 (mm) P1 (mm) 8.4 2.25 2.45 1.2 4.0 178.0 8.4 2.25 2.45 1.2 330.0 12.4 6.5 5.4 2.0 1000 178.0 12.4 5.3 3.4 8 3500 330.0 12.4 5.3 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 1.4 8.0 12.0 Q1 3.4 1.4 8.0 12.0 Q1 LMV344MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMV344MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LMV344MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV341MG/NOPB SC70 DCK 6 1000 210.0 185.0 35.0 LMV341MGX/NOPB SC70 DCK 6 3000 210.0 185.0 35.0 LMV342MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV342MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV342MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMV344MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMV344MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 LMV344MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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