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FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
1
February 2015
FDMS3660S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
Max rDS(on) = 1.8 mΩ at VGS = 10 V, ID = 30 A
Max rDS(on) = 2.2 mΩ at VGS = 4.5 V, ID = 27 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for
lower circuit inductance and reduced switch node
ringing
RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Q1 Q2 Units
VDS Drain to Source Voltage 30 30 V
VGS Gate to Source V oltage (Note 3) ±20 ±12 V
ID
Drain Current -Continuous (Package limited) TC = 25 °C 30 60
A
-Continuous (Silicon limited) T C = 25 °C 60 145
-Continuous TA = 25 °C 131a 301b
-Pulsed 40 120
EAS Single Pulse Avalanche Energy 334865mJ
PDPower Dissipation for Single Operation TA = 25 °C 2.21a 2.51b W
Power Dissipation for Single Operation TA = 25 °C 11c 11d
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJA Thermal Resistance, Junction to Ambient 571a 501b
°C/WRθJA Thermal Resistance, Junction to Ambient 1251c 1201d
RθJC Thermal Resistance, Junction to Case 2.9 2.2
Device Marking Device Package Reel Size Tape Width Quantity
22CF
07OD FDMS3660S Power 56 13 ” 12 mm 3000 units
4
3
2
1
5
6
7
8
Q
1
Q
2
G1 D1 D1 D1
G2 S2 S2S2
D1
PHASE
(S1/D2)
S2
S2
S2
G2
D1
D1
D1
G1
Top
PHASE
Pin 1
Pin 1
Power 56 Bottom
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristic s
On Characteristics
Dynamic Characteristics
Switching Characteristics
Symbol Parameter Test Conditions Type Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V Q1
Q2 30
30 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C Q1
Q2 16
24 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1
Q2 1
500 μA
μA
IGSS Gate to Source Leakage Current VGS = 20 V, VDS= 0 V
VGS = 12 V, VDS= 0 V Q1
Q2
100
100 nA
nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA Q1
Q2 1.1
1.1 1.9
1.5 2.7
2.2 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C Q1
Q2 -6
-3 mV/°C
rDS(on) Drain to Source On Resistance
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C Q1 4
6
5.7
8
11
8.7 mΩ
VGS = 10 V, ID = 30 A
VGS = 4.5 V, ID = 27 A
VGS = 10 V, ID = 30 A , TJ = 125 °C Q2 1.3
1.5
1.86
1.8
2.2
2.6
gFS Forward Transconductance VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 30 A Q1
Q2 62
231 S
Ciss Input Capacitance Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2 1325
4130 1765
5493 pF
Coss Output Capacitance Q1
Q2 466
915 620
1220 pF
Crss Reverse Transfer Capacitance Q1
Q2 46
124 70
185 pF
RgGate Resistance Q1
Q2 0.2
0.2 0.6
0.8 2
3Ω
td(on) Turn-On Delay Time Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 30 A, RGEN = 6 Ω
Q1
Q2 7.7
11 15
20 ns
trRise Time Q1
Q2 2.2
510
10 ns
td(off) Turn-Off Delay Time Q1
Q2 19
40 34
64 ns
tfFall Time Q1
Q2 1.8
3.9 10
10 ns
QgTotal Gate Charge VGS = 0 V to 10 V Q1:
VDD = 15 V,
ID = 13 A
Q2:
VDD = 15 V,
ID = 30 A
Q1
Q2 21
62 29
87 nC
QgTotal Gate Charge VGS = 0 V to 4.5 V Q1
Q2 9.5
29 13
41 nC
Qgs Gate to Source Gate Charge Q1
Q2 3.9
9nC
Qgd Gate to Drain “Miller” Charge Q1
Q2 2.6
7nC
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
3
Electrical Characteristics TJ = 25 °C unless otherwise noted
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Type Min Typ Max Units
VSD Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 13 A (Note 2)
VGS = 0 V, IS = 2 A (Note 2)
VGS = 0 V, IS = 30 A (Note 2)
VGS = 0 V, IS = 2 A (Note 2)
Q1
Q1
Q2
Q2
0.8
0.7
0.8
0.6
1.2
1.2
1.2
1.2
V
trr Reverse Recovery Time Q1:
IF = 13 A, di/dt = 100 A/μs
Q2:
IF = 30 A, di/dt = 300 A/μs
Q1
Q2 26
29 42
46 ns
Qrr Reverse Recovery Charge Q1
Q2 10
32 20
50 nC
Notes:
1: RθJA is determined wi th th e d e vic e m ount ed on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board o f FR-4 ma ter ial . RθJC is guar an tee d by d e sign wh ile RθCA is determined
by the user's board design.
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied with the negative Vgs ra ting .
4: EAS of 33 mJ is based on starting TJ = 25 oC; N-ch: L = 1.9 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A.
5: EAS of 86 mJ is based on starting TJ = 25 oC; N-ch: L = 0.6 mH, IAS = 17 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 31 A.
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copp er
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
4
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
Figure 1.
0.0 0.2 0.4 0.6 0.8 1.0
0
10
20
30
40
VGS = 6 V
VGS = 4 V
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
PULSE D U R ATION = 80 μs
DUTY CYCLE = 0.5% M A X
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 10203040
0
1
2
3
4
VGS = 6 V
VGS = 3.5 V
PULSE D U RATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOU RC E ON-RESISTANC E
ID, DRAIN CURRENT (A)
VGS = 4 V
VGS = 4.5 V VGS = 10 V
Normalized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 13 A
VGS = 10 V
NORMALIZED
DRAIN TO SO UR CE ON-RESISTA NC E
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Te mperature Figure 4.
246810
0
4
8
12
16
20
TJ = 125 oC
ID = 13 A
TJ = 25 oC
VGS, GA TE TO SOU R CE VO LTA GE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE D U RATION = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
1.5 2.0 2.5 3.0 3.5 4.0
0
10
20
30
40
TJ = 150 oC
VDS = 5 V
PULSE D U R ATION = 80 μs
DUTY CYCLE = 0.5% MA X
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
40
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWA R D VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
5
Figure 7.
0 5 10 15 20 25
0
2
4
6
8
10
ID = 13 A
VDD = 20 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
Gate Charge Characteristics Figure 8.
0.1 1 10 30
10
100
1000
2000
f = 1 MHz
VGS = 0 V
CAPACITANCE (p F)
VDS, D RAIN TO SOURCE VOLTAGE ( V)
Crss
Coss
Ciss
Capac ita nce vs Drain
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
Unclampe d Ind ucti ve
Switching Capability Figure 10.
25 50 75 100 125 150
0
20
40
60
80
RθJC = 2.9 oC/W
VGS = 4.5 V
Limited by Package
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
Maximum Continuous Drain
Current vs Case Temperature
Figure 11. Forward Bias Safe
Operating Area Figure 12. Single Pulse Maximum Power
Dissipation
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
0.01 0.1 1 10 100200
0.01
0.1
1
10
100
100 μs
DC
100 ms
10 ms
1 ms
1 s
ID, DRAIN CURREN T (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
TH IS ARE A IS
LIMITE D BY rDS(on)
SINGLE PULS E
TJ = MAX RATED
RθJA = 12 5 oC/W
TA = 25 oC
10 s
10-4 10-3 10-2 10-1 110
100 1000
0.1
1
10
100
1000
SINGLE P U LSE
RθJA = 125 oC/W
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
6
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
10-4 10-3 10-2 10-1 110
100 1000
0.001
0.01
0.1
1
2
SINGLE PULSE
RθJA = 125 oC/W
(Note 1c)
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
PDM
t1t2
NOTES:
DUTY FAC TOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
7
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
0.0 0.2 0.4 0.6 0.8 1.0
0
20
40
60
80
100
120
VGS = 2.5 V
VGS = 3 V
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On-Region Characteristics
020406080100120
0
1
2
3
4
VGS = 3 V
VGS = 3.5 V
PULSE D U RATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOU RC E ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 2.5 V
VGS = 4.5 V VGS = 10 V
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
Figure 16. Normalized On-Resi stance
vs Junction Temperature
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 30 A
VGS = 10 V
NORMALIZED
DRAIN TO SO UR CE ON-RESISTA NC E
TJ, JUNCTION TEMPERATURE (oC)
246810
0
2
4
6
8
TJ = 125 oC
ID = 30 A
TJ = 25 oC
VGS, GA TE TO SOU R CE VO LTA GE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MA X
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 18. Transf er Characteristics
1.0 1.5 2.0 2.5 3.0
0
20
40
60
80
100
120
TJ = 125 oC
VDS = 5 V
PULSE DU RATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
0.0 0.2 0.4 0.6 0.8 1.0
0.001
0.01
0.1
1
10
100
TJ = -55 oC
TJ = 25 oC
TJ = 125 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
Figure 20. Gate Charge Characteristics
0 10203040506070
0
2
4
6
8
10 ID = 30 A
VDD = 20 V
VDD = 10 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
0.1 1 10 30
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 22. Unclamped Inductive
Switching Capability
0.001 0.01 0.1 1 10 100 1000
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
40
80
120
160
Limited by Package
RθJC = 2.2 oC/W
VGS = 4.5 V
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CA SE TEMPERA TURE (oC)
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
Figure 24. Forward Bias Safe
Operating Area Figure 25. Single Pulse Maximum
Power Dissipation
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
8
0.01 0.1 1 10 100200
0.01
0.1
1
10
100
200
100 μs
DC
100 m s
10 m s
1 ms
1s
ID, DRAIN CURREN T (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS A R EA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 120 oC/W
TA = 25 oC
10s
10-4 10-3 10-2 10-1 110
100 1000
0.5
1
10
100
1000
2000
SINGLE PULSE
RθJA = 120 oC/W
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
9
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
10-4 10-3 10-2 10-1 110
100 1000
0.0001
0.001
0.01
0.1
1
2
SINGLE PU LS E
RθJA = 120 oC/W
(No te 1 d )
DUTY CYCLE-DESCENDING ORDER
NORMALIZ ED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURA TION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
PDM
t1t2
NOTES:
DUTY FAC TOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + T A
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
10
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3660S.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
0 100 200 300 400
-5
0
5
10
15
20
25
30
35
didt = 30 0 A/μs
CURRENT (A)
TIME (n s)
Typical Characteristics (continued)
Figure 27. FDMS3660S SyncFETTM body
diode reverse recovery characteristic Figure 28. SyncFETTM body diode reverse
leakage versus drain-sour ce voltage
0 5 10 15 20 25
10-6
10-5
10-4
10-3
10-2
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
IDSS, REVERSE LEAK AG E CURRENT (A)
VDS, REVERS E VO LTA G E (V)
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
11
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary desi gn* that minimizes the peak oversho ot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
12
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current fl ow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
FDMS3660S PowerT rench® Power Stage
©2012 Fairchild Semiconductor Corporation
FDMS3660S Rev.C4 www.fairchildsemi.com
13
Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency condu ction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace conne ction. This eliminates the effect of parasitic inductance and resistance betw een the driver and the
MOSFET and turns the devices o n and off as efficiently as p ossib le. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical hig h frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
3.16
2.80
C
L
L
C
PKG
PKG
5.10
4.90
6.25
5.90
C
3.81
1.02
0.82
TOP VIEW
SIDE VIEW
BOTTOM VIEW
14
85
1 2 3 4
8 7 6
0.10 C A B
0.05 C
2.25
2.05
5
0.65
0.38
(SCALE: 2X)
0.05
0.00
0.35
0.15
0.08 C
SEATING
PLANE
0.10 C
1.10
0.90
RECOMMENDED LAND PATTERN
0.65 TYP
12 3 4
5
6
7
8
1.27
1.34
1.12
A
0.10 C
(2X) B
0.10 C
(2X)
0.00
0.00
1.60
2.52
1.21
2.31
1.18
1.27 TYP
2.00
2.15
0.63
0.63 0.59
3.18
4.00
C
L
C
L
0.65
0.38
2.13
3.15
0.45
0.25
0.70
0.36
4.08
3.70
0.44
0.24
(6X)
0.66±.05
4.16
0.61
0.31
KEEP OUT AREA
8X
PIN # 1
INDICATOR
5.10
SEE
DETAIL A
(8X)
FOR SAWN / PUNCHED TYPE
(SCALE: 2X)
0.35
0.15
0.28
0.08 10°
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
C
L
L
C
PKG
PKG
5.10
4.90
6.25
5.90
C
3.16
2.80
3.81
1.02
0.82
TOP VIEW
SIDE VIEW
14
85
1 2 3 4
8 7 6
0.10 C A B
0.05 C
5
0.65
0.38
SEE
DETAIL B
1.27
0.66±.05
1.34
1.12
(2X)
(2X)
0.65
0.38
0.45
0.25
0.70
0.36
4.08
3.70
0.44
0.24
(6X)
5.00
4.80
5.90
5.70
0.41
0.21 (8X)
2.25
2.05
0.61
0.31
0.10 C
1.10
0.90
0.35
0.15
SEATING
PLANE
8X
SEE
DETAIL C
(SCALE: 2X)
BOTTOM VIEW
(8X)
0.10 C
0.10 C
0.08 C
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