Am29LV004T-90FC - Advanced Micro Devices

PRELIMINARY

This doc um ent contains informa tion on a pr oduc t under deve lopme nt at Advanc ed Micro Devic es. The inf or mation

is intended to help you evaluat e this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 20510 Rev: DAmendment/+1

Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29LV004

4 Megabit (5 12 K x 8-Bit)

CM O S 3 .0 Volt-only Bo ot Secto r Fl ash Me m ory

DISTINCTIVE CHARACTERISTICS

■Si ngle p ower supply operation

— Full v ol t ag e r an ge: 2. 7 t o 3.6 v o l t re ad an d w r ite

operations for battery-powere d applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with

high performance 3.3 volt microprocessors

■High performance

— Full voltage range: access times as fast as 100

— Regulated voltage range: access times as fast

as 90 ns

■Ultra low power consumption (t ypical values at

5 MHz)

— 200 nA A utomati c Sleep mode cur rent

— 200 nA sta ndby mod e cur re nt

— 10 mA read current

— 20 mA program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seve n 64 Kbyte sectors

— Supports full chip erase

— Sector Protection featur es:

A hardware method of locking a sector to

pr eve nt any program or erase operati ons withi n

that sector

Sectors can be locked via programming

equipment

T emporary Sector Unprotect feature allows code

changes in previously locked sectors

■Top or bottom boot block configurati ons

available

■Embedded Algorithms

— Embedded Erase algorithm automaticall y

pr eprograms and erase s the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and ve rifies data at specified addresses

■Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■Package option

— 40-pin TSOP

■Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior ina dvertent write protection

■Dat a# Poll ing and toggle bi ts

— Provide s a software method of detecting

pr ogram or erase operation completion

■Re ady /B u sy # pin (RY/ BY # )

— Provides a hardware method of detecting

prog ram or erase cycle completion

■Er as e Sus pe nd /E r as e Res um e

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■Hardware reset pin (RESET#)

— Hardware method to reset the device to readi ng

array data

2 Am29LV004

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV004 is an 4 Mbit, 3.0 volt-only Flash

memory organized as 524,288 bytes. The device is

offered in a 40-pin TSOP package. The byte-wide (x8)

data appe ars on DQ7 –DQ 0. This dev ice re qu ires onl y

a single , 3.0 volt VCC sup ply to pe rf o rm r ea d, pr og ra m,

and erase operations. A standard EPROM pro-

gram mer can also be used to prog ram and erase the

device.

The standard device offers access times of 90, 100,

120, and 150 ns, allowing high speed microprocessors

to operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), writ e

enable (WE#) and output enab le (OE#) controls.

The device requires only a singl e 3.0 volt power sup-

ply for bot h r ea d an d w ri te fu nct io ns . In te rna l ly g en er -

ated and regulated voltages are provided for the

program and erase operations.

The device is enti rely com mand set compatible with the

JEDEC single-power-supply Flash standard. Com-

mand s ar e w rit t en to the c om ma nd re gis t er us ing st an-

da rd microprocessor write timings. Re gist er contents

serve as input to an internal state-machine that con-

trols the erase and p rogramming circuitry. Write cycles

also internally latch addresses and data needed for the

prog ramm ing and e rase o pera tion s. Read ing d ata ou t

of the device is similar to readin g from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

mat ically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algo-

rithm—an internal algorithm that automatically prepro-

grams the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies

proper cell margin.

The host system can detect whether a program or

eras e op eratio n is co mpl ete by o bserv ing th e RY/B Y#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has b een com p lete d, the dev ic e i s re ad y to rea d a rra y

data or acce pt another co mmand.

The sector erase architecture a llows memo ry sec tor s

to be erased and reprogrammed withou t affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that auto matically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

oper ations in any combination of the sectors of mem-

ory . This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. T rue background erase can thus be achieved.

The hardware RESET# pin terminates a ny operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circu itry. A syst em reset w ould thus a lso

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addr esses ha v e be en stab le for a s p ec if ied a mo un t o f

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Am29LV004 3

PRELIMINARY

PR ODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29LV004

Speed Options Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

Max access time, ns (tACC)90 100 120 150

Max CE# access time, ns (tCE)90 100 120 150

Max OE# access time, ns (tOE)40 40 40 55

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

21522A-1

4 Am29LV004

PRELIMINARY

CONNECTION DIAGRAMS

A16

A15

A14

A13

A12

A11

WE#

RESET#

RY/BY#

A18

A17

DQ0

VSS

A10

DQ7

DQ6

DQ5

OE#

VSS

CE#

DQ4

VCC

DQ3

DQ2

DQ1

A16

A15

A14

A13

A12

A11

WE#

RESET#

RY/BY#

A18

A17

DQ0

VSS

A10

DQ7

DQ6

DQ5

CE#

VSS

CE#

DQ4

VCC

DQ3

DQ2

DQ1

21522A-2

Reverse TSOP

Standard TSOP

Am29LV004 5

PRELIMINARY

PIN CONFIGURATION

A0– A 18 = 19 addr es se s

DQ0–DQ7 = 8 data inputs/outputs

CE# = Chip enable

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

VCC = 3.0 volt-only single power supply

( see Prod uct Selector Guide for speed

options and voltage supply tolerances)

VSS = De vice gr ound

NC = Pin not connected intern ally

LOGIC SYMBOL

21522A-3

19 8

DQ0–DQ7

A0–A18

CE#

OE#

WE#

RESET#

RY/BY#

6 Am29LV004

PRELIMINARY

ORDERING INFORMATION

Standard Products

AM D s ta nd ar d p rod ucts a re ava i lab l e in sev e ra l packa ge s and ope rating ra ng es. The order number (Va lid C o mb i-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBE R/DE SCRIP TION

Am29LV004

4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

CET

Am29LV004 -90R

OPTIONAL PROCESSING

Blank = Standard Proces sing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

Valid Combinations

Am29LV004T-70R,

Am29LV004B-70R EC, EI, FC, FI

Am29LV004T-80,

Am29LV004B-80

EC, EI, EE, FC, FI, FE

Am29LV004T-90,

Am29LV004B-90

Am29LV004T-120,

Am29LV004B-120

Am29LV004 7
PRELIMINARY
DEVI CE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal  command register . The command register itself
does not occupy any addressable memory location.
The r egi ster i s comp osed  of lat ches  t hat st ore  t he com-
mands, along with the address and data information
need ed  to execu te t he com mand . The co ntents  of th e
register serve a s inputs to the internal state machine.
The state machine outputs  dictate the function of the
dev ice. Tab le 1 lists  the de vice bus op erat ions , t he in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV004 Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
 = 12.0 
± 
0.5 V, X = Don’t Care, A
IN
 = Address In, D
IN
 = Data In, D
OUT
 = Data Out
Note: Addresses are A18–A0.
Requirements for Reading Array Data
To read array d ata from the outputs,  the system must
drive the CE# and OE# pins  to VIL. CE# is the power
co ntrol an d selec ts the de vice . OE# is th e outpu t con-
trol and gates array data to the output pins. WE#
should remain at VIH. 
The internal state machine is set for reading array
data upon  dev ice pow er-up,  or  after a  hardw are re set.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert val id addresses on the  d evice address  inp uts pro-
duce valid data on the device data outputs. The
devic e remains enabled  for read ac cess until the c om-
mand register contents are altered.
See  “Re ad ing Arra y Data” fo r more  info rmatio n. R efer
to the AC Read Operations table  for timing specifica-
tions and to Figure 12 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write  a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An  era se op e ra ti o n ca n er as e  on e sec t or, mul tip l e s e c-
tors, or the entire device. Tables 2 and 3 indicate  the
address space that each sector occupies. A “sector ad-
dr ess” consists of the address bits required to uniquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the  device enters the autoselect mode. The
system  ca n th en re ad aut ose lect  codes fr om  the in ter -
nal register (which is separate from the memory array)
on D Q7– DQ0.  Stan dar d re ad c ycle  tim ing s ap ply  in th is
mod e. R e fer  to th e “ Autos ele ct Mo de” and “Au to sel e ct
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents th e ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timi ng diagrams for write operations.
Program and Erase O peration Status
During an  erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Operat ion CE# OE# WE# RESET# Addre sses (See Note) DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
Standby VCC ± 
0.3 V XX V
CC ± 
0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z
Temp orary Sector Unpro tect X X X VID AIN DIN

8 Am29LV004

PRELIMINARY

Stand by Mode

Whe n th e sy stem is not readi ng or wr itin g to the dev ice,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The de v ice en ter s t he CM OS st an dby mode w h en th e

CE# and RESET# pins are both held at VCC ± 0.3 V.

(N ote th at thi s is a m ore r es trict ed volt age rang e tha n

VIH.) If CE# and RESET # are held at VIH, but no t w ithin

VCC ± 0.3 V , the device will be in t he standby mode, but

the standby current will be greater. The device requires

standard access time (tCE) for read access when the

dev ice is in e i th er of t hese st and by modes, b efo re it is

r eady to read data.

If the de vice is desele cte d during era sure or progr am-

ming, the device draws active current until the

operation is completed.

In th e D C Cha racte ristic s table s, ICC3 and ICC4 repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

tACC + 30 ns. The automatic sleep mode is indepen-

dent of the CE # , WE#, and OE# co ntrol s ignals. S tan -

dard address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system. ICC5

in the DC Characteristics table represents the auto-

matic sleep mode current specification.

RESET#: Har dware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period o f t RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to re ading array data. T he operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held a t VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at V IL bu t no t w i thi n VSS±0.3 V, the sta ndby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cu itry. A system rese t w ould th us also re set th e Fl ash

memory, enabling the syste m to rea d the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether t he res et op eration i s compl ete. If R ESET# is

assert ed whe n a program or er ase operati on is not ex -

ecuting (RY/BY# pin is “1”), the reset operation is

completed within a time of tREADY (not during Embed-

ded Algorithms). The system can read data tRH after

the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

di sa ble d . Th e o utp ut p i ns ar e pl ac ed i n t he h i gh im pe d-

ance state.

Am29LV004 9

PRELIMINARY

Table 2. Am29LV004 T Top Boot Block Sector Address Tab le

Table 3. Am29LV004B Bottom Boot Block Sector Address Table

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to a uto mati cal ly ma tch a de vi ce to be prog ramm ed w ith

its corresponding programming algorithm. However,

the aut oselec t co des c an also be a cces sed in -sy stem

through the command register .

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in Table

4. In addition, when verifying sector protection, the sec-

tor address must appear on the appropriate highest

order address bits (see Tables 2 and 3). Tabl e 4 shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equi pment may then read the corresponding iden-

tifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require VID. See “Command Definitions” for

details on using the autos ele ct mode.

Sector A18 A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Rang e

(in hexadecimal)

SA0 0 0 0 X X X 64 00000h-0FFFFh

SA1 0 0 1 X X X 64 10000h-1FFFFh

SA2 0 1 0 X X X 64 20000h-2FFFFh

SA3 0 1 1 X X X 64 30000h-3FFFFh

SA4 1 0 0 X X X 64 40000h-4FFFFh

SA5 1 0 1 X X X 64 50000h-5FFFFh

SA6 1 1 0 X X X 64 60000h-6FFFFh

SA7 1 1 1 0 X X 32 70000h-77FFFh

SA8 1 1 1 1 0 0 8 78000h-79FFFh

SA9 1 1 1 1 0 1 8 7A000h-7BFFFh

SA10 1 1 1 1 1 X 16 7C000h-7FFFFh

Sector A18 A17 A16 A15 A14 A13 Sector Size

(Kbytes) Address Rang e

(in hexadecimal)

SA0 0 0 0 0 0 X 16 00000h-03FFFh

SA1 0 0 0 0 1 0 8 04000h-05FFFh

SA2 0 0 0 0 1 1 8 06000h-07FFFh

SA3 0 0 0 1 X X 32 08000h-0FFFFh

SA4 0 0 1 X X X 64 10000h-1FFFFh

SA5 0 1 0 X X X 64 20000h-2FFFFh

SA6 0 1 1 X X X 64 30000h-3FFFFh

SA7 1 0 0 X X X 64 40000h-4FFFFh

SA8 1 0 1 X X X 64 50000h-5FFFFh

SA9 1 1 0 X X X 64 60000h-6FFFFh

SA10 1 1 1 X X X 64 70000h-7FFFFh

10 Am29LV004

PRELIMINARY

Tab le 4. Am29LV004 Aut o select Codes (High Voltag e Method)

L = Logic Low = V

, H = Logic High = V

, SA = Sector Address, X = Don’t care .

Sector Protection/Unpr otection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It i s pos sibl e t o det ermin e wh ethe r a sec tor is pro tec ted

or unprotected. See “Autos elect Mode” for de tails.

Sector protection/unprotection must be implemented

using programming equipment.The procedure requires

a high voltage (VID) on address pin A9 and OE#. De-

tails on this method are provided in a supplement, pub-

li cati on n umbe r 20 874. C ont act a n A MD repr ese nta tive

to request a copy.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sec tor U n pr ote ct m od e i s a ctiv a ted by setting th e RE -

SE T# pin t o VID. Du ring this mod e, form erly prote cted

sec t or s ca n b e pr o gr amm ed or er ased by sel e cti n g t he

sector addresses. Once VID is removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 19 shows the timing diagrams, for this feature.

Description CE# OE# WE#

A18

A13

A12

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL 01h

Device ID: Am29LV004T

(Top Boot Block) LLHXXV

ID XLXLH B5h

Device ID: Am29LV004B

(Bottom Boot Block) LLHXXV

ID XLXLH B6h

Sector Protection Verification L L H SA X VID XLXHL

01h

(protected)

00h

(unprotected)

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 1. T emporary Sector Unprotect Operation

21522A-4

Am29LV004 11
PRELIMINARY
Hardware Data Pro tection
The comma nd seque nce requir ement of unlock cycle s
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following  hardware
data protection measures prevent accidental erasure
or pr ogra mmi ng, wh ich m ig ht othe rwis e be ca use d by
spurious system level signals during VCC power-up
and power -down  transition s, or from system  noise.
Low VCC Write Inhibit
When VCC is less  than  VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and  power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#  or
WE# d o not initiate a write cycle.
Logical Inhibit
Write cycles are inhibite d by holding  any one of OE# =
VIL, CE#  = VIH or WE# = VIH. To  initia te a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If  WE# = CE# = VIL and  OE# =  VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val -
ues or writing them in  the  improper sequence resets
the device to reading array data. 
All addresses are latc hed on t he falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” se ction.
Reading Array Data
The device is automatically set to reading array data
afte r device po wer-up. No commands ar e requ ired to
retrieve data. The device is also ready to  read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system 
must
 issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while  in  the auto select  mode. Se e the “ R eset C om -
mand” se ction, next.
See also  “Requirements for Reading Array  Data” in the
“D evice Bu s  Op er at ions” se cti o n f or  m ore  i n for ma ti on .
The Re ad Operations table provides th e read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice  to  r ea di n g a rr ay  da ta.  A dd re ss bits  ar e  do n’ t  car e
for this command. 
The reset command may be written between the se-
quence cycles in an erase comm and sequence before
er asing begins. This resets the de vice to reading array
data. Once erasure begins, however, the device ig-
nores re set commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
howe ver,  the  device  ign ores r eset co m mand s un til the
oper ation is  comp lete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the auto select mo de, the reset command 
must
be w ritten to re turn to re ading ar ray data  ( also app lies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
wr iting  the res et comm and r eturn s th e devic e to re ad-
ing ar ray data (also ap plies during Erase Suspend).

12 Am29LV004
PRELIMINARY 
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices cod es,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements.
This  m eth od  is an a lte rnative  to th at sh own in Ta ble  4,
which is intended for PROM programmers and requires
VID on ad dress bit A9 .
The au to s ele c t co mm and se qu en c e is i nit ia te d by  wr it-
ing two unlock cycle s, follo wed by the autos elect com -
mand. The device then enters the autoselect mode,
and t he s yste m may r ead at  any ad dres s any n umbe r
of times, without initiating another command sequence. 
A re ad cycle at address XX00h retrieves the manufac-
ture r code . A rea d cy cle at ad dress X X0 1h r eturn s th e
device code. A read cycle containing a sector address
(SA) and the address  02h returns 01h if  that sector is
protect ed,  or  00 h if i t  is  un pr ote cte d. R e fe r to  Ta bles 2
and 3 for valid sector addresses.
The sy stem must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
co mman d. T he pr ogra m ad dress  an d dat a are  wri tten
next, wh ich in turn in itiate the  Emb edde d  Program  al-
gorithm. The system is 
not
 required to provide further
contr ols or timings. T he device  automatically p rovides
in te rn al l y  gene r at ed  p r og ra m pu l se s a nd  v e rif y  th e  pr o-
gram med  cell ma rg in. Table  5 sh ows th e add ress an d
data requirements for the byte program command se-
quence.
When the Embe dded Program algorithm is complete,
the d evice th en returns to reading array data and ad-
dres ses a re no l ong er latch ed.  The sys tem  can de ter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits. 
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be  reinitia ted once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to  a “1”. Attempting to do so may halt
the op eration and s et DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howeve r, a succeeding read will  sh ow that the
data is still “0”. Only erase o peration s can convert a “0”
to a “1”.
Figure 2 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Note: See Table 5 for program command sequence.
F igure 2. Progr am Operat ion
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress
21522A-4

Am29LV004 13
PRELIMINARY
Chip Erase Command Sequ ence
Chip er ase is a six bus cycle operati on. The  chip erase
command sequence is initiated by writing two unlock
cycles,  followed by a set-up command. Two additional
unl o ck wr i te cy c le s ar e t hen fo l low e d by  the ch i p  erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior to erase. The Embedded Erase algo-
r ithm aut omatically pr eprograms and verifies th e ent ire
mem ory for an all zero da ta pattern prior to ele ctric al
erase. T he system is not  requir ed to provide  any  con-
trols or timings during these operations. Table 5 shows
the ad dress and data requir ements for  the chip erase
comm and seque nce .
Any commands written to the chip  during the Embed-
ded Erase algorithm are ignored. Note that a  hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array  data, to ensure data integrity.
The  sy ste m can det ermi ne the  status of  the e rase op -
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched. 
Figure 3 illustrates the algorithm for the erase opera-
tio n. See the E rase/Pr ogra m Opera tio ns tables  in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unl o ck c y cle s , fo l low ed  by  a set - up  co mman d.  Two  ad-
ditional unlock write cycles are then followed  by  the ad-
dress o f th e s ec to r  to  be  er ase d, an d t he  sec t or  e ras e
command. Table 5 shows the address and data re-
quirements for the sector erase command sequence.
The device does 
not
 require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automaticall y programs and verifies the sector for
an all zero data pattern prior to  electrical erase. The
system is not required to provide any controls or tim-
ings during these operations. 
After t he command sequence is written, a secto r erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands m ay  be written. Loading the secto r eras e buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors.  The  time be-
tw ee n th ese  add i t ion al  cyc le s mu st be  le ss th an  50 µs ,
otherwise the last address and command might not be
ac cepted , and  era sure  ma y beg in. It i s re comm ende d
that processor interrupts  be disabled during  this time to
ensure all commands are accepted. The interrupts can
be re -e nabled  after  t he las t Sec tor Eras e com man d is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must r ewrite the command  sequence
and any additional sector addresses and commands.
The system can  monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase T imer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
Once the sector erase operation has begun, only the
Er ase  S usp en d c o mmand  i s v al i d.  Al l o t he r co mma n ds
are ignored. Note that a  hardware reset during the
se cto r er ase operatio n im me di a tely ter min ate s  the  op -
eration . The Sec t or  Erase co mm an d s e qu en ce s h ou l d
be r einit iated once th e device ha s return ed to readin g
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no lon ger latch ed. The  system can  determ ine the sta -
tus of the er ase operation by using DQ7, DQ6, DQ2, or
R Y/BY# . ( Ref er to  “W rite  Oper ati on S tatus ” f or i nfo rma-
tion on these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operat ions  tables in
the “AC Characteristics” section for parameters, and to
Figure 15 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase S uspend comman d allows  the system to  in-
terrupt a  sector erase o peration and then r ead data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the  chip  eras e o pera tion o r Em bedd ed P rogram  a lgo-
rith m. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out  period an d suspends the  erase  operation. Ad-
dresses  are  “d on’t- car es” whe n w ri tin g th e E r ase Su s-
pend command.
Whe n t he E ra se S usp en d c omma nd  i s wri tt e n du ri ng  a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediate ly ter-
minates the time-out period and suspends the erase
operation.

14 Am29LV004

PRELIMINARY

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

ca n use D Q7 , or DQ6 and D Q2 toge th er, to det er mi n e

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on thes e

stat us bits.

After an erase-suspended program operation is com-

plete, th e system ca n once again r ead array data within

non-suspende d sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

val id op er at io n. S ee “Autos e lec t Comm an d Se qu en c e”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode an d c o nti n ue th e s e cto r e ra se op er a tio n. Furt h er

writes of the Resume command are ig nored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

F igure 3. Erase Ope ration

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21522A-5

Am29LV004 15
PRELIMINARY
Table 5. Am 29LV0 04 Command Definitions
Legend:
X = Don’t care
RA = Address of the memor y loca tion to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory loca tion to be p rogrammed. 
Addresses latch on t he falling edge of the WE# or CE# pulse,  
whichever happens later .
PD = Data to be programmed  at location PA. Data latches  on t he 
rising edge of WE# or CE# pulse, whichever  happens fi rst.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Addr ess bits A18–A13 uniquely select any sector.
Notes:
1. See Table 1 f or  description of bus operations.
2. All values are  in hexadecimal.
3. Except  when reading arra y or autoselect data, all 
commandbus cycles are writ e operations.
4. Address bi ts A18–A11 are don’t cares for unlock and 
comm and cycl es.
5. No unlock or command cycle s required when reading array 
data.
6. The Reset command is required to return to readin g array 
data when dev ice is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
7. The four th cycle of the autoselect comm and sequence i s a 
read cycle.
8. The data is 00h for  an unprotected sector and 01h for a 
prote cted sector. See “Autoselect Command Sequenc e” for 
more information.
9. The system may read and program in non-erasing sectors, or 
enter  the a utose lect mode, when in the Eras e Suspend 
mode. The Erase Sus pend comm and is valid only  during a 
sector erase operation.
10. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-4)
First Second Third Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID, Top Boot Block  4 555 AA 2AA 55 555 90 X01 B5
Device ID,  Bottom Boot  Block 4 555 AA 2AA 55 555 90 X01 B6
Sector Protec t Verify 
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 5 5 555 80 555 AA 2A A 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resu me (Note 10) 1 XXX 30
Cycles

16 Am29LV004

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operatio n: DQ2, DQ 3, DQ5, DQ6, DQ7,

and RY/BY#. Table 6 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# P olling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command se-

quence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

gr ammed to D Q7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Em bedde d Progr am algo rith m is comp lete , the devic e

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected se ctor , Data# Polling on DQ7 is act ive for ap-

proximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device en ters the Eras e

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“ 0.” The sys tem must provide an address within any of

the sectors selecte d fo r erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the sys tem detects DQ7 has changed fro m the

complement to true data, it can read valid data at DQ7–

DQ0 on th e

following

read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 16, Data#

Polling Tim ings (During Embedded Algorithms), in the

“AC Character istics ” se ction illustrates th is.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21522A-6

Figure 4. Data# Poll ing Algorithm

Am29LV004 17
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising  edge of  the final WE# pu lse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 shows R Y/BY# for read, reset, program, and
er ase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Pr ogra m o r Eras e a lgor ith m is in pr ogre ss or com ple te,
or whether the device has entered the Erase Suspend
mod e. Tog gl e  Bit  I may be  rea d at an y addres s, an d is
va lid after the ri sin g edge of the fin al  WE # pu ls e in th e
command sequence (prior to the program or erase op-
er ation), and during the secto r  erase  time-out.
Du ring an  Embe dded  Pr ogra m or E rase al gor ithm op -
erat ion, succe ssive read cy cles to  any add ress c aus e
DQ6 to toggle. (The system may use either OE# or
CE # to contro l the read cycles.) When the operation is
comple te, DQ6 stops toggling.
After an erase command sequence is written,  if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data . If not  al l s el ec ted  se cto rs  ar e  pro te cted , the E m -
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
prot ected. 
The sys tem can use DQ6 and DQ2 toge ther to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is ,  the E m be dd e d Er as e al g or it hm i s i n  pr og re ss ),  DQ6
toggles. When the device enters the Erase Suspend
mod e, D Q6 stop s to ggling . Ho wever, the  syste m mu st
also use DQ2 to determine which sector s are erasing
or erase- susp ende d. Alter native ly, the syste m can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ 6 togg les f or ap proxi mat ely 2 µs  afte r the  prog ram
co mm an d s eq uence  is w r itten, th en  re tur ns  to r ea di n g
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Refer to Figure 5  for the toggle bit al gorithm, and to Fig-
ur e 17  i n  th e “ A C C h arac t er is t ics ”  sec t io n f o r  th e t og gl e
bit timing diagrams. Figure 18 shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that  is, the Embedded Erase algorithm is in progress),
or w het her t hat s ecto r is  eras e-susp ende d.  Tog gle  Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure . (The  syste m  may use  eith er OE # or CE# to  con -
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6. 
Figure 5 shows the toggle bit algorithm in flowchart
form , a nd  th e  section  “ DQ2 : To gg le  B it II” explains  th e
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Fi gure  17 sh ows  the  toggle  bit  timi ng d iagram . Fi gur e
18 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Fi gure 5 for the following di scuss ion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least  twic e in  a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of  the toggle bit after the
first read. A fter the second read, the  system woul d com-
pare the new value of the toggle bit with the first. If the
toggle bit is not togglin g, the device has com pleted the
program or erase operation. The system can read array
data on DQ7–DQ0 on the followi ng read cycle.
Howeve r, if after the initial two read cycles, the syste m
determine s that t he toggle  bit is still  toggling, t he sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
sin ce  the togg l e  bit may  h ave  s t op pe d t og gl ing  just a s
DQ5 went high. If the toggle bit is no longer toggling,
the d evic e has su cce ssfu lly comp let ed the  prog ram o r
erase o peration . If it is  still t oggling, t he de vice did  not
completed the operation successfully, and the system
must write the reset command to return to reading
array data. 

18 Am29LV004

PRELIMINARY

The r emaining sc enario is t hat the system initially de-

ter m in es th at th e t og gl e b i t is t o gg li ng a nd D Q5 ha s n ot

gone high. The system may continue to monitor the

toggle b it and DQ5 through successive read cycles, de-

termining the stat us a s described in the previ ous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ 5 in di ca te s w h eth er th e p ro gr am or e ra se t i me ha s

exceede d a specified inter na l pulse count limit. Unde r

thes e co ndi tions D Q5 p roduc es a “1.” This i s a fa ilur e

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

chan g e a “0 ” back to a “ 1.” Un der this condition, the

device halts the operation, and when the operation has

exceeded the ti min g limits, DQ5 produc es a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chi p erase command.) If additional

sectors are selected for erasure, the enti re time-out also

applies after each additional sector erase command.

When the time-out is complete, DQ3 swi tches from “0”

to “1.” T he system may ignore D Q3 if the system can

guarantee that the time between additional sector

erase commands will always be less than 50 µs. See

also the “Sector Erase Command Sequence” section.

After the sector erase command sequence is written,

the sy st em sh ou ld re ad th e st at u s o n DQ 7 ( Da ta# P oll -

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun ; al l f ur t her c omm an ds (o t he r t ha n Era se S usp en d)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the syste m software should check the status

of DQ3 prio r to and f ollo wing each subs equ ent se cto r

era se command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

21522A-7

Figure 5. Tog gle Bit Algorithm

(Notes

1, 2)

(Note 1)

Am29LV004 19

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a v alid address when reading status inf ormation. Ref er to the appropriate subsection for further details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Er ase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

20 Am29LV004

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions , input or I/O pins may undershoot V

to –2.0 V for periods of up to 20 ns. See Figure 6.

Maximum DC voltage on input or I/O pins is V

+0.5 V.

During voltage transitions, input or I/O pins may overshoot

to V

+2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may undershoot V

to –2.0 V for periods of up

to 20 ns. See Figure 6. Maximum DC input v oltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 6. Maximu m Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperatu re (TA) . . . . . . . . . . . 0°C to +7 0°C

Industrial (I) Devices

Ambient Temperatu re (TA) . . . . . . . . . –40°C to +8 5°C

Extended (E) Devices

Ambient Temperatu re (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for regulated voltage range. . . . . . .3.0 V to 3.6 V

VCC for full voltage range. . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21522A-8

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21522A-9

Am29LV004 21

PRELIMINARY

DC CHARACTERISTICS

CMOS Compatible

Notes:

1. The I

current listed is typically less than 2 mA/MHz, with OE# at V

. Typical V

is 3.0 V.

2. I

active while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30 ns.

4. Not 100% tested.

Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC,

VCC = VCC max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA

ILO Output Leakage Current VOUT = VSS to VCC,

VCC = VCC max ±1.0 µA

ICC1 VCC Active Read Current

(Note 1) CE# = VIL, OE# = VIH 5 MHz 10 16 mA

1 MHz 2 4

ICC2 VCC Active Write Current

(Notes 2 and 4) CE# = VIL, OE# = VIH 20 30 mA

ICC3 VCC Standby Current VCC = VCC max;

CE#, RESET# = VCC±0.3 V 0.2 5 µA

ICC4 VCC Standby Current During Reset VCC = VCC max;

RESET# = VSS ± 0.3 V 0.2 5 µA

ICC5 Automatic Sleep Mode (Note 3) VIH = VCC ± 0.3 V;

VIL = VSS ± 0.3 V 0.2 5 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V

VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V

VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC min V

CC–0.4

VLKO Low VCC Lock-Out Voltage (Note

4) 2.3 2.5 V

22 Am29LV004

PRELIMINARY

DC CHARACTERISTICS (Continued)

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in m A

Time in ns

Note: Addresses are switching at 1 MHz

21522A-10

Figure 8. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

Note: T = 25

21522A-11

Figure 9. Typical ICC1 vs. Frequency

1 2345

F requenc y in MHz

Supply Cur rent in mA

Am29LV004 23

PRELIMINARY

TEST CONDITIONS Tab le 7. Test Specifications

KEY TO SWITCHIN G WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

21522A-12

Fig ur e 10 . Test Se tup

Note: Diodes are IN3064 or equivalent

Test Condition -90R,

-100 -120,

-150 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

21522A-13

Figure 11. Input Waveforms and Measurement Levels

24 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 7 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup -90R -100 -120 -150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 90 100 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 40 40 50 55 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 30 30 30 40 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 30 30 30 40 ns

tOEH Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

21522A-14

Figure 12. Read Operations Ti mings

Am29LV004 25

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 n s

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21522A-15

Figure 13. RESET# Timings

26 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

Erase/Pr ogram Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

-90R -100 -120 -150JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 50 50 50 65 ns

tDVWH tDS Data Setup Time Min 50 50 50 65 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 50 50 50 65 ns

tWHWL tWPH Write Pulse Width High Min 30 30 30 35 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

Am29LV004 27

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

Data

Addresses

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

GHWL

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

Note: PA = program address, PD = program data, D

OUT

is the true data at the program address.

21522A-16

Figure 14. Program Operation Timings

28 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

WE#

Data

2AAh SA

GHWL

WPH

555h for chip erase

10 for Chip Erase

30h

VCS

55h

Progress Complete

WHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

BUSY

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

21522A-17

F igure 15. Chip/Sect or Erase Operation Timings

Am29LV004 29

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21522A-18

Figure 16. Data# Polling Timings (During Embedded Algorith ms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = Valid address; not required f or DQ6. Illustr ation shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

21522A-19

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

30 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21522A-20

Figure 18. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

12 V

0 or 3 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 3 V

21522A-21

Figure 19. Tempo rary Sector Unprotect Timing Diagram

Am29LV004 31

PRELIMINARY

AC CHARACTERISTICS

Alter nate CE# Controlled Erase/Pr og ram Operati ons

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 50 50 50 65 ns

tDVEH tDS Data Setup Time Min 50 50 50 65 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 50 50 50 65 ns

tEHEL tCPH CE# Pulse Width High Min 30 30 30 35 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ sec

32 Am29LV004

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, D

OUT

is the data written

to the device.

2. Figure indicates the last two bus cycles of the command sequence.

21522A-22

Figure 20. Altern ate CE# Contr olled Wr ite Operatio n Timings

Am29LV004 33

PRELIMINARY

ERASE AND PROGRAMMING P E RFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V V

, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5

for further information on command definitions.

6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.

LATCHUP CHARACTERISTICS

Includes all pins except V

. Test conditions: V

= 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 11 s

Byte Programming Time 9 300 µs Excludes system level

overhead (Note 5)

Chip Programming Time

(Note 3) 4.5 13.5 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

34 Am29LV004

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 040—40-Pin Standard TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

18.30

18.50

19.80

20.20

Pin 1 I.D.

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0˚

5˚

16-038-TSOP-1_AE

TS 040

2-27-97 lv

0.10

0.21

0.08

0.20

Am29LV004 35

PRELIMINARY

PHYSICAL DIMENSIONS

TSR048—48-Pin Re verse TSOP (measured in millimeter s)

18.30

18.50

19.80

20.20

Pin 1 I.D.

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0˚

5˚

16-038-TSOP-1_AE

TSR040

2-27-97 lv

0.10

0.21

0.08

0.20

36 Am29LV004

PRELIMINARY

REVISION SUMMARY

Global

Re vised f orm atting to b e con siste nt wi th ot her c urren t

3.0 volt-only data sheets.

Revision D+1

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled

Eras e/Pr ogram Op eration s:

C or rec ted th e notes refer -

ence for tWHWH1 and tWHWH2. These parameters are

100% tested. Corrected the note reference for tVCS.

This parameter is not 100% tested.

Temp orary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not

100% tested .

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used i n this publication are for identification purposes only and may be trademarks of their respective companies.