LTC2358ILX-18#PBF - ANALOG DEVICES

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TYPICAL APPLICATION

FEATURES DESCRIPTION

Buffered Octal, 18-Bit, 200ksps/Ch Differential

±10.24V ADC with 30VP-P Common Mode Range

The LT C

2358-18 is an 18-bit, low noise 8-channel simul-

taneous sampling successive approximation register (SAR)

ADC with buffered differential, wide common mode range

picoamp inputs. Operating from a 5V low voltage supply,

flexible high voltage supplies, and using the internal refer-

ence and buffer, each channel of this SoftSpan

ADC can be

independently configured on a conversion-by-conversion

basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to

5.12V signals. Individual channels may also be disabled

to increase throughput on the remaining channels.

The integrated picoamp-input analog buffers, wide input

common mode range and 128dB CMRR of the LTC2358-18

allow the ADC to directly digitize a variety of signals us-

ing minimal board space and power. This input signal

flexibility, combined with ±3.5LSB INL, no missing codes

at 18 bits, and 96.4dB SNR, makes the LTC2358-18 an

ideal choice for many high voltage applications requiring

wide dynamic range.

The LTC2358-18 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces. Between one and eight

lanes of data output may be employed in CMOS mode,

allowing the user to optimize bus width and throughput.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Analog Devices Inc. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235.

APPLICATIONS

n Simultaneous Sampling of 8 Buffered Channels

n 200ksps per Channel Throughput

n 500pA/12nA Max Input Leakage at 85°C/125°C

n ±3.5LSB INL (Maximum, ±10.24V Range)

n Guaranteed 18-Bit, No Missing Codes

n Differential, Wide Common Mode Range Inputs

n Per-Channel SoftSpan Input Ranges:

n ±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V

n ±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V

n 96.4dB Single-Conversion SNR (Typical)

n −111dB THD (Typical) at fIN = 2kHz

n 128dB CMRR (Typical) at fIN = 200Hz

n Rail-to-Rail Input Overdrive Tolerance

n Integrated Reference and Buffer (4.096V)

n SPI CMOS (1.8V to 5V) and LVDS Serial I/O

n Internal Conversion Clock, No Cycle Latency

n 219mW Power Dissipation (27mW/Ch Typical)

n 48-Lead (7mm x 7mm) LQFP Package

n Programmable Logic Controllers

n Industrial Process Control

n Power Line Monitoring

n Test and Measurement

Integral Nonlinearity vs

Output Code and Channel

0.1µF2.2µF0.1µF0.1µF

1.8V TO 5V5V15V

–15V

SAMPLE

CLOCK

235818 TA01a

VCC VDD VDDLBYP OVDD

BUFFERS

EIGHT BUFFERED

SIMULTANEOUS

SAMPLING CHANNELS

DIFFERENTIAL INPUTS IN+/IN– WITH

WIDE INPUT COMMON MODE RANGE

FULLY

DIFFERENTIAL

+10V

–10V

TRUE BIPOLAR

+10V

–10V

ARBITRARY

+10V

–10V

UNIPOLAR

+5V

–5V

S/H

MUX

SDO0

SDO7

SCKO

SCKI

SDI

BUSY

CNV

• • •

LVDS/CMOS

IN0+

IN0–

IN7+

IN7–

18-BIT

SAR ADC

CMOS OR LVDS

I/O INTERFACE

0.1µF

REFIN

47µF

0.1µF

GNDREFBUFVEE

LTC2358-18

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

vs Output Code and Channel

235818 TA01b

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) .....................–0.3V to (VEE + 40V)

Supply Voltage (VEE) ................................ –17.4V to 0.3V

Supply Voltage Difference (VCC – VEE) ...................... 40V

Supply Voltage (VDD) ..................................................6V

Supply Voltage (OVDD) ................................................6V

Internal Regulated Supply Bypass (VDDLBYP) ... (Note 3)

Analog Input Voltage

IN0+ to IN7+,

IN0– to IN7– (Note 4) ......... (VEE – 0.3V) to (VCC + 0.3V)

REFIN .................................................... –0.3V to 2.8V

REFBUF, CNV (Note 5) ............. –0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 5) ..... –0.3V to (OVDD + 0.3V)

Digital Output Voltage (Note 5) .. –0.3V to (OVDD + 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC2358C ................................................ 0°C to 70°C

LTC2358I .............................................–40°C to 85°C

LTC2358H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

IN6–

IN6+

IN5–

IN5+

IN4–

IN4+

IN3–

IN3+

IN2–

IN2+

IN1–

IN1+

IN0–

IN0+

GND

VCC

VEE

GND

REFIN

GND

REFBUF

LVDS/CMOS

CNV

IN7+

IN7–

GND

VEE

GND

VDD

GND

VDDLBYP

BUSY

SDI

SDO7

SDO–/SDO6

SDO+/SDO5

SCKO–/SDO4

SCKO+/SCKO

OVDD

GND

SCKI–/SCKI

SCKI+/SDO3

SDI–/SDO2

SDI+/SDO1

SDO0

TOP VIEW

LX PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

TJMAX = 150°C, θJA = 53°C/W

ORDER INFORMATION

TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2358CLX-18#PBF LTC2358LX-18 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C

LTC2358ILX-18#PBF LTC2358LX-18 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C

LTC2358HLX-18#PBF LTC2358LX-18 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

http://www.linear.com/product/LTC2358-18#orderinfo

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

ELECTRICAL CHARACTERISTICS

CONVERTER CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+ Absolute Input Range

(IN0+ to IN7+)

(Note 7) lVEE + 4 VCC – 4 V

VIN– Absolute Input Range

(IN0– to IN7–)

(Note 7) lVEE + 4 VCC – 4 V

VIN+ – VIN– Input Differential Voltage

Range

SoftSpan 7: ±2.5 • VREFBUF Range (Note 7)

SoftSpan 6: ±2.5 • VREFBUF/1.024 Range (Note 7)

SoftSpan 5: 0V to 2.5 • VREFBUF Range (Note 7)

SoftSpan 4: 0V to 2.5 • VREFBUF/1.024 Range (Note 7)

SoftSpan 3: ±1.25 • VREFBUF Range (Note 7)

SoftSpan 2: ±1.25 • VREFBUF/1.024 Range (Note 7)

SoftSpan 1: 0V to 1.25 • VREFBUF Range (Note 7)

–2.5 • VREFBUF

–2.5 • VREFBUF/1.024

–1.25 • VREFBUF

–1.25 • VREFBUF/1.024

2.5 • VREFBUF

2.5 • VREFBUF/1.024

2.5 • VREFBUF

2.5 • VREFBUF/1.024

1.25 • VREFBUF

1.25 • VREFBUF/1.024

1.25 • VREFBUF

VCM Input Common Mode Voltage

Range

(Note 7) lVEE + 4 VCC – 4 V

VIN+ – VIN– Input Differential Overdrive

Tolerance

(Note 8) l−(VCC − VEE) (VCC − VEE) V

IOVERDRIVE Input Overdrive

Current Tolerance

VIN+ > VCC, VIN– > VCC (Note 8)

VIN+ < VEE, VIN– < VEE (Note 8)

10 mA

IIN Analog Input Leakage Current

C-Grade and I-Grade

H-Grade

500

RIN Analog Input Resistance For Each Pin >1000 GΩ

CIN Analog Input Capacitance 3 pF

CMRR Input Common Mode

Rejection Ratio

VIN+ = VIN− = 18VP-P 200Hz Sine l100 128 dB

VIHCNV CNV High Level Input Voltage l1.3 V

VILCNV CNV Low Level Input Voltage l0.5 V

IINCNV CNV Input Current VIN = 0V to VDD l–10 10 μA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l18 Bits

No Missing Codes l18 Bits

Transition Noise SoftSpans 7 and 6: ±10.24V and ±10V Ranges

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges

SoftSpans 3 and 2: ±5.12V and ±5V Ranges

SoftSpan 1: 0V to 5.12V Range

1.4

2.8

2.1

4.2

LSBRMS

INL Integral Linearity Error SoftSpans 7 and 6: ±10.24V and ±10V Ranges (Note 10)

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10)

SoftSpans 3 and 2: ±5.12V and ±5V Ranges (Note 10)

SoftSpan 1: 0V to 5.12V Range (Note 10)

–3.5

–4

–6

±1

±1.5

±0.75

3.5

LSB

DNL Differential Linearity Error (Note 11) l−0.9 ±0.2 0.9 LSB

ZSE Zero-Scale Error (Note 12) l−700 ±160 700 μV

Zero-Scale Error Drift ±4 μV/°C

FSE Full-Scale Error VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) l−0.1 ±0.025 0.1 %FS

Full-Scale Error Drift VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) ±2.5 ppm/°C

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 6)

The

l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

DYNAMIC ACCURACY

INTERNAL REFERENCE CHARACTERISTICS

REFERENCE BUFFER CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise +

Distortion) Ratio

SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz

92.7

87.3

89.3

83.6

96.2

90.3

92.5

86.6

SNR Signal-to-Noise Ratio SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz

93.4

87.4

89.5

83.7

96.4

90.4

92.5

86.6

THD Total Harmonic Distortion SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz

–111

–107

–113

–101

–99

–102

–100

SFDR Spurious Free Dynamic

Range

SoftSpans 7 and 6: ±10.24V and ±10V Ranges, fIN = 2kHz

SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz

SoftSpans 3 and 2: ±5.12V and ±5V Ranges, fIN = 2kHz

SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz

101

103

113

107

113

Channel-to-Channel

Crosstalk

One Channel Converting 18VP-P 200Hz Sine in ±10.24V Range,

Crosstalk to All Other Channels

−109 dB

–3dB Input Bandwidth 6 MHz

Aperture Delay 1 ns

Aperture Delay Matching 150 ps

Aperture Jitter 3 psRMS

Transient Response Full-Scale Step, 0.005% Settling 420 ns

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V

Internal Reference Temperature Coefficient (Note 14) l5 20 ppm/°C

Internal Reference Line Regulation VDD = 4.75V to 5.25V 0.1 mV/V

Internal Reference Output Impedance 20 kΩ

VREFIN REFIN Voltage Range REFIN Overdriven (Note 7) 1.25 2.2 V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V l4.091 4.096 4.101 V

REFBUF Voltage Range REFBUF Overdriven (Notes 7, 15) l2.5 5 V

REFBUF Input Impedance VREFIN = 0V, Buffer Disabled 13 kΩ

IREFBUF REFBUF Load Current VREFBUF = 5V, 8 Channels Enabled (Notes 15, 16)

VREFBUF = 5V, Acquisition or Nap Mode (Note 15)

l1.5

0.39

1.9 mA

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 9, 13)

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

The

l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

DIGITAL INPUTS AND DIGITAL OUTPUTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS Digital Inputs and Outputs

VIH High Level Input Voltage l0.8•OVDD V

VIL Low Level Input Voltage l0.2•OVDD V

IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage IOUT = –500μA lOVDD–0.2 V

VOL Low Level Output Voltage IOUT = 500μA l0.2 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = OVDD 50 mA

LVDS Digital Inputs and Outputs

VID Differential Input Voltage l200 350 600 mV

RID On-Chip Input Termination

Resistance

CS = 0V, VICM = 1.2V

CS = OVDD

l90 106

125 Ω

MΩ

VICM Common-Mode Input Voltage l0.3 1.2 2.2 V

IICM Common-Mode Input Current VIN+ = VIN– = 0V to OVDD l–10 10 μA

VOD Differential Output Voltage RL = 100Ω Differential Termination l275 350 425 mV

VOCM Common-Mode Output Voltage RL = 100Ω Differential Termination l1.1 1.2 1.3 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)

POWER REQUIREMENTS

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage l7.5 38 V

VEE Supply Voltage l–16.5 0 V

VCC − VEE Supply Voltage Difference l10 38 V

VDD Supply Voltage l4.75 5.00 5.25 V

IVCC Supply Current 200ksps Sample Rate, 8 Channels Enabled (Note 17)

Acquisition Mode (Note 17)

Nap Mode

Power Down Mode

4.6

8.5

2.9

5.3

9.8

3.3

μA

IVEE Supply Current 200ksps Sample Rate, 8 Channels Enabled (Note 17)

Acquisition Mode (Note 17)

Nap Mode

Power Down Mode

–5.5

–9.8

–3.5

–15

–4.5

–8

–2.8

–4

μA

CMOS I/O Mode

OVDD Supply Voltage l1.71 5.25 V

IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled

200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Notes 15)

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

15.6

13.8

2.1

1.7

106

2.7

2.4

275

500

μA

µA

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (CL = 25pF)

Acquisition or Nap Mode

Power Down Mode

1.6

2.6

μA

PDPower Dissipation 200ksps Sample Rate, 8 Channels Enabled

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

219

258

0.68

259

308

114

1.9

LVDS I/O Mode

OVDD Supply Voltage l2.375 5.25 V

IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled

200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 15)

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

18.4

16.8

3.7

3.4

106

20.7

19.2

4.5

4.1

275

500

μA

µA

IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (RL = 100Ω)

Acquisition or Nap Mode (RL = 100Ω)

Power Down Mode

8.5

8.0

μA

PDPower Dissipation 200ksps Sample Rate, 8 Channels Enabled

Acquisition Mode

Nap Mode

Power Down Mode (C-Grade and I-Grade)

Power Down Mode (H-Grade)

245

284

120

0.68

287

337

143

1.9

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL Maximum Sampling Frequency 8 Channels Enabled

7 Channels Enabled

6 Channels Enabled

5 Channels Enabled

4 Channels Enabled

3 Channels Enabled

2 Channels Enabled

1 Channel Enabled

200

225

250

300

350

425

550

800

ksps

tCYC Time Between Conversions 8 Channels Enabled, fSMPL = 200ksps

7 Channels Enabled, fSMPL = 225ksps

6 Channels Enabled, fSMPL = 250ksps

5 Channels Enabled, fSMPL = 300ksps

4 Channels Enabled, fSMPL = 350ksps

3 Channels Enabled, fSMPL = 425ksps

2 Channels Enabled, fSMPL = 550ksps

1 Channel Enabled, fSMPL = 800ksps

5000

4444

4000

3333

2855

2350

1815

1250

tCONV Conversion Time N Channels Enabled, 1 ≤ N ≤ 8 l450•N 500•N 550•N ns

tACQ Acquisition Time

(tACQ = tCYC – tCONV – tBUSYLH)

8 Channels Enabled, fSMPL = 200ksps

7 Channels Enabled, fSMPL = 225ksps

6 Channels Enabled, fSMPL = 250ksps

5 Channels Enabled, fSMPL = 300ksps

4 Channels Enabled, fSMPL = 350ksps

3 Channels Enabled, fSMPL = 425ksps

2 Channels Enabled, fSMPL = 550ksps

1 Channel Enabled, fSMPL = 800ksps

570

564

670

553

625

670

685

670

980

924

980

813

835

830

795

730

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 9)

The

l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

POWER REQUIREMENTS

ADC TIMING CHARACTERISTICS

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 9)

ADC TIMING CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tCNVH CNV High Time l40 ns

tCNVL CNV Low Time l750 ns

tBUSYLH CNV↑ to BUSY Delay CL = 25pF l30 ns

tQUIET Digital I/O Quiet Time from CNV↑l20 ns

tPDH PD High Time l40 ns

tPDL PD Low Time l40 ns

tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1μF 200 ms

CMOS I/O Mode

tSCKI SCKI Period (Notes 18, 19) l10 ns

tSCKIH SCKI High Time l4 ns

tSCKIL SCKI Low Time l4 ns

tSSDISCKI SDI Setup Time from SCKI↑(Note 18) l2 ns

tHSDISCKI SDI Hold Time from SCKI↑(Note 18) l1 ns

tDSDOSCKI SDO Data Valid Delay from SCKI↑CL = 25pF (Note 18) l7.5 ns

tHSDOSCKI SDO Remains Valid Delay from SCKI↑CL = 25pF (Note 18) l1.5 ns

tSKEW SDO to SCKO Skew (Note 18) l–1 0 1 ns

tDSDOBUSYL SDO Data Valid Delay from BUSY↓CL = 25pF (Note 18) l0 ns

tEN Bus Enable Time After CS↓(Note 18) l15 ns

tDIS Bus Relinquish Time After CS↑(Note 18) l15 ns

LVDS I/O Mode

tSCKI SCKI Period (Note 20) l4 ns

tSCKIH SCKI High Time (Note 20) l1.5 ns

tSCKIL SCKI Low Time (Note 20) l1.5 ns

tSSDISCKI SDI Setup Time from SCKI (Notes 11, 20) l1.2 ns

tHSDISCKI SDI Hold Time from SCKI (Notes 11, 20) l–0.2 ns

tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 11, 20) l6 ns

tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 11, 20) l1 ns

tSKEW SDO to SCKO Skew (Note 11) l–0.4 0 0.4 ns

tDSDOBUSYL SDO Data Valid Delay from BUSY↓(Note 11) l0 ns

tEN Bus Enable Time After CS↓l50 ns

tDIS Bus Relinquish Time After CS↑l15 ns

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

CMOS Timings

0.8 • OVDD

0.2 • OVDD

50% 50%

235818 F01

0.2 • OVDD

0.8 • OVDD

0.2 • OVDD

0.8 • OVDD

tDELAY

tWIDTH

tDELAY

LVDS Timings (Differential)

+200mV

–200mV

0V 0V

235818 F01b

–200mV

+200mV

–200mV

+200mV

tDELAY

tWIDTH

tDELAY

Figure1. Voltage Levels for Timing Specifications

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: VDDLBYP is the output of an internal voltage regulator, and should

only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,

as described in the Pin Functions section. Do not connect this pin to any

external circuitry.

Note 4: When these pin voltages are taken below VEE or above VCC, they

will be clamped by internal diodes. This product can handle input currents

of up to 100mA below VEE or above VCC without latch-up.

Note 5: When these pin voltages are taken below GND or above VDD or

OVDD, they will be clamped by internal diodes. This product can handle

currents of up to 100mA below GND or above VDD or OVDD without latch-

up.

Note 6: –16.5V ≤ VEE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V,

VDD=5V, unless otherwise specified.

Note 7: Recommended operating conditions.

Note 8: Exceeding these limits on any channel may corrupt conversion

results on other channels. Driving an analog input above VCC on any

channel up to 10mA will not affect conversion results on other channels.

Driving an analog input below VEE may corrupt conversion results on other

channels. Refer to Applications Information section for further details.

Refer to Absolute Maximum Ratings section for pin voltage limits related

to device reliability.

Note 9: VCC = 15V, VEE = –15V, VDD = 5V, OVDD=2.5V, fSMPL = 200ksps,

internal reference and buffer, true bipolar input signal drive in bipolar

SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless

otherwise specified.

Note 10: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 11: Guaranteed by design, not subject to test.

Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error

is the offset voltage measured from –0.5LSB when the output code

flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111.

Full-scale error for these SoftSpan ranges is the worst-case deviation of

the first and last code transitions from ideal and includes the effect of

offset error. For unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is

the offset voltage measured from 0.5LSB when the output code flickers

between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full-

scale error for these SoftSpan ranges is the worst-case deviation of the

last code transition from ideal and includes the effect of offset error.

Note 13: All specifications in dB are referred to a full-scale input in the

relevant SoftSpan input range, except for crosstalk, which is referred to

the crosstalk injection signal amplitude.

Note 14: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 15: When REFBUF is overdriven, the internal reference buffer must

be disabled by setting REFIN = 0V.

Note 16: IREFBUF varies proportionally with sample rate and the number of

active channels.

Note 17: Analog input buffer supply currents from IVCC and IVEE are

reduced outside the acquisition period. Refer to nap mode in Applications

Information section.

Note 18: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,

and OVDD = 5.25V.

Note 19: A tSCKI period of 10ns minimum allows a shift clock frequency of

up to 100MHz for rising edge capture.

Note 20: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.

ADC TIMING CHARACTERISTICS

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code and Range

Integral Nonlinearity

vs Output Code DC Histogram (Zero-Scale) DC Histogram (Near Full-Scale)

Integral Nonlinearity

vs Output Code and Channel

Integral Nonlinearity

vs Output Code and Channel

Differential Nonlinearity

vs Output Code and Channel

ALL RANGES

ALL CHANNELS

OUTPUT CODE

65536

131072

196608

262144

–0.5

–0.4

–0.3

–0.2

–0.1

0.0

0.1

0.2

0.3

0.4

0.5

DNL ERROR (LSB)

235818 G03

±10.24V RANGE

σ = 1.35

CODE

–6

–4

–2

10000

20000

30000

40000

50000

60000

70000

80000

90000

100000

COUNTS

235818 G08

±10.24V RANGE

σ = 1.4

CODE

131024

131027

131030

131033

131036

10000

20000

30000

40000

50000

60000

70000

80000

90000

COUNTS

235818 G09

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 200ksps, unless otherwise noted.

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ARBITRARY DRIVE

/IN

–

COMMON MODE

SWEPT –10.24V to 10.24V

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

235818 G07

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

vs Output Code and Channel

235818 G01

±10.24V RANGE

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

ALL CHANNELS

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

235818 G02

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ONE CHANNEL

±10.24V AND ±10V

RANGES

±5.12V AND ±5V

RANGES

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

235818 G04

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

ONE CHANNEL

±10.24V, ±10V

RANGES

±5.12V, AND ±5V

RANGES

OUTPUT CODE

–131072

–65536

65536

131072

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

vs Output Code and Range

235818 G05

UNIPOLAR DRIVE (IN

–

= 0V)

ONE CHANNEL

0V TO 5.12V RANGE

0V TO 10.24V AND

0V TO 10V RANGES

OUTPUT CODE

65536

131072

196608

262144

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL ERROR (LSB)

235818 G06

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TYPICAL PERFORMANCE CHARACTERISTICS

32k Point FFT fSMPL = 200kHz,

fIN=2kHz

SNR, SINAD vs VREFBUF,

fIN=2kHz

THD, Harmonics vs VREFBUF,

fIN=2kHz

SNR, SINAD

vs Input Frequency THD vs Input Frequency

THD, Harmonics vs Input

Common Mode, fIN = 2kHz

32k Point FFT fSMPL=200kHz,

fIN=2kHz

32k Point FFT fSMPL=200kHz,

fIN=2kHz

32k Point Arbitrary Two-Tone FFT

fSMPL=200kHz, IN+=–7dBFS 2kHz

Sine, IN–=–7dBFS 3.1kHz Sine

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

SNR = 96.3dB

THD = –110dB

SINAD = 96.2dB

SFDR = 113dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 G10

±10.24V RANGE

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

SNR = 96.4dB

THD = –114dB

SINAD = 96.3dB

SFDR = 118dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 G11

±10.24V RANGE

ARBITRARY DRIVE

SFDR = 119dB

SNR = 96.4dB

6.2kHz

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 G12

±5.12V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

SNR = 92.8dB

THD = –112dB

SINAD = 92.7dB

SFDR = 117dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 G13

SNR

SINAD

±2.5 • V

REFBUF

RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

REFBUF VOLTAGE (V)

2.5

3.5

4.5

100

SNR, SINAD (dBFS)

235818 G14

THD

2ND

3RD

±2.5 • V

REFBUF

RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

REFBUF VOLTAGE (V)

2.5

3.5

4.5

–130

–125

–120

–115

–110

–105

–100

THD, HARMONICS (dBFS)

235818 G15

2ND

THD

3RD

P–P

FULLY DIFFERENTIAL DRIVE

–11V ≤ V

≤ 11V

±10.24V RANGE

INPUT COMMON MODE (V)

–15

–10

–5

–160

–140

–120

–100

–80

–60

–40

–20

THD, HARMONICS (dBFS)

235818 G18

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 200ksps, unless otherwise noted.

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

FREQUENCY (Hz)

100

10k

100k

100

SNR, SINAD (dBFS)

235818 G16

THD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

50Ω SOURCE

1kΩ

SOURCE

10kΩ

SOURCE

FREQUENCY (Hz)

100

10k

100k

–130

–120

–110

–100

–90

–80

–70

–60

THD (dBFS)

THD vs Input Frequency

235818 G17

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TYPICAL PERFORMANCE CHARACTERISTICS

SNR, SINAD vs Temperature,

fIN=2kHz

THD, Harmonics vs Temperature,

fIN = 2kHz INL, DNL vs Temperature

Analog Input Leakage

Current vs Temperature

Positive Full-Scale Error vs

Temperature and Channel

Zero-Scale Error vs

Temperature and Channel

SNR, SINAD vs Input Level,

fIN=2kHz

CMRR vs Input Frequency

and Channel

Crosstalk vs Input Frequency

and Channel

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

INPUT LEVEL (dBFS)

–40

–30

–20

–10

96.0

96.2

96.4

96.6

96.8

97.0

SNR, SINAD (dBFS)

235818 G19

±10.24V RANGE

= IN

–

= 18V

P–P

SINE

ALL CHANNELS

FREQUENCY (Hz)

100

10k

100k

100

110

120

130

140

CMRR (dB)

235818 G20

CH1

±10.24V RANGE

IN0

= 0V

IN0

–

= 18V

P–P

SINE

ALL CHANNELS CONVERTING

CH7

CH2

FREQUENCY (Hz)

100

10k

100k

–135

–130

–125

–120

–115

–110

–105

–100

–95

–90

–85

–80

CROSSTALK (dB)

235818 G21

SNR

SINAD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

TEMPERATURE (°C)

–55

–35

–15

105

125

94.0

94.5

95.0

95.5

96.0

96.5

97.0

97.5

98.0

SNR, SINAD (dBFS)

235818 G22

THD

2ND

3RD

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

TEMPERATURE (°C)

–55

–35

–15

105

125

–125

–120

–115

–110

–105

–100

–95

THD, HARMONICS (dBFS)

235818 G23

MAX INL

MIN INL

MAX DNL

MIN DNL

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

INL, DNL ERROR (LSB)

235818 G24

±10.24V RANGE

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–5

–4

–3

–2

–1

ZERO–SCALE ERROR (LSB)

235818 G27

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 200ksps, unless otherwise noted.

16 ANALOG INPUT PIN TRACES

FOR EACH INPUT VOLTAGE

IN = 0V

IN = +10V

IN = –10V

TEMPERATURE (°C)

–55

–35

–15

105

125

0.1

100

10k

ANALOG INPUT LEAKAGE CURRENT (pA)

235818 G25

±10.24V RANGE

REFBUF OVERDRIVEN

REFBUF

= 4.096V

ALL CHANNELS

TEMPERATURE (°C)

–55

–35

–15

105

125

–0.100

–0.075

–0.050

–0.025

0.000

0.025

0.050

0.075

0.100

FULL–SCALE ERROR (%)

Temperature and Channel

235818 G26

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Sampling Rate

Power Dissipation vs Sampling

Rate, N-Channels Enabled

Step Response

(Large-Signal Settling)

Supply Current vs Temperature

Power-Down Current

vs Temperature

OVDD

VDD

VEE

VCC

TEMPERATURE (°C)

–55

–35

–15

105

125

–6

–4

–2

SUPPLY CURRENT (mA)

235818 G28

OVDD

VDD

–I

VEE

VCC

TEMPERATURE (°C)

–55

–35

–15

105

125

0.01

0.1

100

1000

POWER-DOWN CURRENT (µA)

235818 G29

Offset Error

vs Input Common Mode

= 38V, V

= 0V

= 4V to 34V

±10.24V RANGE

= 21.5V, V

= –16.5V

= –12.5V to 17.5V

INPUT COMMON MODE (V)

–17

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

OFFSET ERROR (LSB)

235818 G31

Internal Reference Output

vs Temperature

15 UNITS

TEMPERATURE (°C)

–55

–35

–15

105

125

2.045

2.046

2.047

2.048

2.049

2.050

2.051

INTERNAL REFERENCE OUTPUT (V)

235818 G32

OVDD

VDD

VEE

VCC

WITH NAP MODE

CNVL

= 1µs

SAMPLING FREQUENCY (kHz)

120

160

200

–6

–4

–2

SUPPLY CURRENT (mA)

235818 G33

TA = 25°C, VCC=+15V, VEE=–15V, VDD=5V,

OVDD=2.5V, Internal Reference and Buffer (VREFBUF =4.096V), fSMPL = 200ksps, unless otherwise noted.

±10.24V RANGE

= 199.99987kHz SQUARE WAVE

–

= 0V

SETTLING TIME (ns)

–100

100

200

300

400

500

600

700

800

900

–131072

–98304

–65536

–32768

32768

65536

98304

131072

OUTPUT CODE (LSB)

235818 G35

±10.24V RANGE

= 199.99987kHz

SQUARE WAVE

–

= 0V

SETTLING TIME (ns)

–100

100

200

300

400

500

600

700

800

900

–250

–200

–150

–100

–50

100

150

200

250

DEVIATION FROM FINAL VALUE (LSB)

235818 G36

PSRR vs Frequency

= IN

–

= 0V

FREQUENCY (Hz)

100

10k

100k

100

110

120

130

140

150

PSRR (dB)

235818 G30

Step Response

(Fine Settling)

WITH NAP MODE

CNVL

= 750ns

N = 8

N = 1

N = 2

N = 4

SAMPLING FREQUENCY (kHz)

100

200

300

400

500

600

700

800

100

120

140

160

180

200

220

240

260

POWER DISSIPATION (mW)

Rate, N–Channels Enabled

235818 G34

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

PIN FUNCTIONS

Pins that are the Same for All Digital I/O Modes

IN0+/IN0– to IN7+/IN7– (Pins 14/13, 12/11, 10/9, 8/7, 6/5,

4/3, 2/1, and 48/47): Positive and Negative Analog Inputs,

Channels 0 to 7. The converter simultaneously samples

and digitizes (VIN+ – VIN–) for all channels. Wide input

common mode range (VEE + 4V≤ VCM ≤ VCC – 4V) and

high common mode rejection allow the inputs to accept

a wide variety of signal swings. Full-scale input range is

determined by the channel’s SoftSpan configuration.

GND (Pins 15, 18, 20, 30, 41, 44, 46): Ground. Solder

all GND pins to a solid ground plane.

VCC (Pin 16): Positive High Voltage Power Supply. The

range of VCC is 7.5V to 38V with respect to GND and 10V

to 38V with respect to VEE. Bypass VCC to GND close to

the pin with a 0.1μF ceramic capacitor.

VEE (Pins 17, 45): Negative High Voltage Power Supply.

The range of VEE is 0V to –16.5V with respect to GND and

–10V to –38V with respect to VCC. Connect Pins 17 and 45

together and bypass the VEE network to GND close to Pin

17 with a 0.1μF ceramic capacitor. In applications where

VEE is shorted to GND, this capacitor may be omitted.

REFIN (Pin 19): Bandgap Reference Output/Reference Buf-

fer Input. An internal bandgap reference nominally outputs

2.048V on this pin. An internal reference buffer amplifies

VREFIN to create the converter master reference voltage

VREFBUF = 2•VREFIN on the REFBUF pin. When using the

internal reference, bypass REFIN to GND (Pin 20) close to

the pin with a 0.1μF ceramic capacitor to filter the bandgap

output noise. If more accuracy is desired, overdrive REFIN

with an external reference in the range of 1.25V to 2.2V.

Do not load this pin when internal reference is used.

REFBUF (Pin 21): Internal Reference Buffer Output. An

internal reference buffer amplifies VREFIN to create the

converter master reference voltage VREFBUF = 2•VREFIN

on this pin, nominally 4.096V when using the internal

bandgap reference. Bypass REFBUF to GND (Pin 20) close

to the pin with a 47μF ceramic capacitor. The internal ref-

erence buffer may be disabled by grounding its input at

REFIN. With the buffer disabled, overdrive REFBUF with

an external reference voltage in the range of 2.5V to 5V.

When using the internal reference buffer, limit the loading

of any external circuitry connected to REFBUF to less than

200µA. Using a high input impedance amplifier to buffer

VREFBUF to any external circuits is recommended.

PD (Pin 22): Power Down Input. When this pin is brought

high, the LTC2358-18 is powered down and subsequent

conversion requests are ignored. If this occurs during a

conversion, the device powers down once the conversion

completes. If this pin is brought high twice without an

intervening conversion, an internal global reset is initi-

ated, equivalent to a power-on-reset event. Logic levels

are determined by OVDD.

LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD

to select LVDS I/O mode, or to ground to select CMOS I/O

mode. Logic levels are determined by OVDD.

CNV (Pin 24): Conversion Start Input. A rising edge on

this pin puts the internal sample-and-holds into the hold

mode and initiates a new conversion. CNV is not gated

by CS, allowing conversions to be initiated independent

of the state of the serial I/O bus.

BUSY (Pin 38): Busy Output. The BUSY signal indicates

that a conversion is in progress. This pin transitions low-

to-high at the start of each conversion and stays high until

the conversion is complete. Logic levels are determined

by OVDD.

VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The

voltage on this pin is generated via an internal regulator

operating off of VDD. This pin must be bypassed to GND

close to the pin with a 2.2μF ceramic capacitor. Do not

connect this pin to any external circuitry.

VDD (Pins 42, 43): 5V Power Supply. The range of VDD

is 4.75V to 5.25V. Connect Pins 42 and 43 together and

bypass the VDD network to GND with a shared 0.1μF

ceramic capacitor close to the pins.

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

PIN FUNCTIONS

CMOS I/O Mode

SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36):

CMOS Serial Data Outputs, Channels 0 to 7. The most

recent conversion result along with channel configuration

information is clocked out onto the SDO pins on each ris-

ing edge of SCKI. Output data formatting is described in

the Digital Interface section. Leave unused SDO outputs

unconnected. Logic levels are determined by OVDD.

SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with

the serial I/O clock. SCKI rising edges latch serial data in

on SDI and clock serial data out on SDO0 to SDO7. For

standard SPI bus operation, capture output data at the

receiver on rising edges of SCKI. SCKI is allowed to idle

either high or low. Logic levels are determined by OVDD.

OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O

mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising

edges trigger transitions on SCKO that are skew-matched

to the serial output data streams on SDO0 to SDO7. The

resulting SCKO frequency is half that of SCKI. Rising and

falling edges of SCKO may be used to capture SDO data

at the receiver (FPGA) in double data rate (DDR) fashion.

For standard SPI bus operation, SCKO is not used and

should be left unconnected. SCKO is forced low at the

falling edge of BUSY. Logic levels are determined by OVDD.

SDI (Pin 37): CMOS Serial Data Input. Drive this pin with the

desired 24-bit SoftSpan configuration word (see Table1a),

latched on the rising edges of SCKI. If all channels will be

configured to operate only in SoftSpan 7, tie SDI to OVDD.

Logic levels are determined by OVDD.

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI.

Logic levels are determined by OVDD.

LVDS I/O Mode

SDO0, SDO7, SDI (Pins 25, 36, and 37): CMOS Serial

Data I/O. In LVDS I/O mode, these pins are Hi-Z.

SDI+/SDI– (Pins 26/27): LVDS Positive and Negative Serial

Data Input. Differentially drive SDI+/SDI– with the desired

24-bit SoftSpan configuration word (see Table 1a), latched

on both the rising and falling edges of SCKI+/SCKI–. The

SDI+/SDI– input pair is internally terminated with a 100Ω

differential resistor when CS is low.

SCKI+/SCKI– (Pins 28/29): LVDS Positive and Negative

Serial Clock Input. Differentially drive SCKI+/SCKI– with

the serial I/O clock. SCKI+/SCKI– rising and falling edges

latch serial data in on SDI+/SDI– and clock serial data out

on SDO+/SDO–. Idle SCKI+/SCKI– low, including when

transitioning CS. The SCKI+/SCKI– input pair is internally

terminated with a 100Ω differential resistor when CS is low.

OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O

mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD

to GND (Pin 30) close to the pin with a 0.1μF ceramic

capacitor.

SCKO+/SCKO– (Pins 32/33): LVDS Positive and Negative

Serial Clock Output. SCKO+/SCKO– outputs a copy of the

input serial I/O clock received on SCKI+/SCKI–, skew-

matched with the serial output data stream on SDO+/SDO–.

Use the rising and falling edges of SCKO+/SCKO– to cap-

ture SDO+/SDO– data at the receiver (FPGA). The SCKO+/

SCKO– output pair must be differentially terminated with

a 100Ω resistor at the receiver (FPGA).

SDO+/SDO– (Pins 34/35): LVDS Positive and Negative

Serial Data Output. The most recent conversion result

along with channel configuration information is clocked

out onto SDO+/SDO– on both rising and falling edges of

SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–

output pair must be differentially terminated with a 100Ω

resistor at the receiver (FPGA).

CS (Pin 39): Chip Select Input. The serial data I/O bus is

enabled when CS is low, and is disabled and Hi-Z when

CS is high. CS also gates the external shift clock, SCKI+/

SCKI–. The internal 100Ω differential termination resistors

on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled

when CS is high. Logic levels are determined by OVDD.

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

CONFIGURATION TABLES

Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each

Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 24-Bit SoftSpan Configuration Word S[23:0]. Use

Serial Interface to Write SoftSpan Configuration Word to LTC2358-18, as shown in Figure 18

BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE FULL SCALE RANGE BINARY FORMAT OF

CONVERSION RESULT

111 ±2.5 • VREFBUF 5 • VREFBUF Tw o ’s Complement

110 ±2.5 • VREFBUF/1.024 5 • VREFBUF/1.024 Tw o ’s Complement

101 0V to 2.5 • VREFBUF 2.5 • VREFBUF Straight Binary

100 0V to 2.5 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Straight Binary

011 ±1.25 • VREFBUF 2.5 • VREFBUF Tw o ’s Complement

010 ±1.25 • VREFBUF/1.024 2.5 • VREFBUF/1.024 Tw o ’s Complement

001 0V to 1.25 • VREFBUF 1.25 • VREFBUF Straight Binary

000 Channel Disabled Channel Disabled All Zeros

Table 1b. Reference Configuration Table. The LTC2358-18 Supports Three Reference Configurations. Analog Input Range Scales with

the Converter Master Reference Voltage, VREFBUF

REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE

Internal Reference with

Internal Buffer 2.048V 4.096V

111 ±10.24V

110 ±10V

101 0V to 10.24V

100 0V to 10V

011 ±5.12V

010 ±5V

001 0V to 5.12V

External Reference with

Internal Buffer

(REFIN Pin Externally

Overdriven)

1.25V

(Min Value) 2.5V

111 ±6.25V

110 ±6.104V

101 0V to 6.25V

100 0V to 6.104V

011 ±3.125V

010 ±3.052V

001 0V to 3.125V

2.2V

(Max Value) 4.4V

111 ±11V

110 ±10.742V

101 0V to 11V

100 0V to 10.742V

011 ±5.5V

010 ±5.371V

001 0V to 5.5V

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE

SS[2:0] ANALOG INPUT RANGE

External Reference

Unbuffered

(REFBUF Pin

Externally Overdriven,

REFIN Pin Grounded)

0V 2.5V

(Min Value)

111 ±6.25V

110 ±6.104V

101 0V to 6.25V

100 0V to 6.104V

011 ±3.125V

010 ±3.052V

001 0V to 3.125V

0V 5V

(Max Value)

111 ±12.5V

110 ±12.207V

101 0V to 12.5V

100 0V to 12.207V

011 ±6.25V

010 ±6.104V

001 0V to 6.25V

CONFIGURATION TABLES

Table 1b. Reference Configuration Table (Continued). The LTC2358-18 Supports Three Reference Configurations. Analog Input Range

Scales with the Converter Master Reference Voltage, VREFBUF

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

FUNCTIONAL BLOCK DIAGRAM

SDO0

SDO7

SCKO

SDI

SCKI

IN0+

IN0–

BUSY

18-BIT

SAR ADC

CMOS

SERIAL

I/O

INTERFACE

235818 BD01

18 BITS

REFERENCE

BUFFER

REFBUFREFINGND

VCC

VEE

VDDLBYP

VDD OVDD

LTC2358-18

CONTROL

LOGIC

2.048V

REFERENCE

2.5V

REGULATOR

LVDS/CMOSPDCNV

IN1+

IN1–

S/H

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

IN5+

IN5–

IN6+

IN6–

IN7+

IN7–

8-CHANNEL MULTIPLEXER

20k

2×

• • •

BUFFERS

SDO+

SDO–

SCKO+

SCKO–

SDI+

SDI–

SCKI+

SCKI–

IN0+

IN0–

BUSY

18-BIT

SAR ADC

LVDS

SERIAL

I/O

INTERFACE

235818 BD02

18 BITS

REFERENCE

BUFFER

REFBUFREFINGND

VCC

VEE

VDDLBYP

VDD OVDD

LTC2358-18

CONTROL

LOGIC

2.048V

REFERENCE

2.5V

REGULATOR

LVDS/CMOSPDCNV

S/H

IN1+

IN1–S/H

IN2+

IN2–S/H

IN3+

IN3–S/H

IN4+

IN4–S/H

IN5+

IN5–S/H

IN6+

IN6–S/H

IN7+

IN7–S/H

8-CHANNEL MULTIPLEXER

20k

2×

BUFFERS

LVDS I/O Mode

CMOS I/O Mode

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

TIMING DIAGRAM

LVDS I/O Mode

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17 D16 D15

CNV

(CMOS)

CS = PD = 0

235818 TD02

CONVERT

DON’T CARE

ACQUIRE

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

SAMPLE N

• • •

SAMPLE

N + 1

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

CHANNEL 0

CONVERSION N

CHANNEL 1

CONVERSION N

CHANNEL 7

CONVERSION N

CONVERSION RESULT CHANNEL ID SoftSpan

186 187 188 189 190 191 192

D0 SS1SS2 SS0 D17

CHANNEL 0

CONVERSION N

CONVERSION

RESULT

CHANNEL ID SoftSpan

C2 C1 C0 C2 C1 C0

CMOS I/O Mode

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C2 C1 C0

C2 C1 C0

SS1SS2 SS0 D17

CNV

CS = PD = 0

CONVERT

DON’T CARE

ACQUIREBUSY

SDO7

SCKO

SDO0

SCKI

SDI

DON’T CARE

SAMPLE N SAMPLE N + 1

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

CHANNEL 0

CONVERSION N

CHANNEL 1

CONVERSION N

CHANNEL 7

CONVERSION N

CHANNEL 0

CONVERSION N

235818 TD01

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17DON’T CARE

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

• • •

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

APPLICATIONS INFORMATION

OVERVIEW

The LTC2358-18 is an 18-bit, low noise 8-channel si-

multaneous sampling successive approximation register

(SAR) ADC with buffered differential, wide common

mode range picoamp inputs. The ADC operates from a

5V low voltage supply and flexible high voltage supplies,

nominally ±15V. Using the integrated low-drift reference

and buffer (VREFBUF = 4.096V nominal), each channel of

this SoftSpan ADC can be independently configured on a

conversion-by-conversion basis to accept ±10.24V, 0V to

10.24V, ±5.12V, or 0V to 5.12V signals. The input signal

range may be expanded up to ±12.5V using an external

5V reference. Individual channels may also be disabled to

increase throughput on the remaining channels.

The integrated picoamp-input analog buffers, wide input

common mode range, and 128dB CMRR of the LTC2358-

18 allow the ADC to directly digitize a variety of signals

using minimal board space and power. This input signal

flexibility, combined with ±3.5LSB INL, no missing codes

at 18 bits, and 96.4dB SNR, makes the LTC2358-18 an

ideal choice for many high voltage applications requiring

wide dynamic range.

The absolute common mode input range (VEE + 4V to

VCC–4V) is determined by the choice of high voltage

supplies. These supplies may be biased asymmetrically

around ground and include the ability for VEE to be tied

directly to ground.

The LTC2358-18 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces, enabling it to com-

municate equally well with legacy microcontrollers and

modern FPGAs. In CMOS mode, applications may employ

between one and eight lanes of serial output data, allowing

the user to optimize bus width and data throughput. The

LTC2358-18 typically dissipates 219mW when converting

eight channels simultaneously at 200ksps per channel.

Optional nap and power down modes may be employed to

further reduce power consumption during inactive periods.

CONVERTER OPERATION

The LTC2358-18 operates in two phases. During the ac-

quisition phase, the sampling capacitors in each channel’s

sample-and-hold (S/H) circuit connect to their respective

analog input buffers, which track the differential analog

input voltage (VIN+ – VIN–). A rising edge on the CNV pin

transitions all channels’ S/H circuits from track mode to

hold mode, simultaneously sampling the input signals on all

channels and initiating a conversion. During the conversion

phase, each channel’s sampling capacitors are connected,

one channel at a time, to an 18-bit charge redistribution

capacitor D/A converter (CDAC). The CDAC is sequenced

through a successive approximation algorithm, effectively

comparing the sampled input voltage with binary-weighted

fractions of the channel’s SoftSpan full-scale range (e.g.,

VFSR/2, VFSR/4 … VFSR/262144) using a differential

comparator. At the end of this process, the CDAC output

approximates the channel’s sampled analog input. Once

all channels have been converted in this manner, the ADC

control logic prepares the 18-bit digital output codes from

each channel for serial transfer.

TRANSFER FUNCTION

The LTC2358-18 digitizes each channel’s full-scale voltage

range into 218 levels. In conjunction with the ADC master

reference voltage, VREFBUF, a channel’s SoftSpan configu-

ration determines its input voltage range, full-scale range,

LSB size, and the binary format of its conversion result, as

shown in Tables 1a and 1b. For example, employing the

internal reference and buffer (VREFBUF = 4.096V nominal),

SoftSpan 7 configures a channel to accept a ±10.24V

bipolar analog input voltage range, which corresponds

to a 20.48V full-scale range with a 78.125μV LSB. Other

SoftSpan configurations and reference voltages may be

employed to convert both larger and smaller bipolar and

unipolar input ranges. Conversion results are output in

two’s complement binary format for all bipolar SoftSpan

ranges, and in straight binary format for all unipolar

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

SoftSpan ranges. The ideal two’s complement transfer

function is shown in Figure 2, while the ideal straight

binary transfer function is shown in Figure 3.

INPUT VOLTAGE (V)

OUTPUT CODE (TWO’S COMPLEMENT)

–1

LSB

235818 F02

011...111

011...110

000...001

000...000

100...000

100...001

111...110

LSB

BIPOLAR

ZERO

111...111

FSR/2 – 1LSB–FSR/2

FSR = +FS – –FS

1LSB = FSR/262144

Figure2. LTC2358-18 Two’s Complement Transfer Function

INPUT VOLTAGE (V)

OUTPUT CODE (STRAIGHT BINARY)

235818 F03

111...111

111...110

100...001

100...000

000...000

000...001

011...110

UNIPOLAR

ZERO

011...111

FSR – 1LSB0V

FSR = +FS

1LSB = FSR/262144

Figure3. LTC2358-18 Straight Binary Transfer Function

BUFFERED ANALOG INPUTS

Each channel of the LTC2358-18 simultaneously samples

the voltage difference (VIN+–VIN–) between its analog

input pins over a wide common mode input range while

attenuating unwanted signals common to both input pins

by the common-mode rejection ratio (CMRR) of the ADC.

Wide common mode input range coupled with high CMRR

allows the IN+/IN– analog inputs to swing with an arbitrary

relationship to each other, provided each pin remains

between (VEE+4V) and (VCC–4V). This feature of the

APPLICATIONS INFORMATION

LTC2358-18 enables it to accept a wide variety of signal

swings, including traditional classes of analog input signals

such as pseudo-differential unipolar, pseudo-differential

true bipolar, and fully differential, simplifying signal chain

design. For conversion of signals extending to VEE, the

unbuffered LTC2348-18 ADC is recommended.

The wide operating range of the high voltage supplies

offers further input common mode flexibility. As long as

the voltage difference limits of 10V≤(VCC–VEE)≤38V

are observed, VCC and VEE may be independently biased

anywhere within their own individually allowed operating

ranges, including the ability for VEE to be tied directly to

ground. This feature enables the common mode input

range of the LTC2358-18 to be tailored to specific ap-

plication requirements.

In all SoftSpan ranges, each channel’s analog inputs can

be modeled by the equivalent circuit shown in Figure 4. At

the start of acquisition, the sampling capacitors (CSAMP)

connect to the integrated buffers Buffer+/Buffer– through

the sampling switches. The sampled voltage is reset dur-

ing the conversion process and is therefore re-acquired

for each new conversion.

The diodes between the inputs and the VCC and VEE sup-

plies provide input ESD protection. While within the supply

voltages, the analog inputs of the LTC2358-18 draw only

5pA typical DC leakage current and the ESD protection

diodes don’t turn on. This offers a significant advantage

over external op amp buffers, which often have diode

protection that turns on during transients and corrupts

the voltage on any filter capacitors at their inputs.

IN+

RSAMP

750Ω

RSAMP

750Ω

CSAMP

30pF

CSAMP

30pF

VCC

VEE

BIAS

VOLTAGE

IN–235818 F04

BUFFER+

BUFFER–

Figure4. Equivalent Circuit for Differential Analog

Inputs, Single Channel Shown

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

APPLICATIONS INFORMATION

Bipolar SoftSpan Input Ranges

For channels configured in SoftSpan ranges 7, 6, 3,

or 2, the LTC2358-18 digitizes the differential analog

input voltage (VIN+ – VIN–) over a bipolar span of

±2.5•VREFBUF, ±2.5•VREFBUF/1.024, ±1.25•VREFBUF,

or ±1.25•VREFBUF/1.024, respectively, as shown in Table

1a. These SoftSpan ranges are useful for digitizing input

signals where IN+ and IN– swing above and below each

other. Traditional examples include fully differential input

signals, where IN+ and IN– are driven 180 degrees out-of-

phase with respect to each other centered around a common

mode voltage (VIN+ + VIN–)/2, and pseudo-differential

true bipolar input signals, where IN+ swings above and

below a ground reference level, driven on IN–. Regardless

of the chosen SoftSpan range, the wide common mode

input range and high CMRR of the IN+/IN– analog inputs

allow them to swing with an arbitrary relationship to each

other, provided each pin remains between (VCC – 4V) and

(VEE+4V). The output data format for all bipolar SoftSpan

ranges is two’s complement.

Unipolar SoftSpan Input Ranges

For channels configured in SoftSpan ranges 5, 4, or 1, the

LTC2358-18 digitizes the differential analog input voltage

(VIN+ – VIN–) over a unipolar span of 0V to 2.5•VREFBUF,

0V to 2.5•VREFBUF/1.024, or 0V to 1.25•VREFBUF, respec-

tively, as shown in Table 1a. These SoftSpan ranges are

useful for digitizing input signals where IN+ remains above

IN–. A traditional example includes pseudo-differential

unipolar input signals, where IN+ swings above a ground

reference level, driven on IN–. Regardless of the chosen

SoftSpan range, the wide common mode input range and

high CMRR of the IN+/IN– analog inputs allow them to

swing with an arbitrary relationship to each other, provided

each pin remains between (VCC – 4V) and (VEE+4V).

The output data format for all unipolar SoftSpan ranges

is straight binary.

INPUT DRIVE CIRCUITS

The CMOS buffer input stage offers a very high degree of

transient isolation from the sampling process. Most sen-

sors, signal conditioning amplifiers and filter networks with

less than 10kΩ of impedance can drive the passive 3pF

analog input capacitance directly. For higher impedances

and slow-settling circuits, add a 680pF capacitor at the

pins to maintain the full DC accuracy of the LTC2358-18.

The very high input impedance of the unity gain buffers in

the LTC2358-18 greatly reduces the input drive require-

ments and makes it possible to include optional RC filters

with kΩ impedance and arbitrarily slow time constants

for anti-aliasing or other purposes. Micropower op amps

with limited drive capability are also well suited to drive

the high impedance analog inputs directly.

The LTC2358-18 features proprietary circuitry to achieve

exceptional internal crosstalk isolation between channels

(109dB typical). The PC board wiring to the analog inputs

should be short and shielded to prevent external capacitive

crosstalk between channels. The capacitance between adja-

cent package pins is 0.16pF. Low source resistance and/or

high source capacitance help reduce external capacitively

coupled crosstalk. Single ended input drive also enjoys

additional external crosstalk isolation because every other

input pin is grounded, or at a low impedance DC source,

and serves as a shield between channels.

INPUT OVERDRIVE TOLERANCE

Driving an analog input above VCC on any channel up to

10mA will not affect conversion results on other channels.

Approximately 70% of this overdrive current will flow out

of the VCC pin and the remaining 30% will flow out of VEE.

This current flowing out of VEE will produce heat across

the VCC – VEE voltage drop and must be taken into account

for the total Absolute Maximum power dissipation of

500mW. Driving an analog input below VEE may corrupt

conversion results on other channels. This product can

handle input currents of up to 100mA below VEE or above

VCC without latch-up.

Keep in mind that driving the inputs above VCC or below

VEE may reverse the normal current flow from the external

power supplies driving these pins.

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

APPLICATIONS INFORMATION

each pin remains between (VCC – 4V) and (VEE+4V). This

feature of the LTC2358-18 enables it to accept a wide

variety of signal swings, simplifying signal chain design.

The two-tone test shown in Figure 6b demonstrates the

arbitrary input drive capability of the LTC2358-18. This test

simultaneously drives IN+ with a −7dBFS 2kHz single-ended

sine wave and IN− with a −7dBFS 3.1kHz single-ended sine

wave. Together, these signals sweep the analog inputs

across a wide range of common mode and differential

mode voltage combinations, similar to the more general

arbitrary input signal case. They also have a simple spec-

tral representation. An ideal differential converter with no

common-mode sensitivity will digitize this signal as two

−7dBFS spectral tones, one at each sine wave frequency.

The FFT plot in Figure 6b demonstrates the LTC2358-18

response approaches this ideal, with 119dB of SFDR

limited by the converter's second harmonic distortion

response to the 3.1kHz sine wave on IN–.

The ability of the LTC2358-18 to accept arbitrary signal

swings over a wide input common mode range with high

CMRR can simplify application solutions. In practice,

many sensors produce a differential sensor voltage riding

on top of a large common mode signal. Figure 7a depicts

one way of using the LTC2358-18 to digitize signals of

this type. The amplifier stage provides a differential gain

of approximately 10V/V to the desired sensor signal while

the unwanted common mode signal is attenuated by the

ADC CMRR. The circuit employs the ±5V SoftSpan range of

the ADC. Figure7b shows measured CMRR performance

of this solution, which is competitive with the best com-

mercially available instrumentation amplifiers. Figure7c

shows measured AC performance of this solution.

In Figure 8, another application circuit is shown which

uses two channels of the LTC2358-18 to simultaneously

sense the voltage and bidirectional current through a sense

resistor over a wide common mode range.

Input Filtering

The true high impedance analog inputs can accommodate

a very wide range of passive or active signal conditioning

filters. The buffered ADC inputs have an analog bandwidth

of 6MHz, and impose no particular bandwidth requirement

on external filters. The external input filters can therefore be

optimized independent of the ADC to reduce signal chain

noise and interference. A common filter configuration is

the simple anti-aliasing and noise reducing RC filter with its

pole at half the sampling frequency. For example, 100kHz

with R=2.43kΩ and C=680pF as shown in Figure 5.

–15V

15V

LTC2358-18

235818 F05

ONLY CHANNEL 0 SHOWN FOR CLARITY

TRUE BIPOLAR

+10V

–10V

+10V

–10V

UNIPOLAR

0.1µF

47µF

IN0+

IN0–

VCC

REFINREFBUFVEE

OPTIONAL

LOWPASS FILTER

680pF

R = 2.43k

IN+

IN–

Figure5. Filtering Single-Ended Input Signals

High quality capacitors and resistors should be used in

the RC filters since these components can add distortion.

NPO/COG and silver mica type dielectric capacitors have

excellent linearity. Carbon surface mount resistors can

generate distortion from self-heating and from damage

that may occur during soldering. Metal film surface mount

resistors are much less susceptible to both problems.

Arbitrary and Fully Differential Analog Input Signals

The wide common mode input range and high CMRR of

the LTC2358-18 allow each channel’s IN+ and IN– pins to

swing with an arbitrary relationship to each other, provided

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

APPLICATIONS INFORMATION

±10.24V RANGE

SFDR = 119dB

SNR = 96.4dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

Arbitrary Drive

235818 F06b

6.2kHz

Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine,

IN–=–7dBFS 3.1kHz Sine, 32k Point FFT, fSMPL = 200ksps.

CircuitShown in Figure 6a

±10.24V RANGE

SNR = 96.4dB

THD = –114dB

SINAD = 96.3dB

SFDR = 118dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

Fully Differential Drive

235818 F06c

Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine,

VCM=0V, 32k Point FFT, fSMPL = 200ksps. Circuit Shown in

Figure 6a

–15V

15V

LTC2358-18

235818 F06a

ONLY CHANNEL 0 SHOWN FOR CLARITY

FULLY

DIFFERENTIAL

+10V

–10V

TRUE BIPOLAR

+10V

–10V

ARBITRARY

+10V

–10V

UNIPOLAR

0.1µF

47µF

+5V

–5V IN0+

IN0–

VCC

REFINREFBUFVEE

IN+

IN–

Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals

±10.24V RANGE

SNR = 96.3dB

THD = –110dB

SINAD = 96.2dB

SFDR = 113dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

True Bipolar Drive

235818 F06d

Figure 6d. IN+ = –1dBFS 2kHz True Bipolar Sine, IN– = 0V, 32k

Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a

0V to 10.24V RANGE

SNR = 90.9dB

THD = –108dB

SINAD = 90.8dB

SFDR = 109dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 F06e

Unipolar Drive

Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V,

32k Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

–7V

31V

BUFFERED

ANALOG

INPUTS

LTC2358-18

235818 F07a

ONLY CHANNEL 0 SHOWN FOR CLARITY

24V

ARBITRARY

–

0.1µF

47µF

IN0+

IN0–

LTC2057HV

VCC

REFINREFBUFVEE

BW = 10kHz

2.2nF

3.65k

549Ω

IN+

IN–

2.49k

COMMON MODE

INPUT RANGE

DIFFERENTIAL MODE

INPUT RANGE: ±500mV

INTERNAL HI-Z BUFFERS

ALLOW OPTIONAL

kΩ PASSIVE FILTERS

GAIN = 10

Figure 7a. Amplify Differential Signals with Gain of 10

Over a Wide Common Mode Range with Buffered Analog Inputs

APPLICATIONS INFORMATION

±5V RANGE

= IN

–

= 1V

P–P

SINE

FREQUENCY (Hz)

100

10k

100

110

120

130

140

150

160

CMRR (dB)

235818 F07b

Figure 7b. CMRR vs Input Frequency.

Circuit Shown in Figure 7a

SNR = 91.4dB

THD = –108dB

SINAD = 91.3dB

SFDR = 109dB

±5V RANGE

FULLY DIFFERENTIAL DRIVE (IN

–

= –IN

)

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 F07c

Figure 7c. IN+/IN–=450mV 200Hz Fully

Differential Sine, 0V≤VCM≤24V, 32k Point FFT,

fSMPL=200ksps. Circuit Shown in Figure 7a

–15V

15V

LTC2358-18

235818 F08

ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY

0.1µF

47µF

–10.24V ≤ VS1 ≤ 10.24V

–10.24V ≤ VS2 ≤ 10.24V

VS1 – VS2

RSENSE

ISENSE =

IN0+

IN0–

IN1+

IN1–

VCC

REFINREFBUFVEE

ISENSE

RSENSE

VS2

VS1

Figure8. Simultaneously Sense Voltage (CH0) and Current (CH1) Over a Wide Common Mode Range

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

ADC REFERENCE

As shown previously in Table 1b, the LTC2358-18 supports

three reference configurations. The first uses both the in-

ternal bandgap reference and reference buffer. The second

externally overdrives the internal reference but retains the

internal buffer, which isolates the external reference from

ADC conversion transients. This configuration is ideal

for sharing a single precision external reference across

multiple ADCs. The third disables the internal buffer and

overdrives the REFBUF pin externally.

Internal Reference with Internal Buffer

The LTC2358-18 has an on-chip, low noise, low drift

(20ppm/°C maximum), temperature compensated band-

gap reference that is factory trimmed to 2.048V. The

reference output connects through a 20kΩ resistor to

the REFIN pin, which serves as the input to the on-chip

reference buffer, as shown in Figure 9a. When employing

the internal bandgap reference, the REFIN pin should be

bypassed to GND (Pin 20) close to the pin with a 0.1μF

ceramic capacitor to filter wideband noise. The reference

buffer amplifies VREFIN to create the converter master

reference voltage VREFBUF = 2•VREFIN on the REFBUF pin,

nominally 4.096V when using the internal bandgap refer-

ence. Bypass REFBUF to GND (Pin 20) close to the pin with

at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or

X5R, 10V, 0805 size) to compensate the reference buffer,

absorb transient conversion currents, and minimize noise.

External Reference with Internal Buffer

If more accuracy and/or lower drift is desired, REFIN can

be easily overdriven by an external reference since 20kΩ

of resistance separates the internal bandgap reference

output from the REFIN pin, as shown in Figure 9b. The

valid range of external reference voltage overdrive on the

REFIN pin is 1.25V to 2.2V, resulting in converter mas-

ter reference voltages VREFBUF between 2.5V and 4.4V,

respectively. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

many applications. With its small size, low power, and high

accuracy, the LTC6655-2.048 is well suited for use with the

LTC2358-18 when overdriving the internal reference. The

APPLICATIONS INFORMATION

235818 F09a

47µF 6.5k

20k

LTC2358-18

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

0.1µF

REFERENCE

BUFFER

Figure 9a. Internal Reference with Internal

Buffer Configuration

235818 F09b

47µF 6.5k

20k

LTC2358-18

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

2.7µF

LTC6655-2.048

REFERENCE

BUFFER

Figure 9b. External Reference with Internal

Buffer Configuration

235818 F09c

47µF 6.5k

20k

LTC2358-18

REFBUF

REFIN

GND

BANDGAP

REFERENCE

6.5k

LTC6655-5

REFERENCE

BUFFER

Figure 9c. External Reference with Disabled

Internal Buffer Configuration

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

LTC6655-2.048 offers 0.025% (maximum) initial accuracy

and 2ppm/°C (maximum) temperature coefficient for high

precision applications. The LTC6655-2.048 is fully speci-

fied over the H-grade temperature range, complementing

the extended temperature range of the LTC2358-18 up to

125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF

ceramic capacitor close to the REFIN pin is recommended.

External Reference with Disabled Internal Buffer

The internal reference buffer supports VREFBUF = 4.4V

maximum. By grounding REFIN, the internal buffer may

be disabled allowing REFBUF to be overdriven with an

external reference voltage between 2.5V and 5V, as shown

in Figure 9c. Maximum input signal swing and SNR are

achieved by overdriving REFBUF using an external 5V

reference. The buffer feedback resistors load the REFBUF

pin with 13kΩ even when the reference buffer is disabled.

The LTC6655-5 offers the same small size, accuracy, drift,

and extended temperature range as the LTC6655-2.048,

and achieves a typical SNR of 97.9dB when paired with

the LTC2358-18. Bypass the LTC6655-5 to GND (Pin 20)

close to the REFBUF pin with at least a 47μF ceramic ca-

pacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to

absorb transient conversion currents and minimize noise.

The LTC2358-18 converter draws a charge (QCONV) from

the REFBUF pin during each conversion cycle. On short

time scales most of this charge is supplied by the external

REFBUF bypass capacitor, but on longer time scales all of

the charge is supplied by either the reference buffer, or

when the internal reference buffer is disabled, the external

reference. This charge draw corresponds to a DC current

equivalent of IREFBUF = QCONV•f SMPL, which is proportional

to sample rate. In applications where a burst of samples

is taken after idling for long periods of time, as shown in

Figure10, IREFBUF quickly transitions from approximately

0.4mA to 1.5mA (VREFBUF = 5V, fSMPL=200kHz). This

current step triggers a transient response in the external

reference that must be considered, since any deviation in

VREFBUF affects converter accuracy. If an external reference

is used to overdrive REFBUF, the fast settling LTC6655

family of references is recommended.

Internal Reference Buffer Transient Response

For optimum performance in applications employing burst

sampling, the external reference with internal reference

buffer configuration should be used. The internal reference

buffer incorporates a proprietary design that minimizes

movements in VREFBUF when responding to a burst of

conversions following an idle period. Figure 11 compares

the burst conversion response of the LTC2358-18 with an

input near full scale for two reference configurations. The

first configuration employs the internal reference buffer

with REFIN externally overdriven by an LTC6655-2.048,

while the second configuration disables the internal ref-

erence buffer and overdrives REFBUF with an external

LTC6655-4.096. In both cases REFBUF is bypassed to

GND with a 47µF ceramic capacitor.

EXTERNAL REFERENCE ON REFBUF

INTERNAL REFERENCE BUFFER

±10.24V RANGE

= 10V

–

= 0V

TIME (µs)

100

200

300

400

500

–5

DEVIATION FROM FINAL VALUE (LSB)

235818 F11

Figure11. Burst Conversion Response of the LTC2358-18,

fSMPL=200ksps

APPLICATIONS INFORMATION

CNV

IDLE

PERIOD

IDLE

PERIOD

235818 F10

Figure10. CNV Waveform Showing Burst Sampling

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

DYNAMIC PERFORMANCE

Fast Fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion, and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2358-18 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies below half the sampling frequency, exclud-

ing DC. Figure 12 shows that the LTC2358-18 achieves a

typical SINAD of 96.2dB in the ±10.24V range at a 200kHz

sampling rate with a true bipolar 2kHz input signal.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 12 shows

that the LTC2358-18 achieves a typical SNR of 96.4dB in

the ±10.24V range at a 200kHz sampling rate with a true

bipolar 2kHz input signal.

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD =20log V2

2+V3

2+V4

2...V

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through Nth harmonics, respectively. Figure 12 shows

that the LTC2358-18 achieves a typical THD of –111dB

(N=6) in the ±10.24V range at a 200kHz sampling rate

with a true bipolar 2kHz input signal.

±10.24V RANGE

TRUE BIPOLAR DRIVE (IN

–

= 0V)

SNR = 96.4dB

THD = –111dB

SINAD = 96.2dB

SFDR = 113dB

FREQUENCY (kHz)

100

–180

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

235818 F12

Figure12. 32k Point FFT fSMPL = 200ksps, fIN = 2kHz

POWER CONSIDERATIONS

The LTC2358-18 requires four power supplies: the posi-

tive and negative high voltage power supplies (VCC and

VEE), the 5V core power supply (VDD) and the digital input/

output (I/O) interface power supply (OVDD). As long as

the voltage difference limits of 10V ≤ VCC – VEE ≤ 38V

are observed, VCC and VEE may be independently biased

anywhere within their own individual allowed operating

ranges, including the ability for VEE to be tied directly to

ground. This feature enables the common mode input

range of the LTC2358-18 to be tailored to the specific

application’s requirements. The flexible OVDD supply al-

lows the LTC2358-18 to communicate with CMOS logic

operating between 1.8V and 5V, including 2.5V and 3.3V

systems. When using LVDS I/O mode, the range of OVDD

is 2.375V to 5.25V.

Power Supply Sequencing

The LTC2358-18 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2358-18 has

an internal power-on-reset (POR) circuit which resets the

APPLICATIONS INFORMATION

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

When employing the internal reference buffer, allow 200ms

for the buffer to power up and recharge the REFBUF bypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2358-18 sampling and conversion is controlled

by CNV. A rising edge on CNV transitions all channels’ S/H

circuits from track mode to hold mode, simultaneously

sampling the input signals on all channels and initiating

a conversion. Once a conversion has been started, it

cannot be terminated early except by resetting the ADC,

as discussed in the Reset Timing section. For optimum

performance, drive CNV with a clean, low jitter signal and

avoid transitions on data I/O lines leading up to the rising

edge of CNV. Additionally, to minimize channel-to-channel

crosstalk, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

until the conversion is complete. Once CNV is brought high

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimize external disturbances during the internal conver-

sion process. The CNV timing required to take advantage

of the reduced power nap mode of operation is described

in the Nap Mode section.

Internal Conversion Clock

The LTC2358-18 has an internal clock that is trimmed to

achieve a maximum conversion time of 550•N ns with N

channels enabled. With a minimum acquisition time of

570ns when converting eight channels simultaneously,

throughput performance of 200ksps is guaranteed without

any external adjustments. Also note that the minimum

acquisition time varies with sampling frequency (fSMPL)

and the number of enabled channels.

Nap Mode

The LTC2358-18 can be placed into nap mode after a con-

version has been completed to reduce power consumption

between conversions. In this mode a portion of the device

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

by keeping CNV high between conversions, as shown in

Figure 13. To initiate a new conversion after entering nap

mode, bring CNV low and hold for at least 750ns before

bringing it high again. The converter acquisition time (tACQ)

is set by the CNV low time (tCNVL) when using nap mode.

Power Down Mode

When PD is brought high, the LTC2358-18 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

APPLICATIONS INFORMATION

CNV

tCONV

tACQ

BUSY

NAP NAP MODE

tCNVL

235818 F13

Figure13. Nap Mode Timing for the LTC2358-18

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

draws only a small regulator standby current resulting in a

typical power dissipation of 0.68mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Reset Timing

A global reset of the LTC2358-18, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 14. The reset event is trig-

gered on the second rising edge of PD, and asynchronously

ends based on an internal timer. Reset clears all serial data

output registers and restores the internal SoftSpan configu-

ration register default state of all channels in SoftSpan7.

If reset is triggered during a conversion, the conversion

is immediately halted. The normal power down behavior

associated with PD going high is not affected by reset. Once

PD is brought low, wait at least 10ms before initiating a

conversion. When employing the internal reference buffer,

allow 200ms for the buffer to power up and recharge the

REFBUF bypass capacitor. Any conversion initiated before

these times will produce invalid results.

Power Dissipation vs Sampling Frequency

When nap mode is employed, the power dissipation of

the LTC2358-18 decreases as the sampling frequency is

APPLICATIONS INFORMATION

reduced, as shown in Figure 15. This decrease in aver-

age power dissipation occurs because a portion of the

LTC2358-18 circuitry is turned off during nap mode, and

the fraction of the conversion cycle (tCYC) spent napping

increases as the sampling frequency (fSMPL) is decreased.

OVDD

VDD

VEE

VCC

WITH NAP MODE

CNVL

= 1µs

SAMPLING FREQUENCY (kHz)

120

160

200

–6

–4

–2

SUPPLY CURRENT (mA)

235818 F15

Figure15. Power Dissipation of the LTC2358-18

Decreases with Decreasing Sampling Frequency

DIGITAL INTERFACE

The LTC2358-18 features CMOS and LVDS serial interfaces,

selectable using the LVDS/CMOS pin. The flexible OVDD

supply allows the LTC2358-18 to communicate with any

CMOS logic operating between 1.8V and 5V, including

2.5V and 3.3V systems, while the LVDS interface supports

low noise digital designs. In CMOS mode, applications

may employ between one and eight lanes of serial data

output, allowing the user to optimize bus width and data

throughput. Together, these I/O interface options enable

the LTC2358-18 to communicate equally well with legacy

microcontrollers and modern FPGAs.

CNV

tCONV

tCNVH

tPDH

tPDL

BUSY

RESET RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

PD tWAKE

235818 F14

Figure14. Reset Timing for the LTC2358-18

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

APPLICATIONS INFORMATION

Serial CMOS I/O Mode

As shown in Figure 16, in CMOS I/O mode the serial data

bus consists of a serial clock input, SCKI, serial data

input, SDI, serial clock output, SCKO, and eight lanes of

serial data output, SDO0 to SDO7. Communication with

the LTC2358-18 across this bus occurs during predefined

data transaction windows. Within a window, the device

accepts 24-bit SoftSpan configuration words for the next

conversion on SDI and outputs 24-bit packets containing

conversion results and channel configuration information

from the previous conversion on SDO0 to SDO7. New

data transaction windows open 10ms after powering up

or resetting the LTC2358-18, and at the end of each con-

version on the falling edge of BUSY. In the recommended

use case, the data transaction should be completed with

a minimum tQUIET time of 20ns prior to the start of the

next conversion, as shown in Figure 16. New SoftSpan

configuration words are only accepted within this recom-

mended data transaction window, but SoftSpan changes

take effect immediately with no additional analog input

settling time required before starting the next conversion.

It is still possible to read conversion data after starting the

next conversion, but this will degrade conversion accuracy

and therefore is not recommended.

Just prior to the falling edge of BUSY and the opening of

a new data transaction window, SCKO is forced low and

SDO0 to SDO7 are updated with the latest conversion

results from analog input channels 0 to 7, respectively.

Rising edges on SCKI serially clock conversion results

and analog input channel configuration information out

on SDO0 to SDO7 and trigger transitions on SCKO that are

skew-matched to the data on SDO0 to SDO7. The resulting

SCKO frequency is half that of SCKI. SCKI rising edges

also latch SoftSpan configuration words provided on SDI,

C2 C1 C0

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17

CNV

CS = PD = 0

DON’T CARE

tACQ

BUSY

SDO7

SCKO

SDO0

SCKI

SDI

DON’T CARE

SAMPLE N

RECOMMENDED DATA TRANSACTION WINDOW

SAMPLE N + 1

SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1

CHANNEL 0

24-BIT PACKET

CONVERSION N

CHANNEL 1

24-BIT PACKET

CONVERSION N

CHANNEL 7

24-BIT PACKET

CONVERSION N

CHANNEL 0

24-BIT PACKET

CONVERSION N

235818 TD01

CONVERSION RESULT CHANNEL ID SOFTSPAN CONVERSION RESULT

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17DON’T CARE

CONVERSION RESULT CHANNEL ID SOFTSPAN CONVERSION RESULT

• • •

tSCKI

235818 F16

tSCKIH

tBUSYLH

tSCKIL

tHSDOSCKI

tDSDOSCKI

tSSDISCKI

tQUIET

tHSDISCKI

tDSDOBUSYL

tCNVH

tSKEW

tCONV

tCNVL

tCYC

Figure16. Serial CMOS I/O Mode

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

which are used to program the internal 24-bit SoftSpan

configuration register. See the section Programming the

SoftSpan Configuration Register in CMOS I/O Mode for

further details. SCKI is allowed to idle either high or low

in CMOS I/O mode. As shown in Figure 17, the CMOS

bus is enabled when CS is low and is disabled and Hi-Z

when CS is high, allowing the bus to be shared across

multiple devices.

The data on SDO0 to SDO7 are grouped into 24-bit

packets consisting of an 18-bit conversion result, 3-bit

analog channel ID, and 3-bit SoftSpan code, all presented

MSB first. As suggested in Figures 16 and 17, each SDO

lane outputs these packets for all analog input channels

in a sequential, circular manner. For example, the first

24-bit packet output on SDO0 corresponds to analog

input channel 0, followed by the packets for channels 1

through 7. The data output on SDO0 then wraps back

to channel 0, and this pattern repeats indefinitely. Other

SDO lanes follow a similar circular pattern, except the

first packet presented on each lane corresponds to its

associated analog input channel.

When interfacing the LTC2358-18 with a standard SPI

bus, capture output data at the receiver on rising edges of

SCKI. SCKO is not used in this case. Multiple SDO lanes

are also usually not useful in this case. In other applica-

tions, such as interfacing the LTC2358-18 with an FPGA

or CPLD, rising and falling edges of SCKO may be used

to capture serial output data on SDO0 to SDO7 in double

data rate (DDR) fashion. Capturing data using SCKO adds

robustness to delay variations over temperature and supply.

Full Eight Lane Serial CMOS Output Data Capture

As shown in Table 2, full 200ksps per channel throughput

can be achieved with a 45MHz SCKI frequency by capturing

the first packet (24 SCKI cycles total) from all eight serial

data output lanes SDO0 to SDO7. This configuration also

allows conversion results from all channels to be captured

using as few as 18 SCKI cycles if the 3-bit analog channel

ID and 3-bit SoftSpan code are not needed and the device

SoftSpan configuration is not being changed. Multi-lane

data capture is usually best suited for use with FPGA

or CPLD capture hardware, but may be useful in other

application-specific cases.

APPLICATIONS INFORMATION

PD = 0

DON’T CARE

BUSY

SDO7

SCKO

SDO0

SCKI

SDI

DON’T CARE

235818 F17

Hi-Z

Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET CHANNEL 3 PACKET

(PARTIAL)

Hi-Z

CHANNEL 7 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET

(PARTIAL)

• • •

NEW SoftSpan CONFIGURATION WORD

(OVERWRITES INTERNAL CONFIG REGISTER)

TWO ALL-ZERO WORDS AND ONE PARTIAL WORD

(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

tEN tDIS

Figure17. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

Fewer Than Eight Lane Serial CMOS Output Data Capture

Applications that cannot accommodate the full eight lanes

of serial data capture may employ fewer lanes without

reconfiguring the LTC2358-18. For example, capturing

the first two packets (48 SCKI cycles total) from SDO0,

SDO2, SDO4, and SDO6 provides data for analog input

channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec-

tively, using four output lanes. Similarly, capturing the first

four packets (96 SCKI cycles total) from SDO0 and SDO4

provides data for analog input channels 0 to 3 and 4 to

7, respectively, using two output lanes. If only one lane

can be accommodated, capturing the first eight packets

(192 SCKI cycles total) from SDO0 provides data for all

analog input channels. As shown in Table 2, full 200ksps

per channel throughput can be achieved with a 90MHz

SCKI frequency in the four lane case, but the maximum

CMOS SCKI frequency of 100MHz limits the throughput

to less than 200ksps per channel in the two lane and one

lane cases. Finally, note that in choosing the number of

lanes and which lanes to use for data capture, the user is

not restricted to the specific cases mentioned above. Other

choices may be more optimal in particular applications.

Programming the SoftSpan Configuration Register in

CMOS I/O Mode

The internal 24-bit SoftSpan configuration register con-

trols the SoftSpan range for all analog input channels of

the LTC2358-18. The default state of this register after

power-up or resetting the device is all ones, configuring

each channel to convert in SoftSpan 7, the ±2.5 • VREFBUF

range (see Table 1a). The state of this register may be

modified by providing a new 24-bit SoftSpan configuration

word on SDI during the data transaction window shown

in Figure 16. New SoftSpan configuration words are only

accepted within this recommended data transaction win-

dow, but SoftSpan changes take effect immediately with

no additional analog input settling time required before

starting the next conversion. Setting a channel’s SoftSpan

code to SS[2:0] = 000 immediately disables the channel,

resulting in a corresponding reduction in tCONV on the next

conversion. Similarly, enabling a previously disabled chan-

nel requires no additional analog input settling time before

starting the next conversion. The mapping between the

serial SoftSpan configuration word, the internal SoftSpan

configuration register, and each channel’s 3-bit SoftSpan

code is illustrated in Figure 18.

APPLICATIONS INFORMATION

Table2. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels Enabled.

Shaded Entries Denote Throughputs That Are Not Achievable in a Given Configuration. Calculated Using fSCKI = (Number of SCKI

Cycles)/(tACQ(MIN)–tQUIET)

I/O MODE NUMBER OF SDO

LANES

NUMBER OF SCKI

CYCLES

REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF

200ksps/CHANNEL

(tACQ=570ns)

100ksps/CHANNEL

(tACQ=5570ns)

50ksps/CHANNEL

(tACQ=15570ns)

CMOS

8 18 35 4 2

8 24 45 5 2

4 48 90 9 4

2 96 Not Achievable 18 7

1 192 Not Achievable 35 13

LVDS 1 96 180 (360Mbps) 18 (36Mbps) 7 (14Mbps)

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

If fewer than 24 SCKI rising edges are provided during a data

transaction window, the partial word received on SDI will be

ignored and the SoftSpan configuration register will not be

updated. If exactly 24 SCKI rising edges are provided, the

SoftSpan configuration register will be updated to match

the received SoftSpan configuration word, S[23:0]. The

one exception to this behavior occurs when S[23:0] is all

zeros. In this case, the SoftSpan configuration register

will not be updated, allowing applications to retain the

current SoftSpan configuration state by idling SDI low. If

more than 24 SCKI rising edges are provided during a data

transaction window, each complete 24-bit word received

on SDI will be interpreted as a new SoftSpan configuration

word and applied to the SoftSpan configuration register

as described above. Any partial words are ignored.

Typically, applications will update the SoftSpan configura-

tion register in the manner shown in Figures 16 and 17.

After the opening of a new data transaction window at the

falling edge of BUSY, the user supplies a 24-bit SoftSpan

configuration word on SDI during the first 24 SCKI cycles.

This new word overwrites the internal configuration register

contents following the 24th SCKI rising edge. The user then

holds SDI low for the remainder of the data transaction

window causing the register to retain its contents regardless

of the number of additional SCKI cycles applied. SoftSpan

settings may be retained across multiple conversions by

holding SDI low for the entire data transaction window,

regardless of the number of SCKI cycles applied.

Serial LVDS I/O Mode

In LVDS I/O mode, information is transmitted using posi-

tive and negative signal pairs (LVDS+/LVDS−) with bits

differentially encoded as (LVDS+ − LVDS−). These signals

are typically routed using differential transmission lines

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0DON’T CARE

SCKI

SDI

SoftSpan CONFIGURATION WORD

CMOS I/O MODE

SoftSpan CONFIGURATION WORD

INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER

(SAME FOR CMOS AND LVDS)

LVDS I/O MODE

1234567891011121314151617181920212223 0

tSCKI

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0DON’T CARE

SCKI

(LVDS)

SDI

(LVDS)

tSCKI

CHANNEL 7 SoftSpan

CODE SS[2:0]

CHANNEL 6 SoftSpan

CODE SS[2:0]

CHANNEL 5 SoftSpan

CODE SS[2:0]

CHANNEL 4 SoftSpan

CODE SS[2:0]

CHANNEL 3 SoftSpan

CODE SS[2:0]

CHANNEL 2 SoftSpan

CODE SS[2:0]

CHANNEL 1 SoftSpan

CODE SS[2:0]

CHANNEL 0 SoftSpan

CODE SS[2:0]

235818 F18

tSCKIH

tSCKIL

tSSDISCKI

tHSDISCKI

tSCKIH

tSCKIL tHSDISCKI

tHSDISCKI

tSSDISCKI

Figure18. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan

Configuration Register, and SoftSpan Code for Each Analog Input Channel

APPLICATIONS INFORMATION

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

with 100Ω characteristic impedance. Logical 1’s and 0’s

are nominally represented by differential +350mV and

−350mV, respectively. For clarity, all LVDS timing diagrams

and interface discussions adopt the logical rather than

physical convention.

As shown in Figure 19, in LVDS I/O mode the serial data

bus consists of a serial clock differential input, SCKI, serial

data differential input, SDI, serial clock differential output,

SCKO, and serial data differential output, SDO. Communi-

cation with the LTC2358-18 across this bus occurs during

predefined data transaction windows. Within a window,

the device accepts 24-bit SoftSpan configuration words

for the next conversion on SDI and outputs 24-bit packets

containing conversion results and channel configuration

information from the previous conversion on SDO. New

data transaction windows open 10ms after powering up

or resetting the LTC2358-18, and at the end of each con-

version on the falling edge of BUSY. In the recommended

use case, the data transaction should be completed with

a minimum tQUIET time of 20ns prior to the start of the

next conversion, as shown in Figure 19. New SoftSpan

configuration words are only accepted within this recom-

mended data transaction window, but SoftSpan changes

take effect immediately with no additional analog input

settling time required before starting the next conversion.

It is still possible to read conversion data after starting the

next conversion, but this will degrade conversion accuracy

and therefore is not recommended.

Just prior to the falling edge of BUSY and the opening of

a new data transaction window, SDO is updated with the

latest conversion results from analog input channel 0. Both

rising and falling edges on SCKI serially clock conversion

results and analog input channel configuration information

out on SDO. SCKI is also echoed on SCKO, skew-matched

to the data on SDO. Whenever possible, it is recommended

that rising and falling edges of SCKO be used to capture

DDR serial output data on SDO, as this will yield the best

robustness to delay variations over supply and tempera-

ture. SCKI rising and falling edges also latch SoftSpan

configuration words provided on SDI, which are used to

S23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624

S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S3S4 S1S2 S0

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17 D16 D15

CNV

(CMOS)

CS = PD = 0

235818 F19

DON’T CARE

tACQ

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

SAMPLE N

tCNVL

tCYC

RECOMMENDED DATA TRANSACTION WINDOW

SAMPLE N + 1

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

CHANNEL 0

24-BIT PACKET

CONVERSION N

CHANNEL 1

24-BIT PACKET

CONVERSION N

CHANNEL 7

24-BIT PACKET

CONVERSION N

CONVERSION RESULT CHANNEL ID SoftSpan

186185 187 188 189 190 191 192

D0 SS1SS2 SS0 D17

CHANNEL 0

24-BIT PACKET

CONVERSION N

CONVERSION

RESULT

CHANNEL ID SoftSpan

tSKEW

tCNVH

tSCKIH

tSCKIL

tBUSYLH

tDSDOSCKI

tHSDOSCKI

tDSDOBUSYL

tSSDISCKI tSSDISCKI

tHSDISCKI tHSDISCKI

tQUIET

tSCKI

tCONV

C2 C1 C0C2 C1 C0

Figure19. Serial LVDS I/O Mode

APPLICATIONS INFORMATION

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

(CMOS)

PD = 0

DON’T CARE

BUSY

(CMOS)

SCKO

(LVDS)

SDO

(LVDS)

SCKI

(LVDS)

SDI

(LVDS)

DON’T CARE

235818 F20

Hi-Z

Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET CHANNEL 3 PACKET

(PARTIAL)

Hi-Z

NEW SoftSpan CONFIGURATION WORD

(OVERWRITES INTERNAL CONFIG REGISTER)

TWO ALL-ZERO WORDS AND ONE PARTIAL WORD

(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

tEN tDIS

Figure20. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS

program the internal 24-bit SoftSpan configuration register.

See the section Programming the SoftSpan Configuration

Figure 20, the LVDS bus is enabled when CS is low and is

disabled and Hi-Z when CS is high, allowing the bus to be

shared across multiple devices. Due to the high speeds

involved in LVDS signaling, LVDS bus sharing must be

carefully considered. Transmission line limitations imposed

by the shared bus may limit the maximum achievable bus

clock speed. LVDS inputs are internally terminated with a

100Ω differential resistor when CS is low, while outputs

must be differentially terminated with a 100Ω resistor at

the receiver (FPGA). SCKI must idle in the low state in

LVDS I/O mode, including when transitioning CS.

The data on SDO are grouped into 24-bit packets consist-

ing of an 18-bit conversion result, 3-bit analog channel

ID, and 3-bit SoftSpan code, all presented MSB first.

As suggested in Figures 19 and 20, SDO outputs these

packets for all analog input channels in a sequential, cir-

cular manner. For example, the first 24-bit packet output

on SDO corresponds to analog input channel 0, followed

by the packets for channels 1 through 7. The data output

on SDO then wraps back to channel 0, and this pattern

repeats indefinitely.

Serial LVDS Output Data Capture

As shown in Table 2, full 200ksps per channel throughput

can be achieved with a 180MHz SCKI frequency by captur-

ing eight packets (96 SCKI cycles total) of DDR data from

SDO. The LTC2358-18 supports LVDS SCKI frequencies

up to 250MHz.

Programming the SoftSpan Configuration Register in

LVDS I/O Mode

The internal 24-bit SoftSpan configuration register con-

trols the SoftSpan range for all analog input channels of

the LTC2358-18. The default state of this register after

power-up or resetting the device is all ones, configuring

each channel to convert in SoftSpan 7, the ±2.5 • VREFBUF

range (see Table 1a). The state of this register may be

modified by providing a new 24-bit SoftSpan configuration

word on SDI during the data transaction window shown

in Figure 19. New SoftSpan configuration words are only

accepted within this recommended data transaction win-

dow, but SoftSpan changes take effect immediately with

no additional analog input settling time required before

starting the next conversion. Setting a channel’s SoftSpan

code to SS[2:0] = 000 immediately disables the channel,

resulting in a corresponding reduction in tCONV on the next

APPLICATIONS INFORMATION

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

To obtain the best performance from the LTC2358-18, a

four-layer printed circuit board (PCB) is recommended.

Layout for the PCB should ensure the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital clocks or

signals alongside analog signals or underneath the ADC.

Also minimize the length of the REFBUF to GND (Pin 20)

bypass capacitor return loop, and avoid routing CNV near

signals which could potentially disturb its rising edge.

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common re-

turns for these bypass capacitors are essential to the low

noise operation of the ADC. A single solid ground plane

is recommended for this purpose. When possible, screen

the analog input traces using ground.

Reference Design

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2365, the evaluation kit for the LTC2358-18.

BOARD LAYOUT

conversion. Similarly, enabling a previously disabled chan-

nel requires no additional analog input settling time before

starting the next conversion. The mapping between the

serial SoftSpan configuration word, the internal SoftSpan

configuration register, and each channel’s 3-bit SoftSpan

code is illustrated in Figure 18.

If fewer than 24 SCKI edges (rising plus falling) are

provided during a data transaction window, the partial

word received on SDI will be ignored and the SoftSpan

configuration register will not be updated. If exactly 24

SCKI edges are provided, the SoftSpan configuration

configuration word, S[23:0]. The one exception to this

behavior occurs when S[23:0] is all zeros. In this case,

the SoftSpan configuration register will not be updated,

allowing applications to retain the current SoftSpan con-

figuration state by idling SDI low. If more than 24 SCKI

edges are provided during a data transaction window, each

complete 24-bit word received on SDI will be interpreted

as a new SoftSpan configuration word and applied to the

SoftSpan configuration register as described above. Any

partial words are ignored.

Typically, applications will update the SoftSpan configura-

tion register in the manner shown in Figures 19 and 20.

After the opening of a new data transaction window at

the falling edge of BUSY, the user supplies a 24-bit DDR

SoftSpan configuration word on SDI during the first 12

SCKI cycles. This new word overwrites the internal con-

figuration register contents following the 12th SCKI falling

edge. The user then holds SDI low for the remainder of

the data transaction window causing the register to retain

its contents regardless of the number of additional SCKI

cycles applied. SoftSpan settings may be retained across

multiple conversions by holding SDI low for the entire

data transaction window, regardless of the number of

SCKI cycles applied.

APPLICATIONS INFORMATION

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2358-18#packaging for the most recent package drawings.

LX48 LQFP 0113 REV A

0° – 7°

11° – 13°

0.45 – 0.75

1.00 REF

11° – 13°

9.00 BSC

A A

7.00 BSC

9.00 BSC

1.60

MAX

1.35 – 1.45

0.05 – 0.150.09 – 0.20 0.50

BSC 0.17 – 0.27

GAUGE PLANE

0.25

NOTE:

1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE

2. DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

5. DRAWING IS NOT TO SCALE

SEE NOTE: 4

C0.30 – 0.50

R0.08 – 0.20

7.15 – 7.25

5.50 REF

7.15 – 7.25

PACKAGE OUTLINE

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

SECTION A – A

0.50 BSC

0.20 – 0.30

1.30 MIN

LX Package

48-Lead Plastic LQFP (7mm × 7mm)

(Reference LTC DWG # 05-08-1760 Rev A)

LTCXXXX

LX-ES

Q_ _ _ _ _ _

XXYY

TRAY PIN 1

BEVEL PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

LTC2358-18

235818f

For more information www.linear.com/LTC2358-18

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC2358-16 16-Bit, 200ksps/Ch, Buffered 8-Channel

Simultaneous Sampling, ±1LSB INL, Serial ADC

±10.24V Buffered SoftSpan Inputs with 30VP-P Common Mode Range,

94.2dB SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package

LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous

Sampling, ±3LSB/±1LSB INL, Serial ADC

±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB

SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package

LTC2335-18/LTC2335-16 18-/16-Bit, 1Msps/Ch, 8-Channel Multiplexed,

±3LSB/±1LSB INL, Serial ADC

±10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB

SNR, Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package

LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous

Sampling, ±5LSB/±1.25LSB INL, Serial ADC

±4.096V SoftSpan Inputs with Wide Common Mode Range, 92dB/91dB

SNR, Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package

LTC2378-20/LTC2377-20/

LTC2376-20

20-Bit, 1Msps/500ksps/250ksps,

±0.5ppm INL Serial, Low Power ADC

2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and

4mm × 3mm DFN-16 Packages

LTC2338-18/LTC2337-18/

LTC2336-18

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package

LTC2328-18/LTC2327-18/

LTC2326-18

18-Bit, 1Msps/500ksps/250ksps, Serial,

Low Power ADC

5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,

MSOP-16 Package

LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC 5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,

DGC, 5mm × 5mm QFN-32 Package

LTC2379-18/LTC2378-18/

LTC2377-18/LTC2376-18

18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16/

LTC2377-16/LTC2376-16

16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial,

Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps, Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or

Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages

LTC2387-18/LTC2387-16 18-/16-Bit, 15Msps SAR ADC 5V Supply, Differential Input, 93.8dB SNR, 5mm × 5mm QFN Package

LTC1859/LTC1858/

LTC1857

16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,

SSOP-28 Package

DACs

LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges,

SSOP-28/7mm × 7mm LQFP-48 Package

LTC2668 16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package

References

LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

LT6657 Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LTC2057/LTC2057HV High Voltage, Low Noise Zero-Drift Op Amp Maximum Input Offset: 4.5µV, Supply Voltage Range: 4.75V to 60V

LT6020 Dual , Micropower, 5V/µs, Rail-to-Rail Op Amp Maximum Input Offset: 30µV, Maximum Supply Current: 100µA/Amplifier

LT1354/LT1355/LT1356 Single/Dual/Quad 1mA, 12MHz, 400V/µs Op Amp Good DC Precision, Stable with All Capacitive Loads

Amplify Differential Signals with Gain of 10

Over a Wide Common Mode Range with Buffered Analog Inputs

–7V

31V

BUFFERED

ANALOG

INPUTS

LTC2358-18

235818 TA02

ONLY CHANNEL 0 SHOWN FOR CLARITY

24V

ARBITRARY

–

0.1µF

47µF

IN0+

IN0–

LTC2057HV

VCC

REFINREFBUFVEE

BW = 10kHz

2.2nF

3.65k

549Ω

IN+

IN–

2.49k

COMMON MODE

INPUT RANGE

DIFFERENTIAL MODE

INPUT RANGE: ±500mV

INTERNAL HI-Z BUFFERS

ALLOW OPTIONAL

kΩ PASSIVE FILTERS

GAIN = 10

 LINEAR TECHNOLOGY CORPORATION 2017

LT 0317 • PRINTED IN USA