1
Standard Products
UT54ACS169/UT54ACTS169
4-Bit Up-Down Binary Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Fully synchronous operation for counting and programming
Internal look-ahead for fast counting
Carry output for n-bit cascading
Fully independent clock circuit
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS169 - SMD 5962-96560
UT54ACTS169 - SMD 5962-96561
DESCRIPTION
The UT54ACS169 and the UT54ACTS169 are synchronous 4-
bit binary counters that feature an internal carry look-ahead for
cascading in high-speed counting appli cations. Synchronous
operation is provided by having all flip-flop s clo cked simulta-
neously so that the outputs change coincident with each other
when instructed by the count-enable inputs and internal gating.
Synchronous op eration helps eliminate the output counting
spikes that are normally associated with asynchronous (ripple
clock) counters. The clock input triggers the four flip-flops on
the rising (positive-g oing) edge of the clock.
The counters are fully programmable (i.e., the outputs may each
be preset high or low). The load input circuitry allows loading
with the carry-enable output of cascaded counters. Loading is
synchronous; applying a low level at the load input disables the
counter and causes the outputs to agree with the data inputs after
the next clock pulse.
The carry look-ahead circuitry provides for cascaded counters
for n-bit synchronous application without additional gating. In-
strumental in accomplishing this function are two count-enable
inputs and a carry output. Assert both count enable inputs (ENP
and ENT) to count. The direction of the count is determined by
the level of the U/D input. When U/D is high, the counter counts
up; when low, it counts down. Input ENT is fed forward to
enable the carry output. The ripple carry output
RCO enables a low-level pulse while the count is zero (all inputs
low) counting down or maximum (15 ) coun ting up. The low-
level overflow carry pulse can be used to enable successive cas-
caded stages.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpa ck
Top View
Transitions at ENP or ENT are allowed regardless of the level
of the clock input.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, LOAD, U/D) that modify the op-
erating mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
1
2
3
4
5
7
6
16
15
14
13
12
10
11
U/D
CLK
A
B
C
D
ENP
VDD
RCO
QA
QB
QC
ENT
8 9VSS LOAD
QD
1
2
3
4
5
7
6
16
15
14
13
12
10
11
VDD
89
U/D
CLK
A
B
C
D
ENP
RCO
QA
QB
QC
QD
ENT
VSS LOAD
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LOGIC SYMBOL FUNCTION TABLE
(9)
LOAD
(1)
U/D M3 (UP)
M1 (LOAD)
CTRDIV 16
(10)
ENT G5
(7)
ENP G6
(2)
CLK
(3)
A(4)
B(5)
C(6)
D
(15) RCO
(14) QA
(11) QD
M4 (DOWN)
2,3,5,6+/C7
(12) QC
(13) QB
1,7D (1)
(2)
(4)
(8)
3,5CT = 15
M2 (COUNT)
2,3,5,6-
4,5CT = 0
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
OUTPUT LOAD ENP ENT U/D CLK
Count Up H L L H ↑
Count Down H L L L ↑
Load Preset L X X X ↑
Inhibit H
HH
XX
HX
XX
X
3
LOGIC DIAGRAM
C
C
C
C
D
D
D
D
(14)
(13)
(12)
(11)
Q0
Q1
Q2
Q3
(15) RCO
D
C
B
A
(10)
(7)
(9)
(1)
(3)
(4)
(5)
(6)
ENT
LOAD
U/D
ENP
CLK
Q
Q
Q
Q
Q
Q
Q
Q
(2)
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OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITION S
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -5 5 °C < TC < +125°C); Unless otherw ise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input vo ltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD-0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 2.3 mW/
MHz
IDDQ Quiescent Supply Cur rent VDD = 5.5V 10 μA
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
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Notes:
1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH( min ) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above spec ified ran g e, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-3853 5, for current density ≤ 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buf fer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
3. Based on characterization, hold time ( tH1) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPLH CLK to RCO 2 23 ns
tPHL CLK to RCO 4 28 ns
tPLH CLK to any Q 4 24 ns
tPHL CLK to any Q 4 24 ns
tPLH ENT to RCO 1 15 ns
tPHL ENT to RCO 2 16 ns
tPLH U/D to RCO 2 16 ns
tPHL U/D to RCO 2 16 ns
fMAX Maximum clock frequency 71 MHz
tSU1 A, B, C, D setup time before CLK ↑ 9 ns
tSU2 LOAD , ENP, ENT, U/D
Setup time before CLK ↑ 9 ns
tH1 Data hold time after CLK ↑ 2 ns
tH2 All synchronous inputs hold time after CLK ↑ 2 ns
tWMinimum pulse width
CLK high
CLK low
7 ns
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PACKAGING Side-Brazed Packages
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FLATPACK PACKAGES
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UT54ACS169/U T54ACTS169: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96560 = UT54ACS169
96561 = UT54AC TS169
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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