Standard Products UT54ACS169/UT54ACTS169 4-Bit Up-Down Binary Counters Datasheet November 2010 www.aeroflex.com/logic PINOUTS FEATURES Fully synchronous operation for counting and programming Internal look-ahead for fast counting Carry output for n-bit cascading Fully independent clock circuit 1.2 CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack UT54ACS169 - SMD 5962-96560 UT54ACTS169 - SMD 5962-96561 16-Pin DIP Top View 16 VDD 2 15 RCO 3 14 B C 4 5 13 12 QA QB D ENP 6 7 11 10 VSS 8 9 U/D 1 CLK A QC QD ENT LOAD 16-Lead Flatpack Top View DESCRIPTION The UT54ACS169 and the UT54ACTS169 are synchronous 4bit binary counters that feature an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. Synchronous operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. The clock input triggers the four flip-flops on the rising (positive-going) edge of the clock. The counters are fully programmable (i.e., the outputs may each be preset high or low). The load input circuitry allows loading with the carry-enable output of cascaded counters. Loading is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. 1 16 VDD CLK 2 15 RCO A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT VSS 8 9 LOAD Transitions at ENP or ENT are allowed regardless of the level of the clock input. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, U/D) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The carry look-ahead circuitry provides for cascaded counters for n-bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Assert both count enable inputs (ENP and ENT) to count. The direction of the count is determined by the level of the U/D input. When U/D is high, the counter counts up; when low, it counts down. Input ENT is fed forward to enable the carry output. The ripple carry output RCO enables a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. The lowlevel overflow carry pulse can be used to enable successive cascaded stages. U/D The devices are characterized over full military temperature range of -55C to +125C. 1 LOGIC SYMBOL LOAD U/D ENT (9) (1) (10) (7) ENP (2) CLK A (3) (4) B (5) C (6) D FUNCTION TABLE CTRDIV 16 M1 (LOAD) M2 (COUNT) M3 (UP) M4 (DOWN) 3,5CT = 15 G5 4,5CT = 0 G6 (15) RCO 2,3,5,6+/C7 2,3,5,61,7D (1) (2) (4) (8) (14) (13) (12) (11) QA QB QC QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 OUTPUT LOAD ENP ENT U/D CLK Count Up H L L H Count Down H L L L Load Preset L X X X Inhibit H H H X X H X X X X LOGIC DIAGRAM CLK U/D (2) (1) DQ C Q LOAD (9) ENP ENT (14) Q0 (7) DQ (10) C Q A (13) Q 1 (3) DQ (4) C B Q (12) C Q2 (5) DQ C Q (11) D (6) Q3 (15) RCO 3 OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 4 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.3 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD-0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF 5 Notes: 1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 6 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CLK to RCO 2 23 ns tPHL CLK to RCO 4 28 ns tPLH CLK to any Q 4 24 ns tPHL CLK to any Q 4 24 ns tPLH ENT to RCO 1 15 ns tPHL ENT to RCO 2 16 ns tPLH U/D to RCO 2 16 ns tPHL U/D to RCO 2 16 ns fMAX Maximum clock frequency 71 MHz tSU1 A, B, C, D setup time before CLK 9 ns tSU2 LOAD , ENP, ENT, U/D Setup time before CLK 9 ns tH1 Data hold time after CLK 2 ns tH2 All synchronous inputs hold time after CLK 2 ns tW Minimum pulse width CLK high CLK low 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (tH1) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested. 7 PACKAGING Side-Brazed Packages 8 FLATPACK PACKAGES 9 UT54ACS169/UT54ACTS169: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack C = 16-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96560 = UT54ACS169 96561 = UT54ACTS169 Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 10 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. 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