Publication Release Date: April 14, 2005
- I - Revision 2.0
W83782D/W83782G
WINBOND
H/W MONITORING IC
W83782D/W83782G
- II -
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 1
2. FEATURES ................................................................................................................................. 1
3. KEY SPECIFICATIONS.............................................................................................................. 2
4. PIN CONFIGURATION............................................................................................................... 3
5. PIN DESCRIPTION..................................................................................................................... 3
6. FUNCTIONAL DESCRIPTION.................................................................................................... 6
6.1 General Description ........................................................................................................ 6
6.2 Access Interface ............................................................................................................. 6
6.3 Analog Inputs................................................................................................................ 11
6.4 FAN Speed Count and FAN Speed Control ................................................................. 14
6.5 Temperature Measurement Machine............................................................................ 16
7. REGISTERS AND RAM............................................................................................................ 19
7.1 Address Register (Port x5h) ......................................................................................... 19
7.2 Data Register (Port x6h) ............................................................................................... 20
7.3 Configuration Register − Index 40h .............................................................................. 21
7.4 Interrupt Status Register 1 − Index 41h........................................................................ 21
7.5 Interrupt Status Register 2 − Index 42h........................................................................ 22
7.6 SMI# Mask Register 1 − Index 43h............................................................................... 22
7.7 SMI# Mask Register 2 − Index 44h............................................................................... 23
7.8 Reserved Register − Index 45h .................................................................................... 23
7.9 Chassis Clear Register − Index 46h ............................................................................. 23
7.10 VID/Fan Divisor Register − Index 47h .......................................................................... 24
7.11 Serial Bus Address Register − Index 48h..................................................................... 24
7.12 Value RAM − Index 20h- 3Fh or 60h - 7Fh (auto-increment) ....................................... 25
7.13 Voltage ID (VID4) & Device ID − Index 49h.................................................................. 26
7.14 Temperature 2 and Temperature 3 Serial Bus Address Register − Index 4Ah............ 27
7.15 Pin Control Register − Index4Bh .................................................................................. 27
7.16 IRQ#/OVT# Property Select − Index 4Ch..................................................................... 28
7.17 FAN IN/OUT and BEEP/GPO# Control Register − Index 4Dh ..................................... 29
7.18 Register 50h ~ 5Fh Bank Select − Index 4Eh............................................................... 30
7.19 Winbond Vendor ID − Index 4Fh .................................................................................. 30
7.20 Winbond Test Register − Index 50h - 55h (Bank 0) ..................................................... 30
7.21 BEEP Control Register 1 − Index 56h (Bank 0)............................................................ 31
7.22 BEEP Control Register 2 − Index 57h (Bank 0)............................................................ 31
7.23 Chip ID − Index 58h (Bank 0)....................................................................................... 32
7.24 Diode Selection Register − Index 59h (Bank 0)............................................................ 32
7.25 PWMOUT2 Control − Index 5Ah (Bank 0).................................................................... 33
7.26 PWMOUT1 Control − Index 5Bh (Bank 0).................................................................... 33
W83782D/W83782G
Publication Release Date: April 14, 2005
- III - Revision 2.0
7.27 PWMOUT1/2 Clock Select − Index 5Ch (Bank 0)........................................................ 34
7.28 VBAT Monitor Control Register − Index 5Dh (Bank 0)................................................. 34
7.29 PWMOUT3 Control − Index 5Eh (Bank 0).................................................................... 35
7.30 PWMOUT4 Control − Index 5Fh (Bank 0).................................................................... 36
7.31 Temperature Sensor 2 Temperature (High Byte) Register − Index 50h (Bank 1)........ 36
7.32 Temperature Sensor 2 Temperature (Low Byte) Register − Index 51h (Bank 1)......... 37
7.33 Temperature Sensor 2 Configuration Register − Index 52h (Bank 1).......................... 37
7.34 Temperature Sensor 2 Hysteresis (High Byte) Register − Index 53h (Bank 1)............ 38
7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register − Index 54h (Bank 1)............. 38
7.36 Temperature Sensor 2 Over-temperature (High Byte) Register − Index 55h (Bank 1)38
7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register − Index 56h (Bank 1).39
7.38 Temperature Sensor 3 Temperature (High Byte) Register − Index 50h (Bank 2)........ 39
7.39 Temperature Sensor 3 Temperature (Low Byte) Register − Index 51h (Bank 2)......... 40
7.40 Temperature Sensor 3 Configuration Register − Index 52h (Bank 2).......................... 40
7.41 Temperature Sensor 3 Hysteresis (High Byte) Register − Index 53h (Bank 2)............ 41
7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register − Index 54h (Bank 2)............. 41
7.43 Temperature Sensor 3 Over-temperature (High Byte) Register − Index 55h (Bank 2)42
7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register − Index 56h (Bank 2).42
7.45 Interrupt Status Register 3 − Index 50h (Bank4).......................................................... 43
7.46 SMI# Mask Register 3 − Index 51h (Bank 4)................................................................ 43
7.47 BEEP Control Register 3 − Index 53h (Bank 4)............................................................ 44
7.48 Reserved Register − Index 54h-58h............................................................................. 44
7.49 Real Time Hardware Status Register I − Index 59h (Bank 4) ...................................... 44
7.50 Real Time Hardware Status Register II − Index 5Ah (Bank 4)..................................... 45
7.51 Real Time Hardware Status Register III − Index 5Bh (Bank 4).................................... 46
7.52 PWMOUT3/4 Clock Select − Index 5Ch (Bank 4)........................................................ 46
7.53 Value RAM 2 − Index 50h - 5Ah (auto-increment) (Bank 5)......................................... 47
7.54 Winbond Test Register − Index 50h (Bank 6)............................................................... 47
8. ELECTRICAL CHARACTERISTICS......................................................................................... 48
8.1 Absolute Maximum Ratings .......................................................................................... 48
8.2 DC Characteristics........................................................................................................ 48
8.3 AC Characteristics ........................................................................................................ 50
9. HOW TO READ THE TOP MARKING...................................................................................... 53
10. PACKAGE DIMENTIONS ......................................................................................................... 54
11. APPLICATION CIRCUITS ........................................................................................................ 55
W83782D/W83782G
Publication Release Date: April 14, 2005
- 1 - Revision 2.0
1. GENERAL DESCRIPTION
W83782D/G is an evolving version of W83781D/G -- Winbond's most popular hardware status
monitoring IC. The W83782D/G can be used to monitor several critical hardware parameters of the
system, including power supply voltages, fan speeds, and temperatures, which are very important for
a high-end computer system to work stable and properly. W83782D/G provides both ISA and I2CTM
serial bus interface.
An 8-bit analog-to-digital converter (ADC) was built inside W83782D/G. The W83782D/G can
simultaneously monitor 9 analog voltage inputs, 2 fan tachometer inputs, 3 remote temperature, one
case-open detection signal. The remote temperature sensing can be performed by thermistors, or
2N3904 NPN-type transistors, or directly from IntelTM Deschutes CPU thermal diode output. Also the
W83782D/G provides 4 PWM (pulse width modulation) outputs for the fan speed control; beep tone
output for warning; SMI#, OVT#, GPO# signals for system protection events.
Through the application software or BIOS, the users can read all the monitored parameters of system
from time to time. And a pop-up warning can be also activated when the monitored item was out of
the proper/preset range. The application software could be Winbond's Hardware DoctorTM, or IntelTM
LDCM (LanDesk Client Management), or other management application software. Also the users can
set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate
one programmable and maskable interrupts. An optional beep tone could be used as warning signal
when the monitored parameters are out of the preset range.
Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. PentiumTM II) if applicable. This is
to provide the Vcore voltage correction automatically. Also W83782D/G uniquely provides an optional
feature: early stage (before BIOS was loaded) beep warning. This is to detect if the fatal elements
present --- Vcore or +3.3V voltage fail, and the system can not be boomed up. Also there are 3
specific pins to provide selectable address setting for application of multiple devices (up to 8 devices)
wired through I2CTM interface.
2. FEATURES
Monitoring Items
• 3 thermal inputs from remote thermistors or 2N3904 NPN-type transistors or PentiumTM II
(Deschutes) thermal diode output
• 9 voltage inputs
− Typical for Vcore, +3.3V, +12V, -12V, +5V, -5V, +5V Vsb, Vbat, and one reserved
• 3 fan speed monitoring inputs
• Case open detection input
• WATCHDOG comparison of all monitored values
• Programmable hysteresis and setting points (alarm thresholds) for all monitored items
Actions Enabling
• Beep tone warning
• 4 PWM (pulse width modulation) outputs for fan speed control (3 are MUX optional)
− Total up to 3 sets of fan speed monitoring and controlling
• Issue SMI#, OVT#, GPO# signals to activate system protection
• Warning signal pop-up in application software
W83782D/W83782G
- 2 -
General
• ISA and I2CTM serial bus interface
• 5 VID input pins for CUP Vcore identification (for PentiumTM II)
• Initial power fault beep (for +3.3V, Vcore)
• Master reset input to W83782D/G
• Independent power plane of digital Vcc and analog Vcc (inputs to IC)
• 3 pins (IA0, IA1, IA2) to provide selectable address setting for application of multiple devices (up
to 8 devices) wired through I2CTM interface
• IntelTM LDCM (DMI driver 2.0) support
• AcerTM ADM (DMI driver 2.0) support
• Winbond hardware monitoring application software (Hardware DoctorTM ) support, for both
Windows 95/98 and Windows NT 4.0/5.0
• Input clock rate optional for 24, 48, 14.318 MHz
• 5V Vcc operation
Package
• 48-pin LQFP
3. KEY SPECIFICATIONS
• Voltage monitoring accuracy ±1% (Max.)
• Monitoring Temperature Range and Accuracy
− 40°C to +120°C ± 3°C (Max.)
• Supply Voltage 5V
• Operating Supply Current 5 mA typ.
• ADC Resolution 8 Bits
W83782D/W83782G
Publication Release Date: April 14, 2005
- 3 - Revision 2.0
4. PIN CONFIGURATION
VCC
GNDD
SCL
SDA
I
O
W
#
C
L
K
I
N
D
0
/
P
W
M
O
U
T
3
D
1
/
P
W
M
O
U
T
4
D
2
D
3
D
4
D
5
D
6
D
7
W83782D
112
13
24
25
MR
36
37
48
V
C
O
R
E
A
V
I
N
R
0
+
3.3
V
I
N
+
5
V
I
N
+
12
V
I
N
-
12
V
I
N
V
B
A
T
5
V
S
B
-
5
V
I
N
G
N
D
A
V
I
D
3
CASEOPEN
I
O
R
#
V
I
D
1
B
E
E
P
/
G
P
O
#
CS#
SA0/IA0
SA1/IA1
SA2/IA2
SMI#
ARDMSEL
OVT#
VID0
VTIN1/PIITD1
VTIN3/PIITD3
VTIN2/PIITD2
VREF
VID4
FAN3IO/PWMOUT2
FAN2IO
FAN1IO
PWMTOUT1
VID2
5. PIN DESCRIPTION
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12ts - TTL level and schmitt trigger
OUT12 - Output pin with 12 mA source-sink capability
AOUT - Output pin(Analog)
OD12 - Open-drain output pin with 12 mA sink capability
INt - TTL level input pin
INts - TTL level input pin and schmitt trigger
AIN - Input pin(Analog)
W83782D/W83782G
- 4 -
PIN NAME PIN NO. TYPE DESCRIPTION
IOR# 1 INts An active low standard ISA bus I/O Read Control.
IOW# 2 INts An active low standard ISA bus I/O Write Control.
CLKIN 3 INtSystem clock input. Can select 48MHz or 24MHz or
14.318MHz. The default is 24MHz.
D7~D2 4-9 I/O12t
Bi-directional ISA bus Data lines. D0 corresponds to the
low order bit, with D7 the high order bit. These pins are
activated if pin ADRMSEL=0.
D1 /
PWMOUT4 10
I/O12t
OUT12
Bi-directional ISA bus Data lines. This pin is activated if
pin ADRMSEL=0. /
Fan speed control PWM output. This pin is activated if
pin ADRMSEL=1.
D0 /
PWMOUT3 11
I/O12t
OUT12
Bi-directional ISA bus Data lines. This pin is activated if
pin ADRMSEL=0. /
Fan speed control PWM output. This pin is activated if
pin ADRMSEL=1.
VID1 12 INtVoltage Supply readouts from P6. This value is read in
the VID/Fan Divisor Register.
VCC (+5V) 13 POWER
+5V VCC power. Bypass with the parallel combination of
10μF (electrolytic or tantalum) and 0.1μF (ceramic)
bypass capacitors.
GNDD 14 DGROUND Internally connected to all digital circuitry.
MR 15 INts Master reset input.
CASEOPEN# 16 INt
CASE OPEN detection. An active low input from an
external device when case is opened. This signal can
be latched if pin VBAT is connect to battery, even
W83782D/G is power off.
VID4 17 INtVoltage Supply readouts from P6. This value is read in
the bit <0> of Device ID Register.
FAN3IO/
PWMOUT2 18 I/O12t
0V to +5V amplitude fan tachometer input. /
Fan speed control PWM output.
FAN2IO-
FAN1IO 19-20 I/O12t
0V to +5V amplitude fan tachometer input /
Fan on-off control output. These multi-functional pins
can be programmable input or output.
SCL 21 INts Serial Bus Clock.
SDA 22 OD12 Serial Bus bi-directional Data.
PWMOUT1 23 OUT12 Fan speed control PWM output.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 5 - Revision 2.0
Pin Description, continued
PIN NAME PIN NO. TYPE DESCRIPTION
VID2 24 INtVoltage Supply readouts from P6. This value is read in the
VID/Fan Divisor Register.
VID3 25 INtVoltage Supply readouts from P6. This value is read in the
VID/Fan Divisor Register.
BEEP/GPO# 26 OD12
Beep (Default) / General purpose output
This multi-functional pin is programmable.
GNDA 27
AGROU
ND
Internally connected to all analog circuitry. The ground
reference for all analog inputs.
-5VIN 28 AIN 0V to 4.096V FSR Analog Inputs.
5VSB 29 AIN 0V to 4.096V FSR Analog Inputs.
VBAT 30 AIN
0V to 4.096V FSR Analog Inputs. (This pin should be
connected to 3V BATTERY.)
-12VIN 31 AIN 0V to 4.096V FSR Analog Inputs.
+12VIN 32 AIN 0V to 4.096V FSR Analog Inputs.
+5VIN 33 AIN
This pin is Analog Vcc and connects internal monitor
channel IN3 with fixed scale.
+3.3VIN 34 AIN 0V to 4.096V FSR Analog Inputs.
VINR0 35 AIN 0V to 4.096V FSR Analog Inputs.
VCOREA 36 AIN 0V to 4.096V FSR Analog Inputs.
VREF 37 AOUT Reference Voltage.
VTIN3 /
PIITD3 38 AIN
Thermistor 3 terminal input.(Default) /
PentiumTM II diode 3 input.
This multi-functional pin is programmable.
VTIN2 /
PIITD2 39 AIN
Thermistor 2 terminal input. (Default)/
PentiumTM II diode 2 input.
This multi-functional pin is programmable.
VTIN1 /
PIITD1 40 AIN
Thermistor 1 terminal input. (Default)/
PentiumTM II diode 1 input.
This multi-functional pin is programmable.
VID0 41 INtVoltage Supply readouts from P6. This value is read in the
VID/Fan Divisor Register.
OVT# 42 OD12 Over temperature Shutdown Output.
W83782D/W83782G
- 6 -
Pin Description, continued
PIN NAME PIN NO. TYPE DESCRIPTION
ADRMSEL 43 INt
Pin 45--47 mode selection.
0 = The 3 lowest order bits of ISA Address Bus.(Default,
internal pull-down 47K ohm)
1 = 7 bit I2CTM address setting pin.(bit2 - bit0)
SMI# 44 OD12
System Management Interrupt (open drain). This output is
enabled when Bit 1 in the Configuration Register is set to 1.
The default state is disabled.
SA2-SA0
IA2, IA1, IA0
45-47
INt
INt
The three lowest order bits of the 16-bit ISA Address Bus.
A0 corresponds to the lowest order bit.
(Default, when ARDMSEL =0 or left open )
The hardware setting pin of 7 bit I2CTM serial address bit2,
bit1 and bit0 at CR[48h]. (When ARDMSEL =1)
CS# 48 INt
Chip Select input from an external decoder which decodes
high order address bits on the ISA Address Bus. This is an
active low input.
6. FUNCTIONAL DESCRIPTION
6.1 General Description
The W83782D/G provides 7 analog positive inputs, 3 fan speed monitors, at most 4 sets for fan PWM
(Pulse Width Modulation) control, 3 thermal inputs from remote thermistors or 2N3904 transistors or
PentiumTM II (Deschutes) thermal diode outputs, case open detection and beep function output when
the monitor value exceed the set limit value including voltage, temperature, or fan counter. When
starting the monitor unction on the chip, the watch dog machine monitors every function and stores the
value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1.
6.2 Access Interface
The W83782D/G provides two interfaces for microprocessor to read/write internal registers.
6.2.1 ISA interface
The first interface uses ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port
5h and 6h. The high byte (from ISA address bus bit15~bit3) of these ports is decoded by Chip Select
(CS#), the general decoded address is set to port 295h and port 296h. These two ports are described
as following:
Port 295h: W83782D/G Index register port.
Port 296h: Data port.
The register structure is showed as the Figure 1.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 7 - Revision 2.0
Configuration Register
40h
SMI# Status/Mask Registers
41h, 42h, 44h, 45h
VID<3:0>/Fan Divisor Register
47h
Serial Bus Address
48h
Monitor Value Registers
20h~3Fh
and
60h~7Fh (auto-increment)
VID<4>/Device ID
49h
Temperature 2, 3 Serial
Bus Address
4Ah
Control Register
4Bh~4Dh
Select Bank for 50h~5Fh Reg.
4Eh
Winbond Vendor ID
4Fh
BANK 0
R-T Table Value
BEEP Control Register
Winbond Test Register
50h~58h
BANK 1
Temperature 2 Control/Staus
Registers
50h~56h
BANK 2
Temperature 3 Control/Staus
Registers
50h~56h
Data
Register
Port 6h
Port 5h
Index
Register
ISA
Data
Bus
ISA
Address
Bus
BANK 4
Additional Control/Staus
Registers
50h~5Ch
BANK 5
Additional Limit Value &
Value RAM
50h~57h
Figure 1. ISA interface access diagram
W83782D/W83782G
- 8 -
6.2.2 I2C interface
The second interface uses I2C Serial Bus. In the W83782D/G has three serial bus addresses. That is,
the first address defined at CR [48h] can read/write all registers excluding Bank 1 and Bank 2
temperature sensor 2/3 registers. The second address defined at CR [4Ah] bit2-0 only read/write
temperature sensor 2 registers, and the third address defined at CR [4Ah] bit6-4 only can access
(read/write) temperature sensor 3 registers.
The first serial bus address of W83782D/G has 3 hardware setting bits set by pin47-45 when pin 43 is
set to high. The address is 00101[pin45] [pin46] [pin47]. If pin45=1, pin46=1, pin47=0, for example,
the content of CR [48h] is 0101110. If CR [4Ah] bit 2-0 is XXX, the temperature sensor 2 serial
address is 1001XXXG, in which G is the read/write bit. If CR [4Ah] bit 6-4 is YYY, the temperature
sensor 3 serial address is 1001YYYG, in which G is the read/write bit.
6.2.3 The first serial bus access timing is shown as follows:
(a) Serial bus write to internal address register followed by the data byte
0
Start By
Master
0101101 D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
781D
R/W
Ack
by
781D
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
781D
Stop
by
Master
SCL
SDA (Continued)
780 78
0
78
Frame 2
Internal Index Register Byte
(Continued)
Frame 3
Data Byte
Frame 1
Serial Bus Address Byte
Figure 2. Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0
Start By
Master
0101101 D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
781D
R/W
Ack
by
781D
SCL
SDA
780 78
0
Frame 2
Internal Index Register Byte
Frame 1
Serial Bus Address Byte
Figure 3. Serial Bus Write to Internal Address Register Only
Stop by
Master
W83782D/W83782G
Publication Release Date: April 14, 2005
- 9 - Revision 2.0
(c) Serial bus read from a register with the internal address register prefer to desired location
0
Start By
Master
0101101 D7 D6 D5 D4 D3 D2 D1 D0
Ack
by
Master
R/W
Ack
by
781D
SCL
SDA
780 78
0
Frame 2
Internal Index Register Byte
Frame 1
Serial Bus Address Byte
Figure 4. Serial Bus Write to Internal Address Register Only
Stop by
Master
6.2.4 The serial bus timing of the temperature 2 and 3 is shown as follow:
(a) Typical 2-byte read from preset pointer location (Temp, TOS, THYST)
0
Start By
Master
0101101 D7 D1 D0
Ack
by
Master
R/W
Ack
by
782D
SCL
SDA
780 78
Frame 2
MSB Data Byte
Frame 1
Serial Bus Address Byte
Figure 5. Typical 2-Byte Read From Preset Pointer Location
D7 D1 D0
07
Stop by
Master
...
... ...
Ack
by
Master
...
Frame 3
LSB Data Byte
(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, THYST)
0
Start By
Master
D7 D1 D0
Ack
by
Master
Ack
by
782D
SCL
SDA
780 78
0
Frame 4
MSB Data Byte
Frame 3
Serial Bus Address Byte
Figure 6. Typical Pointer Set Followed by Immediate Read for 2-Byte Register
D7 D1 D0
07
Stop by
Master
...
... ...
No Ack
by
Master
...
Frame 5
LSB Data Byte
0
Start By
Master
1001A2A1 A0 R/W
Ack
by
782D
SCL
SDA
780
Frame 1
Serial Bus Address Byte
4
D1 D0
Ack
by
782D
Frame 2
Pointer Byte
1 0 0 1 A2 A1 A0 R/W
000000
W83782D/W83782G
- 10 -
(c) Typical read 1-byte from configuration register with preset pointer
0
Start By
Master
D7 D2
Ack
by
782D
SCL
SDA
780
Frame 2
Data Byte
Frame 1
Serial Bus Address Byte
Figure 7. Typical 1-Byte Read From Configuration With Preset Pointer
D0
7
Stop by
Master
No Ack
by
Master
1 0 0 1 A2 A1 A0 R/W D1D5 D4 D3D6
8
(d) Typical pointer set followed by immediate read from configuration register
0
Repea
Start
By
Master
D7 D5 D4
Ack
by
782D
SCL (Cont..)
SDA (Cont..)
780
Frame 4
MSB Data Byte
Frame 3
Serial Bus Address Byte
Figure 8. Typical Pointor Set Followed by Immediate Read from Temp 2/3
Configuration Register
D2 D1 D0
7
Stop by
Master
No Ack
by
Master
0
Start By
Master
1001A2A1 A0 R/W
Ack
by
782D
SCL
SDA
780
Frame 1
Serial Bus Address Byte
4
D1 D0
Ack
by
782D
Frame 2
Pointer Byte
1 0 0 1 A2 A1 A0 R/W
...
...
D6 D3
8
78
000000
(e) Temperature 2/3 configuration register Write
0
Ack
by
782D
SCL (Cont...)
SDA (Cont...)
78
Frame 3
Configuration Data Byte
Figure 9. Configuration Register Write
0
Start By
Master
1001A2A1 A0 R/W
Ack
by
782D
SCL
SDA
780
Frame 1
Serial Bus Address Byte
4
D1 D0
Ack
by
782D
Frame 2
Pointer Byte
0 0 D4 D3 D2 D10 D0
Stop
by
Master
0000000
78
W83782D/W83782G
Publication Release Date: April 14, 2005
- 11 - Revision 2.0
(f) Temperature 2/3 TOS and THYST write
0
Ack
by
781D
SCL (Cont...)
SDA (Cont...)
78
Frame 3
MSB Data Byte
Figure 10. Configuration Register Write
0
Start By
Master
1001A2A1 A0 R/W
Ack
by
782D
SCL
SDA
780
Frame 1
Serial Bus Address Byte
4
D1 D0
Ack
by
782D
Frame 2
Pointer Byte
D6 D5 D4 D3 D2 D1D7 D0
078
D6 D5 D4 D3 D2 D1D7 D0
Ack
by
782D
Stop
by
Master
Frame 4
LSB Data Byte
78
000000
6.3 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB.
Really, the application of the PC monitoring would most often be connected to power suppliers. The
CPU V-core voltage, +3.3V and battery voltage can directly connect to these analog inputs. The 5VSB
and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As
Figure 11 shows.
Pin 36
+2.5VINA
+2.5VINB Pin 35
+3.3VIN
12VIN
Pin 34
Pin 32
Pin 33
VDD(+5V)
N12VIN
VBAT
Pin 31
Pin 30
R6
R1
V1
N5VIN
Positive Input
Negative Input
8-bit ADC
with
16mV LSB
Typical Thermister Connection
10K, 1%
R
THM
VREF Pin 37
VTIN3
VTIN2
VTIN1
Pin 38
Pin 39
Pin 40
5VSB Pin 29
Pin 28
Positive Inputs
R5
R7
R8
10K, 25 C
**The Connections of VTIN1 and VTIN2
are same as VTIN3
R2
R3
R4
R
V2
V3
V4
Figure 11.
W83782D/W83782G
- 12 -
6.3.1 Monitor over 4.096V voltage:
The input voltage +12VIN can be expressed as following equation.
12 1
2
12
VIN V R
RR
=× +
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input
voltage V1 is 12V. The node voltage of +12VIN can be subject to less than 4.096V for the maximum
input range of the 8-bit ADC. Similarly, the node voltage of 5VSB (measure standby power VSB for
ATX power supply) also can be evaluated by using two series resistors R3 and R4 which real value
can be 5.1K ohms and 7.5K ohms so as to obtain the 5VSB is limited to less than 4.096V. The Pin 33
is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first
function is to supply internal analog power in the W83782D/G and the second function is that this
voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The values of two
serial resistors are 34K ohms and 50K ohms so that input voltage to ADC is 2.98V which is less than
4.096V of ADC maximum input voltage. The express equation can represent as follows.
VVCC
K
KK V
in =× +≅
50
50 34 298
Ω
ΩΩ
.
where VCC is set to 5V.
6.3.2 Monitor negative voltage:
The negative voltage should be connected two series resistors and a positive voltage VREF (is equal
to 3.6V). In the Figure 11, the voltage V3 and V4 are two negative voltages which are -12V and -5V,
respectively. The voltage V3 is connected to two serial resistors then is connected to another terminal
VREF which is positive voltage. So as that the voltage node N12VIN can be obtain a posedge voltage
if the scales of the two serial resirtors are carefully selected. It is recommended from Winbond that
the scale of two serial resistors are R5=232K ohms and R6=56K ohm. The input voltage of node -
12VIN can be calculated by following equation.
N VIN VREF V
K
KK
V12 232
232 56
55
=+× ++()( )
Ω
ΩΩ
where VREF is equal 3.6V.
If the V5 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set
to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative
voltage and the express equation is shown as follows.
VN VIN VREF
5
12
1
=−
×
−
β
β
Where
β
is 232K/(232K+56K). If the N2VIN is 0.567 then the V5 is approximately equal to -12V.
The other negative voltage input V6 (approximate -5V) also can be evaluated by the similar method
and the serial resistors can be selected with R7=120K ohms and R8=56K ohms by the Winbond
recommended. The expression equation of V6 With -5V voltage is shown as follows.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 13 - Revision 2.0
V
N
VI
N
VREF
6
5
1
=−
×
−
γ
γ
Where the
β
is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635,
VREF=3.6V and the parameter
β
is 0.6818 then the negative voltage of V6 can be evalated to be -5V.
6.3.3 Monitor temperature from thermistor
The W83782D/G can connect three thermistors to measure three different envirment temperatures.
The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K
ohms at 25°C. In the Figure 11, the themistor is connected by a serial resistor with 10K Ohms, then
connect to VREF (Pin 37).
6.3.4 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904
The W83782D/G can alternate the thermistor to Pentium IITM (Deschutes) thermal diode interface or
transistor 2N3904 and the circuit connection is shown as Figure 12. The pin of Pentium IITM D- is
connected to power supply ground (GND) and the pin D+ is connected to pin PIITDx in the
W83782D/G. The resistor R=30K ohms should be connected to VREF to supply the diode bias current
and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor
2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the
2N3904 should be tied together to act as a thermal diode.
2N3904
C
E
B
R=30K, 1%
C=3300pF
Bipolar Transistor
Temperature Sensor
Pentium II
CPU D+
D-
Therminal
Diode C=3300pF
R=30K, 1%
VREF
PIITDx
PIITDx
OR
W83782D
Figure 12.
W83782D/W83782G
- 14 -
6.4 FAN Speed Count and FAN Speed Control
6.4.1 Fan speed count
Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals
should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from
the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the
voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure
13.
Determine the fan counter according to:
Count RPM Divisor
=×
×
135 106
.
In other words, the fan speed counter has been read from register CR28 or CR29 or CR2A, the fan
speed can be evaluated by the following equation.
RPM Count Divisor
=×
×
135 106
.
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are
three bits for divisor. That provides very low speed fan counter such as power supply fan. The
followed table is an example for the relation of divisor, PRM, and count.
DIVISOR NOMINAL
PRM
TIME PER
REVOLUTION COUNTS 70% RPM TIME FOR 70%
1 8800 6.82 ms 153 6160 9.74 ms
2 (default) 4400 13.64 ms 153 3080 19.48 ms
4 2200 27.27 ms 153 1540 38.96 ms
8 1100 54.54 ms 153 770 77.92 ms
16 550 109.08 ms 153 385 155.84 ms
32 275 218.16 ms 153 192 311.68 ms
64 137 436.32 ms 153 96 623.36 ms
128 68 872.64 ms 153 48 1246.72 ms
Table 1
W83782D/W83782G
Publication Release Date: April 14, 2005
- 15 - Revision 2.0
FAN
Connector
FAN Out
+12V
GND
Pull-up resister
4.7K Ohms
+5V
+12V
Fan Input Pin 18/19/20
W83782D FAN
Connector
FAN Out
+12V
GND
Pull-up resister
4.7K Ohms
+12V
Fan Input Pin 18/19/20
W83782D
14K~39K
10K
Figure 13-2. Fan with Tach Pull-Up to +12V, or Totem-Pole
Output and Register Attenuator
Figure 13-1. Fan with Tach Pull-Up to +5V
FAN
Connector
FAN Out
+12V
GND
Pull-up resister
> 1K
+12V
Fan Input Pin 18/19/20
W83782D FAN
Connector
FAN Out
+12V
GND
Pull-up resister < 1K
or totem-pole output
+12V
Fan Input Pin 18/19/20
W83782D
> 1K
Figure 13-4. Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
Figure 13-3. Fan with Tach Pull-Up to +12V
and Zener Clamp
3.9V Zener 3.9V Zener
Fan speed control
The W83782D/G provides four sets for fan PWM speed control. The duty cycle of PWM can be
programmed by an 8-bit registers which are defined in the Bank0 CR5A, CR5B, CR5E, and CR5F.
The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression
of duty can be represented as follows.
Duty cycle Programme
d
8-
b
it Register Value
255
−= ×(%) 100%
W83782D/W83782G
- 16 -
The PWM clock frequency also can be program and defined in the Bank0.CR5C and Bank4.CR5C.
The application circuit is shown as follows.
+12V
FAN
R1
R2
NMOS
PNP Transistor
C
+
-
PWM Clock Input
D
S
G
Figure 14.
6.5 Temperature Measurement Machine
The temperature data format is 8-bit two - complement for sensor 1 and 9-bit two - complement for
sensor 2/3. The 8-bit temperature data can be obtained by reading the CR [27h]. The 9-bit
temperature data can be obtained by reading the 8 MSBs from the Bank1/2 CR [50h] and the LSB
from the Bank1/2 CR [51h] bit 7. The format of the temperature data is show in Table 1.
8-BIT DIGITAL OUTPUT 9-BIT DIGITAL OUTPUT
TEMPERATURE 8-Bit Binary 8-Bit Hex 9-Bit Binary 9-Bit Hex
+125°C 0111,1101 7Dh 0,1111,1010 0FAh
+25°C 0001,1001 19h 0,0011,0010 032h
+1°C 0000,0001 01h 0,0000,0010 002h
+0.5°C - - 0,0000,0001 001h
+0°C 0000,0000 00h 0,0000,0000 000h
-0.5°C - - 1,1111,1111 1FFh
-1°C 1111,1111 FFh 1,1111,1110 1FFh
-25°C 1110,0111 E7h 1,1100,1110 1CEh
-55°C 1100,1001 C9h 1,1001,0010 192h
Table 2
W83782D/W83782G
Publication Release Date: April 14, 2005
- 17 - Revision 2.0
6.5.1 The W83782D/G temperature sensor 1 SMI# interrupt has two modes
(1) Comparator Interrupt Mode
Setting the THYST (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to
the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an
interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an
interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the
TO, the interrupt will occur again when the next conversion has completed. If an interrupt event
has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will
continue to occur in this manner until the temperature goes below TO. (Figure 16-1)
(2) Two-Times Interrupt Mode
Setting the THYST lower than TO will set temperature sensor 1SMI# to the Two-Times Interrupt
Mode. Temperature exceeding TO causes an interrupt and then temperature going below THYST
will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt
Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the
temperature remains above the THYST, the interrupt will not occur. (Figure 15-2)
T
OI
T
HYST
**
Figure 15-1. Comparator Interrupt Mode
*Interrupt Reset when Interrupt Status Registers are read
T
OI
T
HYST
Figure 15-2. Two-Times Interrupt Mode
SMI# SMI#
** * **
127'C
6.5.2 The W83782D/G temperature sensor 2 and sensor 3 SMI# interrupt has two modes
and it is programmed at CR [4Ch] bit 6.
(1) Comparator Interrupt Mode
Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the
Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the
temperature remains above the THYST, the interrupt will occur again when the next conversion has
completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will
not occur again. The interrupts will continue to occur in this manner until the temperature goes
below THYST. (Figure 16-1)
W83782D/W83782G
- 18 -
(2) Two-Times Interrupt Mode
Temperature exceeding TO causes an interrupt and then temperature going below THYST will also
cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature
remains above the THYST, the interrupt will not occur. (Figure 16-2)
T
OI
T
HYST
***
Figure 16-1. Comparator Interrupt Mode
*Interrupt Reset when Interrupt Status Registers are read
T
OI
T
HYST
Figure 16-2. Two-Times Interrupt Mode
SMI# SMI#
** * **
6.5.3 The W83782D/G temperature sensor 2 and 3 Over-Temperature (OVT#) has two
modes, and they are programmed at Bank1 and Bank2 CR [52h] bit1. These two bits
needs to be programmed the same value.
(1) Comparator Mode:
Temperature exceeding TO causes the OVT# output activated until the temperature is less than
THYST. (Figure 17)
(2) Interrupt Mode:
Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading
temperature sensor 2 or sensor 3 registers. Temperature exceeding TO, then OVT# reset, and then
temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading
temperature sensor2 or sensor 3 registers. Once the OVT# is activated by exceeding TO, then
reset, if the temperature remains above THYST, the OVT# will not be activated again. (Figure 17)
T
HYST
***
Figure 17. Over-Temperature Response Diagram
*Interrupt Reset when Temperature 2/3 is read
OVT#
OVT#
*
(Comparator Mode; default)
(Interrupt Mode)
To
W83782D/W83782G
Publication Release Date: April 14, 2005
- 19 - Revision 2.0
7. REGISTERS AND RAM
7.1 Address Register (Port x5h)
Data Port: Port x5h
Power on Default Value 00h
Attribute: Bit 6:0 Read/write, Bit 7: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
Data
Bit7: Read Only
The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus
transaction. With checking this bit, multiple ISA drivers can use W83782D/G without interfering
with each other or a Serial Bus driver.
It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time.
This bit is:
Set: with a write to Port x5h or when a Serial Bus transaction is in progress.
Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus
transaction is finished.
Bit 6-0: Read/Write
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Busy Address Pointer (Power On default 00h)
(Power On default 0) A6 A5 A4 A3 A2 A1 A0
W83782D/W83782G
- 20 -
Address Pointer Index (A6-A0)
Registers and RAM A6-A0
in Hex
Power On Value of Registers:
<k7:0>in Binary Notes
Configuration Register 40h 00001000
Interrupt Status Register 1 41h 00000000
Auto-increment to the address of Interrupt
Status Register 2 after a read or write to Port
x6h.
Interrupt Status Register 2 42h 00000000
SMI#Ý Mask Register 1 43h 00000000 Auto-increment to the address of SMIÝ Mask
Register 2 after a read or write to Port x6h.
SMIÝ Mask Register 2 44h 00000000
NMI Mask Register 1 45h 00000000 Auto-increment to the address of NMI Mask
Register 2 after a read or write to Port x6h
NMI Mask Register 2 46h 01000000
VID/Fan Divisor Register 47h <7:4> = 0101;
<3:0> = VID3-ID0
Serial Bus Address
Register 48h <6:0> = 0101101; <7> = 0
POST RAM 00-1Fh Auto-increment to the next location after a
read or write to Port x6h and stop at 1Fh.
Value RAM 20-3Fh
Value RAM 60-7Fh Auto-increment to the next location after a
read or write to Port x6h and stop at 7Fh.
7.2 Data Register (Port x6h)
Data Port: Port x6h
Power on Default Value 00h
Attribute: Read/write
Size: 8 bits
7 6 5 4 3 2 1 0
Data
Bit 7-0: Data to be read from or to be written to RAM and Register.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 21 - Revision 2.0
7.3 Configuration Register − Index 40h
Register Location: 40h
Power on Default Value 00000001 binary
Attribute: Read/write
Size: 8 bits
7 6 5 4 3 2 1 0
START
SMI#Enable
RESERVED
INT_Clear
RESERVED
RESERVED
BEEP/GPO#
INITIALIZATION
Bit 7: A one restores power on default value to all registers except the Serial Bus Address register.
This bit clears itself since the power on default is zero.
Bit 6: The logical 1 in this bit drives a zero on BEEP/GPO# pin.
Bit 5: Reserved
Bit 4: Reserved
Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The
device will stop monitoring. It will resume upon clearing of this bit.
Bit 2: Reserved
Bit 1: A one enables the SMI# Interrupt output.
Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred
unlike "INT_Clear'' bit.
7.4 Interrupt Status Register 1 − Index 41h
Register Location: 41h
Power on Default Value 00h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
VCOREA
VINRO
+3.3VIN
+5VIN
TEMP1
TEMP2
FAN1
FAN2
Bit 7: A one indicates the fan count limit of FAN2 has been exceeded.
Bit 6: A one indicates the fan count limit of FAN1 has been exceeded.
W83782D/W83782G
- 22 -
Bit 5: A one indicates a High limit of VTIN2 has been exceeded from temperature sensor 2.
Bit 4: A one indicates a High limit of VTIN1 has been exceeded from temperature sensor 1.
Bit 3: A one indicates a High or Low limit of +5VIN has been exceeded.
Bit 2: A one indicates a High or Low limit of +3.3VIN has been exceeded.
Bit 1: A one indicates a High or Low limit of VINR0 has been exceeded.
Bit 0: A one indicates a High or Low limit of VCOREA has been exceeded.
7.5 Interrupt Status Register 2 − Index 42h
Register Location: 42h
Power on Default Value 00h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
+12VIN
-12VIN
-5VIN
FAN3
Chassis Intrusion
Temp3
Reserved
Reserved
Bit 7-6:Reserved.This bit should be set to 0.
Bit 5: A one indicates a High limit of VTIN3 has been exceeded from temperature sensor 3.
Bit 4: A one indicates Chassis Intrusion has gone high.
Bit 3: A one indicates the fan count limit of FAN3 has been exceeded.
Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded.
Bit1: A one indicates a High or Low limit of -12VIN has been exceeded.
Bit0: A one indicates a High or Low limit of +12VIN has been exceeded.
7.6 SMI# Mask Register 1 − Index 43h
Register Location: 43h
Power on Default Value 00h
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
VCOREA
VINRO
+3.3VIN
+5VIN
TEMP1
TEMP2
FAN1
FAN2
Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 23 - Revision 2.0
7.7 SMI# Mask Register 2 − Index 44h
Register Location: 44h
Power on Default Value 00h
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
+12VIN
-12VIN
-5VIN
FAN3
Chassis Intrusion
TEMP3
Reserved
Reserved
Bit 7-6: Reserved. This bit should be set to 0.
Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt.
7.8 Reserved Register − Index 45h
7.9 Chassis Clear Register − Index 46h
Register Location: 46h
Power on Default Value <7:0> = 00000000 binary
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Chassis Clear
Bit 7: Set 1, clear Chassis Intrusion event. This bit self clears after clearing Chassis Intrusion event.
Bit 6-0: Reserved. This bit should be set to 0.
W83782D/W83782G
- 24 -
7.10 VID/Fan Divisor Register − Index 47h
Register Location: 47h
Power on Default Value <7:4> is 0101, <3:0> is mapped to VID<3:0>
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
VID0
VID1
VID2
VID3
FAN1DIV_B0
FAN1DIV_B1
FAN2DIV_B0
FAN2DIV_B1
Bit 7-6: FAN2 Speed Control.
Bit 5-4: FAN1 Speed Control.
Bit 3-0: The VID <3:0> inputs
Note: Please refer to Bank0 CR [5Dh] , Fan divisor table.
7.11 Serial Bus Address Register − Index 48h
Register Location: 48h
Power on Default Value Serial Bus address <6:0> = 0101101 and <7> = 0 binary
Size: 8 bits
7 6 5 4 3 2 1 0
Serial Bus Address
Reserved
Bit 7: Read Only - Reserved.
Bit 6-0: Read/Write - Serial Bus address <6:0>.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 25 - Revision 2.0
7.12 Value RAM − Index 20h- 3Fh or 60h - 7Fh (auto-increment)
ADDRESS A6-
A0
ADDRESS A6-A0 WITH
AUTO-INCREMENT DESCRIPTION
20h 60h VCOREA reading
21h 61h VINR0 reading
22h 62h +3.3VIN reading
23h 63h +5VIN reading
24h 64h +12VIN reading
25h 65h -12VIN reading
26h 66h -5VIN reading
27h 67h Temperature reading
28h 68h
FAN1 reading
Note: This location stores the number of counts of the internal
clock per revolution.
29h 69h
FAN2 reading
Note: This location stores the number of counts of the internal
clock per revolution.
2Ah 6Ah
FAN3 reading
Note: This location stores the number of counts of the internal
clock per revolution.
2Bh 6Bh
VCOREA High Limit, default value is defined by
Vcore Voltage +0.2v.
2Ch 6Ch
VCOREA Low Limit, default value is defined by
Vcore Voltage -0.2v.
2Dh 6Dh VINR0 High Limit.
2Eh 6Eh VINR0 Low Limit.
2Fh 6Fh +3.3VIN High Limit
30h 70h +3.3VIN Low Limit
31h 71h +5VIN High Limit
32h 72h +5VIN Low Limit
33h 73h +12VIN High Limit
34h 74h +12VIN Low Limit
35h 75h -12VIN High Limit
36h 76h -12VIN Low Limit
37h 77h -5VIN High Limit
38h 78h -5VIN Low Limit
W83782D/W83782G
- 26 -
Value RAM − Index 20h- 3Fh or 60h - 7Fh (auto-increment), continued
ADDRESS A6-A0 ADDRESS A6-A0 WITH
AUTO-INCREMENT
DESCRIPTION
39h 79h Temperature sensor 1 (VTIN1) High Limit
3Ah 7Ah Temperature sensor 1 (VTIN1) Hysteresis Limit
3Bh 7Bh FAN1 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low
Limit of the fan speed.
3Ch 7Ch FAN2 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low
Limit of the fan speed.
3Dh 7Dh FAN3 Fan Count Limit
Note: It is the number of counts of the internal clock for the Low
Limit of the fan speed.
3E- 3Fh 7E- 7Fh Reserved
Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means
interrupts will never be generated except the case when voltages go below the low limits.
7.13 Voltage ID (VID4) & Device ID − Index 49h
Register Location: 49h
Power on Default Value <7:1> is 000,0001b
<0> is mapped to VID <4>
Size: 8 bits
7 6 5 4 3 2 1 0
DID<6:0>
VID4
Bit 7-1: Read Only - Device ID<6:0>
Bit 0: Read/Write - The VID4 inputs.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 27 - Revision 2.0
7.14 Temperature 2 and Temperature 3 Serial Bus Address Register − Index 4Ah
Register Location: 4Ah
Power on Default Value <7:0> = 0000, 0001 binary. Reset by MR
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
I2CADDR2
I2CADDR2
I2CADDR2
DIS_T2
I2CADDR3
I2CADDR3
I2CADDR3
DIS_T3
Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3.
Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx, where xxx are defined in
these bits.
Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2.
Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx, where xxx are defined in
these bits.
7.15 Pin Control Register − Index4Bh
Register Location: 4Bh
Power on Default Value <7:0> 44h. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
Reserved
Reserved
CLKINSEL
CLKINSEL
ADCOVSEL
ADCOVSEL
FAN3DIV_B0
FAN3DIV_B1
Bit 7-6:Fan3 speed divisor.
Please refer to Bank0 CR [5Dh], Fan divisor table.
Bit 5-4: Select A/D Converter Clock Input.
<5:4> = 00 - default. ADC clock select 22.5 Khz.
<5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4)
W83782D/W83782G
- 28 -
<5:4> = 10 - ADC clock select 1.4 KHz. (22.5K/16)
<5:4> = 11 - ADC clock select 0.35 KHz. (22.5K/64)
Bit 3-2: Clock Input Select.
<3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock.
<3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock.
<3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock .
<3:2> = 11 - Reserved. Pin3 no clock input.
Bit 1-0: Reserved. User defined.
7.16 IRQ#/OVT# Property Select − Index 4Ch
Register Location: 4Ch
Power on Default Value <7:0> --0000,0001. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
Reserved
Reserved
OVTPOL
DIS_OVT1
DIS_OVT2
Reserved
T23_INTMode
Reserved
Bit 7: Reserved. User Defined.
Bit6: Set to 1, the SMI# output type of Temperature 2 and 3 is set to Comparator Interrupt mode. Set
to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0)
Bit5: Reserved. User Defined.
Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable
OVT2 output through pin OVT#.
Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable
OVT1 output through pin OVT#.
Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0.
Bit 1: Reserved. User Defined.
Bit 0: Reserved. User Defined.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 29 - Revision 2.0
7.17 FAN IN/OUT and BEEP/GPO# Control Register − Index 4Dh
Register Location: 4Dh
Power on Default Value <7:0> 0001, 0101. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
FANINC1
FANOPV1
FANINC2
FANOPV2
FANINC3
FANOPV3
GPOSEL
DIS_ABN
Bit 7: Disable power-on abnormal the monitor voltage including V-Core A and +3.3V. If these voltages
exceed the limit value, the pin (Open Drain) of BEEP will drives 300Hz and 600Hz frequency
signal. Write 1, the frequency will be disabled. Default is 0. After power on, the system should
set 1 to this bit to 1 in order to disable BEEP.
Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function.
This bit default 0.
Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high signal.
Write 0, pin 18 always generates logic low signal. This bit default 0.
Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0,
this pin 18 acts as FAN control signal and the output value of FAN control is set by this register
bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF.
Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 19 always generate logic high signal.
Write 0, pin 19 always generates logic low signal. This bit default 0.
Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0,
this pin 19 acts as FAN control signal and the output value of FAN control is set by this register
bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF.
Bit 1: FAN 1 output value if FANINC1 sets to 0. Write 1, then pin 20 always generate logic high signal.
Write 0, pin 20 always generates logic low signal. This bit default 0.
Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0,
the pin 20 acts as FAN control signal and the output value of FAN control is set by this register t
1. This output pin can connect to power PMOS gate to control FAN ON/OFF.
W83782D/W83782G
- 30 -
7.18 Register 50h ~ 5Fh Bank Select − Index 4Eh
Register Location: 4Eh
Power on Default Value <6:3> = Reserved, <7> = 1, <2:0> = 0. Reset by MR
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
BANKSEL0
BANKSEL1
BANKSEL2
Reserved
Reserved
Reserved
Reserved
HBACS
Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register.
Set to 0, access Register 4Fh low byte register. Default 1.
Bit 6-3: Reserved. This bit should be set to 0.
Bit 2-0: Index ports 0x50~0x5F Bank select.
7.19 Winbond Vendor ID − Index 4Fh
Register Location: 4Fh
Power on Default Value <15:0> = 5CA3h
Attribute: Read Only
Size: 16 bits
15 8 7 0
VIDH
VIDL
Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch.
Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.
7.20 Winbond Test Register − Index 50h - 55h (Bank 0)
Reserved
W83782D/W83782G
Publication Release Date: April 14, 2005
- 31 - Revision 2.0
7.21 BEEP Control Register 1 − Index 56h (Bank 0)
Register Location: 56h
Power on Default Value <7:0> 0000, 0000. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
EN_VCA_BP
EN_Vr0_BP
EN_V33_BP
EN_V5_BP
EN_T1_BP
EN_T2_BP
EN_FAN1_BP
EN_FAN2_BP
Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceeds the limit value. Write 1, enable
BEEP output, which is default value.
Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceeds the limit value. Write 1, enable
BEEP output, which is default value.
Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceeds the limit value.
Write 1, enable BEEP output. Default 0
Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceeds the limit value.
Write 1, enable BEEP output. Default 0
Bit 3: Enable BEEP output from VDD (+5V), Write 1, enable BEEP output if the monitor value exceeds
the limits value. Default 0, that is disable BEEP output.
Bit 2: Enable BEEP output from +3.3V. Write 1, enable BEEP output, which is default value.
Bit 1: Enable BEEP output from VINR0. Write 1, enable BEEP output, which is default value.
Bit 0: Enable BEEP Output from VCOREA if the monitor value exceeds the limits value. Write 1,
enable BEEP output, which is default value
7.22 BEEP Control Register 2 − Index 57h (Bank 0)
Register Location: 57h
Power on Default Value <7:0> 1000-0000. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
EN_V12_BP
EN_NV12_BP
EN_NV5_BP
EN_FAN3_BP
EN_CASO_BP
EN_T3_BP
Reserved
EN_GBP
W83782D/W83782G
- 32 -
Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP
output.
Bit 6: Reserved. This bit should be set to 0.
Bit 5: Enable BEEP Output from Temperature Sensor 3 if the monitor value exceeds the limit value.
Write 1, enable BEEP output. Default 0
Bit 4: Enable BEEP output for case open if the monitor value exceeds the limit value. Write 1, enable
BEEP output. Default 0.
Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceeds the limit value. Write 1, enable
BEEP output. Default 0.
Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the
limits value. Default 0, that is disable BEEP output.
7.23 Chip ID − Index 58h (Bank 0)
Register Location: 58h
Power on Default Value <7:0> 0011-0000. Reset by MR.
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
CHIPID
Bit 7: Winbond Chip ID number. Read this register will return 30h.
7.24 Diode Selection Register − Index 59h (Bank 0)
Register Location: 59h
Power on Default Value <7>=0 and <6:4> = 111 and <3:0> = 0000
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved
Reserved
SELPIIV1
SELPIIV2
SELPIIV3
Reserved
W83782D/W83782G
Publication Release Date: April 14, 2005
- 33 - Revision 2.0
Bit 7: Reserved
Bit 6: Temperature sensor diode 3. Set to 1, select Pentium II compatible Diode. Set to 0 to select
2N3904 bipolar mode.
Bit 5: Temperature sensor diode 2. Set to 1, select Pentium II compatible Diode. Set to 0 to select
2N3904 bipolar mode.
Bit 4: Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set to 0 to select
2N3904 bipolar mode.
Bit 3-0: Reserved
7.25 PWMOUT2 Control − Index 5Ah (Bank 0)
Register Location: 5Ah
Power on default value: <7:0> 1111-1111. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
PWM2_DUTY
Bit 7: PWMOUT2 duty cycle control
Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%.
7.26 PWMOUT1 Control − Index 5Bh (Bank 0)
Register Location: 5Bh
Power on default value: <7:0> 1111-1111. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
PWM1_DUTY
Bit 7: PWMOUT1 duty cycle control
Write FF, Duty cycle is 100%,
Write 00, Duty cycle is 0%.
W83782D/W83782G
- 34 -
7.27 PWMOUT1/2 Clock Select − Index 5Ch (Bank 0)
Register Location: 5Ch
Power on Default Value <7:0> 0001-0001. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
PWM2CLKSEL
PWM2CLKSEL
PWM2CLKSEL
EN_FANPWM2
PWM1CLKSEL
PWM1CLKSEL
PWM1CLKSEL
Reserved
Bit 7: Reserved
Bit 6-4: PWMOUT1 clock selection.
The clock defined frequency is same as PWMOUT2 clock selection.
Bit 3: Set to 1. Enable PWMOUT2 PWM Control
Bit 2-0: PWMOUT2 clock Selection.
<2:0> = 000: 46.87K Hz
<2:0> = 001: 23.43K Hz (Default)
<2:0> = 010: 11.72K Hz
<2:0> = 011: 5.85K Hz
<2:0> = 100: 2.93K Hz
7.28 VBAT Monitor Control Register − Index 5Dh (Bank 0)
Register Location: 5Dh
Power on Default Value <7:0> 0000-0000. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
EN_VBAT_MNT
DIODES1
DIODES2
DIODES3
RESERVE
FANDIV1_B2
FANDIV2_B2
FANDIV3_B2
Bit 7: Fan3 divisor Bit 2.
Bit 6: Fan2 divisor Bit 2.
Bit 5: Fan1 divisor Bit 2.
Bit 4: Reserve.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 35 - Revision 2.0
Bit 3: Temperature sensor 3 select into thermal diode such as Pentium II CPU supported. Set to 1,
select bipolar sensor. Set to 0, select thermistor sensor.
Bit 2: Sensor 2 type selection. Defined as DIODES3 described in the bit 3.
Bit 1: Sensor 1 type selection. Defined as DIODES2 described in the bit 3.
Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this
bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least
300ms for W83782D.
Fan divisor table:
BIT 2 BIT 1 BIT 0 FAN DIVISOR BIT 2 BIT 1 BIT 0 FAN DIVISOR
0 0 0 1 1 0 0 16
0 0 1 2 1 0 1 32
0 1 0 4 1 1 0 64
0 1 1 8 1 1 1 128
7.29 PWMOUT3 Control − Index 5Eh (Bank 0)
Register Location: 5Eh
Power on Default Value <7:0> 1111-1111. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
PWM3_DUTY
Bit 7: PWMOUT3 duty cycle control
Write FF, Duty cycle is 100%,
Write 00, Duty cycle is 0%.
W83782D/W83782G
- 36 -
7.30 PWMOUT4 Control − Index 5Fh (Bank 0)
Register Location: 5Fh
Power on Default Value <7:0> 1111-1111. Reset by MR.
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
PWM4_DUTY
Bit 7: PWMOUT4 duty cycle control
Write FF, Duty cycle is 100%,
Write 00, Duty cycle is 0%.
7.31 Temperature Sensor 2 Temperature (High Byte) Register − Index 50h (Bank 1)
Register Location: 50h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
TEMP2<8:1>
Bit 7: Temperature <8:1> of sensor 2, which is high byte.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 37 - Revision 2.0
7.32 Temperature Sensor 2 Temperature (Low Byte) Register − Index 51h (Bank 1)
Register Location: 51h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
TEMP2<0>
Reserved
Bit 7: Temperature <0> of sensor2, which is low byte.
Bit 6-0: Reserved. This bit should be set to 0.
7.33 Temperature Sensor 2 Configuration Register − Index 52h (Bank 1)
Register Location: 52h
Power on Default Value <7:0> = 0x00
Size: 8 bits
7 6 5 4 3 2 1 0
STOP2
INTMOD
Reserved
FAULT
FAULT
Reserved
Reserved
Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0.
Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due
to noise.
Bit 2: Read - Reserved. This bit should be set to 0.
Bit 1: Read/Write - OVT# Interrupt mode select. This bit default is set to 0, which is compared mode.
When set to 1, interrupt mode will be selected.
Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
W83782D/W83782G
- 38 -
7.34 Temperature Sensor 2 Hysteresis (High Byte) Register − Index 53h (Bank 1)
Register Location: 53h
Power on Default Value <7:0> = 0x4B
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
THYST2<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default is 75 degree C.
7.35 Temperature Sensor 2 Hysteresis (Low Byte) Register − Index 54h (Bank 1)
Register Location: 54h
Power on Default Value <7:0> = 0x0
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
THYST2<0>
Reserved
Bit 7: Temperature hysteresis bit 0, which is low Byte.
Bit 6-0: Reserved. This bit should be set to 0.
7.36 Temperature Sensor 2 Over-temperature (High Byte) Register − Index 55h
(Bank 1)
Register Location: 55h
Power on Default Value <7:0> = 0x50
Attribute: Read/Write
Size: 8 bits
W83782D/W83782G
Publication Release Date: April 14, 2005
- 39 - Revision 2.0
7 6 5 4 3 2 1 0
TOVF2<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default is 80 degree C.
7.37 Temperature Sensor 2 Over-temperature (Low Byte) Register − Index 56h
(Bank 1)
Register Location: 56h
Power on Default Value <7:0> = 0x0
Size: 8 bits
7 6 5 4 3 2 1 0
TOVF2<0>
Reserved
Bit 7: Read/Write- Over-temperature bit 0, which is low Byte.
Bit 6-0: Read Only- Reserved. This bit should be set to 0.
7.38 Temperature Sensor 3 Temperature (High Byte) Register − Index 50h (Bank 2)
Register Location: 50h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
TEMP2<8:1>
Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.
W83782D/W83782G
- 40 -
7.39 Temperature Sensor 3 Temperature (Low Byte) Register − Index 51h (Bank 2)
Register Location: 51h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
TEMP2<0>
Reserved
Bit 7: Temperature <0> of sensor2, which is low byte.
Bit 6-0: Reserved. This bit should be set to 0.
7.40 Temperature Sensor 3 Configuration Register − Index 52h (Bank 2)
Register Location: 52h
Power on Default Value <7:0> = 0x00
Size: 8 bits
7 6 5 4 3 2 1 0
STOP3
INTMOD
Reserved
FAULT
FAULT
Reserved
Reserved
Reserved
Bit 7-5: Read - Reserved. This bit should be set to 0.
Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due
to noise.
Bit 2: Read - Reserved. This bit should be set to 0.
Bit 1: Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode.
When set to 1, Interrupt Mode will be selected.
Bit 0: Read/Write - When set to 1 the sensor will stop monitor.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 41 - Revision 2.0
7.41 Temperature Sensor 3 Hysteresis (High Byte) Register − Index 53h (Bank 2)
Register Location: 53h
Power on Default Value <7:0> = 0x4B
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
THYST3<8:1>
Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default is 75 degree C.
7.42 Temperature Sensor 3 Hysteresis (Low Byte) Register − Index 54h (Bank 2)
Register Location: 54h
Power on Default Value <7:0> = 0x0
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
THYST3<0>
Reserved
Bit 7: Temperature hysteresis bit 0, which is low Byte.
Bit 6-0: Reserved. This bit should be set to 0.
W83782D/W83782G
- 42 -
7.43 Temperature Sensor 3 Over-temperature (High Byte) Register − Index 55h
(Bank 2)
Register Location: 55h
Power on Default Value <7:0> = 0x50
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
TOVF3<8:1>
Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default is 80 degree C.
7.44 Temperature Sensor 3 Over-temperature (Low Byte) Register − Index 56h
(Bank 2)
Register Location: 56h
Power on Default Value <7:0> = 0x0
Size: 8 bits
7 6 5 4 3 2 1 0
TOVF3<0>
Reserved
Bit 7: Read/Write- Over-temperature bit 0, which is low Byte.
Bit 6-0: Read Only- Reserved. This bit should be set to 0.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 43 - Revision 2.0
7.45 Interrupt Status Register 3 − Index 50h (Bank4)
Register Location: 50h
Power on Default Value <7:0> = 00h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
5VSB
VBAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7-2: Reserved.
Bit 1: A one indicates a High or Low limit of VBAT has been exceeded.
Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded.
7.46 SMI# Mask Register 3 − Index 51h (Bank 4)
Register Location: 51h
Power on Default Value <7:0> = 0000, 0000h
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
5VSB
VBAT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7-2: Reserved.
Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt.
Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt.
W83782D/W83782G
- 44 -
7.47 BEEP Control Register 3 − Index 53h (Bank 4)
Register Location: 53h
Power on Default Value <7:0> 0000, 0000. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
EN_5VSB_BP
EN_VBAT_BP
Reserved
Reserved
Reserved
EN_USER_BP
Reserved
Reserved
Bit 7-6: Reserved.
Bit 5: User defines BEEP output function. Write 1, the BEEP is always active. Write 0, this function is
inactive. (Default 0)
Bit 4-2: Reserved.
Bit 1: Enable BEEP output from VBAT. Write 1, enable BEEP output, which is default value.
Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP output, which is default value.
7.48 Reserved Register − Index 54h-58h
7.49 Real Time Hardware Status Register I − Index 59h (Bank 4)
Register Location: 59h
Power on Default Value <7:0> 0000, 0000. Reset by MR.
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
VCOREA_STS
VINR0_STS
+3.3VIN_STS
+5VIN_STS
TEMP1_STS
TEMP2_STS
FAN1_STS
FAN2_STS
Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter
is in the limit range.
Bit 6: FAN 1 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter
is in the limit range.
Bit 5: Temperature sensor 2 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
W83782D/W83782G
Publication Release Date: April 14, 2005
- 45 - Revision 2.0
Bit 4: Temperature sensor 1 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
Bit 3: +5V Voltage Status. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is
in the limit range.
Bit 2: +3.3V Voltage Status. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of
+3.3V is in the limit range.
Bit 1: VINR0 Voltage Status. Set 1, the voltage of VINR0 is over the limit value. Set 0, the voltage of
VINR0 is in the limit range.
Bit 0: VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the
voltage of VCORE A is in the limit range.
7.50 Real Time Hardware Status Register II − Index 5Ah (Bank 4)
Register Location: 5Ah
Power on Default Value <7:0> 0000, 0000. Reset by MR.
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
+12VIN_STS
-12VIN_STS
-5VIN_STS
FAN3_STS
CASE_STS
TEMP3_STS
Reserved
Reserved
Bit 7-6: Reserved
Bit 5: Temperature sensor 3 Status. Set 1, the voltage of temperature sensor is over the limit value.
Set 0, the voltage of temperature sensor is in the limit range.
Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0
Bit 3: FAN3 Voltage Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed
counter is during the limit range.
Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is
during the limit range.
Bit 1: -12V Voltage Status. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of -12V
is during the limit range.
Bit 0: +12V Voltage Status. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of
+12V is in the limit range.
W83782D/W83782G
- 46 -
7.51 Real Time Hardware Status Register III − Index 5Bh (Bank 4)
Register Location: 5Bh
Power on Default Value <7:0> = 0000, 0000h
Attribute: Read Only
Size: 8 bits
7 6 5 4 3 2 1 0
5VSB_STS
VBAT_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7-2: Reserved.
Bit 1: VBAT Voltage Status. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of
VBAT is during the limit range.
Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of
5VSB is in the limit range.
7.52 PWMOUT3/4 Clock Select − Index 5Ch (Bank 4)
Register Location: 5Ch
Power on Default Value <7:0> 0001, 0001. Reset by MR.
Attribute: Read/Write
Size: 8 bits
7 6 5 4 3 2 1 0
PWM3CLKSEL
PWM3CLKSEL
PWM3CLKSEL
Reserved
PWM4CLKSEL
PWM4CLKSEL
PWM4CLKSEL
Reserved
Bit 7: Reserved.
Bit 6-4: PWMOUT4 clock selection.
The clock defined frequency is same as PWMOUT3 clock selection.
Bit 3: Reserved.
Bit 2-0: PWMOUT3 clock Selection.
<2:0> = 000: 46.87K Hz
<2:0> = 001: 23.43K Hz (Default)
<2:0> = 010: 11.72K Hz
<2:0> = 011: 5.85K Hz
<2:0> = 100: 2.93K Hz
W83782D/W83782G
Publication Release Date: April 14, 2005
- 47 - Revision 2.0
7.53 Value RAM 2 − Index 50h - 5Ah (auto-increment) (Bank 5)
ADDRESS A6-A0
AUTO-INCREMENT DESCRIPTION
50h 5VSB reading
51h VBAT reading
52h Reserved
53h Reserved
54h 5VSB High Limit
55h 5VSB Low Limit.
56h VBAT High Limit
57h VBAT Low Limit
7.54 Winbond Test Register − Index 50h (Bank 6)
Reserved.
W83782D/W83782G
- 48 -
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage -0.5 to 7.0 V
Input Voltage -0.5 to VDD+0.5 V
Operating Temperature 0 to +70 ° C
Storage Temperature -55 to +150 ° C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2 DC Characteristics
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage VIL
0.8 V
Input High Voltage VIH 2.0 V
Output Low Voltage VOL
0.4 V IOL = 12 mA
Output High Voltage VOH 2.4 V IOH = - 12 mA
Input High Leakage ILIH
+10 μA VIN = VDD
Input Low Leakage ILIL
-10 μA VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger
level input
Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V
Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V
Hysteresis VTH 0.5 1.2 V VDD = 5 V
Output Low Voltage VOL
0.4 V IOL = 12 mA
Output High Voltage VOH 2.4 V IOH = - 12 mA
Input High Leakage ILIH
+10 μA VIN = VDD
Input Low Leakage ILIL
-10 μA VIN = 0V
W83782D/W83782G
Publication Release Date: April 14, 2005
- 49 - Revision 2.0
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage VOL
0.4 V IOL = 12 mA
Output High Voltage VOH 2.4 V IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA
Output Low Voltage VOL
0.4 V IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA
Output Low Voltage VOL
0.4 V IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA
Output Low Voltage VOL
0.4 V IOL = 48 mA
INt - TTL level input pin
Input Low Voltage VIL
0.8 V
Input High Voltage VIH 2.0 V
Input High Leakage ILIH
+10 μA VIN = VDD
Input Low Leakage ILIL
-10 μA VIN = 0 V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V
Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V
Hysteresis VTH 0.5 1.2 V VDD = 5 V
Input High Leakage ILIH
+10 μA VIN = VDD
Input Low Leakage ILIL
-10 μA VIN = 0 V
W83782D/W83782G
- 50 -
8.3 AC Characteristics
8.3.1 ISA Read/Write Interface Timing
AEN
SA[2:0],CS#
IOR#
SD[7:0]
IRQ
tAR
tRVD
VALID DATA
tRD
tRA
tRDH
tRI
tRCU
RC
ISA Bus Read Timing
IOW#
AEN
SA[2:0],CS#
IOW#
SD[7:0]
IRQ
tAW
tDS
VALID DATA
tWR
tWA
tDH
tWI
tWCU
WC
IOR#
VALID VALID
ISA Bus Write Timing
W83782D/W83782G
Publication Release Date: April 14, 2005
- 51 - Revision 2.0
ISA Read/Write Timing
PARAMETER SYMBOL MIN. MAX. UNIT
Valid Address to Read Active t-AR 10 nS
Valid Address to Write Active tAW 10 nS
Data Hold tDH 5 nS
Data Setup tDS 80 nS
Address Hold from Inactive Read tRA 40 nS
Read Cycle Update tRCU 200 nS
Read Strobe Width tRD 120 nS
Read Data Hold tRDH 40 nS
Read Strobe to Clear IRQ tRI 60 nS
Active Read to Valid Data tRVD 115 nS
Address Hold from Inactive Write tWA 5 nS
Write Cycle Update tWCU 80 nS
Write Strobe to Clear IRQ tWI 60 nS
Write Strobe Width tWR 120 nS
Read Cycle = tAR + tRD+tRCV RC 330 nS
Write Cycle = tAW+tWR+tWCV WC 210 nS
W83782D/W83782G
- 52 -
8.3.2 Serial Bus Timing Diagram
VALID DATA
SCL
SDA IN
SDA OUT
tHD;SDA
tSCL
tHD;DAT tSU;STO
tSU;DAT
Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
SCL Clock Period t-SCL 10 uS
Start Condition Hold Time tHD;SDA 4.7 uS
Stop Condition Setup-up Time tSU;STO 4.7 uS
DATA to SCL Setup Time tSU;DAT 120 nS
DATA to SCL Hold Time tHD;DAT 5 nS
SCL and SDA Rise Time tR 1.0 uS
SCL and SDA Fall Time tF 300 nS
W83782D/W83782G
Publication Release Date: April 14, 2005
- 53 - Revision 2.0
9. HOW TO READ THE TOP MARKING
The top marking of W83782D
W83782D
825AA
Left: Winbond logo
1st line: Type number W83782D, D means LQFP (Thickness = 1.4 mm).
2nd line: Tracking code 825 A A
825: packages made in '98, week 25
A: assembly house ID; A means ASE, O means OSE
A: IC revision; A means version A, B means version B
The top marking of W83782G
W83782G
825AA
Left: Winbond logo
1st line: Type number W83782G, G means Lead-free Package.
2nd line: Tracking code 825 A A
825: packages made in '98, week 25
A: assembly house ID; A means ASE, O means OSE
A: IC revision; A means version A, B means version B
W83782D/W83782G
- 54 -
10. PACKAGE DIMENTIONS
48-pin QFP
2
1
A
H
D
D
eb
EHE
y
A
A
Seating Plane L
L1
See Detail F
Detail F
c
37
48
112
13
24
25
36
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Notes:
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inch Dimension in mm
A
b
c
D
e
HD
HE
L
y
0
A
A
L1
1
2
E
1.40
0.20
0.50
1.00
7.00
9.00
9.00
7.00
---
---
--- 1.60
0.15
1.45
1.35
0.05
0.17 0.27
---
0.09 0.20
0.45 0.60 0.75
0.08
03.5 7
--- ---
W83782D/W83782G
Publication Release Date: April 14, 2005
- 55 - Revision 2.0
11. APPLICATION CIRCUITS
0.3
W83781D-W83782D Application Circuit
Winbond Electronic Corp.
Custom
12Thursday, July 23, 1998
Title
Size Document Number Rev
Date: Sheet of
VCC
VCC
+12V
VCC
3VCC
3VCC
3VCC
VBAT
5VSB
VCC
-12V
-5V
CPU Voltage ID output
Beep Circuits
{
TO PIIX4
VOLTAGE SENSING
bits of ISA address bus
Set A2-A0 as 3 lowest order
Select one of the two setting.
Set A2-A0 as bit2, bit1, bit0
of 7 bit I2C address setting
VCOREA
VINR0
3VIN
+12VIN
GNDA
-12VIN
VBAT/-12VOUT
VREF VREF VID2
GNDA SDA
SCL
VID0
OVT#
5VSB/-5VOUT ADRMSEL
SMI# VID4
A2
A1
A0 GNDD
-5VIN VCC
OVT#
SMI#
GNDA GNDD
BEEP/GPO#
ADRMSELIN
A2 VID4
A1 VID3
A0 VID2
VID1
VID0
ADRMSELIN SDA
A2 SCL
A1
A0
ADRMSELIN
ADRMSEL
GNDA
VCOREA
VINR0
3VIN
+12VIN
-12VIN
VBAT/-12VOUT
5VSB/-5VOUT
-5VIN
GNDA
BEEP/GPO#
VID3 VID1
U1
W83782D
VREF
37
VTIN3/PIITD3
38
VTIN2/PIITD2
39
VTIN1/PIITD1
40
VID0
41
OVT#
42
ADRMSEL
43
SMI#
44
SA2/IA2
45
SA1/IA1
46
SA0/IA0
47
CS#
48
IOR# 1
IOW# 2
CLKIN 3
D7 4
D6 5
D5 6
D4 7
D3 8
D2 9
D1/PWMOUT4 10
D0/PWMOUT3 11
VID1 12
VCC 13
GNDD 14
MR 15
CASEOPEN# 16
VID4 17
FAN3IO/PWMOUT2 18
FAN2IO 19
FAN1IO 20
SCL 21
SDA 22
PWMOUT1 23
VID2 24
VID3
25
BEEP/GPO#
26
GNDA
27
-5VIN
28
5VSB
29
VBAT
30
-12VIN
31
+12VIN
32
AVCC
33
+3.3VIN
34
VINR0
35
VCOREA
36
R1 R
10K
R2 R
10K
R3 R
28K 1%
R4 R
10K 1%
LS1
SPEAKER
R5
R0
R6
R0
R7
R
4.7K
R8
R
4.7K
R9
R
4.7K
R10
R
4.7K
R11 R
10K
C1
CAP
10u
C2
CAP
0.1u
C3
CAP
10u
C4
CAP
0.1u
L1
INDUCTOR
FB
L2
INDUCTOR
FB
R12
R
10K
R13
R
10K
R14
R
10K
R15
R
10K
R16
R
10K
R18 R
56K 1%/782D
R19 R
56K 1%/782D
R20 R
120K 1%/782D
90.9K 1%/781D
R21 R
232K 1%/782D
210K 1%/781D
R22 R
0 /782D
R23 R
0 /782D
R24 R
0 /781D
R25 R
0 /781D
R26 R
0 /782D
R27 R
60.4K 1%/781D
R28 R
60.4K 1%/781D
R29 R
0/782D
R30 R
0/781D
Q1
NPN
3904/782D
R31
R
510/782D
R32
R
0/781D
R33
R
100
R34
R
10K/782D
R35
R
0/782D
R36 R
7.5K 1%/782D
R37 R
0/782D
R38 R
5.1K 1%/782D
SD[0..7]
CLKIN
IOW#
IOR#
GTLVOLT
3VCC
PIIVID4
PIIVID3
PIIVID2
PIIVID1
PIIVID0
VREF
SMCLK
SMDAT
FAN1IN
FAN2IN PWMOUT2
PWMOUT1
RESETDRV
CS#
THRM#
EXTSMI#
T1
T2
T3
CPUVCOA
GNDA
SA2
SA1
SA0
IA2
IA1
IA0
IRQ
RSTOUT#
FAN3IN
CASEOPEN#
W83782D/W83782G
- 56 -
0.3
W83781D-W83782D Application Circuit
Winbond Electronic Corp.
Custom
22Wednesday, July 22, 1998
Title
Size Document Number Rev
Date: Sheet of
+12V
+12V
+12V
VBAT
(for system)
(for cpu1)
(from PII CPU)
Temperature Sensing
(for system)
(for cpu2)
(for cpu2)
PWM Circuit for FAN speed control
Measuring temperature by either
thermistor or diode.
Choosing the more accurate measuring method
between the above is recommanded.
Case Open Circuits
These two inverters consume VBAT
RT1
THERMISTOR
10K 1%
T
RT2
THERMISTOR
10K 1%
T
C5
CAPACITOR
3300p
RT3
THERMISTOR
10K 1%
T
Q2
NPN
3904
C6
CAPACITOR
3300p
C7
CAPACITOR
3300p
Q3
NPN
3904
JP1
HEADER 3
1
2
3
JP2
HEADER 3
1
2
3
R39 R
10K 1%
R40 R
10K 1%
R41 R
10K 1%
D1
DIODE
1N4148 R45
R
4.7K
R46 R
27K R47
R
10K
D2
DIODE
1N4148 R48
R
4.7K
R49 R
27K R50
R
10K
JP3
HEADER 3
1
2
3
D3
DIODE
1N4148 R51
R
4.7K
R52 R
27K R53
R
10K
R54 R
510/782D
R55 R
510/782D
R56 R
1K/782D
R57 R
4.7K/782D
R58 R
1K/782D
R59 R
4.7K/782D
Q5
PNP
3906/782D
R60
R
0/781D
R61 R
0/782D
R62
R
0/781D
R63 R
0/782D
Q7
PNP
3906/782D
R42 R
30K 1%
R43 R
30K 1%
R44 R
30K 1%
C9
47u/782D
+
C8
47u/782D
+
S1
CASEOPEN SW
R64
R
0/782D
R65
R
0/782D
R66
R
0/781D
R67
R
2.2M/781D
R68
R
0/781D
R69
R
10K/781D
U2A
74HC14
/781D
1 2
U2B
74HC14
/781D
34
R70
R
0/781D
R17
R
10M/782D C10
CAP
1000p
/781D
Q6
MOSFET N
2N7002/782D
Q4
MOSFET N
2N7002/782D
VREF
T1
T2
T3 GNDA
GNDA
VREF
D+
D-
T2
GNDA
VREF
T3
GNDA
VREF
T1
FAN1IN
PWMOUT1
FAN2IN
PWMOUT2
FAN3IN
CASEOPEN#
CASEOPEN
W83782D/W83782G
Publication Release Date: April 14, 2005
- 57 - Revision 2.0
0.3
W83781D-W83782D Application Circuit
Winbond Electronic Corp.
B
33Thursday, July 23, 1998
Title
Size Document Number Rev
Date: Sheet of
Change CASEOPEN circuit for W83781D/782D co-layout.
Change 2N3904 in Fan Speed Control circuit to 2N7002.
Rev. Description
0.1 First published.
0.2
0.3
W83782D/W83782G
- 58 -
REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a.
All the version before 0.50 are for internal
use.
0.5 98/7 n.a. First publication.
0.55 99/4 P.40
Add the content of Diode Selection Register
Index 59h(Bank0)
0.55 99/4 P.42
Add the content of VBAT Monitor Control
Register Index 5Dh (Bank0)
1.0 02/4 n.a.
Change version and version on web site to
1.0
1.1 02/10 P.58 Verify ISA Bus RD Timing. (210=>330ns)
1.2 05/01 n.a. Lead-free package version
2.0 April 14, 2005 58 ADD Important Notice
W83782D/W83782G
Publication Release Date: April 14, 2005
- 59 - Revision 2.0
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property
or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
