uPD44164185F5-E30-EQ1 - NEC Electronics

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MOS I NTEGRATED CIRCUIT

µµ

44164085, 44164185, 44164365

18M- BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Docume nt No. M158 23E J 2V0D S0 0 (2n d edi ti on)

Date Published April 2002 NS CP(K)

Printed in Japan

PRELIMIN ARY DATA SHEET

The mark !

! shows major revised points.

Description

The

PD44164085 is a 2,097,152-word by 8-bit, the

PD44164185 is a 1,048,576-word by 18-bit and the

PD44164365

is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using

full CMOS six-transistor memory cell.

The

PD44164085,

PD44164185 and

PD44164365 integrates unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.

These products are suitable for applications which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with

s restart

• User programmable impedence output

• Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

2Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Ordering Information

Part number Cycle Clock Organization Core Supply I/O Package

Time Frequency (word x bit) Voltage Interf ace

ns MHz V

PD44164085F5-E30-EQ1 3. 0 333 2 M x 8-bit 1.8 ± 0.1 HSTL 165-pin PLASTIC

PD44164085F5-E33-EQ1 3. 3 300 FBGA (13 x 15)

PD44164085F5-E40-EQ1 4.0 250

PD44164085F5-E50-EQ1 5.0 200

PD44164085F5-E60-EQ1 6.0 167

PD44164185F5-E30-EQ1 3. 0 333 1 M x 18-bit

PD44164185F5-E33-EQ1 3.3 300

PD44164185F5-E40-EQ1 4.0 250

PD44164185F5-E50-EQ1 5.0 200

PD44164185F5-E60-EQ1 6.0 167

PD44164365F5-E30-EQ1 3. 0 333 512 K x 36-bit

PD44164365F5-E33-EQ1 3.3 300

PD44164365F5-E40-EQ1 4.0 250

PD44164365F5-E50-EQ1 5.0 200

PD44164365F5-E60-EQ1 6.0 167

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Pin Configurations (Marking Si de)

/××× indicates active low signal.

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

µµ

PD44164085F5-EQ1]

1234567891011

A/CQ V

SS A R, /W /NW1 /K NC /LD A VSS CQ

B NC NC NC A NC K /NW0 A NC NC Q3

CNC NC NC V

SS AAAV

SS NC NC D3

DNC D4 NC V

SS VSS VSS VSS VSS NC NC NC

ENC NC Q4 V

DDQV

SS VSS VSS VDDQNC D2 Q2

FNC NC NCV

DDQV

DD VSS VDD VDDQNC NC NC

GNC D5 Q5 V

DDQV

DD VSS VDD VDDQNC NC NC

H/DLL V

REF VDDQV

DDQV

DD VSS VDD VDDQV

DDQV

REF ZQ

JNC NC NCV

DDQV

DD VSS VDD VDDQNC Q1 D1

KNC NC NC V

DDQV

DD VSS VDD VDDQNC NC NC

LNC Q6 D6 V

DDQV

SS VSS VSS VDDQNC NC Q0

MNC NC NC V

SS VSS VSS VSS VSS NC NC D0

NNC D7 NC V

SS AAAV

SS NC NC NC

PNCNCQ7 A A C A A NCNCNC

RTDOTCKAAA/CAAATMSTDI

A : Address inputs TMS : IEEE 1149.1 Test input

D0 to D7 : Data inputs TDI : IEEE 1149.1 Test input

Q0 to Q7 : Data outputs TCK : IEEE 1149.1 Clock input

/LD : Synchronous load TDO : IEEE 1149.1 Test output

R, /W : Read Write input CQ, /CQ : Echo clock

/NW0, /NW1 : Nybble Write data select VREF : HSTL input reference input

K, /K : Input clock VDD : Power Supply

C, /C : Output clock VDDQ : Power Supply

ZQ : Output impedance matching VSS : Ground

/DLL : DLL disable NC : No connection

Remark Refer to Package Drawing for the index mark.

4Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

µµ

PD44164185F5-EQ1]

1234567891011

A/CQ V

SS NC R, /W /BW1 /K NC /LD A VSS CQ

B NC Q9 D9 A NC K /BW0 A NC NC Q8

CNC NC D10 V

SS AAAV

SS NC Q7 D8

DNC D11 Q10 V

SS VSS VSS VSS VSS NC NC D7

ENC NC Q11V

DDQV

SS VSS VSS VDDQNC D6 Q6

FNC Q12D12V

DDQV

DD VSS VDD VDDQNC NC Q5

GNC D13 Q13V

DDQV

DD VSS VDD VDDQNC NC D5

H/DLL V

REF VDDQV

DDQV

DD VSS VDD VDDQV

DDQV

REF ZQ

JNC NC D14V

DDQV

DD VSS VDD VDDQNC Q4 D4

KNC NC Q14V

DDQV

DD VSS VDD VDDQNC D3 Q3

LNC Q15D15V

DDQV

SS VSS VSS VDDQNC NC Q2

MNC NC D16 V

SS VSS VSS VSS VSS NC Q1 D2

NNC D17 Q16 V

SS AAAV

SS NC NC D1

PNCNCQ17AACAANCD0Q0

RTDOTCKAAA/CAAATMSTDI

A : Address inputs TMS : IEEE 1149.1 Test input

D0 to D17 : Data inputs TDI : IEEE 1149.1 Test input

Q0 to Q17 : Data outputs TCK : IEEE 1149.1 Clock input

/LD : Synchronous load TDO : IEEE 1149.1 Test output

R, /W : Read Write input CQ, /CQ : Echo clock

/BW0, /BW1 : Byte Write data select VREF : HSTL input reference input

K, /K : Input clock VDD : Power Supply

C, /C : Output clock VDDQ : Power Supply

ZQ : Output impedance matching VSS : Ground

/DLL : DLL disable NC : No connection

Remark Refer to Package Drawing for the index mark.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

µµ

PD44164365F5-EQ1]

1234567891011

A/CQ V

SS NC R, /W /BW2 /K /BW1 /LD NC VSS CQ

B Q27 Q18 D18 A /BW3 K /BW0 A D17 Q17 Q8

C D27 Q28 D19 VSS AAAV

SS D16 Q7 D8

D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

E Q29 D29 Q20 VDDQV

SS VSS VSS VDDQQ15 D6 Q6

F Q30 Q21 D21 VDDQV

DD VSS VDD VDDQD14 Q14 Q5

G D30 D22 Q22 VDDQV

DD VSS VDD VDDQQ13 D13 D5

H/DLL V

REF VDDQV

DDQV

DD VSS VDD VDDQV

DDQV

REF ZQ

J D31 Q31 D23 VDDQV

DD VSS VDD VDDQD12 Q4 D4

K Q32 D32 Q23 VDDQV

DD VSS VDD VDDQQ12 D3 Q3

L Q33 Q24 D24 VDDQV

SS VSS VSS VDDQD11 Q11 Q2

M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

N D34 D26 Q25 VSS AAAV

SS Q10 D9 D1

P Q35 D35 Q26 A A C A A Q9 D0 Q0

RTDOTCKAAA/CAAATMSTDI

A : Address inputs TMS : IEEE 1149.1 Test input

D0 to D35 : Data inputs TDI : IEEE 1149.1 Test input

Q0 to Q35 : Data outputs TCK : IEEE 1149.1 Clock input

/LD : Synchronous load TDO : IEEE 1149.1 Test output

R, /W : Read Write input CQ, /CQ : Echo clock

/BW0 to /BW3 : Byte Write data select VREF : HSTL input reference input

K, /K : Input clock VDD : Power Supply

C, /C : Output clock VDDQ : Power Supply

ZQ : Output impedance matching VSS : Ground

/DLL : DLL disable NC : No connection

Remark Refer to Package Drawing for the index mark.

6Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Pin Identification

Symbol Description

A Synchronous Address I nputs: These i nputs are registered and must meet the setup and hold times around the

rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address i nputs on fut ure

devices. All trans actions operate on a burst of two words (one clock period of bus activity). These inputs are

ignored when device is deselected.

/LD Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transact i ons operate on a burst of 2 data (one clock periods of

bus activit y).

R, /W Synchronous Read/W rite Input: When /LD is LOW, this input designates the access type (READ when /R, W is

HIGH, WRITE when /R, W is LOW) for the loaded address. /R, W must meet the setup and hold times around

the rising edge of K.

/NWx

/BWx Synchronous Byte W rites (Nybble Writes on x8): When LOW these inputs cause their respective byte or nybbl e

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Confi gurations

for signal t o data relationships.

K, /K Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous

inputs must meet setup and hol d times around the clock risi ng edges.

C, /C Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

C is used as the output timing reference for first output dat a. The risi ng edge of /C is used as the output

reference f or second output dat a. Ideally, /C is 180 degrees out of phas e with C. C and /C may be tied HIGH to

force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied

HIGH, C and /C must remain HIGH and not be toggled during device operation.

/DLL DLL Disable: When LOW, this input causes the DLL to be bypassed f or stable low frequency operat i on.

ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. Alternat el y, this pi n can be connect ed directl y t o VDDQ, which enables the minimum impedance mode.

This pin cannot be connected directly to GND or left unconnected.

TMS

TDI IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a referenc e voltage for t he input buffers.

D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the risi ng edges of K and /K

during WRITE operations. See Pin Configurations for ball site locat i on of individual signals .

x8 device uses D0-D7. Rem aining signal s are NC.

x18 device uses D0-D17. Rem ai ni ng signals are NC.

x36 device uses D0-D35.

NC signals are read in the JTAG scan chain as the logic level appli ed to the ball site.

CQ, /CQ Synchronous Echo Clock Outputs. The ris i ng edges of these outputs are tightl y m atched to the sync hronous

data outputs and can be used as a data valid indication. These signals run f reel y and do not stop when Q

tristates.

TDO IEEE 1149.1 Test Output: 1.8V I/O level.

Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K ris i ng edges

if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball sit e

locati on of individual signals .

x8 device uses Q0-Q7. Remainin g signals are NC.

x18 device uses Q0-Q17. Remaining signals are NC.

x36 device uses Q0-Q35.

NC signals are read in the JTAG scan chain as the logic l evel applied to the ball site.

VDD Power Supply: 1.8V nomi nal. See DC Characteris tics and Operating Conditions for range.

VDDQ Power Supply: Isol ated Output Buffer Supply. Nominally 1.5V. 1.8V is also permiss i bl e. S ee DC Characteristics

and Operating Conditi ons for range.

VSS Power Supply: Ground

NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level

applied to the ball sit es. These signals m ay be connect ed to ground to improve package heat dissipation.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Block Diagram

[

µµ

PD44164085]

R, /W

/NW0

/NW1

/LD

/K K

/LD

R, /W

ADDRESS 20

D0 - D7 Q0 - Q7

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 16

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C

K, /K

CQ,

/CQ

816 16 16 8

[

µµ

PD44164185]

R, /W

/BW0

/BW1

/LD

/K K

/LD

R, /W

ADDRESS 19

D0 - D17 Q0 - Q17

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 36

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C

K, /K

CQ,

/CQ

18 36 36 36 18

[

µµ

PD44164365]

R, /W

/BW0

/BW1

/LD

/K K

/LD

R, /W

ADDRESS 18

D0 - D35 Q0 - Q35

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 72

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C

K, /K

CQ,

/CQ

72 72 72 36

/BW2

/BW3

8Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Truth Table

Operation / LD R, /W CLK D or Q

WRITE cycle L L L → H Data in

Load address, input write data on two Input data D(A+0) D(A+1)

consecuti ve K and /K rising edge Input clock K(t+1) ↑/K(t+1) ↑

READ cycle L H L → H Dat a out

Load address, read data on two Output data Q(A+0) Q(A+1)

consecuti ve C and /C rising edge Output clock /C(t+1) ↑C(t+2) ↑

NOP (No operation) H X L → HHi-Z

STANDBY(Cl ock stopped) X X Stopped Previous st ate

Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Byte Write Operation

[

µµ

PD44164085]

Operation K /K /NW0 /NW1

Write D0-7 L → H –00

–L → H0 0

Write D0-3 L → H –01

–L → H0 1

Write D4-7 L → H –10

–L → H1 0

Write nothing L → H –11

–L → H1 1

Remark H : High level, L : Low level, → : rising edge.

[

µµ

PD44164185]

Operation K /K /BW0 /BW1

Write D0-17 L → H –00

–L → H0 0

Write D0-8 L → H –01

–L → H0 1

Write D9-17 L → H –10

–L → H1 0

Write nothing L → H –11

–L → H1 1

Remark H : High level, L : Low level, → : rising edge.

[

µµ

PD44164365]

Operation K /K /BW0 /BW1 /BW2 /BW3

Write D0-35 L → H –0000

–L → H0000

Write D0-8 L → H –0111

–L → H0111

Write D9-17 L → H –1011

–L → H1011

Write D18-26 L → H –1101

–L → H1101

Write D27-35 L → H –1110

–L → H1110

Write nothing L → H –1111

–L → H1111

Remark H : High level, L : Low level, → : rising edge.

10 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Bus Cycle State Diagram

READ DOUBLE

Count = Count + 2 WRITE DOUBLE

COUNT = Count + 2

Power UP

Write

NOP

Supply voltage provided

LOAD NEW

ADDRESS

Count = 0

NOP

Load, Count = 2

Read

Load, Count = 2

Load

NOP,

Count = 2

NOP,

Count = 2

Remark State machine control timing sequence is controlled by K.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply volt age VDD –0.5 +2.9 V

Output supply voltage VDDQ –0.5 VDD V

Input volt age VIN –0.5 VDD + 0.5 (2.9 V MAX.) V

Input / Output voltage VI/O –0.5 VDDQ + 0. 5 (2.9 V MAX.) V

Junction temperature Tj+125 °C

Storage temperature Tstg –55 +125 °C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (Tj = 20 to 110 °

°°

°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

Supply volt age VDD 1.7 1.9 V

Output supply voltage VDDQ1.4V

DD V

High level input voltage VIH VREF + 0.1 V DDQ + 0. 3 V 1

Low level input voltage VIL –0.3 VREF – 0.1 V 1

Clock input voltage VIN –0.3 VDDQ + 0.3 V 1

Reference voltage VREF 0.68 0.95 V

Note1 Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2

Undershoot: VIL (AC) ≥ – 0.5V for t ≤ TKHKH/2

Power-up: VIH ≤ VDDQ + 0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V for t ≤ 200 ms

During normal operation, VDDQ must not exceed VDD.

Control input signals may not have pulse widths less than TKHKL(MIN) or operate at cycle rates

less than TKHKH (MIN).

Capacitance (TA = 25 °

°°

°C, f = 1MHz)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Input capacitance CIN VIN = 0 V 4 5 pF

Input / Output capacitance CI/O VI/O = 0 V 6 7 pF

Clock Input capac itance Cclk Vclk = 0 V 5 6 pF

Remark These parameters are periodically sampled and not 100% tested.

12 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

DC Characteristics (Tj = 20 to 110°C, VDD = 1.8 ± 0.1 V)

Parameter Sym bol Test c onditi on MIN. TYP. MAX. Unit Note

x8, x1 8 x36

Input leakage current ILI –2 – +2

I/O leakage current ILO –2 – +2

Operating suppl y current IDD VIN ≤ VIL or VIN ≥ VIH, –E30 525 710 mA

(Read Write cycle) II/O = 0 mA –E 33 475 640

Cycle = MAX. –E40 400 545

–E50 330 445

–E60 280 380

Standby supply current ISB1 VIN ≤ VIL or VIN ≥ VIH, –E30 255 265 mA

(NOP) II/O = 0 mA –E33 235 240

Cycle = MAX. –E40 200 210

–E50 170 180

–E60 150 160

High level output voltage VOH(Low) |IOH| ≤ 0.1 mA VDDQ – 0.2 – VDDQV3, 4

VOH Note1 VDDQ/2–0.08 – VDDQ/ 2+0.08 V 3, 4

Low level output volt age VOL(Low) IOL ≤ 0.1 mA VSS –0.2V3, 4

VOL Note2 VDDQ/2–0.08 – VDDQ/ 2+0.08 V 3, 4

Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impeda nce-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values. AC I/O curves are available upon request.

4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

AC Characteristics (Tj = 20 °

°°

°C to 110 °

°°

°C, VDD = 1.8 ± 0.1 V)

AC Test Conditions

Input waveform (Rise / Fall time ≤

≤≤

≤ 0.3 ns)

0.75 V 0.75 V

Test Points

1.25 V

0.25 V

Output waveform

Q / 2 V

Q / 2

Test Points

Output load condition

Figure 1. External load at test

Q / 2

0.75 V 50 Ω

= 50 Ω

250 Ω

SRAM

REF

Remark CL includes capacitances of the probe and jig, and stray capacitances.

14 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Read and Write Cycle

Parameter Symbol -E30 -E33 -E40 -E50 -E60 Unit Note

(333 MHz) (300 MHz) (250 MHz) (200 MHz) (167 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Average Clock cycle time (K, /K, C, /C) TKHKH 3.0 3.6 3.3 4.0 4.0 5.0 5.0 6.0 6.0 7.5 ns 1

Clock phas e jitt er (K, /K, C, /C) TK C var – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 ns 2

Clock HIGH time (K, /K, C, /C) TKHKL 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns

Clock LOW time (K, /K, C, /C) TKLKH 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns

Clock to /clock (K→/K., C→/C.) TKH /KH 1.35 – 1.49 – 1.8 – 2.2 – 2.7 – ns

Clock to /clock (/K→K., /C→C. ) T /KHKH 1.35 – 1.49 – 1.8 – 2.2 – 2.7 – ns

Clock to data cl ock (K→C., /K→/C.) TKHCH 0 1.30 0 1.45 0 1.8 0 2.3 0 2.8 ns

DLL lock time (K, C) TKC lock 1,024 – 1,024 – 1,024 – 1,024 – 1,024 – Cycle 3

K static to DLL reset TKC reset 30 – 30 – 30 – 30 – 30 – ns

Output Times

C, /C HIGH to output valid TCHQV –0.27–0.29–0.35–0.38–0.40

C, /C HIGH to output hold TCHQX – 0.27–– 0.29–– 0.35–– 0.38–– 0.40– ns

C, /C HIGH to echo clock valid TCHCQV –0.25–0.27–0.33–0.36–0.38

C, /C HIGH to echo clock hold TCHCQX – 0.25 –– 0.27–– 0.33–– 0.36–– 0.38– ns

CQ, /CQ HIGH to output valid TCQHQV –0.27–0.29–0.35–0.38–0.40

ns 4

CQ, /CQ HIGH to output hold TCQHQX – 0.27–– 0.29–– 0.35–– 0.38–– 0.40– ns 4

C HIGH to output High-Z TCHQZ –0.27–0.29–0.35–0.38–0.40

C HIGH to output Low-Z TCHQX1 – 0.27–– 0.29–– 0.35–– 0.38–– 0.40– ns

Setup Times

Address valid to K rising edge TAVKH 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns 5

Control inputs val i d to K rising edge TIVKH 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns 5

Data-in valid to K, /K rising edge TDVKH 0.3 – 0.33 – 0.4 – 0.5 – 0.6 – ns 5

Hold Times

K rising edge to address hold TKHAX 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns 5

K rising edge to control inputs hold TKHIX 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns 5

K, /K rising edge to data-in hold TKHDX 0.3 – 0.33 – 0.4 – 0.5 – 0.6 – ns 5

Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).

2. Clock phase jitter is the variance from clock rising edge to the next expected colck rising edge.

3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.

DLL lock time begins once VDD and input clock are stable.

It is recommended that the device is kept inactive during these cycles.

4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

5. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN).

4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.

5. VDDQ is 1.5 VDC.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Read and Write Timing

Address

Data in

246813 5 7

TKH/KH

TKHCH

NOP READ

(burst of 2) WRITE

(burst of 2)

TKHKL TKLKH

Q01 Q11

Data out

Q02 Q12

/LD

R, /W

TKHCH

TKHKL TKLKH TKH/KH T/KHKH

TKHKH

TCHQX1 TCHQX TCHQZ

D21 D31D22 D32

TDVKH TKHDX

TKHKH

TIVKH TKHIX

TAVKH TKHAX

/CQ

TCQHQV

TCHQV

TCHCQX

TCHCQV

TCHCQX

TCHCQV

READ

(burst of 2) READ

(burst of 2) NOP

Qx2 Q41 Q42

TCHQX

TCHQV

WRITE

(burst of 2)

A0 A1 A2 A3 A4

T/KHKH

Remarks 1. Q01 refers to output from address A0+0.

Q02 refers to output from the next internal burst address following A0, i.e., A0+1.

2. Outputs are disable (High-Z) one clock cycle after a NOP.

3. In this example, if address A3=A4, data Q41=D31, Q42=D32.

Write data is forwarded immediately as read results.

16 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

JT AG Specificatio n

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name Pin assignments Description

TCK 2R Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

TMS 10R Test Mode Select. This is the command input for the TAP controller state machine.

TDI 11R Test Data Input. This is the input side of the serial registers pl aced bet ween TDI and

TDO. The register placed between TDI and TDO is deter-m i ned by the st ate of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO 1R Test Data Output. Output changes in response to the falling edge of TCK. This is the

output side of the serial registers pl aced bet ween TDI and TDO.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (20 °

°°

°C ≤

≤≤

≤ Tj ≤

≤≤

≤ 110 °

°°

°C, 1.7 V ≤

≤≤

≤ VDD ≤

≤≤

≤ 1.9 V, unless otherwise noted)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD –5.0 – +5.0

JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ, –5.0 – +5.0

Outputs disabled

JTAG input high voltage VIH 1.3 – VDD+0.3 V

JTAG input low voltage VIL –0.3 – +0.5 V

JTAG output high voltage VOH1 | IOHC | = 100

A1.6––V

VOH2 | IOHT | = 2 mA 1.4 – – V

JTAG output low voltage V OL1 IOLC = 100

A––0.2V

VOL2 IOLT = 2 mA – – 0.4 V

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤

≤≤

≤ 1 ns)

0.9 V 0.9 V

Test Points

1.8 V

0 V

Output waveform

0.9 V 0.9 V

Test Points

Output load

Figure 2. External load at test

TDO Z

= 50 Ω

= 0.9 V

20 pF

50 Ω

18 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

JTAG AC Characteristics (Tj = 5 to 110 °

°°

°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Note

Clock

Clock cycle time tTHTH 100 – – ns

Clock frequency fTF ––10MHz

Clock high tim e tTHTL 40 – – ns

Clock low time tTLTH 40 – – ns

Output time

TCK low to TDO unknown tTLOX 0––ns

TCK low to TDO valid tTLOV – – 20 ns

TDI valid to TC K h ig h tDVTH 10 – – ns

TCK high to TDI invalid tTHDX 10 – – ns

Setup time

TMS setup time tMVTH 10 – – ns

Capture set up time tCS 10 – – ns

Hold time

TDI hold time tTHMX 10 – – ns

Capture hold time tCH 10 – – ns

JTAG Timing Diagram

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Scan Register Definition (1)

Instruc tion regi ster The instruction register hol ds the inst ructions that are executed by the TAP controller when it is

moved into the run-test/i dle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The ins truction register is automaticall y preloaded with the

IDCODE inst ruct i on at power-up whenever the controller is placed in test-logic-res et st ate.

Bypass regist er The bypass register is a single bit register that can be placed between TDI and TDO. It all ows s eri al

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controll er is put i n capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary regist er The boundary regi ster, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR st at e and then is placed between the TDI and

TDO pins when the controller is moved to shift -DR st ate. Several TAP instruct i ons can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects t o each boundary register

location. The first column defines the bit’s position in the boundary register. The shift register bit

nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the

input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Instructi on regis ter 3 bit

Bypass regist er 1 bit

ID register 32 bit

Boundary register 107 bit

ID Register Definition

Part number Organization I D [31:28] vendor revision no. I D [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit

PD44164085 2M x 8 XXXX 0000 0000 0001 1000 00000010000 1

PD44164185 1M x 18 XXXX 0000 0000 0001 1001 00000010000 1

PD44164365 512K x 36 XXXX 0000 0000 0001 1010 00000010000 1

20 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

SCAN Exit Order

Bit Signal name Bump Bit Signal nam e Bump Bit Signal name Bump

no. x8 x18 x36 ID no. x8 x18 x36 ID no. x8 x18 x36 ID

1 /C 6R 37 NC NC D15 10D 73 NC NC Q28 2C

2 C 6P 38 NC NC Q15 9E 74 Q4 Q11 Q20 3E

3 A 6N 39 NC Q7 Q7 10C 75 D4 D11 D20 2D

4 A 7P 40 NC D7 D7 11D 76 NC NC D29 2E

5 A 7N 41 NC NC D16 9C 77 NC NC Q29 1E

6 A 7R 42 NC NC Q16 9D 78 NC Q12 Q21 2F

7 A 8R 43 Q3 Q8 Q8 11B 79 NC D12 D21 3F

8 A 8P 44 D3 D8 D8 11C 80 NC NC D30 1G

9 A 9R 45 NC NC D17 9B 81 NC NC Q30 1F

10 NC Q0 Q0 11P 46 NC NC Q17 10B 82 Q5 Q13 Q22 3G

11 NC D0 D0 10P 47 CQ 11A 83 D5 D13 D22 2G

12 NC NC D9 10N 48 VSS 10A 84 NC NC D31 1J

13 NC NC Q9 9P 49 A A NC 9A 85 NC NC Q31 2J

14 NC Q1 Q1 10M 50 A 8B 86 NC Q14 Q23 3K

15 NC D1 D1 11N 51 A 7C 87 NC D14 D23 3J

16 NC NC D10 9M 52 A 6C 88 NC NC D32 2K

17 NC NC Q10 9N 53 /LD 8A 89 NC NC Q32 1K

18 Q0 Q2 Q2 11L 54 NC NC /BW1 7A 90 Q6 Q15 Q24 2L

19 D0 D2 D2 11M 55 /NW0 /BW0 /BW0 7B 91 D6 D15 D24 3L

20 NC NC D11 9L 56 K 6B 92 NC NC D33 1M

21 NC NC Q11 10L 57 /K 6A 93 NC NC Q33 1L

22 NC Q3 Q3 11K 58 NC NC /BW3 5B 94 NC Q16 Q25 3N

23 NC D3 D3 10K 59 /NW1 /BW1 /BW2 5A 95 NC D16 D25 3M

24 NC NC D12 9J 60 R, /W 4A 96 NC NC D34 1N

25 NC NC Q12 9K 61 A 5C 97 NC NC Q34 2M

26 Q1 Q4 Q4 10J 62 A 4B 98 Q7 Q17 Q26 3P

27 D1 D4 D4 11J 63 A NC NC 3A 99 D7 D17 D26 2N

28 ZQ 11H 64 VSS 2A 100 NC NC D35 2P

29 NC NC D13 10G 65 /CQ 1A 101 NC NC Q35 1P

30 NC NC Q13 9G 66 NC Q9 Q18 2B 102 A 3R

31 NC Q5 Q5 11F 67 NC D9 D18 3B 103 A 4R

32 NC D5 D5 11G 68 NC NC D27 1C 104 A 4P

33 NC NC D14 9F 69 NC NC Q27 1B 105 A 5P

34 NC NC Q14 10F 70 NC Q10 Q19 3D 106 A 5N

35 Q2 Q6 Q6 11E 71 NC D10 D19 3C 107 A 5R

36 D2 D6 D6 10E 72 NC NC D28 1D

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

JTAG Instructions

Instructions Description

EXTEST EXTEST is an IEEE 1149.1 mandatory public instructi on. It is to be executed whenever the inst ruction

in this device. Therefore this devi ce is not 1149.1 compliant. Nevertheless, this RA Ms TAP does

respond to an all zeros inst ruct i on, as follows. Wit h the EXTEST (000) instruct i on l oaded in the

instruction register the RAM responds just as it does in respons e to the SAMPLE instruc ti on, except the

RAM output are forced to Hi-Z any time the instruct i on is loaded.

IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruct i on is the default inst ruction l oaded i n at power up and any time the controller is placed

in the test-l ogic-reset state.

BYPASS The BYPASS instruction is loaded in the instruction regis t er when the bypass regist er is pl aced between

TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the

board level scan pat h to be shortened to facil ita t e test i ng of other devices in the scan path.

SAMPLE SAMP LE is a Standard 1149.1 mandatory publ i c instruction. When the SAMPLE instruction is loaded in

the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs

input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from

the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input

buffers are in trans iti on (i.e., i n a metastable stat e). Alt hough allowing the TAP to SAMPLE metast abl e

input will not harm the device, repeatable results cannot be expected. RAM input s ignals must be

stabilized f or l ong enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The

RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring

contents int o the boundary sc an regis ter. Moving the controller to shift-DR state then places the

boundary scan regist er between the TDI and TDO pins. This functionalit y is not Standard 1149.1

compliant.

SAMPLE-Z I f the SAMPLE-Z instruction is loaded in the instructi on regis t er, al l RAM outputs are forc ed to an inactive

drive state (Hi-Z) and the boundary regist er is connect ed between TDI and TDO when the TAP control l er

is moved to the shift-DR state.

JTAG Instruction Coding

IR2 IR1 IR0 Instruction Note

000 EXTEST 1

0 0 1 IDCODE

0 1 0 SAMPLE-Z 1

0 1 1 RESERVED

1 0 0 SAMPLE

1 0 1 RESERVED

1 1 0 RESERVED

1 1 1 BYPASS

Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.

22 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

TAP Controller State Diagram

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs.

TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and

may be left unconnected. But they may also be tied to VDD through a 1k resistor.

TDO should be left unconnected.

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Test Logic Operation (Instruction Scan)

TCK

Controller

state

TDI

TMS

TDO

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Shift-IR

Exit1-IR

Update-IR

Run-Test/Idle

IDCODE

Instruction

Output Inactive Output from Instruction Register Output from Instruction Register

24 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Test Logic Operation (Data Scan)

TCK

Controller

state

TDI

TMS

TDO

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Shift-DR

Exit1-DR

Update-DR

Test-Logic-Reset

Instruction

Output Inactive

Output from Instruction Register Output from Instruction Register

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Package Draw in g

y1 S

A B

A2 A

INDEX MARK

ZD ZE

RPNMLKJHGFEDCBA

ITEM MILLIMETERS

13.00

15.00

1.50

0.50

1.00

0.60

1.40

0.40

1.00

0.45

0.08

0.15

0.20

This package drawing is a preliminary version. It may be changed in the future.

165-PIN PLASTIC FBGA (13x15)

26 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

PD44164085F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

PD44164185F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

PD44164365F5-EQ1: 165-pin PLASTIC FBGA (13 x 15)

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

Revision History

Edition/ Page Type of Location Description

Date This Previous revisi on (Previous edi tion → This edition)

edition edition

2nd edition/ Throughout Throughout Modificat i on Pi n Configurations, Pin Identification, Addres s i nputs : Ax → A

April 2002 Scan Exit Order

p.1 p.1 Modifi cation Function Name 18M-BIT CMOS SYNCHRONOUS

FAST SRAM DOUBLE DATA RATE

→ 18M-BIT DDRII SRAM

Addition Description

PD44164365

p.2 p.2 Modification Ordering Information Package code: Fx-EQx → F5-EQ1

Deletion Remark

p.3-5 p. 3-5 Modification Pin Configurations Package code: Fx → F5-EQ1

p.6 p.6 Modification Pin Identification ZQ: VDD → VDDQ

D0 to Dxx: K# → /K

p.14 p.14 Modificati on TKC var (MAX.) -E30: 0.08 → 0.2, -E33: 0.08 → 0.2,

-E40: 0.10 → 0.2, -E50: 0.13 → 0.2,

-E60: 0.15 → 0.2

TKH /KH (MAX.) -E30: 1.65 → −, -E33: 1. 82 → −,

-E40: 2.2 → −, -E50: 2.75 → −,

-E60: 3.3 → −

Addition T /KHKH

Modification TAVKH, TIVKH, TKHAX, TKHIX (MIN.) -E40: 0.4 → 0.5

TDVKH, TKHDX (MIN.) -E30: 0.4 → 0.3, -E33: 0.4 → 0.33,

-E50: 0.6 → 0.5, -E60: 0.7 → 0.6

Addition Note 1, 2, 4

Modificat i on Note 1 → 5, Note 2 → 3

Modificat i on Note 3

Addition Remark 5

p.15 p.15 Addition Read and Write Timing T/KHKH

p.20 p.20 Modificati on Scan Exit Order Bit no. 48, 64: NC → VSS

p.25 p.25 Addition Package Drawing Package drawing (Prel iminary version)

p.26 p.26 Modificati on Types of S urfac e Mount Devices P ackage code: Fx → F5-EQ1

28 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

[MEMO]

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

[MEMO]

30 Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

[MEMO]

Preliminary Data Sheet M15823EJ2V0DS

µµ

PD44164085, 44164185, 44164365

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µµ

PD44164085, 44164185, 44164365

M8E 00. 4

The information in this document is current as of April, 2002. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data

books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products

and/or types are available in every country. Please check with an NEC sales representative for

availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

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patents, copyrights or other intellectual property rights of NEC or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

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(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

•