True 18-Bit, Voltage Output DAC 0.5 LSB INL, 0.5 LSB DNL AD5781 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VREFPF VREFPS VDD VCC AD5781 IOVCC A1 R1 RFB RFB INV SDIN INPUT SHIFT REGISTER AND CONTROL LOGIC SCLK SYNC SDO 18 DAC REG 18 18-BIT DAC VOUT 6k LDAC CLR POWER-ON-RESET AND CLEAR LOGIC RESET APPLICATIONS 6.8k 6.8k DGND VSS AGND VREFNF VREFNS 09092-001 Single 18-bit DAC, 0.5 LSB INL 7.5 nV/Hz noise spectral density 0.05 LSB long-term linearity stability <0.05 ppm/C temperature drift 1 s settling time 1.4 nV-sec glitch impulse Operating temperature range: -40C to +125C 20-lead TSSOP package Wide power supply range of up to 16.5 V 35 MHz Schmitt triggered digital interface 1.8 V compatible digital interface Figure 1. Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION The AD57811 is a single 18-bit, unbuffered voltage output digitalto-analog converter (DAC) that operates from a bipolar supply of up to 33 V. The AD5781 accepts a positive reference input range of 5 V to VDD - 2.5 V and a negative reference input range of VSS + 2.5 V to 0 V. The AD5781 offers a relative accuracy specification of 0.5 LSB maximum, and operation is guaranteed monotonic with a 0.5 LSB differential nonlinearity (DNL) maximum specification. The part uses a versatile 3-wire serial interface that operates at clock rates of up to 35 MHz and is compatible with standard serial peripheral interface (SPI), QSPITM, MICROWIRETM, and DSP interface standards. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V and in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state. 1 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. True 18-Bit Accuracy. Wide Power Supply Range of Up to 16.5 V. -40C to +125C Operating Temperature Range. Low 7.5 nV/Hz Noise. Low 0.05 ppm/C Temperature Drift. Table 1. Complementary Devices Part No. AD8675 AD8676 ADA4898-1 Description Ultraprecision, 36 V, 2.8 nV/Hz rail-to-rail output op amp Ultraprecision, 36 V, 2.8 nV/Hz dual rail-torail output op amp High voltage, low noise, low distortion, unity gain stable, high speed op amp Table 2. Related Devices Part No. AD5791 AD5541A/AD5542A Description 20-bit, 1 ppm accurate DAC 16-bit, 1 LSB accurate 5 V DAC Protected by U.S. Patent No 7,884,747, and other patents are pending. Rev. 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Technical Support www.analog.com AD5781 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Control Pins .............................................................. 20 Applications ....................................................................................... 1 On-Chip Registers ...................................................................... 21 Functional Block Diagram .............................................................. 1 AD5781 Features ............................................................................ 24 General Description ......................................................................... 1 Power-On to 0 V......................................................................... 24 Product Highlights ........................................................................... 1 Power-Up Sequence ................................................................... 24 Revision History ............................................................................... 2 Configuring the AD5781 .......................................................... 24 Specifications..................................................................................... 3 DAC Output State ...................................................................... 24 Timing Characteristics ................................................................ 5 Linearity Compensation ............................................................ 24 Absolute Maximum Ratings............................................................ 7 Output Amplifier Configuration.............................................. 24 ESD Caution .................................................................................. 7 Applications Information .............................................................. 26 Pin Configuration and Function Description .............................. 8 Typical Operating Circuit ......................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 19 REVISION HISTORY 4/2018--Rev. D to Rev. E Added Power-Up Sequence Section and Figure 50; Renumbered Sequentially ..................................................................................... 24 7/2013--Rev. C to Rev. D Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5 Deleted Figure 4 ................................................................................ 7 Deleted Daisy-Chain Operation Section ..................................... 20 11/2011--Rev. B to Rev. C Added Figure 48; Renumbered Sequentially .............................. 17 Change to Ideal Transfer Function Equation.............................. 22 8/2011--Rev. 0 to Rev. A Change to Features Section ..............................................................1 Changes to Specifications Section ...................................................3 Deleted t14 Parameter from Timing Specifications Section, Table 4 .................................................................................................5 Changes to Figure 2 and Figure 3 ....................................................6 Changes to Figure 4 ...........................................................................7 Replaced Figure 42 and Figure 43 ................................................ 16 Added New Figure 44, Figure 45, and Figure 46, Renumbered Sequentially ..................................................................................... 16 7/2010--Revision 0: Initial Version 9/2011--Rev. A to Rev. B Added Patent Note ........................................................................... 1 Changes to Table 3 ............................................................................ 3 Changes to OPGND Description, Table 12 ................................ 23 Rev. E | Page 2 of 27 Data Sheet AD5781 SPECIFICATIONS VDD = +12.5 V to +16.5 V, VSS = -16.5 V to -12.5 V, VREFP = +10 V, VREFN = -10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 3. Parameter STATIC PERFORMANCE 2 Resolution Integral Nonlinearity Error (Relative Accuracy) Differential Nonlinearity Error Min 18 -0.5 -0.5 -1 -4 -0.5 -0.5 -1 Linearity Error Long-Term Stability 5 Full-Scale Error -1.75 -2.75 -5.25 -1 -1 -1.5 Full-Scale Error Temperature Coefficient3 Zero-Scale Error -1.75 -2.5 -5.25 -1 -1 -1.5 Zero-Scale Error Temperature Coefficient3 Gain Error Gain Error Temperature Coefficient3 R1, RFB Matching OUTPUT CHARACTERISTICS3 Output Voltage Range Output Slew Rate Output Voltage Settling Time Output Noise Spectral Density Output Voltage Noise -6 -10 -20 A, B Version 1 Typ Max 0.25 +0.5 0.25 0.5 2 0.25 0.25 0.5 0.04 0.05 0.03 0.25 0.062 0.2 0.25 +0.5 +1 +4 +0.5 +0.5 +1 +1.75 +2.75 +5.25 +1 0.062 0.2 0.02 0.025 0.38 0.19 0.025 +1 +1.5 0.38 0.19 0.04 0.3 0.4 0.4 0.04 0.01 +1 +1.5 VREFN +1.75 +2.5 +5.25 +1 +6 +10 +20 VREFP Unit Test Conditions/Comments Bits LSB B version, VREFP = +10 V, VREFN = -10 V LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm FSR/C LSB LSB LSB LSB LSB LSB ppm FSR/C ppm FSR ppm FSR ppm FSR ppm FSR/C % 50 1 V V/s s 1 7.5 7.5 7.5 1.1 s nV/Hz nV/Hz nV/Hz V p-p Rev. E | Page 3 of 27 B version, VREFP = +10 V, VREFN = 0 V 3 B version, VREFP = +5 V, VREFN = 0 V3 A version 4 VREFP = +10 V, VREFN = -10 V VREFP = +10 V, VREFN = 0 V3 VREFP = +5 V, VREFN = 0 V3 After 500 hours at TA = 125C After 1000 hours at TA = 125C After 1000 hours t TA = 100C VREFP = +10 V, VREFN = -10 V3 VREFP = +10 V, VREFN = 0 V3 VREFP = +5 V, VREFN = 0 V3 VREFP = +10 V, VREFN = -10 V3, TA = 0C to 105C VREFP = 10 V, VREFN = 0 V3, TA = 0C to 105C VREFP = 5 V, VREFN = 0 V3, TA = 0C to 105C VREFP = +10 V, VREFN = -10 V3 VREFP = +10 V, VREFN = 0 V3 VREFP = +5 V, VREFN = 0 V3 VREFP = +10 V, VREFN = -10 V3, TA = 0C to 105C VREFP = 10 V, VREFN = 0 V3, TA = 0C to 105C VREFP = 5 V, VREFN = 0 V3, TA = 0C to 105C VREFP = +10 V, VREFN = -10 V3 VREFP = +10 V, VREFN = 0 V3 VREFP = +5 V, VREFN = 0 V3 Unbuffered output, 10 M||20 pF load 10 V step to 0.02%, using AD845 buffer in unity-gain mode 125 code step to 1 LSB6 at 1 kHz, DAC code = midscale at 10 kHz, DAC code = midscale at 100 kHz, DAC code = midscale DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 7 AD5781 Parameter Midscale Glitch Impulse Data Sheet Min MSB Segment Glitch Impulse6 Output Enabled Glitch Impulse Digital Feedthrough DC Output Impedance (Normal Mode) DC Output Impedance (Output Clamped to Ground) Spurious Free Dynamic Range Total Harmonic Distortion REFERENCE INPUTS3 VREFP Input Range VREFN Input Range DC Input Impedance Input Capacitance LOGIC INPUTS3 Input Current 8 Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC OUTPUT (SDO)3 Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS VDD VSS VCC IOVCC IDD ISS ICC IOICC DC Power Supply Rejection Ratio3, 9 AC Power Supply Rejection Ratio3 A, B Version 1 Typ Max 3.1 1.7 1.4 9.1 3.6 1.9 45 0.4 3.4 6 100 97 5 VSS + 2.5 V 5 VDD - 2.5 V 0 Unit nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec k k Test Conditions/Comments VREFP = +10 V, VREFN = -10 V VREFP = +10 V, VREFN = 0 V VREFP = +5 V, VREFN = 0 V VREFP = +10 V, VREFN = -10 V, see Figure 42 VREFP = 10 V, VREFN = 0 V, see Figure 43 VREFP = 5 V, VREFN = 0 V, see Figure 44 On removal of output ground clamp dB dB 1 kHz tone, 10 kHz sample rate 1 kHz tone, 10 kHz sample rate V 6.6 k 15 pF -1 +1 0.3 x IOVCC A V V pF 0.4 V 1 A pF VSS + 33 -2.5 5.5 5.5 5.2 4.9 900 140 V V V V mA mA A A V/V V/V dB dB 0.7 x IOVCC 5 IOVCC - 0.5 V 3 VREFP, VREFN, code dependent, typical at midscale code VREFP, VREFN IOVCC = 1.71 V to 5.5 V IOVCC = 1.71 V to 5.5 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA IOVCC = 1.71 V to 5.5 V, sourcing 1 mA All digital inputs at DGND or IOVCC 7.5 VDD - 33 2.7 1.71 4.2 4 600 52 0.6 0.6 95 95 IOVCC VCC SDO disabled VDD 10%, VSS = 15 V VSS 10%, VDD = 15 V VDD 200 mV, 50 Hz/60 Hz, VSS = -15 V VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V Temperature range: -40C to +125C, typical conditions: TA = 25C, VDD = +15 V, VSS = -15 V, VREFP = +10 V, VREFN = -10 V. Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 Valid for all voltage reference spans. 5 Guaranteed by design and characterization, not production tested. 6 The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 , C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 7 Includes noise contribution from AD8676BRZ voltage reference buffers. 8 Current flowing in an individual logic pin. 9 Includes PSRR of AD8676BRZ voltage reference buffers. 1 2 Rev. E | Page 4 of 27 Data Sheet AD5781 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 1 2 Limit 1 IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V 40 28 92 60 15 10 9 5 5 5 2 2 48 40 8 6 9 7 12 7 13 10 20 16 14 11 130 130 130 130 50 50 140 140 0 0 65 60 62 45 0 0 35 35 150 150 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns min ns typ ns min ns max ns max ns min ns typ ns typ Test Conditions/Comments SCLK cycle time SCLK cycle time (readback mode) SCLK high time SCLK low time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge hold time Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignore Data setup time Data hold time LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low LDAC falling edge to output response time SYNC rising edge to output response time (LDAC tied low) CLR pulse width low CLR pulse activation time SYNC falling edge to first SCLK rising edge SYNC rising edge to SDO tristate (CL = 50 pF) SCLK rising edge to SDO valid (CL = 50 pF) SYNC rising edge to SCLK rising edge ignore RESET pulse width low RESET pulse activation time All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode. Rev. E | Page 5 of 27 AD5781 Data Sheet t7 t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t9 t8 SDIN DB23 DB0 t10 t12 t11 LDAC t13 VOUT t14 VOUT t15 CLR t16 VOUT t21 RESET 09092-002 t22 VOUT Figure 2. Write Mode Timing Diagram t1 t17 SCLK 1 2 24 t3 t6 t20 t7 1 2 24 t2 t5 t4 t5 t17 SYNC SDIN t9 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION t18 t19 DB23 SDO REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. E | Page 6 of 27 DB0 09092-003 t8 Data Sheet AD5781 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to AGND VSS to AGND VDD to VSS VCC to DGND IOVCC to DGND Digital Inputs to DGND VOUT to AGND VREFPF to AGND VREFPS to AGND VREFNF to AGND VREFNS to AGND DGND to AGND Operating Temperature Range, TA Industrial Storage Temperature Range Maximum Junction Temperature, TJ max Power Dissipation TSSOP Package JA Thermal Impedance JC Thermal Impedance Lead Temperature Soldering ESD (Human Body Model) Rating -0.3 V to +34 V -34 V to +0.3 V -0.3 V to +34 V -0.3 V to +7 V -0.3 V to VCC + 3 V or +7 V (whichever is less) -0.3 V to IOVCC + 0.3 V or +7 V (whichever is less) -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V VSS - 0.3 V to +0.3 V VSS - 0.3 V to +0.3 V -0.3 V to +0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance integrated circuit with an ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION -40C to + 125C -65C to +150C 150C (TJ max - TA)/JA 143C/W 45C/W JEDEC industry standard J-STD-020 1.5 kV Rev. E | Page 7 of 27 AD5781 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTION INV 1 20 RFB VOUT 2 19 VREFPS 3 18 VSS VREFPF 4 17 VREFNS VDD 5 RESET 6 15 DGND CLR 7 14 SYNC LDAC 8 13 SCLK VCC 9 12 SDIN IOVCC 10 11 SDO AD5781 AGND 09092-005 TOP VIEW (Not to Scale) 16 VREFNF Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 Mnemonic INV VOUT VREFPS 4 VREFPF 5 VDD 6 7 RESET CLR 8 LDAC 9 10 VCC IOVCC 11 12 SDO SDIN 13 SCLK 14 SYNC 15 16 DGND VREFNF 17 VREFNS 18 VSS 19 20 AGND RFB Description Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details. Analog Output Voltage. Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD - 2.5 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFPF pin. See the AD5781 Features section for further details. Positive Reference Force Voltage Input. A voltage range of 5 V to VDD - 2.5 V can be connected. A unity gain amplifier must be connected at these pin, in conjunction with the VREFPS pin. See AD5781 Features section for further details. Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. VDD should be decoupled to AGND. Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status. Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin should not be left unconnected. Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND. Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of 1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC. Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input. Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock rates of up to 35 MHz. Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The input shift register is updated on the rising edge of SYNC. Ground Reference Pin for Digital Circuitry. Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier must be connected at this pin, in conjunction with the VREFNS pin. See the AD5781 Features section for further details. Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier must be connected at these pin, in conjunction with the VREFNF pin. See the AD5781 Features section for further details. Negative Analog Supply Connection. A voltage range of -16.5 V to -2.5 V can be connected. VSS should be decoupled to AGND. Ground Reference Pin for Analog Circuitry. Feedback Connection for External Amplifier. See the AD5781 Features section for further details. Rev. E | Page 8 of 27 Data Sheet AD5781 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 TA = +125C TA = +25C TA = -40C 0.3 0.2 0.2 INL ERROR (LSB) 0.3 0.1 0 -0.1 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +10V VREFN = -10V VDD = +15V VSS = -15V -0.3 -0.4 50000 100000 150000 DAC CODE -0.1 -0.4 200000 250000 -0.5 0 50000 100000 150000 DAC CODE 200000 250000 Figure 8. Integral Nonlinearity Error vs. DAC Code, 10 V Span, X2 Gain Mode 0.5 0.5 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER TA = +125C TA = +25C TA = -40C 0.3 0.2 0.2 DNL ERROR (LSB) 0.3 0.1 0 -0.1 -0.2 VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 50000 0 -0.1 -0.2 -0.4 -0.5 0 0.1 100000 150000 DAC CODE 200000 250000 -0.5 0 Figure 6. Integral Nonlinearity Error vs. DAC Code, +10 V Span 200000 250000 0.5 TA = +125C TA = +25C TA = -40C AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 0.4 0.3 0.4 0.2 DNL ERROR (LSB) 0.6 0.2 0 -0.2 TA = +125C TA = +25C TA = -40C 0.1 0 -0.1 -0.2 -0.3 -0.4 200000 250000 -0.5 09092-008 -0.4 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.6 VREFP = +5V VREFN = 0V -0.8 VDD = +15V VSS = -15V -1.0 0 50000 100000 150000 DAC CODE 100000 150000 DAC CODE Figure 9. Differential Nonlinearity Error vs. DAC Code, 10 V Span 1.0 0.8 50000 09092-010 -0.4 TA = +125C TA = +25C TA = -40C -0.3 09092-007 -0.3 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +10V VREFN = -10V VDD = +15V VSS = -15V 0.4 0 Figure 7. Integral Nonlinearity Error vs. DAC Code, +5 V Span 50000 100000 150000 DAC CODE 200000 250000 09092-011 0.4 INL ERROR (LSB) 0 -0.3 Figure 5. Integral Nonlinearity Error vs. DAC Code, 10 V Span INL ERROR (LSB) 0.1 -0.2 -0.5 0 TA = +25C TA = -40C TA = +125C 09092-009 -0.2 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 0.4 09092-006 INL ERROR (LSB) 0.4 Figure 10. Differential Nonlinearity Error vs. DAC Code, +10 V Span Rev. E | Page 9 of 27 AD5781 0.5 Data Sheet AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +5V VREFN = 0V 0.4 0.3 0.3 TA = +125C TA = +25C TA = -40C 0.2 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VDD = +15V VSS = -15V DNL ERROR (LSB) DNL ERROR (LSB) 0.1 0.2 0.1 0 -0.1 -0.2 0 -0.1 -0.2 -0.3 -0.3 100000 150000 DAC CODE 200000 250000 -0.5 -55 Figure 11. Differential Nonlinearity Error vs. DAC Code, +5 V Span 85 105 125 0.10 0 -0.1 0.04 0.02 -0.2 0 -0.3 -0.02 -0.4 -0.04 -0.5 50000 100000 150000 DAC CODE 200000 250000 TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.06 INL MIN -0.06 12.5 Figure 12. Differential Nonlinearity Error vs. DAC Code, 10 V Span, X2 Gain Mode 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 09092-016 0.1 0 INL MAX 0.08 INL ERROR (LSB) 0.2 0.12 09092-013 16.5 Figure 15. Integral Nonlinearity Error vs. Supply Voltage, 10 V Span 0.5 0.4 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VDD = +15V VSS = -15V 0.3 INL MAX 0.2 INL ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 0.1 0 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.1 -0.3 -0.5 -55 -35 -15 +10V SPAN MAX INL 10V SPAN MIN INL +5V SPAN MIN INL 5 25 45 65 TEMPERATURE (C) 85 -0.2 INL MIN 105 125 09092-014 10V SPAN MAX INL +5V SPAN MAX INL +10V SPAN MIN INL -0.4 Figure 13. Integral Nonlinearity Error vs. Temperature -0.3 7.5 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) 09092-017 DNL ERROR (LSB) 0.3 INL ERROR (LSB) 5 25 45 65 TEMPERATURE (C) 0.14 TA = +25C TA = -40C TA = +125C AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 0.4 0.3 -15 Figure 14. Differential Nonlinearity Error vs. Temperature 0.5 0.4 -35 +10V SPAN MAX DNL 10V SPAN MIN DNL +5V SPAN MIN DNL 09092-015 50000 09092-012 -0.5 0 10V SPAN MAX DNL +5V SPAN MAX DNL +10V SPAN MIN DNL -0.4 VDD = +15V VSS = -15V -0.4 Figure 16. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span Rev. E | Page 10 of 27 Data Sheet AD5781 0.14 0.08 0.06 ZERO-SCALE ERROR (LSB) TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.02 -0.04 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 09092-018 -0.08 12.5 0.04 0 7.5 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) Figure 20. Zero-Scale Error vs. Supply Voltage, +5 V Span Figure 17. Differential Nonlinearity Error vs. Supply Voltage, 10 V Span 0.05 0.10 0.04 0.05 MID-SCALE ERROR (LSB) DNL MAX 0 DNL ERROR (LSB) 0.06 0.02 DNL MIN -0.06 0.08 09092-021 0 0.10 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.05 -0.10 -0.15 DNL MIN -0.20 0.03 TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.02 0.01 0 -0.01 -0.02 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) -0.03 12.5 13.0 13.5 09092-019 -0.25 7.5 Figure 18. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 09092-022 DNL ERROR (LSB) 0.04 0.02 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.12 DNL MAX Figure 21. Midscale Error vs. Supply Voltage, 10 V Span 0.14 0.05 0.12 0.06 0.04 0.02 0 12.5 TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 Figure 19. Zero-Scale Error vs. Supply Voltage, 10 V Span -0.05 -0.10 -0.15 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.20 7.5 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) Figure 22. Midscale Error vs. Supply Voltage, +5 V Span Rev. E | Page 11 of 27 09092-023 MID-SCALE ERROR (LSB) 0.08 09092-020 ZERO-SCALE ERROR (LSB) 0 0.10 AD5781 Data Sheet -0.015 0.10 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.05 GAIN ERROR (ppm FSR) 0 -0.025 -0.030 -0.035 TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.045 12.5 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 16.0 16.5 -0.40 7.5 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) 09092-027 -0.040 09092-024 FULL-SCALE ERROR (LSB) -0.020 Figure 26. Gain Error vs. Supply Voltage, +5 V Span Figure 23. Full-Scale Error vs. Supply Voltage, 10 V Span 0.15 0.07 0.06 0.03 0.02 0.01 TA = 25C VREFP = +5V VREFN = 0V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0 -0.02 7.5 8.5 9.5 10.5 -2.5 -3.9 -5.3 -6.7 0.05 0 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.05 -0.10 11.5 12.5 13.5 14.5 15.5 16.5 VDD (V) -9.1 -10.5 -12.9 -14.2 -15.5 -16.5 VSS (V) -0.15 5.0 INL MIN 5.5 6.0 6.5 7.0 7.5 8.0 VREFP /|VREFN | (V) 8.5 9.0 9.5 10.0 09092-028 INL ERROR (LSB) 0.04 -0.01 Figure 27. Integral Nonlinearity Error vs. Reference Voltage Figure 24. Full-Scale Error vs. Supply Voltage, +5 V Span -0.30 0.10 TA = 25C VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.35 0.05 DNL ERROR (LSB) -0.40 DNL MAX -0.45 -0.50 0 -0.05 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.55 -0.10 -0.60 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 -0.15 5.0 5.5 6.0 6.5 7.0 7.5 8.0 VREFP /|VREFN | (V) 8.5 9.0 9.5 10.0 Figure 28. Differential Nonlinearity Error vs. Reference Voltage Figure 25. Gain Error vs. Supply Voltage, 10 V Span Rev. E | Page 12 of 27 09092-029 DNL MIN -0.65 12.5 09092-026 GAIN ERROR (ppm FSR) INL MAX 09092-025 FULL-SCALE ERROR (LSB) 0.10 0.05 Data Sheet AD5781 -0.30 0.16 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.14 GAIN ERROR (ppm FSR) ZERO-SCALE ERROR (LSB) -0.35 0.12 0.10 0.08 0.06 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.04 -0.40 -0.45 -0.50 -0.55 6.0 6.5 7.0 7.5 8.0 VREFP /|VREFN | (V) 8.5 9.0 9.5 10.0 -0.60 5.0 0.03 0.3 0.02 0.2 0.01 0 -0.01 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.02 -0.03 -0.04 5.5 6.0 6.5 7.0 7.5 8.0 VREFP /|VREFN | (V) 8.5 9.0 9.5 10.0 8.5 9.0 9.5 10.0 0 -0.1 -0.2 -0.3 -0.4 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VDD = +15V VSS = -15V VREFP = +10V VREFN = -15V -0.6 -55 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125 Figure 33. Full-Scale Error vs. Temperature 0.40 TA = 25C VDD = +15V VSS = -15V AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 0.02 0.01 0 -0.01 -0.02 0.30 0.25 0.20 0.15 0.10 0.05 6.0 6.5 7.0 7.5 8.0 VREFP /|VREFN | (V) 8.5 9.0 9.5 10.0 09092-032 -0.03 5.5 10V SPAN +10V SPAN 5V SPAN 0.35 MID-SCALE ERROR (LSB) 0.03 Figure 31. Full-Scale Error vs. Reference Voltage 0 -55 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VDD = +15V VSS = -15V VREFP = +10V VREFN = -15V -35 -15 5 25 45 65 TEMPERATURE (C) 85 Figure 34. Midscale Error vs. Temperature Rev. E | Page 13 of 27 105 125 09092-035 0.04 FULL-SCALE ERROR (LSB) 7.0 7.5 8.0 VREFP /|VREFN | (V) 10V SPAN +10V SPAN 5V SPAN Figure 30. Midscale Error vs. Reference Voltage -0.04 5.0 6.5 0.1 -0.5 09092-031 -0.05 5.0 6.0 Figure 32. Gain Error vs. Reference Voltage FULL-SCALE ERROR (LSB) MID-SCALE ERROR (LSB) Figure 29. Zero-Scale Error vs. Reference Voltage 5.5 09092-034 5.5 09092-030 0 5.0 09092-033 0.02 AD5781 Data Sheet 1.2 1.0 0.8 4 0.6 IDD, ISS (mA) 0.2 0 -0.2 AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER -0.4 VDD = +15V VSS = -15V -0.6 VREFP = +10V -0.8 VREFN = -15V -35 -15 -1 -3 ISS -4 5 25 45 65 TEMPERATURE (C) 4 GAIN ERROR (ppm FSR) 0 -2 85 105 125 -5 -20 -15 -10 -5 0 5 VDD, VSS (V) 10 15 20 Figure 38. Power Supply Currents vs. Power Supply Voltages Figure 35. Zero-Scale Error vs. Temperature 1 1 10V SPAN +10V SPAN +5V SPAN AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER VDD = +15V VSS = -15V VREFP = +10V VREFN = -15V 0 VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS OUTPUT UNBUFFERED LOAD = 10M||20pF 3 -1 -2 -4 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125 4 09092-037 -5 -55 CH3 5V Figure 36. Gain Error vs. Temperature 900 TA = 25C 800 700 200ns Figure 39. Rising Full-Scale Voltage Step IOVCC = 5V, LOGIC VOLTAGE INCREASING IOVCC = 5V, LOGIC VOLTAGE DECREASING IOVCC = 3V, LOGIC VOLTAGE INCREASING IOVCC = 3V, LOGIC VOLTAGE DECREASING VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V AD8676 REFERENCE BUFFERS OUTPUT UNBUFFERED LOAD = 10M||20pF 500 3 400 300 100 4 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5 6 CH3 5V Figure 37. IOICC vs. Logic Input Voltage CH4 5V 200ns Figure 40. Falling Full-Scale Voltage Step Rev. E | Page 14 of 27 09092-041 200 09092-038 IOICC (A) 600 CH4 5V 09092-040 -3 09092-039 -1.0 -55 2 IDD 2 0.4 3 TA = 25C 3 09092-036 ZERO-SCALE ERROR (LSBs) 5 10V SPAN +10V SPAN 5V SPAN Data Sheet AD5781 10.8 10.4 5V VREF OUTPUT GAIN OF 1 BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER 2.6 OUTPUT GLITCH (nV-sec) 10.6 10.2 10.0 9.8 9.6 2.2 NEGATIVE CODE CHANGE POSITIVE CODE CHANGE 1.8 1.4 1.0 0.6 0.2 2 3 4 5 TIME (s) -0.2 09092-061 1 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 0 09092-063 CODE Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF Figure 41. 125 Code Step Settling Time 10 8 5V VREF OUTPUT GAIN OF 1 BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER 40 NEGATIVE CODE CHANGE 7 20 6 5 10V VREF OUTPUT GAIN OF 1 BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER 30 VOUT (mV) OUTPUT GLITCH (nV-sec) 9 POSITIVE CODE CHANGE 4 10 0 3 2 CX = 143pF CX = 143pF CX = 143pF CX = 143pF -10 1 -20 -1.0 CODE 2.5 1.0 1.5 2.0 Figure 45. Midscale Peak-to-Peak Glitch for 10 V POSITIVE CODE CHANGE OUTPUT VOLTAGE (nV) 3.0 0.5 800 10V VREF OUTPUT GAIN OF 1 BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER NEGATIVE CODE CHANGE 2.0 1.5 1.0 TA = 25C VDD = +15V 600 VSS = -15V VREFP = +10V VREFN = -10V 400 MID-SCALE CODE LOADED OUTPUT UNBUFFERED AD8676 REFERENCE BUFFERS 200 0 -200 -400 0.5 -600 CODE 09092-060 0 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 OUTPUT GLITCH (nV-sec) 3.5 0 TIME (s) Figure 42. 6 MSB Segment Glitch Energy for 10 V VREF 4.0 -0.5 09092-059 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 0 + 0pF + 220pF + 470pF + 1,000pF 09092-062 9.4 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF Rev. E | Page 15 of 27 10 09092-044 VOUT (mV) 3.0 10V VREF OUTPUT GAIN OF 1 BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR RC LOW-PASS FILTER AD5781 Data Sheet 350 VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V CODE = MIDSCALE TA = 25C VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V AD8675 OUTPUT BUFFER OUTPUT VOLTAGE (mV) 300 10 250 200 150 100 50 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k -50 -1 0 1 2 3 TIME (s) 4 5 Figure 48. Glitch Impulse on Removal of Output Clamp Figure 47. Noise Spectral Density vs. Frequency Rev. E | Page 16 of 27 6 09092-049 0 09092-064 NSD (nV/ Hz) 100 Data Sheet AD5781 TERMINOLOGY Relative Accuracy Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. A typical DNL error vs. code plot is shown in Figure 9. Linearity Error Long-Term Stability Linearity error long-term stability is a measure of the stability of the linearity of the DAC over a long period of time. It is specified in LSB for a time period of 500 hours and 1000 hours at an elevated ambient temperature. Zero-Scale Error Zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the DAC register. Ideally, the output voltage should be VREFNS. Zero-scale error is expressed in LSBs. Zero-Scale Error Temperature Coefficient Zero-scale error temperature coefficient is a measure of the change in zero-scale error with a change in temperature. It is expressed in ppm FSR/C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0x3FFFF) is loaded to the DAC register. Ideally, the output voltage should be VREFPS - 1 LSB. Full-scale error is expressed in LSBs. Full-Scale Error Temperature Coefficient Full-scale error temperature coefficient is a measure of the change in full-scale error with a change in temperature. It is expressed in ppm FSR/C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed in ppm of the full-scale range. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/C. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (VREFPS - VREFNS)/2 +VREFNS. Midscale error is expressed in LSBs. Midscale Error Temperature Coefficient Midscale error temperature coefficient is a measure of the change in mid-scale error with a change in temperature. It is expressed in ppm FSR/C. Output Slew Rate Slew rate is a measure of the limitation in the rate of change of the output voltage. The slew rate of the AD5781 output voltage is determined by the capacitive load presented to the VOUT pin. The capacitive load in conjunction with the 3.4 k output impedance of the AD5781 set the slew rate. Slew rate is measured from 10% to 90% of the output voltage change and is expressed in V/s. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output voltage to settle to a specified level for a specified change in voltage. For fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 k output impedance of the AD5781, in which case, it is the amplifier that determines the settling time. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (see Figure 42). Output Enabled Glitch Impulse Output enabled glitch impulse is the impulse injected into the analog output when the clamp to ground on the DAC output is removed. It is specified as the area of the glitch in nV-sec (see Figure 48). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is measured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). SFDR is measured when the signal is a digitally generated sine wave. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of the harmonics of the DAC output to the fundamental value. Only the second to fifth harmonics are included. Rev. E | Page 17 of 27 AD5781 Data Sheet DC Power Supply Rejection Ratio. DC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the DAC. It is measured for a given dc change in power supply voltage and is expressed in V/V. AC Power Supply Rejection Ratio (AC PSRR) AC power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Rev. E | Page 18 of 27 Data Sheet AD5781 THEORY OF OPERATION R R 2R R VOUT 2R 2R ..................... 2R 2R 2R .......... 2R S0 S1 ..................... S11 E62 E61.......... E0 VREFPF VREFPS VREFNF VREFNS 12-BIT R-R LADDER DAC ARCHITECTURE 09092-053 The AD5781 is a high accuracy, fast settling, single, 18-bit, serial input, voltage output DAC. It operates from a VDD supply voltage of 7.5 V to 16.5 V and a VSS supply of -16.5 V to -2.5 V. Data is written to the AD5781 in a 24-bit word format via a 3-wire serial interface. The AD5781 incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V with the VOUT pin clamped to AGND through a ~6 k internal resistor. SIX MSBs DECODED INTO 63 EQUAL SEGMENTS Figure 49. DAC Ladder Structure Serial Interface The architecture of the AD5781 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 49. The six MSBs of the 18-bit data-word are decoded to drive 63 switches, E0 to E62. Each of these switches connects one of 63 matched resistors to either the VREFP or VREFN voltage. The remaining 12 bits of the data-word drive the S0 to S11 switches of a 12-bit voltage mode R-R ladder network. The AD5781 has a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs (see Figure 2 for a timing diagram). Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of an R/W bit, three address bits, and twenty data bits as shown in Table 7. The timing diagram for this operation is shown in Figure 2. Table 7. Input Shift Register Format MSB DB23 R/W DB22 DB21 Register address DB20 DB19 Table 8. Decoding the Input Shift Register R/W X1 0 0 0 0 1 1 1 1 Register Address 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Description No operation (NOP). Used in readback operations. Write to the DAC register. Write to the control register. Write to the clearcode register. Write to the software control register. Read from the DAC register. Read from the control register. Read from the clearcode register. X is don't care. Rev. E | Page 19 of 27 LSB DB0 Register data AD5781 Data Sheet Standalone Operation HARDWARE CONTROL PINS The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The input shift register is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. Once the write cycle is complete, the output can be updated by taking LDAC low while SYNC is high. Load DAC Function (LDAC) After data has been transferred into the input register of the DAC, there are two ways to update the DAC register and DAC output. Depending on the status of both SYNC and LDAC, one of two update modes is selected: synchronous DAC updating or asynchronous DAC updating. Synchronous DAC Update In this mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC. Asynchronous DAC Update In this mode, LDAC is held high while data is being clocked into the input shift register. The DAC output is asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. Readback Reset Function (RESET) The contents of all the on-chip registers can be read back via the SDO pin. Table 8 outlines how the registers are decoded. After a register has been addressed for a read, the next 24 clock cycles clock the data out on the SDO pin. The clocks must be applied while SYNC is low. When SYNC is returned high, the SDO pin is placed in tristate. For a read of a single register, the NOP function can be used to clock out the data. Alternatively, if more than one register is to be read, the data of the first register to be addressed can be clocked out at the same time the second register to be read is being addressed. The SDO pin must be enabled to complete a readback operation. The SDO pin is enabled by default. The AD5781 can be reset to its power-on state by two means: either by asserting the RESET pin or by utilizing the software RESET control function (see Table 14). If the RESET pin is not used, it should be hardwired to IOVCC. Asynchronous Clear Function (CLR) The CLR pin is an active low clear that allows the output to be cleared to a user defined value. The 18-bit clear code value is programmed to the clearcode register (see Table 13). It is necessary to maintain CLR low for a minimum amount of time to complete the operation (see Figure 2). When the CLR signal is returned high, the output remains at the clear value (if LDAC is high) until a new value is loaded to the DAC register. The output cannot be updated with a new value while the CLR pin is low. A clear operation can also be performed by setting the CLR bit in the software control register (see Table 14). Rev. E | Page 20 of 27 Data Sheet AD5781 Table 9. Hardware Control Pins Truth Table LDAC CLR RESET X1 X1 0 0 1 X1 X1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Function The AD5781 is in reset mode. The device cannot be programmed. The AD5781 is returned to its power-on state. All registers are set to their default values. The DAC register is loaded with the clearcode register value, and the output is set accordingly. The output is set according to the DAC register value. The DAC register is loaded with the clearcode register value, and the output is set accordingly. The output is set according to the DAC register value. The output remains at the clear code value. The output remains set according to the DAC register value. The output remains at the clear code value. The DAC register is loaded with the clearcode register value and the output is set accordingly. The DAC register is loaded with the clearcode register value and the output is set accordingly. The output remains at the clear code value. The output is set according to the DAC register value. X is don't care. ON-CHIP REGISTERS DAC Register Table 10 outlines how data is written to and read from the DAC register. Table 10. DAC Register MSB DB23 R/W DB22 R/W 0 1 LSB DB21 DB20 DB19 Register address 0 1 18-bits of data The following equation describes the ideal transfer function of the DAC: (VREFP - VREFN ) x D + V 218 - 1 DB1 DB0 X1 X1 DAC register data X is don't care. VOUT = DB2 REFN where: VREFN is the negative voltage applied at the VREFNS input pin. VREFP is the positive voltage applied at the VREFPS input pin. D is the 18-bit code programmed to the DAC. Rev. E | Page 21 of 27 AD5781 Data Sheet Control Register The control register controls the mode of operation of the AD5781. Table 11. Control Register MSB DB23 LSB DB22 R/W R/W DB21 DB20 DB19...DB11 DB10 DB9 DB8 Reserved Reserved LIN COMP Register address 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BIN/2sC DACTRI OPGND RBUF Reserved Control register data 0 SDODIS Table 12. Control Register Functions Function Reserved RBUF OPGND DACTRI BIN/2sC SDODIS LIN COMP Description These bits are reserved and should be programmed to zero. Output amplifier configuration control. 0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 53. This allows an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details. 1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 52 so that the resistance between the RFB and INV pins is 3.4 k, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section for further details. Output ground clamp control. 0: DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) DAC output is clamped to ground through a ~6 k resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DAC tristate control. 0: DAC is in normal operating mode. 1: (default) DAC is in tristate mode. DAC register coding select. 0: (default) DAC register uses twos complement coding. 1: DAC register uses offset binary coding. SDO pin enable/disable control. 0: (default) SDO pin is enabled. 1: SDO pin is disabled (tristate). Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details. 0 0 0 0 (Default) reference input span up to 10 V. 1 1 0 0 Reference input span of 20 V. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. Table 13. Clearcode Register MSB DB23 R/W DB22 R/W 0 1 LSB DB21 DB20 Register address 1 DB19 DB2 Clearcode register data 1 18-bits of data X is don't care. Rev. E | Page 22 of 27 DB1 DB0 X1 X1 Data Sheet AD5781 Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 14. Software Control Register MSB DB23 R/W DB22 0 1 1 2 LSB DB21 DB20 Register address 0 0 DB19 Reserved DB3 DB2 DB1 Software control register data RESET CLR 1 DB0 LDAC 2 The CLR function has no effect if the LDAC pin is low. The LDAC function has no effect if the CLR pin is low. Table 15. Software Control Register Functions Function LDAC CLR RESET Description Setting this bit to 1 updates the DAC register and consequently the DAC output. Setting this bit to 1 sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Setting this bit to 1 returns the AD5781 to its power-on state. Rev. E | Page 23 of 27 AD5781 Data Sheet AD5781 FEATURES POWER-ON TO 0 V LINEARITY COMPENSATION The AD5781 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 k resistor. The DAC remains in this state until programmed otherwise via the control register. This is a useful feature in applications where it is important to know the state of the DAC output while it is in the process of powering up. The integral nonlinearity (INL) of the AD5781 can vary according to the applied reference voltage span; the LIN COMP bits of the control register can be programmed to compensate for this variation in INL. The specifications in this data sheet are obtained with LIN COMP = 0000 for reference spans up to and including 10 V and with LIN COMP = 1100 for a reference span of 20 V. The default value of the LIN COMP bits is 0000. POWER-UP SEQUENCE To power up the part in a known safe state, ensure that VCC does not come up while VDD is unpowered during power-on by powering up the VDD supply before the VCC supply. If this cannot be achieved, connect an external Schottky diode across the VDD and VCC supplies as shown in Figure 50. VCC OUTPUT AMPLIFIER CONFIGURATION There are a number of different ways that an output amplifier can be connected to the AD5781, depending on the voltage references applied and the desired output voltage span. Unity Gain Configuration Figure 51 shows an output amplifier configured for unity gain, in this configuration the output spans from VREFN to VREFP. VREFP VDD 1/2 AD8676 VCC VDD VREFPF VREFPS R1 AD5781 09092-050 A1 RFB RFB 6.8k 6.8k INV 18-BIT DAC Figure 50. Schottky Diode Connection AD8675, ADA4898-1, ADA4004-1 VOUT VOUT CONFIGURING THE AD5781 DAC OUTPUT STATE The DAC output can be placed in one of three states, controlled by the DACTRI and OPGND bits of the control register, as shown in Table 16. Table 16. AD5781 Output State Truth Table DACTRI 0 0 1 1 OPGND 0 1 0 1 Output State Normal operating mode. Output is clamped via ~6 k to AGND. Output is in tristate. Output is clamped via ~6 k to AGND. VREFNF VREFNS AD5781 1/2 AD8676 VREFN 09092-054 After power-on, the AD5781 must be configured for normal operating mode before programming the output. To do this, the control register must be programmed. The DAC is removed from tristate by clearing the DACTRI bit, and the output clamp is removed by clearing the OPGND bit. At this point, the output goes to VREFN unless an alternative value is first programmed to the DAC register. Figure 51. Output Amplifier in Unity Gain Configuration A second unity gain configuration for the output amplifier is one that removes an offset from the input bias currents of the amplifier. It does this by inserting a resistance in the feedback path of the amplifier that is equal to the output resistance of the DAC. The DAC output resistance is 3.4 k. By connecting R1 and RFB in parallel, a resistance equal to the DAC resistance is available on-chip. Because the resistors are all on one piece of silicon, they are temperature coefficient matched. To enable this mode of operation, the RBUF bit of the control register must be set to Logic 1. Figure 52 shows how the output amplifier is connected to the AD5781. In this configuration, the output amplifier is in unity gain and the output spans from VREFN to VREFP. This unity gain configuration allows a capacitor to be placed in the amplifier feedback path to improve dynamic performance. Rev. E | Page 24 of 27 Data Sheet AD5781 VREFP VREFP 1/2 AD8676 1/2 AD8676 VREFPS VREFPF R1 RFB R1 6.8k RFB INV 18-BIT DAC VREFNF 6.8k VOUT VREFNS AD5781 A1 10pF RFB RFB 6.8k 6.8k 10pF INV VOUT VOUT 18-BIT DAC VOUT AD8675, ADA4898-1, ADA4004-1 VREFNF 1/2 AD8676 VREFNS AD5781 AD8675, ADA4898-1, ADA4004-1 1/2 AD8676 09092-055 VREFN VREFPS Figure 52. Output Amplifier in Unity Gain with Amplifier Input Bias Current Compensation Gain of Two Configuration Figure 53 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.8 k resistors, which are exactly twice the DAC resistance, having the effect of removing an offset from the input bias current of the external amplifier. In this configuration, the output spans from 2 x VREFN - VREFP to VREFP. This configuration is used to generate a bipolar output span from a single-ended reference input, with VREFN = 0 V. For this mode of operation, the RBUF bit of the control register must be cleared to Logic 0. Rev. E | Page 25 of 27 VREFN = 0V Figure 53. Output Amplifier in Gain of Two Configuration 09092-056 VREFPF AD5781 Data Sheet APPLICATIONS INFORMATION 09092-057 TYPICAL OPERATING CIRCUIT Figure 54. Typical Operating Circuit Figure 54 shows a typical operating circuit for the AD5781 using an AD8676 for reference buffers and an AD8675 as an output buffer. To meet the specified linearity, force sense buffers must be used on the reference inputs. Because the output impedance of the AD5781 is 3.4 k, an output buffer is required for driving low resistive, high capacitive loads. EVALUATION BOARD An evaluation board is available for the AD5781 to aid designers in evaluating the high performance of the part with minimum effort. The AD5781 evaluation kit includes a populated and tested AD5781 PCB. The evaluation board interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program the AD5781. The software runs on any PC that has Microsoft(R) Windows(R) XP (SP2) or Vista (32 bits) installed. The EVALAD5781 data sheet is available, which gives full details on the operation of the evaluation board Rev. E | Page 26 of 27 Data Sheet AD5781 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 55. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5781BRUZ AD5781BRUZ-REEL7 AD5781ARUZ AD5781ARUZ-REEL7 EVAL-AD5781SDZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C INL 0.5 LSB 0.5 LSB 4 LSB 4 LSB Z = RoHS Compliant Part. (c)2010-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09092-0-4/18(E) Rev. E | Page 27 of 27 Package Description 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP Evaluation Board Package Option RU-20 RU-20 RU-20 RU-20