True 18-Bit, Voltage Output DAC
±0.5 LSB INL, ±0.5 LSB DNL
Data Sheet
AD5781
Rev. E Document Feedback
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FEATURES
Single 18-bit DAC, ±0.5 LSB INL
7.5 nV/√Hz noise spectral density
0.05 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
1.4 nV-sec glitch impulse
Operating temperature range: −40°C to +125°C
20-lead TSSOP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
FUNCTIONAL BLOCK DIAGRAM
A1 6.8kΩ
6kΩ
6.8kΩ
R1 RFB
18-BIT
DAC
DAC
REG 18
18
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON-RESET
AND CLEAR LO GI C
AD5781
IOVCC
SDIN
VCC VDD VREFPF VREFPS
VREFNF
AGNDVSS
DGND VREFNS
SCLK
SYNC
SDO
LDAC
CLR
RESET
RFB
INV
VOUT
09092-001
Figure 1.
GENERAL DESCRIPTION
The AD57811 is a single 18-bit, unbuffered voltage output digital-
to-analog converter (DAC) that operates from a bipolar supply of
up to 33 V. T h e AD5781 accepts a positive reference input range
of 5 V to VDD − 2.5 V and a negative reference input range of VSS
+ 2.5 V to 0 V. T he AD5781 offers a relative accuracy specifi-
cation of ±0.5 LSB maximum, and operation is guaranteed
monotonic with a ±0.5 LSB differential nonlinearity (DNL)
maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
serial peripheral interface (SPI), QSPI™, MICROWIRE™, and
DSP interface standards. The part incorporates a power-on
reset circuit that ensures that the DAC output powers up to 0 V
and in a known output impedance state and remains in this state
until a valid write to the device takes place. The part provides
an output clamp feature that places the output in a defined load
state.
PRODUCT HIGHLIGHTS
1. True 18-Bit Accuracy.
2. Wide Power Supply Range of Up to ±16.5 V.
3. −40°C to +125°C Operating Temperature Range.
4. Low 7.5 nV/√Hz Noise.
5. Low 0.05 ppm/°C Temperature Drift.
Table 1. Complementary Devices
Part No.
Description
AD8675
Ultraprecision, 36 V, 2.8 nV/√Hz rail-to-rail
output op amp
AD8676 Ultraprecision, 36 V, 2.8 nV/√Hz dual rail-to-
rail output op amp
ADA4898-1 High voltage, low noise, low distortion, unity
gain stable, high speed op amp
Table 2. Related Devices
Part No. Description
AD5791
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
1 Protected by U.S. Patent No 7,884,747, and other patents are pending.
AD5781 Data Sheet
Rev. E | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Description .............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
DAC Architecture ....................................................................... 19
Hardware Control Pins .............................................................. 20
On-Chip Registers ...................................................................... 21
AD5781 Features ............................................................................ 24
Power-On to 0 V ......................................................................... 24
Power-Up Sequence ................................................................... 24
Configuring the AD5781 .......................................................... 24
DAC Output State ...................................................................... 24
Linearity Compensation ............................................................ 24
Output Amplifier Configuration.............................................. 24
Applications Information .............................................................. 26
Typical Operating Circuit ......................................................... 26
Evaluation Board ........................................................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/2018—Rev. D to Rev. E
Added Power-Up Sequence Section and Figure 50; Renumbered
Sequentially ..................................................................................... 24
7/2013—Rev. C to Rev. D
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4 ................................................................................ 7
Deleted Daisy-Chain Operation Section ..................................... 20
11/2011—Rev. B to Rev. C
Added Figure 48; Renumbered Sequentially .............................. 17
Change to Ideal Transfer Function Equation .............................. 22
9/2011—Rev. A to Rev. B
Added Patent Note ........................................................................... 1
Changes to Table 3 ............................................................................ 3
Changes to OPGND Description, Table 12 ................................ 23
8/2011—Rev. 0 to Rev. A
Change to Features Section .............................................................. 1
Changes to Specifications Section ................................................... 3
Deleted t14 Parameter from Timing Specifications Section,
Table 4 ................................................................................................. 5
Changes to Figure 2 and Figure 3 .................................................... 6
Changes to Figure 4 ........................................................................... 7
Replaced Figure 42 and Figure 43 ................................................ 16
Added New Figure 44, Figure 45, and Figure 46, Renumbered
Sequentially ..................................................................................... 16
7/2010—Revision 0: Initial Version
Data Sheet AD5781
Rev. E | Page 3 of 27
SPECIFICATIONS
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, V REFP = +1 0 V, V REFN = −10 V, VCC = +2.7 V to +5.5 V, IOV CC = +1.71 V to +5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 3.
A, B Version1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2
Resolution 18 Bits
Integral Nonlinearity Error (Relative
Accuracy)
−0.5 ±0.25 +0.5 LSB B version, VREFP = +10 V, VREFN = −10 V
−0.5
±0.25
+0.5
LSB
B version, V
REFP
= +10 V, V
REFN
= 0 V
3
−1 ±0.5 +1 LSB B version, VREFP = +5 V, VREFN = 0 V3
−4 ±2 +4 LSB A version4
Differential Nonlinearity Error −0.5 ±0.25 +0.5 LSB VREFP = +10 V, VREFN = −10 V
−0.5 ±0.25 +0.5 LSB VREFP = +10 V, VREFN = 0 V3
−1 ±0.5 +1 LSB VREFP = +5 V, VREFN = 0 V3
Linearity Error Long-Term Stability5 0.04 LSB After 500 hours at TA = 125°C
0.05 LSB After 1000 hours at TA = 125°C
0.03 LSB After 1000 hours t TA = 100°C
Full-Scale Error −1.75 ±0.25 +1.75 LSB VREFP = +10 V, VREFN = −10 V3
−2.75 ±0.062 +2.75 LSB VREFP = +10 V, VREFN = 0 V3
−5.25
±0.2
+5.25
LSB
V
REFP
= +5 V, V
REFN
= 0 V
3
−1 ±0.25 +1 LSB VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
−1 ±0.062 +1 LSB VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
−1.5 ±0.2 +1.5 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Full-Scale Error Temperature Coefficient3 ±0.02 ppm FSR/°C
Zero-Scale Error −1.75 ±0.025 +1.75 LSB VREFP = +10 V, VREFN = −10 V3
−2.5 ±0.38 +2.5 LSB VREFP = +10 V, VREFN = 0 V3
−5.25 ±0.19 +5.25 LSB VREFP = +5 V, VREFN = 0 V3
−1 ±0.025 +1 LSB VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
−1
±0.38
+1
LSB
V
REFP
= 10 V, V
REFN
= 0 V3, T
A
= 0°C to 105°C
−1.5 ±0.19 +1.5 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Zero-Scale Error Temperature Coefficient3 ±0.04 ppm FSR/°C
Gain Error −6 ±0.3 +6 ppm FSR VREFP = +10 V, VREFN = −10 V3
−10 ±0.4 +10 ppm FSR VREFP = +10 V, VREFN = 0 V3
−20 ±0.4 +20 ppm FSR VREFP = +5 V, VREFN = 0 V3
Gain Error Temperature Coefficient
3
±0.04
ppm FSR/°C
R1, RFB Matching 0.01 %
OUTPUT CHARACTERISTICS3
Output Voltage Range VREFN VREFP V
Output Slew Rate 50 V/µs Unbuffered output, 10 MΩ||20 pF load
Output Voltage Settling Time 1 µs 10 V step to 0.02%, using AD845
buffer in unity-gain mode
1 µs 125 code step to ±1 LSB6
Output Noise Spectral Density
7.5
nV/√Hz
at 1 kHz, DAC code = midscale
7.5 nV/√Hz at 10 kHz, DAC code = midscale
7.5 nV/√Hz at 100 kHz, DAC code = midscale
Output Voltage Noise 1.1 µV p-p DAC code = midscale, 0.1 Hz to
10 Hz bandwidth7
AD5781 Data Sheet
Rev. E | Page 4 of 27
A, B Version1
Parameter Min Typ Max Unit Test Conditions/Comments
Midscale Glitch Impulse 3.1 nV-sec VREFP = +10 V, VREFN = −10 V
1.7 nV-sec VREFP = +10 V, VREFN = 0 V
1.4 nV-sec VREFP = +5 V, VREFN = 0 V
MSB Segment Glitch Impulse6 9.1 nV-sec VREFP = +10 V, VREFN = −10 V, see Figure 42
3.6 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 43
1.9 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 44
Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp
Digital Feedthrough 0.4 nV-sec
DC Output Impedance (Normal Mode)
3.4
kΩ
DC Output Impedance (Output
Clamped to Ground)
6 kΩ
Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate
Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS3
VREFP Input Range 5 VDD − 2.5 V V
VREFN Input Range VSS + 2.5 V 0
DC Input Impedance 5 6.6 kΩ VREFP, VREFN, code dependent,
typical at midscale code
Input Capacitance 15 pF VREFP, VREFN
LOGIC INPUTS3
Input Current8 −1 +1 µA
Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V
Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, VOH IOVCC − 0.5 V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current ±1 µA
High Impedance Output Capacitance
3
pF
POWER REQUIREMENTS All digital inputs at DGND or IOVCC
VDD 7.5 VSS + 33 V
VSS VDD − 33 −2.5 V
VCC 2.7 5.5 V
IOVCC 1.71 5.5 V IOVCC ≤ VCC
IDD 4.2 5.2 mA
ISS 4 4.9 mA
I
CC
600
900
µA
IOICC 52 140 µA SDO disabled
DC Power Supply Rejection Ratio3, 9 ±0.6 µV/V VDD ± 10%, VSS = 15 V
±0.6 µV/V VSS ± 10%, VDD = 15 V
AC Power Supply Rejection Ratio3 95 dB VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
95 dB VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4 Valid for all voltage reference spans.
5 Guaranteed by design and characterization, not production tested.
6 The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
7 Includes noise contribution from AD8676BRZ voltage reference buffers.
8 Current flowing in an individual logic pin.
9 Includes PSRR of AD8676BRZ voltage reference buffers.
Data Sheet AD5781
Rev. E | Page 5 of 27
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit1
Unit Test Conditions/Comments
IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V
t12 40 28 ns min SCLK cycle time
92 60 ns min SCLK cycle time (readback mode)
t2 15 10 ns min SCLK high time
t
3
9
5
ns min
SCLK low time
t4 5 5 ns min SYNC to SCLK falling edge setup time
t5 2 2 ns min SCLK falling edge to SYNC rising edge hold time
t6 48 40 ns min Minimum SYNC high time
t7 8 6 ns min SYNC rising edge to next SCLK falling edge ignore
t8 9 7 ns min Data setup time
t
9
12
7
ns min
Data hold time
t10 13 10 ns min LDAC falling edge to SYNC falling edge
t11 20 16 ns min SYNC rising edge to LDAC falling edge
t12 14 11 ns min LDAC pulse width low
t13 130 130 ns typ LDAC falling edge to output response time
t14 130 130 ns typ SYNC rising edge to output response time (LDAC tied low)
t15 50 50 ns min CLR pulse width low
t16 140 140 ns typ CLR pulse activation time
t17 0 0 ns min SYNC falling edge to first SCLK rising edge
t18 65 60 ns max SYNC rising edge to SDO tristate (CL = 50 pF)
t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)
t
20
0
0
ns min
SYNC rising edge to SCLK rising edge ignore
t21 35 35 ns typ RESET pulse width low
t22 150 150 ns typ RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
AD5781 Data Sheet
Rev. E | Page 6 of 27
t
7
2421
DB23 DB0
t10
t8
t4
t6
t5
t3
t1
t2
t9
t11
t12
t13
t14
t15
t16
t21
t22
V
OUT
V
OUT
V
OUT
V
OUT
RESET
CLR
LDAC
SDIN
SYNC
SCLK
09092-002
Figure 2. Write Mode Timing Diagram
DB23 DB0
NOP CONDITION
REGISTER CONTENTS CLOCKED OUT
t
1
t
17
t
2
t
5
t
17
t
5
t
19
t
18
t
20
t
3
t
4
t
8
t
9
t
6
t
7
24221241
DB23 DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
SDIN
SYNC
SCLK
09092-003
Figure 3. Readback Mode Timing Diagram
Data Sheet AD5781
Rev. E | Page 7 of 27
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
V
DD
to AGND
−0.3 V to +34 V
VSS to AGND −34 V to +0.3 V
VDD to VSS −0.3 V to +34 V
VCC to DGND −0.3 V to +7 V
IOVCC to DGND −0.3 V to VCC + 3 V or +7 V
(whichever is less)
Digital Inputs to DGND −0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
VOUT to AGND −0.3 V to VDD + 0.3 V
VREFPF to AGND −0.3 V to VDD + 0.3 V
VREFPS to AGND −0.3 V to VDD + 0.3 V
V
REFNF
to AGND
V
SS
− 0.3 V to +0.3 V
VREFNS to AGND
VSS − 0.3 V to +0.3 V
DGND to AGND −0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial −40°C to + 125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature,
TJ max
150°C
Power Dissipation (TJ max − TA)/θJA
TSSOP Package
θJA Thermal Impedance 143°C/W
θJC Thermal Impedance 45°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 1.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance integrated circuit with an
ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
AD5781 Data Sheet
Rev. E | Page 8 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
9
10
V
OUT
V
REFPS
V
REFPF
CLR
RESET
V
DD
INV
IOV
CC
V
CC
LDAC
20
19
18
17
16
15
14
13
12
11
AGND
V
SS
V
REFNS
SYNC
DGND
V
REFNF
SDO
SDIN
SCLK
R
FB
AD5781
TOP VIEW
(No t t o Scal e)
09092-005
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 INV Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details.
2 VOUT Analog Output Voltage.
3 VREFPS Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFPF pin. See the AD5781 Features section for further details.
4 VREFPF Positive Reference Force Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFPS pin. See AD5781 Features section for further details.
5 VDD Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. VDD should be decoupled to
AGND.
6 RESET Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status.
7 CLR Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and
updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
8 LDAC Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output.
When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write
cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin
should not be left unconnected.
9 VCC Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
10 IOVCC Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of
1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC.
11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
12 SDIN Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at clock rates of up to 35 MHz.
14 SYNC Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When
SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks.
The input shift register is updated on the rising edge of SYNC.
15 DGND Ground Reference Pin for Digital Circuitry.
16 VREFNF Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFNS pin. See the AD5781 Features section for further details.
17 VREFNS Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFNF pin. See the AD5781 Features section for further details.
18 VSS Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. VSS should be decoupled to
AGND.
19 AGND Ground Reference Pin for Analog Circuitry.
20 RFB Feedback Connection for External Amplifier. See the AD5781 Features section for further details.
Data Sheet AD5781
Rev. E | Page 9 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
INL E RROR (LSB)
09092-006
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +10V
V
REFN
= –10V
V
DD
= +15V
V
SS
= –15V
Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
INL E RROR (LSB)
09092-007
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 6. Integral Nonlinearity Error vs. DAC Code, +10 V Span
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0050000 100000 150000 200000 250000
DAC CODE
INL E RROR (LSB)
09092-008
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
Figure 7. Integral Nonlinearity Error vs. DAC Code, +5 V Span
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
INL E RROR (LSB)
09092-009
TA = +25°C
TA = –40° C
TA = +125°C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
VREFP = + 10V
VREFN = 0V
VDD = + 15V
VSS = –15V
Figure 8. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, X2 Gain Mode
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
DNL ERROR (LSB)
09092-010
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +10V
V
REFN
= –10V
V
DD
= +15V
V
SS
= –15V
Figure 9. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
DNL ERROR (LSB)
09092-011
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
Figure 10. Differential Nonlinearity Error vs. DAC Code, +10 V Span
AD5781 Data Sheet
Rev. E | Page 10 of 27
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
DNL ERROR (LSB)
09092-012
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
Figure 11. Differential Nonlinearity Error vs. DAC Code, +5 V Span
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5050000 100000 150000 200000 250000
DAC CODE
DNL ERROR (LSB)
09092-013
T
A
= +25°C
T
A
= –40° C
T
A
= +125°C
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
Figure 12. Differential Nonlinearity Error vs. DAC Code, ±10 V Span,
X2 Gain Mode
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
INL E RROR (LSB)
09092-014
±10V SPAN MAX INL
+5V S PAN M AX INL
+10V SPAN MIN I NL
+10V SPAN MAX INL
±10V SPAN MIN I NL
+5V S PAN M IN I NL
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
VDD = + 15V
VSS = –15V
Figure 13. Integral Nonlinearity Error vs. Temperature
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
DNL ERROR (LSB)
09092-015
±10V SPAN MAX DNL
+5V S PAN M AX DNL
+10V SPAN MIN DN L
+10V SPAN MAX DNL
±10V SPAN MIN DN L
+5V S PAN M IN DN L
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
VDD = + 15V
VSS = –15V
Figure 14. Differential Nonlinearity Error vs. Temperature
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
INL E RROR (LSB)
09092-016
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
INL MAX
INL MIN
Figure 15. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
INL E RROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
09092-017
TA = 25° C
VREFP = +5V
VREFN = 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
INL MAX
INL MIN
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span
Data Sheet AD5781
Rev. E | Page 11 of 27
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
DNL ERROR (LSB)
09092-018
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
DNL M AX
DNL M IN
Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span
0.10
0.05
0
–0.15
–0.10
–0.05
–0.20
–0.25
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
DNL ERROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
09092-019
TA = 25° C
VREFP = +5V
VREFN = 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
DNL M AX
DNL M IN
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
VDD/|VSS| (V)
ZERO-S CALE E RROR (LSB)
09092-020
TA = 25° C
VREFP = + 10V
VREFN = –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 19. Zero-Scale Error vs. Supply Voltage, ±10 V Span
0.14
0.12
0.10
0.04
0.06
0.08
0.02
0
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
ZERO-S CALE E RROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
09092-021
TA = 25° C
VREFP = +5V
VREFN = 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 20. Zero-Scale Error vs. Supply Voltage, +5 V Span
0.05
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
MI D- S CALE ERROR (LSB)
09092-022
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 21. Midscale Error vs. Supply Voltage, ±10 V Span
0.05
0
–0.15
–0.10
–0.05
–0.20
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
MI D- S CALE ERROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
09092-023
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 22. Midscale Error vs. Supply Voltage, +5 V Span
AD5781 Data Sheet
Rev. E | Page 12 of 27
–0.015
–0.020
–0.025
–0.030
–0.035
–0.040
–0.045
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
FULL- S CALE E RROR (LSB)
09092-024
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–0.01
–0.02
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
FULL- S CALE E RROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
09092-025
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 24. Full-Scale Error vs. Supply Voltage, +5 V Span
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
GAI N E RROR (pp m FSR)
09092-026
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 25. Gain Error vs. Supply Voltage, ±10 V Span
0.10
0.05
0
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
–0.40
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
GAI N E RROR (pp m FSR)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
09092-027
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 26. Gain Error vs. Supply Voltage, +5 V Span
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
INL E RROR (LSB)
09092-028
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
INL MAX
INL MIN
Figure 27. Integral Nonlinearity Error vs. Reference Voltage
0.10
0.05
0
–0.05
–0.10
–0.15
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
DNL ERROR (LSB)
09092-029
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
DNL M AX
DNL M IN
Figure 28. Differential Nonlinearity Error vs. Reference Voltage
Data Sheet AD5781
Rev. E | Page 13 of 27
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VREFP/|VREFN| (V)
ZERO-S CALE E RROR (LSB)
09092-030
TA = 25° C
VDD = + 15V
VSS = –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 29. Zero-Scale Error vs. Reference Voltage
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
MI D- S CALE ERROR (LSB)
09092-031
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 30. Midscale Error vs. Reference Voltage
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
FULL- S CALE E RROR (LSB)
09092-032
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 31. Full-Scale Error vs. Reference Voltage
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
GAI N E RROR (pp m FSR)
09092-033
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
Figure 32. Gain Error vs. Reference Voltage
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
FULL- S CALE E RROR (LSB)
09092-034
±10V SPAN
+10V SPAN
±5V SPAN
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
VDD = + 15V
VSS = –15V
VREFP = + 10V
VREFN = –15V
Figure 33. Full-Scale Error vs. Temperature
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
MI D- S CALE ERROR (LSB)
09092-035
±10V SPAN
+10V SPAN
±5V SPAN
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
VDD = + 15V
VSS = –15V
VREFP = + 10V
VREFN = –15V
Figure 34. Midscale Error vs. Temperature
AD5781 Data Sheet
Rev. E | Page 14 of 27
1.2
1.0
0.8
0.6
0.4
0
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
ZERO-SCALE ERROR (LSBs)
09092-036
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –15V
±10V SPAN
+10V SPAN
±5V SPAN
Figure 35. Zero-Scale Error vs. Temperature
4
3
2
1
0
–1
–2
–3
–4
–5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
GAIN ERROR (ppm FSR)
09092-037
±10V SPAN
+10V SPAN
+5V SPAN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = –15V
Figure 36. Gain Error vs. Temperature
900
800
700
600
500
400
300
200
100
001
T
A
= 25°C
23456
LOGIC INPUT VOLTAGE (V)
IOI
CC
(µA)
09092-038
IOV
CC
= 5V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 5V, LOGIC VOLTAGE
DECREASING
IOV
CC
= 3V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 3V, LOGIC VOLTAGE
DECREASING
Figure 37. IOICC vs. Logic Input Voltage
5
4
3
2
1
0
–1
–2
–3
–4
–5
–20 –15 –10 –5 0 5 10 15 20
VDD, VSS (V)
IDD, ISS (mA)
09092-039
TA = 25°C
IDD
ISS
Figure 38. Power Supply Currents vs. Power Supply Voltages
09092-040
CH3 5V CH4 5V 200ns
3
4
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
Figure 39. Rising Full-Scale Voltage Step
09092-041
CH3 5V CH4 5V 200ns
3
4
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
Figure 40. Falling Full-Scale Voltage Step
Data Sheet AD5781
Rev. E | Page 15 of 27
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
01 5432
V
OUT
(mV)
TIME (µs)
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
09092-063
Figure 41. 125 Code Step Settling Time
10
0
1
2
3
4
5
6
7
8
9
16384
65536
OUTPUT GLITCH (nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
POSITIVE CODE
CHANGE
NEGATIVE CODE
CHANGE
5V
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
09092-059
V
REF
Figure 42. 6 MSB Segment Glitch Energy for ±10 V VREF
4.0
0
2.0
1.5
1.0
0.5
2.5
3.0
3.5
16384
65536
OUTPUT GLITCH (nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
POSITIVE CODE
CHANGE
NEGATIVE CODE
CHANGE
10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
09092-060
Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF
3.0
–0.2
2.2
1.0
1.4
1.8
0.6
0.2
2.6
16384
65536
OUTPUT GLITCH (nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
NEGATIVE CODE
CHANGE
5V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
POSITIVE CODE
CHANGE
09092-061
Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF
40
–20
–10
0
10
20
30
–1.0 –0.5 2.01.51.00.50
V
OUT
(mV)
TIME (µs)
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
C
X
= 143pF + 0pF
C
X
= 143pF + 220pF
C
X
= 143pF + 470pF
C
X
= 143pF + 1,000pF
09092-062
Figure 45. Midscale Peak-to-Peak Glitch for ±10 V
800
600
400
200
0
–200
–400
–600
012345678 910
TIME (Seconds)
OUTPUT VOLTAGE (nV)
09092-044
MID-SCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
AD5781 Data Sheet
Rev. E | Page 16 of 27
100
1
0.1 100k
NSD (nV/Hz)
FRE Q UE NCY ( Hz )
110 100 1k 10k
10
09092-064
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
CODE = M IDSCALE
Figure 47. Noise Spectral Density vs. Frequency
350
300
250
200
150
100
50
0
–50 0 1–1 23456
TIME (µs)
OUTPUT VOLTAGE (mV)
09092-049
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUT P UT BUF FER
Figure 48. Glitch Impulse on Removal of Output Clamp
Data Sheet AD5781
Rev. E | Page 17 of 27
TERMINOLOGY
Relative Accuracy
Relative accuracy, or integral nonlinearity (INL), is a measure of
the maximum deviation, in LSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL error vs. code plot is shown in Figure 5.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 9.
Linearity Error Long-Term Stability
Linearity error long-term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is
specified in LSB for a time period of 500 hours and 1000 hours
at an elevated ambient temperature.
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be VREFNS. Zero-scale error is expressed in LSBs.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0x3FFFF) is loaded to the DAC register. Ideally, the
output voltage should be VREFPS − 1 LSB. Full-scale error is
expressed in LSBs.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with a change in temperature. It is expressed in ppm
FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x20000) is loaded to the DAC register. Ideally, the output
voltage should be (VREFPS – VREFNS)/2 +VREFNS. Midscale error is
expressed in LSBs.
Midscale Error Temperature Coefficient
Midscale error temperature coefficient is a measure of the
change in mid-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Output Slew Rate
Slew rate is a measure of the limitation in the rate of change of
the output voltage. The slew rate of the AD5781 output voltage
is determined by the capacitive load presented to the VOUT pin.
The capacitive load in conjunction with the 3.4 kΩ output impe-
dance of the AD5781 set the slew rate. Slew rate is measured
from 10% to 90% of the output voltage change and is expressed
in V/µs.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5781, in which case, it is the
amplifier that determines the settling time.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 42).
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 48).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the usable dynamic range of a
DAC before spurious noise interferes or distorts the fundamental
signal. It is measured by the difference in amplitude between the
fundamental and the largest harmonically or nonharmonically
related spur from dc to full Nyquist bandwidth (half the DAC
sampling rate, or fS/2). SFDR is measured when the signal is a
digitally generated sine wave.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value. Only
the second to fifth harmonics are included.
AD5781 Data Sheet
Rev. E | Page 18 of 27
DC Power Supply Rejection Ratio.
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in µV/V.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Data Sheet AD5781
Rev. E | Page 19 of 27
THEORY OF OPERATION
The AD5781 is a high accuracy, fast settling, single, 18-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V.
Data is written to the AD5781 in a 24-bit word format via a 3-wire
serial interface. The AD5781 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5781 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49. The
six MSBs of the 18-bit data-word are decoded to drive 63 switches,
E0 to E62. Each of these switches connects one of 63 matched
resistors to either the VREFP or VREFN voltage. The remaining
12 bits of the data-word drive the S0 to S11 switches of a 12-bit
voltage mode R-R ladder network.
2R
S0
2R
S1
2R
S11
2R
E62
2R
E61
2R
E0
12-BIT R-R LADDER
.....................
.....................
..........
..........
R R
R
2R
V
REFPF
V
REFPS
V
REFNF
V
REFNS
V
OUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
09092-053
Figure 49. DAC Ladder Structure Serial Interface
The AD5781 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of an R/W bit, three address bits, and
twenty data bits as shown in Table 7. The timing diagram for
this operation is shown in Figure 2.
Table 7. Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB0
R/W Register address Register data
Table 8. Decoding the Input Shift Register
R/W Register Address Description
X1 0 0 0 No operation (NOP). Used in readback operations.
0 0 0 1 Write to the DAC register.
0 0 1 0 Write to the control register.
0 0 1 1 Write to the clearcode register.
0 1 0 0 Write to the software control register.
1
0
0
1
Read from the DAC register.
1 0 1 0 Read from the control register.
1 0 1 1 Read from the clearcode register.
1 X is don’t care.
AD5781 Data Sheet
Rev. E | Page 20 of 27
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input shift register is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register. Once the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Readback
The contents of all the on-chip registers can be read back via
the SDO pin. Table 8 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
applied while SYNC is low. When SYNC is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first register
to be addressed can be clocked out at the same time the second
register to be read is being addressed. The SDO pin must be
enabled to complete a readback operation. The SDO pin is
enabled by default.
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both SYNC and LDAC, one
of two update modes is selected: synchronous DAC updating or
asynchronous DAC updating.
Synchronous DAC Update
In this mode, LDAC is held low while data is being clocked into
the input shift register. The DAC output is updated on the rising
edge of SYNC.
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5781 can be reset to its power-on state by two means:
either by asserting the RESET pin or by utilizing the software
RESET control function (see Table 14). If the RESET pin is not
used, it should be hardwired to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clear code value is
programmed to the clearcode register (see Table 13). It is
necessary to maintain CLR low for a minimum amount of time
to complete the operation (see Figure 2). When the CLR signal
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 14).
Data Sheet AD5781
Rev. E | Page 21 of 27
Table 9. Hardware Control Pins Truth Table
LDAC CLR RESET Function
X1 X1 0 The AD5781 is in reset mode. The device cannot be programmed.
X1 X1
The AD5781 is returned to its power-on state. All registers are set to their default values.
0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
0 1 1 The output is set according to the DAC register value.
1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
1 1 The output is set according to the DAC register value.
0 1 The output remains at the clear code value.
1 1 The output remains set according to the DAC register value.
0 1 The output remains at the clear code value.
1
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
0
1 The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1 The output remains at the clear code value.
0
1 The output is set according to the DAC register value.
1 X is don’t care.
ON-CHIP REGISTERS
DAC Register
Table 10 outlines how data is written to and read from the DAC register.
Table 10. DAC Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0
R/W Register address DAC register data
R/W 0 0 1 18-bits of data X1 X1
1 X is don’t care.
The following equation describes the ideal transfer function of the DAC:
( )
REFN
REFNREFP
OUT
V
DVV
V+
−
×−
=12
18
where:
VREFN is the negative voltage applied at the VREFNS input pin.
VREFP is the positive voltage applied at the VREFPS input pin.
D is the 18-bit code programmed to the DAC.
AD5781 Data Sheet
Rev. E | Page 22 of 27
Control Register
The control register controls the mode of operation of the AD5781.
Table 11. Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19...DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W Register address Control register data
R/W 0 1 0 Reserved Reserved LIN COMP SDODIS BIN/2sC DACTRI OPGND RBUF Reserved
Table 12. Control Register Functions
Clearcode Register
The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends
on the DAC coding that is being used, either binary or twos complement. The default register value is 0.
Table 13. Clearcode Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0
R/W Register address Clearcode register data
R/W 0 1 1 18-bits of data X1 X1
1 X is don’t care.
Function Description
Reserved These bits are reserved and should be programmed to zero.
RBUF Output amplifier configuration control.
0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 53. This allows
an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details.
1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 52
so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV
pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section
for further details.
OPGND Output ground clamp control.
0: DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DACTRI
DAC tristate control.
0: DAC is in normal operating mode.
1: (default) DAC is in tristate mode.
BIN/2sC DAC register coding select.
0: (default) DAC register uses twos complement coding.
1: DAC register uses offset binary coding.
SDODIS SDO pin enable/disable control.
0: (default) SDO pin is enabled.
1: SDO pin is disabled (tristate).
LIN COMP Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details.
0 0 0 0 (Default) reference input span up to 10 V.
1 1 0 0 Reference input span of 20 V.
Data Sheet AD5781
Rev. E | Page 23 of 27
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 14. Software Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB3 DB2 DB1 DB0
R/W Register address Software control register data
0 1 0 0 Reserved RESET CLR1 LDAC2
1 The CLR function has no effect if the LDAC pin is low.
2 The LDAC function has no effect if the CLR pin is low.
Table 15. Software Control Register Functions
Function Description
LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output.
CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output
value depends on the DAC register coding that is being used, either binary or twos complement.
RESET Setting this bit to 1 returns the AD5781 to its power-on state.
AD5781 Data Sheet
Rev. E | Page 24 of 27
AD5781 FEATURES
POWER-ON TO 0 V
The AD5781 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control
register. This is a useful feature in applications where it is
important to know the state of the DAC output while it is in the
process of powering up.
POWER-UP SEQUENCE
To power up the part in a known safe state, ensure that VCC does
not come up while VDD is unpowered during power-on by
powering up the VDD supply before the VCC supply. If this
cannot be achieved, connect an external Schottky diode across
the VDD and VCC supplies as shown in Figure 50.
09092-050
AD5781
V
CC
V
DD
V
CC
V
DD
Figure 50. Schottky Diode Connection
CONFIGURING THE AD5781
After power-on, the AD5781 must be configured for normal
operating mode before programming the output. To do this, the
control register must be programmed. The DAC is removed
from tristate by clearing the DACTRI bit, and the output clamp
is removed by clearing the OPGND bit. At this point, the output
goes to VREFN unless an alternative value is first programmed to
the DAC register.
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 16.
Table 16. AD5781 Output State Truth Table
DACTRI OPGND Output State
0 0 Normal operating mode.
0 1 Output is clamped via ~6 kΩ to AGND.
1 0 Output is in tristate.
1 1 Output is clamped via ~6 kΩ to AGND.
LINEARITY COMPENSATION
The integral nonlinearity (INL) of the AD5781 can vary
according to the applied reference voltage span; the LIN COMP
bits of the control register can be programmed to compensate
for this variation in INL. The specifications in this data sheet
are obtained with LIN COMP = 0000 for reference spans up to
and including 10 V and with LIN COMP = 1100 for a reference
span of 20 V. The default value of the LIN COMP bits is 0000.
OUTPUT AMPLIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5781, depending on the voltage
references applied and the desired output voltage span.
Unity Gain Configuration
Figure 51 shows an output amplifier configured for unity gain,
in this configuration the output spans from VREFN to VRE F P.
A1
6.8kΩ 6.8kΩ
R1 R
FB
18-BIT
DAC
V
REFPS
V
REFPF
V
REFP
V
REFN
V
REFNS
AD5781
1/2 AD8676
AD8675,
ADA4898-1,
ADA4004-1
1/2 AD8676
V
REFNF
R
FB
INV
V
OUT
V
OUT
09092-054
Figure 51. Output Amplifier in Unity Gain Configuration
A second unity gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on-chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation, the RBUF bit of the control register must be set
to Logic 1. Figure 52 shows how the output amplifier is connected
to the AD5781. In this configuration, the output amplifier is in
unity gain and the output spans from VREFN to VREFP. This unity
gain configuration allows a capacitor to be placed in the
amplifier feedback path to improve dynamic performance.
Data Sheet AD5781
Rev. E | Page 25 of 27
18-BIT
DAC
VREFPS
10pF
VREFPF
VREFP
VREFN
VREFNS
AD5781
1/2 AD8676
AD8675,
ADA4898-1,
ADA4004-1
1/2 AD8676
VREFNF
VOUT
RFB
RFB
VOUT
09092-055
INV
6.8kΩ
6.8kΩ
R1
Figure 52. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
Gain of Two Configuration
Figure 53 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched 6.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect
of removing an offset from the input bias current of the external
amplifier. In this configuration, the output spans from 2 × VREFN −
VREFP to VR E F P. This configuration is used to generate a bipolar
output span from a single-ended reference input, with VREFN =
0 V. For this mode of operation, the RBUF bit of the control
register must be cleared to Logic 0.
A1 6.8kΩ 6.8kΩ
R
1
R
FB
18-BIT
DAC
V
REFPS
V
REFPF
V
REFP
V
REFN
= 0V
V
REFNS
AD5781
1/2 AD8676
1/2 AD8676
V
REFNF
R
FB
INV
V
OUT
09092-056
10pF
AD8675,
ADA4898-1,
ADA4004-1
V
OUT
Figure 53. Output Amplifier in Gain of Two Configuration
AD5781 Data Sheet
Rev. E | Page 26 of 27
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
09092-057
Figure 54. Typical Operating Circuit
Figure 54 shows a typical operating circuit for the AD5781
using an AD8676 for reference buffers and an AD8675 as an
output buffer. To meet the specified linearity, force sense buffers
must be used on the reference inputs. Because the output
impedance of the AD5781 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitive loads.
EVALUATION BOARD
An evaluation board is available for the AD5781 to aid
designers in evaluating the high performance of the part with
minimum effort. The AD5781 evaluation kit includes a
populated and tested AD5781 PCB. The evaluation board
interfaces to the USB port of a PC. Software is available with the
evaluation board to allow the user to easily program the
AD5781. The software runs on any PC that has Microsoft®
Windows® XP (SP2) or Vista (32 bits) installed. The EVAL-
AD5781 data sheet is available, which gives full details on the
operation of the evaluation board
Data Sheet AD5781
Rev. E | Page 27 of 27
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10 6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC 1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARITY
0.10
Figure 55. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range INL Package Description Package Option
AD5781BRUZ −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20
AD5781BRUZ-REEL7 −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20
AD5781ARUZ −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20
AD5781ARUZ-REEL7
−40°C to +125°C
±4 LSB
20-Lead TSSOP
RU-20
EVAL-AD5781SDZ Evaluation Board
1 Z = RoHS Compliant Part.
©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09092-0-4/18(E)