(R) Technology SiI 1362/A & SiI 1364/A SDVO PanelLink Transmitter Data Sheet Document # SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Silicon Image, Inc. SiI-DS-0112-B1 March 2006 Application Information To obtain the most updated Application Notes and other useful information for your design, visit the Silicon Image web site at www.siliconimage.com or contact your local Silicon Image sales office. Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink(R), TMDS(R) and the PanelLink(R) Digital logo are registered trademarks of Silicon Image, Inc. VESA(R) is a registered trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Semiconductor. Intel(R) is a registered trademark of Intel Corp. SDVO (Serial Digital Video Output) is a data format proprietary to Intel Corporation for use by Intel Graphics Chipsets. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. All information contained herein is subject to change without notice. Revision History Revision Date A A1 A2 B 07/04 08/05 08/05 10/05 B1 03/06 Comment Revision A Release Added 1362A and 1364A part number. Adjusted 64 pin A1 & A2 overlap. Added SiI 1362A & 1364A new power numbers. Updated PVCC1 Voltage range to 3.30V + 10%. Voltage Regulation for PVCC1 omitted for SiI 1362A & SiI 1364A. Included new QFN package dimensions and ordering number. (c) 2004-2006 Silicon Image. Inc. ii SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet TABLE OF CONTENTS General Description ..................................................................................................................................... 1 SiI 1362/A & SiI 1364/A Pin Diagrams........................................................................................................ 1 Functional Blocks......................................................................................................................................... 3 PanelLink TMDS Digital Core ..................................................................................................................... 3 SDVO Receiver Core.................................................................................................................................. 3 I2C Slave Interface and Display Detection.................................................................................................. 4 Electrical Specifications .............................................................................................................................. 5 Absolute Maximum Conditions ................................................................................................................... 5 Normal Operating Conditions ..................................................................................................................... 5 DC Digital I/O Specifications....................................................................................................................... 5 DC Specifications........................................................................................................................................ 6 AC Specifications........................................................................................................................................ 6 Input Timing Diagrams................................................................................................................................. 7 Pin Descriptions ........................................................................................................................................... 8 SDVO Receiver Core Pins.......................................................................................................................... 8 Configuration/Programming Pins................................................................................................................ 8 Differential Signal Data Pins ....................................................................................................................... 9 I2C Master Interface Pins ............................................................................................................................ 9 Factory Test Mode Pins .............................................................................................................................. 9 Power and Ground Pins............................................................................................................................ 10 Feature Information.................................................................................................................................... 11 I2C Slave Interface .................................................................................................................................... 11 Design Recommendations ........................................................................................................................ 12 EXT_SWING Selection ............................................................................................................................. 12 EXT_RES Selection.................................................................................................................................. 12 SDVO I2C Bus Interface............................................................................................................................ 12 DDC I2C Bus Interface .............................................................................................................................. 12 EEPROM I2C Bus Interface ...................................................................................................................... 13 PCB Ground Planes.................................................................................................................................. 13 Power Plane Sequencing and Switching .................................................................................................. 13 Voltage Ripple Regulation ........................................................................................................................ 13 Power Plane Filters................................................................................................................................... 16 Filter Capacitor and Ferrite Placement ................................................................................................. 16 Source Termination Resistors on Differential Outputs ............................................................................. 17 Transmitter Layout .................................................................................................................................... 18 Hot Plug Circuit ......................................................................................................................................... 20 Package Dimensions and Marking Specification.................................................................................... 21 64-pin TQFP Ordering Information ........................................................................................................... 21 64-pin QFN Ordering Information ............................................................................................................. 22 48-pin Ordering Information ...................................................................................................................... 23 SiI-DS-0112-B1 iii SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet LIST OF TABLES Table 1. SDVO Clock Multiplication ............................................................................................................... 4 Table 2. Absolute Maximum Conditions......................................................................................................... 5 Table 3. Normal Operating Conditions ........................................................................................................... 5 Table 4. DC Digital I/O Specifications ............................................................................................................ 5 Table 5. DC Specifications ............................................................................................................................. 6 Table 6. AC Specifications ............................................................................................................................. 6 Table 7. Power Regulator Circuit Suggestions ............................................................................................ 13 Table 8. Power Plane Filter Recommendations for SiI 1362/A & SiI 1364/A............................................... 16 Table 9. Routing Guidelines for DVI Traces................................................................................................. 19 LIST OF FIGURES Figure 1. SiI 1362/A Pin Diagram - 48-pin package ...................................................................................... 1 Figure 2. SiI 1364/A Pin Diagram - 64-pin package ...................................................................................... 2 Figure 3. Functional Block Diagram ............................................................................................................... 3 Figure 4. I2C Data Valid Delay (driving Read Cycle data).............................................................................. 7 Figure 5. RESET# Minimum Timing ............................................................................................................... 7 Figure 6. I2C Byte Read................................................................................................................................ 11 Figure 7. I2C Byte Write ................................................................................................................................ 11 Figure 8. Variation of Differential Swing versus REXT_SWING Value................................................................ 12 Figure 9. Suggested 3.42V Voltage Supply Circuit for SiI 1362 and SiI 1364 only...................................... 14 Figure 10. Suggested 5V Voltage Supply Circuit ......................................................................................... 14 Figure 11. Suggested 1.8V Voltage Supply Circuit ...................................................................................... 15 Figure 12. Suggested 2.5V Voltage Supply Circuit ...................................................................................... 15 Figure 13. Decoupling and Bypass Capacitor Placement............................................................................ 16 Figure 14. Differential Output Source Terminations .................................................................................... 17 Figure 15. Source Termination Layout Illustration ....................................................................................... 17 Figure 16. Example of Incorrect Differential Signal Routing ........................................................................ 18 Figure 17. Example of Correct Differential Signal Routing........................................................................... 19 Figure 18. Source Termination to DVI Connector Illustration....................................................................... 19 Figure 19. Recommended Hot Plug Connection.......................................................................................... 20 Figure 20. 64-pin TQFP Package Dimensions............................................................................................. 21 Figure 21. 64-pin QFN Package Dimensions and ePad Diagram ............................................................... 22 Figure 22. 48-pin LQFP Package Dimensions............................................................................................. 23 iv SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet General Description Features The SiI 1362/A & SiI 1364/A TMDS transmitter uses PanelLink(R) Digital technology to support displays ranging from VGA to UXGA resolutions in a single link interface. The chip supports the Intel-proprietary SDVO serial interface to provide a display interface to DVI monitors. * * * * * Designed explicitly to accommodate the ultra highspeeds needed for SDVO signaling, the SiI 1362/A & SiI 1364/A transmitter reduces pin count yet provides an upgrade path for future feature expansion. The innovative design of the SiI 1362/A & SiI 1364/A eases board design requirements as well. * * * * PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. * * * Scaleable Output Bandwidth: 25 - 165 megapixels per second SiI 1362/1364 fully compliant with Intel SDVO 1.0 SiI 1362A/1364A fully compliant with Intel SDVO 1.1 I2C Slave interface for access to internal registers Dual I2C pass-through interfaces for host I2C access of EDID (via DDC) and configuration EEPROM (on 64-pin package only) Monitor Detection supported through Hot Plug or Receiver Sense Low Power: 1.8V core operation; power down mode Cable Distance Support: greater than 10 meters DVI 1.0 compliant, with significantly greater margin than competitive solutions SiI 1362/A: 48-pin LQFP without EEPROM interface SiI 1364: 64-pin TQFP package with EEPROM interface SiI 1364A: 64-pin TQFP or QFN package with EEPROM interface. SiI 1362/A & SiI 1364/A Pin Diagrams SDVO Interrupt VCC PVCC2 EXT_SWING 28 27 26 25 29 PGND2 HTPLG 30 32 31 33 GND SDI+ 34 TEST SDI- 35 Clock VCC Blue EXT_RES SDVO Interface 36 Green SVCC Red Filter PLL SDR+ 37 24 AGND SDR- 38 23 TX2+ SGND 39 22 TX2- SDG+ 40 21 AVCC SDG- 41 20 TX1+ SVCC 42 19 TX1- SDB+ 43 18 AGND SDB- 44 17 TX0+ SGND 45 16 TX0- SDC+ 46 15 AVCC SDC- 47 14 TXC+ SPVCC 48 13 TXC- SiI 1362/A Tx 48-Pin LQFP (Top View) PVCC1 AGND SDADDC 12 SCLDDC VCC 9 GND 11 8 A1 I2C to DDC 10 6 7 SPGND SDSCL RESET# SDSDA 3 5 2 OVCC 4 1 I2C from SDVO Main TMDS PLL Figure 1. SiI 1362/A Pin Diagram - 48-pin package SiI-DS-0112-B1 1 DVI Interface SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet SDVO Interrupt RSVD5 GND TEST HTPLG VCC RSVD6 RSVD7 RSVD8 44 43 42 41 40 39 38 37 36 35 34 RSVD4 45 33 RSVD3 46 RSVD9 GND 47 PGND2 SDI- 48 SDI+ VCC Filter PLL 49 32 PVCC2 SVCC 50 31 EXT_SWING SDR+ 51 30 AGND SDR- 52 29 TX2+ SGND 53 28 TX2- SDG+ 54 27 AVCC SDG- 55 26 TX1+ SVCC 56 25 TX1- SDB+ 57 24 AGND SDB- 58 23 TX0+ SGND 59 22 TX0- SDC+ 60 21 AVCC SDC- 61 20 TXC+ SPVCC 62 19 TXC- SPGND 63 18 AGND OVCC 64 17 PVCC1 Red EXT_RES Green SDVO Interface Blue SiI 1364/A Tx 64-Pin TQFP or QFN (Top View) Clock 16 15 14 12 13 11 10 9 8 7 6 5 4 3 2 1 PGND1 VCC SCLROM SDAROM SDADDC SCLDDC GND VCC A1 SDSCL SDSDA GND RSVD2 RSVD1 RSVD0 RESET# I2 C to DDC I2 C from SDVO DVI Interface Main TMDS PLL I2 C to Config. PROM Figure 2. SiI 1364/A Pin Diagram - 64-pin package 2 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet TX2+ TX1+ TX0+ TXC+ SDADDC SCLDDC Functional Blocks SDAROM I2C Logic EXT_SWING EXT_RES SDB+ SDR+ SDG+ SDVO Receiver Core SDC+ HTPLG RESET# A1 A1 SCL SDSCL SDSDA SDA I2C Slave PanelLink TMDS Digital core SDI+ Registers & Configuration Logic Block TEST SCLROM Figure 3. Functional Block Diagram PanelLink TMDS Digital Core The PanelLink TMDS core encodes video information onto three TMDS differential data lines and the differential clock. Decoded video input data comes from the SDVO Receiver Core. A resistor tied to the EXT_SWING pin is used to control the TMDS swing amplitude. SDVO Receiver Core Data is input to the SiI 1362/A & SiI 1364/A by way of the SDVO bus. SDVO data is encoded, therefore this core decodes the data per the Intel specification before passing it to the TMDS Receiver Core. Refer to the Intel "Serial Digital Video Out (SDVO) Port" specification for further details. A resistor (value specified in the Pin Description section) must be connected between the EXT_RES pin and ground to set the SDVO circuit bias. The device may be powered down with an internal register. It is initialized or reset by using the RESET# pin. SiI-DS-0112-B1 3 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet The SDVO Clock rate will always fall between 100MHz and 200MHz. Anytime the effective PCLK is below 100MHz, the SDVO clock will be a multiple of the Pixel rate as listed in the Multiplier column of Table 1. Table 1. SDVO Clock Multiplication Mode Resolution (pixels) VGA SVGA XGA SXGA SXGA (Hi Ref) UXGA 640x480 800x600 1024x768 1280x1024 1280x1024 1600x1200 Refresh (Vsync) (Hz) 60 60 60 60 75 60 DVI CLK (MHz) Multiplier SDVO CLK (MHz) 25 40 65 108 135 162 X4 X4 X2 X1 X1 X1 100 160 130 108 135 162 I2C Slave Interface and Display Detection The SiI 1362/A & SiI 1364/A supports only I2C mode of operation. There is no strap option mode. The logic uses a slave I2C interface capable of running up to 1MHz for communication with the host chipset. This slave interface is 3.3V-tolerant and accepts 2.5V and 1.8V signaling as well. If the switching levels from the host are greater than 3.3V, then a voltage level shifter must be used. The SiI 1362/A & SiI 1364/A Tx provides I2C ports to communicate with a configuration EEPROM and the DDC bus with an attached monitor. The SDVO I2C port operates at 2.5V and does not require level shifters. The EEPROM I2C port operates at 3.3V level, via internal 3.3V pull ups, for direct connection to a 3.3V EEPROM. To operate the EEPROM I2C port at 5V an external 3.3V to 5V level shifter is required. The DDC I2C port is set to operate at 5V without requiring any level shifters. A connected display EDID may be detected using the DVI Hot Plug signal, through the HTPLG pin. A powered up attached receiver can be detected with the Receiver Sense logic internal to the SiI 1362/A & SiI 1364/A. The state of the detection may be read from the registers and can optionally be signaled to the host by an interrupt. For systems with multiple SDVO devices, pin A1 can be used to change the slave I2C address of the SiI 1362/A & SiI 1364/A. 4 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Electrical Specifications Absolute Maximum Conditions Absolute Maximum Conditions are defined as the worst-case condition the part will tolerate without sustaining damage. Permanent device damage may occur if absolute maximum conditions are exceeded. Proper operation under these conditions is not guaranteed. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Table 2. Absolute Maximum Conditions Symbol VI VO TJ TSTG Parameter All 1.8V Supply Voltages All 3.3V Supply Voltages Input Voltage Output Voltage Junction Temperature (with power applied) Min -0.3 -0.3 -0.3 -0.3 Storage Temperature -65 Typ Max 2.5 4.0 VCC+ 0.3 VCC+ 0.3 125 Units V V V V 150 C Max 1.8 + 10% 3.6 3.6 3.6 3.6 3.6 100 70 Units V V V V V V mVP-P 50 C/W 25 C/W 60 C/W C Normal Operating Conditions Table 3. Normal Operating Conditions Symbol Parameter All 1.8V Supply Voltages Analog supply AVCC Main PLL supply PVCC1 Filter PLL supply PVCC2 SDVO PLL supply SPVCC Output driver supply OVCC PLL Supply Voltage Noise Ambient Temperature (with power applied) VCCN TA JA-64QFP 64-pin Thermal Resistance (Junction to Ambient) JA-64QFN 64-pin Thermal Resistance (Junction to Ambient) JA-48 48-pin Thermal Resistance (Junction to Ambient) Notes: 1. 2. 3. 4. Min 1.8 - 10% 3.0 3.3 3.0 3.0 3.0 Typ 1.8 3.3 3.33or 3.452 3.33or 3.452 3.33 or 3.452 3.3 0 25 4 C Airflow at 0m/s. SiI 1362 and SiI 1364 only requirement 3.45V should be used when sharing the power supply with PVCC1. SiI 1362A and SiI 1364A can operate within 3.30V + 10% for all 3.30V power supply pins. SiI 1364A QFN Package only with ePad soldered to landing area on four-layer board. DC Digital I/O Specifications Under normal operating conditions unless otherwise specified. Table 4. DC Digital I/O Specifications Symbol VIH VIL VIH5V VIL5V VCINL VCIPL IIL Notes: 1. Parameter High-level Input Voltage - digital input pins Low-level Input Voltage - digital input pins High-level Input Voltage - 5V-tolerant pins Low-level Input Voltage - 5V-tolerant pins Input Clamp Voltage1 Input Clamp Voltage1 Input Leakage Current Conditions Min 2.0 -0.3 2.0 -0.3 ICL = -18mA ICL = 18mA -10 Typ Max VCC + 0.3 0.8 5.5 0.8 GND -0.8 VCC + 0.8 10 Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions. SiI-DS-0112-B1 5 Units V V V V V V A SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet DC Specifications Under normal operating conditions with REXT_SWING = 360 and source termination present unless otherwise specified. Table 5. DC Specifications Symbol IDOS IPDQ IPD18 Parameter Differential Output Short Circuit Current1 Conditions VOUT = 0V Quiet Power-down Current2 25C ambient, Vcc = 3.3V Standby mode3 Power-down Current 3 Min Typ 3 IPD33 ICCT18 1.8V Transmitter Supply Current Typical4 3.3V Transmitter Supply Current Typical4 5 mA mA 320 mA 80/1106 mA mA 50/806 Worst Case5 Units A mA 5/0.56 240 Worst Case5 ICCT33 Max 5 mA All SDVO-related DC specifications are met. SDVO specifications are Intel-proprietary and are not published here. Notes: 1. 2. 3. 4. 5. 6. Guaranteed by Characterization. Quiet Power-down current measured with no transmitter input pins toggling, but includes source termination current. Power-down current measured with device in D3 state and no SDVO input present. Typical uses a pattern containing a gray scale area, a checkerboard area and a text area. Worst Case uses a pattern containing a black and white checkerboard; each checker is one pixel wide. SiI 1362A and SiI 1364A power consumption only. AC Specifications Under normal operating conditions unless otherwise specified. Table 6. AC Specifications Symbol FCIP TI2CDVD Parameter Internal IDCK Frequency SDA Data Valid Delay from SCL high to low transition Conditions one pixel per clock CL = 400pf CL = 10pf Min 25 Typ Max 165 1000 300 Units MHz ns Figure Figure 4 Notes 2 1 TRESET ISEL/RST# Signal Low Time 50 s Figure 5 required for valid reset All SDVO-related AC specifications are met by design but are Intel-proprietary and are not published here. Notes: 1. 2. 3. 2 All Standard mode (100kHz and 400kHz) & SDVO 1MHz I C timing requirements are guaranteed by design. Minimum frequency (maximum IDCK period) defined per DVI 1.0 Specification, section 2.3.1. Typical VCC is defined at 3.3V. 6 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Input Timing Diagrams All SDVO timings are met according to Intel specifications and are not illustrated here. SDA TI2CDVD SCL Figure 4. I2C Data Valid Delay (driving Read Cycle data) VIH VCC RESET# TRESET Figure 5. RESET# Minimum Timing Note that VCC must be stable between its limits for Normal Operating Conditions for TRESET before RESET# is high. SiI-DS-0112-B1 7 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Pin Descriptions SDVO Receiver Core Pins Pin Name SDR+ SDR- SDG+ SDG- SDB+ SDB- SDC+ SDC- 64-pin # 51 52 54 55 57 58 60 61 48-pin # 37 38 40 41 43 44 46 47 Type Analog SDI+ SDI- 46 47 32 33 Analog EXT_RES 49 35 Analog Analog Description SDVO Input Data. This bus receives encoded serial data from the host graphics chipset. The signals are AC-coupled through capacitors that are typically present on the motherboard and therefore not needed on an ADD2 card. SDVO Input Clock. The SDVO clock signal comes in on this signal pair. The signals are ACcoupled through capacitors that are typically present on the motherboard and therefore not needed on an ADD2 card. Interrupt. Enabled interrupts are transmitted to the host chipset on this signal pair. The signals are AC-coupled through capacitors that are typically NOT present on the motherboard, so separate 100nF coupling capacitors are required on these pins on an ADD2 card. External Resistor. A resistor value 1.0K is connected from this pin to SGND to generate a reference bias current for the SDVO analog circuits. Configuration/Programming Pins Pin Name 64-pin # 48-pin # Type RESET# 1 2 Digital In SDSCL 7 5 SDSDA 6 4 A1 8 6 HTPLG 39 29 Description Reset. When LOW, the chip logic is reset and all register values are set to their initial default state. In/Out SDVO Register Access I2C Clock. 5VThis 5V-tolerant pin operates with an external pull-up resistor to 1.8tolerant 3.3V. It is typically pulled up to 2.5V with a 5.6K resistor for proper operation with the SDVO host. In/Out SDVO Register Access I2C Data. 5VThis 5V-tolerant pin uses an open collector output driver and requires a tolerant pull-up resistor to 1.8-3.3V for proper operation. It is typically pulled up to 2.5V with a 5.6K resistor for proper operation with the SDVO host. Digital Slave I2C Address bit A1. In This pin selects bit 1 of the I2C slave address. It has an internal weak pull-down resistor, so if the pin is left unconnected the address will default to 0x70. LOW: Address = 0x70 HIGH: Address = 0x72 Digital Hot Plug input. In This pin is used to monitor the "Hot Plug" detect signal (refer to the DVI Specification). This input is 5V-tolerant and includes an internal pull 5Vtolerant down. 8 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Differential Signal Data Pins Pin Name TX0+ TX0- TX1+ TX1- TX2+ TX2- TXC+ TXC- 64-pin # 23 22 26 25 29 28 20 19 48-pin # 17 16 20 19 23 22 14 13 Type Analog Description TMDS Low Voltage Differential Signal output data pairs. Analog TMDS Low Voltage Differential Signal output clock pair. EXT_SWING 31 25 Analog Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor sets the amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing and vice versa. Recommended value is 360, 5% tolerance used with source termination as described in the Design Recommendations section. This recommendation may change with future silicon revisions. Type Description I2C Master Interface Pins Pin Name 64-pin # 48-pin # SDADDC 12 9 SCLDDC 11 8 SDAROM 13 na SCLROM 14 na In/Out DDC Access I2C Data. 5VThis pin should be connected to the DDC I2C Data pin on the DVI tolerant connector. It uses an open collector output driver and requires a 2.2K pull-up resistor to 5V for proper operation. In/Out DDC Access I2C Clock. 5VThis pin should be connected to the DDC I2C Clock pin on the DVI tolerant connector. It uses an open collector output driver and requires a 2.2K pull-up resistor to 5V for proper operation. In/Out ROM Access II2C Data. Only available on the 64-pin SiI 1364/A, this pin should be connected to the EEPROM I2C Data pin. It uses an open collector output driver. This pin incorporates an internal pull-up resistor to 3.3V and does not require an external 3.3V pull up. Out ROM Access I2C Clock. Only available on the 64-pin SiI 1364/A, this pin should be connected to the EEPROM I2C Clock pin. It uses an open collector output driver. This pin incorporates an internal pull-up resistor to 3.3V and does not require an external 3.3V pull up. Factory Test Mode Pins Pin Name 64-pin # 48-pin # Type TEST 40 30 Digital In RSVD0-9 2, 3, 4, 44, 43, 42, 37,36, 35, 34 na Digital In/Out SiI-DS-0112-B1 Description Factory Test Mode strap. Tie this pin LOW for normal operation. Reserved Factory Test Mode signals. Tie to GND or leave as No Connects. 9 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Power and Ground Pins Pin Name VCC AVCC PVCC1 64-pin # 9, 15, 38, 48 21, 27 17 48-pin # 10, 28, 34 15, 21 11 Type Power Power Power PVCC2 32 26 Power SVCC SPVCC 50, 56 62 36, 42 48 Power Power OVCC GND 64 5, 10, 41, 45 Power Ground AGND PGND1 PGND2 SGND SPGND 18, 24, 30 16 33 53, 59 63 1 7, 31 (39, 45) 12, 18, 24 (12) 27 39, 45 3 Description Digital Core VCC, must be set to 1.8V nominal. Analog VCC for TMDS Tx Core, must be set to 3.3V nominal. TMDS Main PLL Analog VCC, must be set to 3.3-3.45V nominal for SiI1362 and SiI1364 only. SiI1362A and SiI1364A can be set to 3.3V nominal. Filter PLL Analog VCC, must be set to 3.3-3.45V nominal for SiI1362 and SiI1364 only. SiI1362A and 1364A can be set to 3.3V nominal. SDVO Analog VCC, must be set to 1.8V nominal. SDVO PLL Analog VCC, must be set to 3.3-3.45V nominal for SiI1362 and SiI1364 only. SiI1362A and 1364A can be set to 3.3V nominal. Digital I/O VCC, must be set to 3.3V nominal. Digital Ground (shared with SDVO Ground on 48-pin package) Ground Ground Ground Ground Ground Analog Ground. TMDS Main PLL Ground (shared with AGND on 48-pin package) TMDS Filter PLL Ground. SDVO Analog Ground SDVO PLL Ground. Notes 1. Connect all ground pins to main PCB ground plane. Do not split planes. 2. Apply separate filters to each PLL VCC/GND pair as noted in the Design Recommendations section. 10 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Feature Information I2C Slave Interface The SiI 1362/A & SiI 1364/A slave state machine does not require an internal clock. It supports byte-read and byte-write operations, and also burst read/write to both the internal registers and to the EEPROM and DDC. The 7-bit binary address of the I2C machine is "0111 00A1R" where R =1 sets a read operation while R=0 sets a write operation. Pin A1 by default has an internal pull down resistor. Therefore, the port address is 0x70/0x71 by default. To set the I2C address for the SiI 1362/A & SiI 1364/A to 0x72/0x73, pin A1 must be pulled up through a resistor to VCC. The interface also accepts accesses at ports 0xA0/0xA1 that are destined for the EEPROM or DDC. A W 1 R AR 1 D S A C K A C K Bus Activity : SDVO I2C Slave Address Stop S Internal Register Address P A C K Data Data Stop SDA Line Slave Address Start Bus Activity : Master Start See Figure 6 for a byte read operation and Figure 7 for a byte write operation. N o A C K Bus Activity : Master Start Figure 6. I2C Byte Read SDA Line S Bus Activity : SDVO I2C Slave Address Internal Register Address AW 1 R P A C K A C K A C K Figure 7. I2C Byte Write Multiple data bytes may be transferred in each transaction, regardless of whether a read or a write is taking place. The operations will be similar to those in the figures except that there will be more than one data phase. An ACK will follow each byte, except the last byte in a read operation. Byte addresses increment, with the least significant byte transferred first, and the most significant byte last. For more detailed information on I2C protocols refer to the I2C Bus Specification version 2.1 available from Philips Semiconductors Inc. SiI-DS-0112-B1 11 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Design Recommendations EXT_SWING Selection The recommended REXT_SWING resistor value for the EXT_SWING pin is provided in the Pin Descriptions section. This value can be adjusted as needed to optimize the DVI signal swing levels according to the needs of the application. This adjustment might become necessary, for example, when deviating from the recommended source termination values (described in the Source Termination Resistors on Differential Outputs section) to optimize for a specific board layout. Figure 8 illustrates the relationship of the REXT_SWING resistor to the differential swing voltage, across representative extremes of the chip. Differential Swing (T_3.3V_RT) 1500 1400 1300 Differential Vswing (mV) 1200 T1-3.3V_RT 1100 T2-3.3V_RT 1000 T3-3.3V_RT T4-3.3V_RT 900 T5-3.3V_RT 800 T6-3.3V_RT 700 T7-3.3V_RT T8-3.3V_RT 600 T9-3.3V_RT 500 T10-3.3V_RT 400 T11-3.3V_RT T12-3.3V_RT 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 1100 Rext (Ohm) Figure 8. Variation of Differential Swing versus REXT_SWING Value EXT_RES Selection The resistor value specified in the Pin Descriptions section must connect the EXT_RES pin to SGND. The resistor is used to generate a reference bias current for SDVO analog circuits. SDVO I2C Bus Interface To program the SiI 1362/A & SiI 1364/A via its slave I2C bus connection with the SDVO host, SDSDA and SDSCL swing level should be 2.5V. This is the standard SDVO signaling level for this interface. These pins should be pulled to 2.5V with 5.6K resistors. DDC I2C Bus Interface The VESA DDC Specification (available at http://www.vesa.org) defines the DDC interconnect bus to be a 100kbit/s 5V signaling path. The DDC I2C pins on the SiI 1362/A & SiI 1364/A Tx chip are 5V-tolerant. Therefore, board designers can connect the pins without using a level-shifting circuit. These pins should be pulled to 5V with 2.2K resistors. If the host system is using a DVI-I connector to support both a DVI and a VGA (analog) connection, only the host VGA I2C interface should be connected to the DVI-I connector. The DDC interface of the SiI 1362/A & SiI 1364/A Tx chip should be tied only to 2.2K resistors to 5V but should not connect to the DVI-I connector. 12 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet EEPROM I2C Bus Interface The 64-pin version of the SiI 1362/A & SiI 1364/A Tx provides a communications path from the SDVO host to a configuration EEPROM. The interface can support up to 400Kb/s with commonly available EEPROMs. The interface pins are internally pulled up to 3.3V, and therefore do not require external pull-up resistors. PCB Ground Planes All ground pins on the device should be connected to the same, contiguous ground plane in the PCB. This helps to avoid ground loops and inductances from one ground plane segment to another. Such low-inductance ground paths are critical for return currents, which affect EMI performance. The entire ground plane surrounding the PanelLink transmitter should be in one piece and include the ground vias for the DVI connector. Power Plane Sequencing and Switching As with any device using multiple power rails, the SiI 1362/A & SiI 1364/A Tx employs ESD protection diodes that can allow a current flow between the 3.3V and 1.8V planes. No special sequencing or voltage ramping precautions are necessary as long as both planes reach their nominal operating voltage within a few seconds of each other. However, if the 1.8V plane voltage remains greater than any 3.3V plane voltage by more than one diode drop (0.7V), there will be a continuous current flow through the protection diodes that could damage the device over time. For this reason, it is recommended that the 1.8V power plane voltage not be allowed to exceed any 3.3V power plane voltage by more than 0.7V under any steady-state operating condition. Voltage Ripple Regulation The power supply to PVCC pins is very important to the proper operation of the transmitter. Table 7 provides simple regulator circuits that are appropriate for each chip power plane. Please note that SiI 1362A & SiI 1364A do not require 3.45V regulation and as such designers can omit the Voltage Regulation component and use the 3.30V power supply available from the motherboard. Tx Sample regulator circuits are shown in the figures noted. Note that alternative voltage regulator circuits should be considered only if they meet the LM317 standards of line/load regulation. Table 7. Power Regulator Circuit Suggestions Voltage to be Regulated 3.45V (For SiI 1362 /SiI 1364 only) Max current 3.3V 20mA 5V 1.8V 55mA 320mA 2.5V 10mA SiI-DS-0112-B1 60mA Power Plane, % of Total Load PVCC1: 60-75% PVCC2: 5-15% SPVCC: 15-35% Voltage Regulation Description 12V to 3.42 V Active Voltage Regulator Components LM317EMP Figure 9 AVCC: 5-15% OVCC: 80-95% external SVCC: 70-85% VCC: 25-35% external Use available 3.3V none -- 12V to 5V 3.3V to 1.8V, Low Drop Out regulation 3.3V to 2.5V LM317LM LM1117_1.8V Figure 10 Figure 11 Simple Voltage Divider R1= 316 1%, R2 = 1.0K 1% Figure 12 13 Figure SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet LM317EMP Vin 12V Vout 3.42V Vin Vout ADJ 240 1% 412 1% Figure 9. Suggested 3.42V Voltage Supply Circuit for SiI 1362 and SiI 1364 only LM317L Vin 12V Vout 5V Vin Vout ADJ 240 1% 732 1% Figure 10. Suggested 5V Voltage Supply Circuit 14 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Vin 3.3V LM1117-1.8 Vin Vout 1.8V Vout GND Figure 11. Suggested 1.8V Voltage Supply Circuit Vout 2.5V Vin 3.3V 316 1% 1K 1% Figure 12. Suggested 2.5V Voltage Supply Circuit SiI-DS-0112-B1 15 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Power Plane Filters Recommended power plane filtering is shown in Table 8. The value of the capacitors is chosen to approximately cover the range of 162.5MHz to 2.5GHz for high frequency noise. Any higher frequency noise will be filtered by the inherent capacitance of the trace line followed by internal high frequency capacitors in the SiI 1362/A & SiI 1364/A Tx. Each group of pins should have one Ferrite whose impedance value must be greater than 100 but smaller than 300. Table 8. Power Plane Filter Recommendations for SiI 1362/A & SiI 1364/A Power Supply Component Applications High Frequency C1 1nF - One per pin Mid Band C2 0.1uF - One per pin OVCC None required 0.1uF - One per pin PVCC1 1nF - Two per pin 1nF - Two per pin 1nF - Two per pin 1nF - One per pin 0.1uF - Two per pin 0.1uF - Two per pin 0.1uF - Two per pin 0.1uF - One per pin 1nF - One per pin 0.1uF - One per pin AVCC PVCC2 SPVCC SVCC VCC Storage C3 Ferrite Bead and Voltage Regulator One Ferrite Bead 10uF - One shared for two AVCC pins 10uF - One on OVCC None required None required Regulator required, shared by PVCC1, PVCC2 and SPVCC. Each power plane requires its own Ferrite Bead None required None required 10uF - One shared for three SVCC pins 10uF - One shared for all VCC pins One Ferrite Bead One Ferrite Bead Filter Capacitor and Ferrite Placement Designers should include decoupling and bypass capacitors at each power pin in the layout. Place these components as close as possible to the PanelLink device pins, and avoid routing through vias if possible, as shown in Figure 13, which is representative of the various types of power pins on the transmitter. Ensure that the correct Power and Ground pin are coupled with the filter capacitors as illustrated in Figure 13. For example, PVCC1 should have PGND1 as its ground pin and PVCC2 should have PGND2 as its ground pin. Note that for the 48-pin package, pin 12 should be used for the PGND1 capacitor connection. VCC C1 C2 L1 VCC Ferrite GND C3 Via to GND Figure 13. Decoupling and Bypass Capacitor Placement 16 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Source Termination Resistors on Differential Outputs Source termination, consisting of a 300 resistor and a 0.1F capacitor, should be used on the differential outputs of the SiI 1362/A & SiI 1364/A to improve signal swings. See Figure 14 for an illustration. Repeat the circuit for each of the four differential output pairs: TX0, TX1, TX2, TXC. Note that the specific value for the source termination resistor and capacitor will depend on the PCB layout and construction. Different values may be needed to create the best DVI-compliant output waveforms. TX0+ 300 TX0TX1+ 300 0.1uF 300 0.1uF 300 0.1uF TX2TX3+ TX3TXC+ TXC0.1uF Figure 14. Differential Output Source Terminations Source termination suppresses signal reflection to prevent non-DVI compliant receivers from erroneously sampling the TMDS signals when operating at high frequencies (beyond ~135MHz). The impact on DVI compliant receivers is minimal. Therefore Silicon Image recommends source termination for applications at all frequencies. C R Detail of Source termination (magnified) R and C 0603 size components installed. Figure 15. Source Termination Layout Illustration SiI-DS-0112-B1 17 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Note that the capacitor is required to meet DVI idle mode DC offset requirements and must not be omitted. Note also that the signal suppression requires the REXT_SWING value to be changed. Power consumption will be slightly higher when using source termination. The layout shown has been developed to minimize trace stubs on the differential TMDS lines, while providing pads for the source termination components (left-hand magnified view). Source termination components should be placed close to the transmitter pins. The resistor and capacitor are shown installed on the pads provided (right-hand magnified view). Transmitter Layout The routing for the SiI 1362/A & SiI 1364/A chip is relatively simple since no spiral skew compensation is needed. However, a few small precautions are required to achieve the full performance and reliability of DVI. The Transmitter can be placed fairly far from the output connector, but care should be taken to route each differential signal pair together and achieve impedance of 100 between the differential signal pair. However, note that the longer the differential traces are between the transmitter and the output connector, the higher the chance that external signal noise will couple onto the low-voltage signals and affect image quality. Do not split or have asymmetric trace routing between the differential signal pair. Vias are very inductive and can cause phase delay if applied unevenly within a differential pair. Vias should be minimized or avoided if possible by placing all differential traces on the top layer of the PCB. Figure 16 illustrates an incorrect routing of the differential signal from the SiI 1362/A & SiI 1364/A to the DVI connector. SiI 1362 Figure 16. Example of Incorrect Differential Signal Routing Figure 17 illustrates the correct method to route the differential signal from the SiI 1362/A & SiI 1364/A to the DVI connector. Figure 18 illustrates recommended routing for differential traces at the DVI connector. 18 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet SiI 1362 Figure 17. Example of Correct Differential Signal Routing In addition to following the trace routing recommendations, length differences between intra-pair traces and interpair traces should be controlled to minimize DVI skew. Spacing between inter-pair DVI traces should be observed to reduce trace-to-trace couplings. For example, having wider gaps between inter-pair DVI traces will minimize noise coupling. It is also strongly advised that ground not be placed adjacent to the DVI traces on the same layer. Table 9 lists the recommended limits for the parameters listed above. Table 9. Routing Guidelines for DVI Traces Parameter Max Intra-Pair (differential pair) Length Inter-Pair (differential pair to differential pair) Length +0.75" +3" Min Recommended Inter-pair Trace Separation Based on 2 Layer Board Recommended Inter- pair Trace Separation Based on 4 Layer Board 2x trace width 2x trace width The layout in Figure 18 illustrates an optimized ADD2 Card with source termination and DVI connector mapping that follows the guidelines listed above. The trace length from the SiI 1362/A & SiI 1364/A to the DVI connector can be long; however, it is strongly recommended that the intra-pair and inter-pair trace lengths follow the guidelines provided above. Figure 18. Source Termination to DVI Connector Illustration SiI-DS-0112-B1 19 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Hot Plug Circuit The Hot Plug pin on the DVI connector carries a 5V return signal from the monitor to indicate that its EDID is available for reading. The SiI 1362/A & SiI 1364/A chip can indicate a display-attached status) or generate an interrupt by monitoring this pin. The HTPLG input of the chip is 5V-tolerant. However, a protection circuit such as that shown in Figure 19 is recommended to bring the DVI connector hot plug detect signal to the HTPLG pin on the SiI 1362/A & SiI 1364/A. 5V Optional ESD protection diodes (1N4148 typ.) SiI 1362/4 HTPLG input pin Hot Plug Detect pin from DVI Connector 1-5k Figure 19. Recommended Hot Plug Connection Receiver sense indicates that a powered monitor is attached, but will not indicate the presence of a monitor that is powered off. Therefore, in this default configuration the host system must read EDID at power-up regardless of the attach state reported by the SiI 1362/A & SiI 1364/A device, and must re-read EDID any time the attach state changes. The chip defaults to using the receiver sense function, not the HTPLG input, for display-attached status after a Reset. However, Intel SDVO drivers automatically initializes the SiI 1362/A & SiI 1364/A Tx to support the Hot Plug function. 20 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet Package Dimensions and Marking Specification 64-pin TQFP Ordering Information Part Numbers of Universal package for both Standard and Pb-free applications: SiI 1364 Tx (SDVO 1.0 Compliant): SiI1364CTU SiI 1364A Tx (SDVO 1.1 Compliant): SiI1364ACTU JEDEC Package Code MS026-ACD L1 typ TMDS(R) PanelLink(R) E1 Device # Lot # Date Code Revision Code F1 SiINNNNLCTU LLLLLL.LLLL YYWW TTTTTTm A A1 A2 D1 E1 F1 G1 L1 b c e Thickness Stand-off 0.15 Body Thickness 1.00 Body Size 10.00 Body Size 10.00 Footprint 12.00 Footprint 12.00 Lead Length 1.00 Lead Width 0.20 Lead Thickness Lead Pitch G1 c A2 Legend SiINNNNLCTU A1 e b LLLLLL.LLLL YY WW TTTTTT m Figure 20. 64-pin TQFP Package Dimensions SiI-DS-0112-B1 21 1.05 0.27 0.20 0.50 Dimensions in millimeters. Overall thickness A=A1+A2. D1 max 1.20 Description Device number SiI1364CTU or SiI1364ACTU Lot Number Year of Mfr Week of Mfr Trace Code Maturity Code SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet 64-pin QFN Ordering Information Part Number of Universal package for both Standard and Pb-free applications: SiI 1364A Tx(SDVO 1.1 Compliant): SiI1364ACNU JEDEC Package Code MO-220 typ A A1 A2 D E L1 b e TMDS(R) PanelLink(R) E Device # Lot # Date Code Revision Code SiIxxxxCNU LLLLLL.LLLL YYWW TTTTTTm Thickness max 0.90 Stand-off 0.05 Body Thickness .65 Body Size 9.00 Body Size 9.00 Terminal Length 0.40 Terminal Width 0.25 Terminal Pitch 0.50 0.70 0.30 Dimensions in millimeters. Overall thickness A=A1+A2. D Universal Package: SiIxxxxCNU A2 e b A1 Legend LLLLLL.LLLL YY WW TTTTTT m Description Lot Number Year of Mfr Week of Mfr Trace Code Maturity Code ePad Dimensions E2 typ D2 E2 T ePad Height ePad Width Tolerance max 6.30 6.30 0.05 Dimensions in millimeters. ePad is centered on the package center lines. D2 Figure 21. 64-pin QFN Package Dimensions and ePad Diagram 22 SiI-DS-0112-B1 SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet 48-pin Ordering Information Part Numbers of Universal package for both Standard and Pb-free applications: SiI 1362 Tx (SDVO 1.0 Compliant): SiI1362CLU SiI 1362A Tx (SDVO 1.1 Compliant): SiI1362ACLU L1 JEDEC Package Code MS026-BBC typ TMDS(R) PanelLink(R) Device # Lot # Date Code Revision Code SiINNNNLCLU LLLLLL.LLLL YYWW TTTTTTm E1 F1 D1 G1 A A1 A2 D1 E1 F1 G1 L1 b c e Thickness Stand-off 0.15 Body Thickness 1.40 Body Size 7.00 Body Size 7.00 Footprint 9.00 Footprint 9.00 Lead Length 1.00 Lead Width 0.20 Lead Thickness Lead Pitch A2 A1 e b Legend SiINNNNLCLU LLLLLL.LLLL YY WW TTTTTT m Figure 22. 48-pin LQFP Package Dimensions SiI-DS-0112-B1 23 1.45 0.27 0.20 0.50 Dimensions in millimeters. Overall thickness A=A1+A2. c max 1.60 Description Device number SiI1362CLU or SiI1362ACLU Lot Number Year of Mfr Week of Mfr Trace Code Maturity Code SiI 1362/A & SiI 1364/A PanelLink Transmitter Data Sheet (c) 2004-2006 Silicon Image. Inc. Tel: Fax: E-mail: Web: Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA 24 (408) 616-4000 (408) 830-9530 salessupport@siimage.com www.siliconimage.com SiI-DS-0112-B1