TQFN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
45
21
22
23
24
25
26
27
28
31
30
29
49
50
51
56
55
54
53
52
40
39
38
37
36
35
34
33
32
44
43
42
41
48
46
47
GND
A0
A1
VCC
NC
GND
A2
A3
GND
VCC
A4
A5
GND
A6
A7
GND
SEL
VCC
A8
A9
0B1
1B1
0B2
1B2
GND
2B1
3B1
2B2
3B2
GND
VCC
4B1
5B1
4B2
5B2
GND
6B1
7B1
6B2
7B2
VCC
GND
NC
GND
NC
NC
VCC
GND
GND
8B1
9B1
GND
8B2
9B2
VCC
GND
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
5-CHANNEL DIFFERENTIAL 10:20 MULTIPLEXER SWITCH FOR DVI/HDMI APPLICATIONS
Check for Samples: TS3DV520
1FEATURES
• Compatible With HDMI v1.2a (Type A) DVI 1.0
High-Speed Digital Interface
– Wide Bandwidth of Over 1.65 Gbps
(Bandwidth 2.4 Gbps Typ)
– 165-MHz Speed Operation
– Serial Data Stream at 10× Pixel Clock Rate
– Supports All Video Formats up to 1080p
and SXGA (1280 × 1024 at 75 Hz)
– Total Raw Capacity 4.95 Gbps (Single Link)
– HDCP Compatible
• Low Crosstalk (XTALK = –41 dB Typ)
• Low Bit-to-Bit Skew (tsk(o) = 0.1 ns Max)
• Low and Flat ON-State Resistance
(ron =6ΩMax, ron(flat) = 0.5 ΩTyp)
• Low Input/Output Capacitance
(CON = 7.8 pF Typ)
• Rail-to-Rail Switching on Data I/O Ports
(0 to 5 V)
• VCC Operating Range From 3 V to 3.6 V
• Ioff Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II) NC – No internal connection
– 1000-V Charged-Device Model (C101)
APPLICATIONS
• DVI/HDMI Signal Switching
• Differential DVI, HDMI Signal Multiplexing for
Audio/Video Receivers and High-Definition
Televisions (HDTVs)
• 10/100/1000 Base-T Signal Switching
• Hub and Router Signal Switching
DESCRIPTION/ORDERING INFORMATION
The TS3DV520 is a 20-bit to 10-bit multiplexer/demultiplexer digital video switch with a single select (SEL) input.
SEL controls the data path of the multiplexer/demultiplexer. The device provides five differential channels for
digital video signal switching. This device can also be used to replace mechanical relays in LAN applications and
allows for signals to be routed from a 10/100/1000 Base-T transceiver to the RJ-45 connectors in laptops or
docking stations.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DigitalTV
HDMI
Receiver
TS3DV520
DVDPlayer
STB
DigitalTV
HDMI
Receiver
TS3DV520
DVDPlayer
STB
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
This device provides low and flat ON-state resistance (ron) and excellent ON-state resistance match. Low
input/output capacitance, high bandwidth, low skew, and low crosstalk among channels make this device suitable
for various digital video applications, such as DVI and HDMI.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
Table 1. ORDERING INFORMATION(1)
TAPACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 85°C TQFN Tape and reel TS3DV520RHUR SD520
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
INPUT INPUT/OUTPUT FUNCTION
SEL An
L nB1An= nB1nB2high-impedance mode
H nB2An= nB2nB1high-impedance mode
PIN DESCRIPTION
NAME DESCRIPTION
AnData I/O
nBmData I/O
SEL Select input
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Product Folder Link(s): TS3DV520
A00B1
0B2
SEL
248
46
17
1B2
45
A11B1
347
A22B1
2B2
7 43
41
3B2
40
A33B1
8 42
A44B1
4B2
11 37
35
5B2
34
A55B1
12 36
A66B1
6B2
14 32
30
7B2
29
A77B1
15 31
A88B1
8B2
19 22
25
26
A99B1
20 23
9B2
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
LOGIC DIAGRAM (POSITIVE LOGIC)
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TS3DV520
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VIN Control input voltage range(2) (3) –0.5 7 V
VI/O Switch I/O voltage range(2) (3) (4) –0.5 7 V
IIK Control input clamp current VIN < 0 –50 mA
II/OK I/O port clamp current VI/O < 0 –50 mA
II/O ON-state switch current(5) ±128 mA
Continuous current through VCC or GND ±100 mA
θJA Package thermal impedance(6) 31.8 °C/W
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for VI/O.
(5) IIand IOare used to denote specific conditions for II/O.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN MAX UNIT
VCC Supply voltage 3 3.6 V
VIH High-level control input voltage (SEL) 2 5.5 V
VIL Low-level control input voltage (SEL) 0 0.8 V
VI/O Input/output voltage 0 5.5 V
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Product Folder Link(s): TS3DV520
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
Electrical Characteristics(1)
for high-frequency switching over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
VIK SEL VCC = 3.6 V, IIN = –18 mA –0.7 –1.2 V
IIH SEL VCC = 3.6 V, VIN = VCC ±1 μA
IIL SEL VCC = 3.6 V, VIN = GND ±1 μA
Ioff VCC = 0, VO= 0 to 3.6 V, VI= 0 1 μA
ICC VCC = 3.6 V, II/O = 0, Switch ON or OFF 250 500 μA
CIN SEL f = 1 MHz, VIN = 0 2 2.5 pF
COFF B port VI= 0, f = 1 MHz, Outputs open, Switch OFF 2.5 3 pF
CON VI= 0, f = 1 MHz, Outputs open, Switch ON 7.8 8.5 pF
ron VCC = 3 V, 1.5 V ≤VI≤VCC, IO= –40 mA 3.5 6 Ω
ron(flat) (3) VCC = 3 V, VI= 1.5 V and VCC, IO= –40 mA 0.5 Ω
Δron (4) VCC = 3 V, 1.5 V ≤VI≤VCC, IO= –40 mA 0.4 1 Ω
(1) VI, VO, II, and IOrefer to I/O pins. VIN refers to the control inputs.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.
(3) ron(flat) is the difference of ron in a given channel at specified voltages.
(4) Δron is the difference of ron from center (A4, A5) ports to any other port.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, RL= 200 Ω, CL= 10 pF
(unless otherwise noted) (see Figure 4 and Figure 5)
FROM TO
PARAMETER MIN TYP (1) MAX UNIT
(INPUT) (OUTPUT)
tpd (2) A or B B or A 0.25 ns
tPZH, tPZL SEL A or B 0.5 15 ns
tPHZ, tPLZ SEL A or B 0.5 9 ns
tsk(o) (3) A or B B or A 0.05 0.1 ns
tsk(p) (4) 0.05 0.1 ns
(1) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
(3) Output skew between center port (A4to A5) to any other port
(4) Skew between opposite transitions of the same output in a given device |tPHL – tPLH|
Dynamic Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TYP (1) UNIT
XTALK RL= 100 Ω, f = 250 MHz, See Figure 7 –41 dB
OIRR RL= 100 Ω, f = 250 MHz, See Figure 8 –39 dB
BW RL= 100 Ω, See Figure 6 1.2 GHz
(1) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TS3DV520
−100
−80
−60
−40
−20
0
Frequency (MHz)
0.1 11000
10 100
Attenuation (dB)
10,000
−12
−10
−8
−6
−4
−2
0
Frequency (MHz)
0.1 1 100010 100
Frequency (MHz)
10,000
Gain (dB)
0
1
2
3
4
5
6
0 1 2 3 4 5 6
VCOM (V)
ron (W)
−100
−80
−60
−40
−20
0
Frequency (MHz)
0.1 11000
10 100
Attenuation (dB)
10,000
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
OPERATING CHARACTERISTICS
Figure 1. Gain/Phase vs Frequency Figure 2. OFF Isolation vs Frequency
Figure 3. Crosstalk vs Frequency Figure 4. ron and V0vs V1
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Product Folder Link(s): TS3DV520
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
APPLICATION INFORMATION
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TS3DV520
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
50 Ω
VG1
VCC
DUT
50 Ω
VIN
50 Ω
VG2 50 Ω
VI
TEST RL
S1 V∆
CL
VCC VI
tPLZ/tPZL 3.3 V ± 0.3 V 2 × VCC 200 ΩGND 10 pF 0.3 V
Input Generator
Input Generator VO
tPHZ/tPZH 3.3 V ± 0.3 V GND 200 ΩVCC 10 pF 0.3 V
tPZL
VOH −0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
Output Control
(VIN)1.25 V 2.5 V
VOH
VOL +0.3 V
VOH
VOL
0 V
1.25 V
tPZH
tPLZ
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2 y VCC
(see Note B)
VOL
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
Figure 5. Test Circuit and Voltage Waveforms
8Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TS3DV520
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
VOH
VOL
VOLTAGE WAVEFORMS
OUTPUT SKEW (tsk(o))
Data Out at
YB1 or YB2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
50 Ω
VG1
VCC
DUT
50 Ω
VIN
50 Ω
VG2 50 Ω
VI
TEST RL
S1 V∆
CL
3.3 V ± 0.3 V
VCC VI
tsk(p)
tsk(o)
3.3 V ± 0.3 V
Open
Open
200 Ω
200 Ω
VCC or GND
VCC or GND
10 pF
10 pF
Input Generator
Input Generator VO
(VOH + VOL)/2
VOH
VOL
Data Out at
XB1 or XB2(VOH + VOL)/2
3.5 V
1.5 V
Data In at
Ax or Ay2.5 V
tPLHx tPHLx
tsk(o) tsk(o)
tPLHy tPHLy
tsk(o) = |tPLHy − tPLHx| or |tPHLy − tPHLx|
VOH
VOL
VOLTAGE WAVEFORMS
PULSE SKEW (tsk(p))
Output (VOH + VOL)/2
Input 2.5 V
tPLH tPHL
tsk(p) = |tPLH − tPLH|
3.5 V
1.5 V
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION
(Skew)
Figure 6. Test Circuit and Voltage Waveforms
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TS3DV520
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 7. Test Circuit for Frequency Response (BW)
Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0is the
input, the output is measured at 0B1. All unused analog I/O ports are left open.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST=2s
P1 = 0 dBM
10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TS3DV520
Network Analyzer
(HP8753ES)
RL = 100 Ω
EXT TRIGGER
BIAS
P1 P2
DUT
A0
SEL
0B1
VSEL
VCC
VBIAS
A1
1B2
NOTES: A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
1B1
RL = 100 Ω
2B1
3B1
A2
A3
0B2
3B2
2B2
TS3DV520
www.ti.com
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION
Figure 8. Test Circuit for Crosstalk (XTALK)
Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A0is the
input, the output is measured at 1B1. All unused analog input (A) ports are connected to GND, and output (B)
ports are connected to GND through 50-Ωpulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST=2s
P1 = 0 dBM
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TS3DV520
Network Analyzer
(HP8753ES)
RL = 100 Ω
EXT TRIGGER
BIAS
P1 P2
DUT
A0
SEL
0B1
VSEL
VCC
VBIAS
0B2
NOTES: A. CL includes probe and jig capacitance.
B. A 50-Ω termination resistor is needed to match the loading of the network analyzer.
A11B1
1B2
TS3DV520
SCDS197D –DECEMBER 2005–REVISED OCTOBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 9. Test Circuit for OFF Isolation (OIRR)
OFF isolation is measured at the output of the OFF channel. For example, when VSEL = VCC and A0is the input,
the output is measured at 0B2. All unused analog input (A) ports are left open, and output (B) ports are
connected to GND through 50-Ωpulldown resistors.
HP8753ES setup
Average = 4
RBW = 3 kHz
VBIAS = 0.35 V
ST = 2
P1 = 0 dBM
12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TS3DV520
PACKAGE OPTION ADDENDUM
www.ti.com 3-Jun-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TS3DV520ERHUR ACTIVE WQFN RHU 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS3DV520RHUR ACTIVE WQFN RHU 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS3DV520RHURG4 ACTIVE WQFN RHU 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TS3DV520ERHUR WQFN RHU 56 2000 330.0 24.4 5.3 11.3 1.0 12.0 24.0 Q1
TS3DV520RHUR WQFN RHU 56 2000 330.0 24.4 5.3 11.3 1.0 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jun-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS3DV520ERHUR WQFN RHU 56 2000 346.0 346.0 35.0
TS3DV520RHUR WQFN RHU 56 2000 346.0 346.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Jun-2011
Pack Materials-Page 2
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